[picodrive.git] / pico / videoport.c

/*\r
 * PicoDrive\r
 * (c) Copyright Dave, 2004\r
 * (C) notaz, 2006-2009\r
 * (C) irixxxx, 2020-2024\r
 *\r
 * This work is licensed under the terms of MAME license.\r
 * See COPYING file in the top-level directory.\r
 */\r
\r
#include "pico_int.h"\r
#define NEED_DMA_SOURCE\r
#include "memory.h"\r
\r
\r
enum { clkdiv = 2 };    // CPU clock granularity: one of 1,2,4,8\r
\r
// VDP Slot timing, taken from http://gendev.spritesmind.net/\r
//     forum/viewtopic.php?f=22&t=851&sid=d5701a71396ee7f700c74fb7cd85cb09\r
//     http://plutiedev.com/mirror/kabuto-hardware-notes\r
// Thank you very much for the great work, Nemesis, Kabuto!\r
\r
// Slot clock is sysclock/20 for h32 and sysclock/16 for h40.\r
// One scanline is 63.7us/64.3us (ntsc/pal) long which is ~488.57 68k cycles.\r
// Approximate by 488 for VDP.\r
// 1 slot is 20/7 = 2.857 68k cycles in h32, and 16/7 = 2.286 in h40. That's\r
// 171 slots in h32, and ~214 (really 193 plus 17 prolonged in HSYNC) in h40.\r
enum { slcpu = 488 };\r
\r
// VDP has a slot counter running from 0x00 to 0xff every scanline, but it has\r
// a gap depending on the video mode. The slot in which a horizontal interrupt\r
// is generated also depends on the video mode.\r
// NB Kabuto says gapend40 is 0xe4. That's technically correct, since slots 0xb6\r
// and 0xe4 are only half slots. Ignore 0xe4 here and make 0xb6 a full slot.\r
enum { hint32 = 0x85, gapstart32 = 0x94, gapend32 = 0xe9};\r
enum { hint40 = 0xa5, gapstart40 = 0xb7, gapend40 = 0xe5};\r
\r
// Basic timing in h32: 38 slots (~108.5 cycles) from hint to VDP output start\r
// at slot 0x00. vint takes place on the 1st VBLANK line in slot 0x01 (~111.5).\r
// Rendering takes 128 slots (~365.5), and right border starts at slot 0x80\r
// (~474 cycles). hint occurs after 5 slots into the border (~488.5 cycles).\r
\r
// The horizontal sync period (HBLANK) is 30/37 slots (h32/h40):\r
// h32: 4 slots front porch (1.49us), 13 HSYNC (4.84us), 13 back porch (4.84us)\r
// h40: 5 slots front porch (1.49us), 16 HSYNC (4.77us), 16 back porch (4.77us)\r
// HBLANK starts at slot 0x93/0xb4 and ends in the middle of slot 0x05/0x06,\r
// NB VDP slows down the h40 clock to h32 during HSYNC for 17 slots to get the\r
// right sync timing. Ignored in the slot calculation, but hblen40 is correct.\r
enum { hboff32 = 0x93-hint32, hblen32 = 0xf8-(gapend32-gapstart32)-hint32};//30\r
enum { hboff40 = 0xb4-hint40, hblen40 = 0xf8-(gapend40-gapstart40)-hint40};//37\r
\r
// number of slots in a scanline\r
#define slots32	(0x100-(gapend32-gapstart32)) // 171\r
#define slots40	(0x100-(gapend40-gapstart40)) // 210\r
\r
// In blanked display, all slots but the refresh slots are usable for transfers,\r
// in active display only 16(h32) / 18(h40) slots can be used.\r
\r
// dma and refresh slots for active display, 16 for H32\r
static u8 dmaslots32[] =\r
    { 145,243, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 129,130 };\r
static u8 refslots32[] =\r
    {        250,     26,       58,       90,         122 };\r
// dma and refresh slots for active display, 18 for H40\r
static u8 dmaslots40[] =\r
    {     232, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 130,138,146, 161,162 };\r
static u8 refslots40[] =\r
    {        250,     26,       58,       90,         122,         154 };\r
\r
// table sizes\r
enum { cycsz = slcpu/clkdiv };\r
enum { sl32blsz=slots32-sizeof(refslots32)+1, sl32acsz=sizeof(dmaslots32)+1 };\r
enum { sl40blsz=slots40-sizeof(refslots40)+1, sl40acsz=sizeof(dmaslots40)+1 };\r
\r
// Tables must be considerably larger than one scanline, since 68k emulation\r
// isn't stopping in the middle of an operation. If the last op is a 32 bit\r
// VDP access 2 slots may need to be taken from the next scanline, which can be\r
// more than 100 CPU cycles. For safety just cover 2 scanlines.\r
\r
// table for hvcounter mapping. check: Sonic 3D Blast bonus, Cannon Fodder,\r
// Chase HQ II, 3 Ninjas kick back, Road Rash 3, Skitchin', Wheel of Fortune\r
static u8  hcounts_32[2*cycsz], hcounts_40[2*cycsz];\r
// tables mapping cycles to slots\r
static u16 vdpcyc2sl_32_bl[2*cycsz],vdpcyc2sl_40_bl[2*cycsz];\r
static u16 vdpcyc2sl_32_ac[2*cycsz],vdpcyc2sl_40_ac[2*cycsz];\r
// tables mapping slots to cycles\r
// NB the sl2cyc tables must cover all slots present in the cyc2sl tables.\r
static u16 vdpsl2cyc_32_bl[2*sl32blsz],vdpsl2cyc_40_bl[2*sl40blsz];\r
static u16 vdpsl2cyc_32_ac[2*sl32acsz],vdpsl2cyc_40_ac[2*sl40acsz];\r
\r
\r
// calculate timing tables for one mode (H32 or H40)\r
// NB tables aligned to HINT, since the main loop uses HINT as synchronization\r
#define INITTABLES(s) { \\r
  float factor = (float)slcpu/slots##s;					\\r
  int ax, bx, rx, ac, bc;						\\r
  int i, n;								\\r
									\\r
  /* calculate internal VDP slot numbers */				\\r
  for (i = 0; i < cycsz; i++) {						\\r
    n = hint##s + i*clkdiv/factor;					\\r
    if (n >= gapstart##s) n += gapend##s-gapstart##s;			\\r
    hcounts_##s[i] = n % 256;						\\r
  }									\\r
									\\r
  ax = bx = ac = bc = rx = 0;						\\r
  for (i = 0; i < cycsz; i++) {						\\r
    n = hcounts_##s[i];							\\r
    if (i == 0 || n != hcounts_##s[i-1]) {				\\r
      /* fill slt <=> cycle tables, active scanline */			\\r
      if (ax < ARRAY_SIZE(dmaslots##s) && dmaslots##s[ax] == n) {	\\r
        vdpsl2cyc_##s##_ac[++ax]=i;					\\r
        while (ac < i) vdpcyc2sl_##s##_ac[ac++] = ax-1;			\\r
      }									\\r
      /* fill slt <=> cycle tables, scanline off */			\\r
      if (rx >= ARRAY_SIZE(refslots##s) || refslots##s[rx] != n) {	\\r
        vdpsl2cyc_##s##_bl[++bx]=i;					\\r
        while (bc < i) vdpcyc2sl_##s##_bl[bc++] = bx-1;			\\r
      } else								\\r
        ++rx;								\\r
    }									\\r
  }									\\r
  /* fill up cycle to slot mappings for last slot */			\\r
  while (ac < cycsz)							\\r
    vdpcyc2sl_##s##_ac[ac] = ARRAY_SIZE(dmaslots##s),		ac++;	\\r
  while (bc < cycsz)							\\r
    vdpcyc2sl_##s##_bl[bc] = slots##s-ARRAY_SIZE(refslots##s),	bc++;	\\r
									\\r
  /* extend tables for 2nd scanline */					\\r
  memcpy(hcounts_##s+cycsz, hcounts_##s, ARRAY_SIZE(hcounts_##s)-cycsz);\\r
  i = ARRAY_SIZE(dmaslots##s);						\\r
  while (ac < ARRAY_SIZE(vdpcyc2sl_##s##_ac))				\\r
    vdpcyc2sl_##s##_ac[ac] = vdpcyc2sl_##s##_ac[ac-cycsz]+i,	ac++;	\\r
  while (ax < ARRAY_SIZE(vdpsl2cyc_##s##_ac)-1)			ax++,	\\r
    vdpsl2cyc_##s##_ac[ax] = vdpsl2cyc_##s##_ac[ax-i]+cycsz;		\\r
  i = slots##s - ARRAY_SIZE(refslots##s);				\\r
  while (bc < ARRAY_SIZE(vdpcyc2sl_##s##_bl))				\\r
    vdpcyc2sl_##s##_bl[bc] = vdpcyc2sl_##s##_bl[bc-cycsz]+i,	bc++;	\\r
  while (bx < ARRAY_SIZE(vdpsl2cyc_##s##_bl)-1)			bx++,	\\r
    vdpsl2cyc_##s##_bl[bx] = vdpsl2cyc_##s##_bl[bx-i]+cycsz;		\\r
}\r
 \r
\r
// initialize VDP timing tables\r
void PicoVideoInit(void)\r
{\r
  INITTABLES(32);\r
  INITTABLES(40);\r
}\r
\r
\r
static int linedisabled;    // display disabled on this line\r
static int lineenabled;     // display enabled on this line\r
static int lineoffset;      // offset at which dis/enable took place\r
\r
u32 SATaddr, SATmask;       // VRAM addr of sprite attribute table\r
\r
int (*PicoDmaHook)(u32 source, int len, unsigned short **base, u32 *mask) = NULL;\r
\r
\r
/* VDP FIFO implementation\r
 * \r
 * fifo_slot: last slot executed in this scanline\r
 * fifo_total: #total FIFO entries pending\r
 * fifo_data: last values transferred through fifo\r
 * fifo_queue: fifo transfer queue (#writes, flags)\r
 *\r
 * FIFO states:		empty	total=0\r
 *			inuse	total>0 && total<4\r
 *			full	total==4\r
 *			wait	total>4\r
 * Conditions:\r
 * fifo_slot is normally behind slot2cyc[cycles]. Advancing it beyond cycles\r
 * implies blocking the 68k up to that slot.\r
 *\r
 * A FIFO write goes to the end of the FIFO queue, but DMA running in background\r
 * is always the last queue entry (transfers by CPU intervene and come 1st).\r
 * There can be more pending writes than FIFO slots, but the CPU will be blocked\r
 * until FIFO level (without background DMA) <= 4.\r
 * This is only about correct timing, data xfer must be handled by the caller.\r
 * Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be\r
 * executed by the caller.\r
 *\r
 * FIFOSync "executes" FIFO write slots up to the given cycle in the current\r
 * scanline. A queue entry completely executed is removed from the queue.\r
 * FIFOWrite pushes writes to the transfer queue. If it's a blocking write, 68k\r
 * is blocked if more than 4 FIFO writes are pending.\r
 * FIFORead executes a 68k read. 68k is blocked until the next transfer slot.\r
 */\r
\r
// NB code assumes fifo_* arrays have size 2^n\r
static struct VdpFIFO { // XXX this must go into save file!\r
  // last transferred FIFO data, ...x = index  XXX currently only CPU\r
  u16 fifo_data[4], fifo_dx;\r
\r
  // queued FIFO transfers, ...x = index, ...l = queue length\r
  // each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags (FQ_*)\r
  u32 fifo_queue[8], fifo_qx, fifo_ql;\r
  int fifo_total;             // total# of pending FIFO entries (w/o BGDMA)\r
\r
  unsigned short fifo_slot;   // last executed slot in current scanline\r
  unsigned short fifo_maxslot;// #slots in scanline\r
\r
  const unsigned short *fifo_cyc2sl;\r
  const unsigned short *fifo_sl2cyc;\r
  const unsigned char  *fifo_hcounts;\r
} VdpFIFO;\r
\r
enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!\r
\r
\r
// NB should limit cyc2sl to table size in case 68k overdraws its aim. That can\r
// happen if the last op is a blocking acess to VDP, or for exceptions (e.g.irq)\r
#define Cyc2Sl(vf,lc)   ((vf)->fifo_cyc2sl[(lc)/clkdiv])\r
#define Sl2Cyc(vf,sl)   ((vf)->fifo_sl2cyc[sl]*clkdiv)\r
\r
// do the FIFO math\r
static int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)\r
{\r
  u32 *qx = &vf->fifo_queue[vf->fifo_qx];\r
  int l = slots, b = *qx & FQ_BYTE;\r
  int cnt = *qx >> 3;\r
\r
  // advance currently active FIFO entry\r
  if (l > cnt)\r
    l = cnt;\r
  if (!(*qx & FQ_BGDMA))\r
    vf->fifo_total -= ((cnt & b) + l) >> b;\r
  *qx -= l << 3;\r
\r
  // if entry has been processed...\r
  if (cnt == l) {\r
    // remove entry from FIFO\r
    *qx = 0;\r
    vf->fifo_qx = (vf->fifo_qx+1) & 7;\r
    vf->fifo_ql --;\r
  }\r
\r
  return l;\r
}\r
\r
static void SetFIFOState(struct VdpFIFO *vf, struct PicoVideo *pv)\r
{\r
  u32 st = pv->status, cmd = pv->command;\r
  // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore\r
  if (vf->fifo_total <= 4) {\r
    st &= ~PVS_CPUWR;\r
    if (!(st & (PVS_DMABG|PVS_DMAFILL))) {\r
      st &= ~SR_DMA;\r
      cmd &= ~0x80;\r
    }\r
  }\r
  if (vf->fifo_ql == 0) {\r
    st &= ~PVS_CPURD;\r
    // terminate DMA if applicable\r
    if (!(st & PVS_DMAFILL)) {\r
      st &= ~(SR_DMA|PVS_DMABG);\r
      cmd &= ~0x80;\r
    }\r
  }\r
  pv->status = st;\r
  pv->command = cmd;\r
}\r
\r
// sync FIFO to cycles\r
void PicoVideoFIFOSync(int cycles)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int slots, done;\r
\r
  // calculate #slots since last executed slot\r
  slots = Cyc2Sl(vf, cycles) - vf->fifo_slot;\r
  if (slots <= 0 || !vf->fifo_ql) return;\r
\r
  // advance FIFO queue by #done slots\r
  done = slots;\r
  while (done > 0 && vf->fifo_ql) {\r
    int l = AdvanceFIFOEntry(vf, pv, done);\r
    vf->fifo_slot += l;\r
    done -= l;\r
  }\r
\r
  if (done != slots)\r
    SetFIFOState(vf, pv);\r
}\r
\r
// drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.\r
static int PicoVideoFIFODrain(int level, int cycles, int bgdma)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  unsigned ocyc = cycles;\r
  int bd = vf->fifo_queue[vf->fifo_qx] & bgdma;\r
  int burn = 0;\r
\r
  if (!(vf->fifo_ql && ((vf->fifo_total > level) | bd))) return 0;\r
\r
  // process FIFO entries until low level is reached\r
  while (vf->fifo_slot < vf->fifo_maxslot &&\r
         vf->fifo_ql && ((vf->fifo_total > level) | bd)) {\r
    int b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;\r
    int c = vf->fifo_queue[vf->fifo_qx] >> 3;\r
    int cnt = bd ? c : ((vf->fifo_total-level)<<b) - (c&b);\r
    int slot = (c < cnt ? c : cnt) + vf->fifo_slot;\r
\r
    if (slot > vf->fifo_maxslot) {\r
      // target slot in later scanline, advance to eol\r
      slot = vf->fifo_maxslot;\r
    }\r
    if (slot > vf->fifo_slot) {\r
      // advance FIFO to target slot and CPU to cycles at that slot\r
      vf->fifo_slot += AdvanceFIFOEntry(vf, pv, slot - vf->fifo_slot);\r
      cycles = Sl2Cyc(vf, vf->fifo_slot);\r
      bd = vf->fifo_queue[vf->fifo_qx] & bgdma;\r
    }\r
  }\r
  if (vf->fifo_ql && ((vf->fifo_total > level) | bd))\r
    cycles = slcpu; // not completed in this scanline\r
  if (cycles > ocyc)\r
    burn = cycles - ocyc;\r
\r
  SetFIFOState(vf, pv);\r
\r
  return burn;\r
}\r
\r
// read VDP data port\r
static int PicoVideoFIFORead(void)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
  int burn = 0;\r
\r
  if (vf->fifo_ql) {\r
    // advance FIFO and CPU until FIFO is empty\r
    burn = PicoVideoFIFODrain(0, lc, FQ_BGDMA);\r
    lc += burn;\r
  }\r
\r
  if (vf->fifo_ql)\r
    pv->status |= PVS_CPURD; // target slot is in later scanline\r
  else {\r
    // use next VDP access slot for reading, block 68k until then\r
    vf->fifo_slot = Cyc2Sl(vf, lc) + 1;\r
    burn += Sl2Cyc(vf, vf->fifo_slot) - lc;\r
  }\r
\r
  return burn;\r
}\r
 \r
// write VDP data port\r
int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
  int burn = 0, x;\r
\r
  // sync only needed if queue is too full or background dma might be deferred\r
  if ((vf->fifo_ql >= 6) | (pv->status & PVS_DMABG))\r
    PicoVideoFIFOSync(lc);\r
\r
  // determine last ent, ignoring bg dma (pushed back below if new ent created)\r
  x = (vf->fifo_qx + vf->fifo_ql - 1 - !!(pv->status & PVS_DMABG)) & 7;\r
\r
  pv->status = (pv->status & ~sr_mask) | sr_flags;\r
  vf->fifo_total += count * !(flags & FQ_BGDMA);\r
  if (!vf->fifo_ql)\r
    vf->fifo_slot = Cyc2Sl(vf, lc+7); // FIFO latency ~3 vdp slots\r
\r
  // determine queue position for entry\r
  count <<= (flags & FQ_BYTE)+3;\r
  if (vf->fifo_queue[x] && (vf->fifo_queue[x] & 7) == flags) {\r
    // amalgamate entries if of same type and not empty (in case of bgdma)\r
    vf->fifo_queue[x] += count;\r
  } else {\r
    // create new xfer queue entry\r
    vf->fifo_ql ++;\r
    x = (x+1) & 7;\r
    vf->fifo_queue[(x+1)&7] = vf->fifo_queue[x]; // push back bg dma if exists\r
    vf->fifo_queue[x] = count | flags;\r
  }\r
\r
  // if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
  // do this only if it would exhaust the available slots since last sync\r
  x = (Cyc2Sl(vf,lc) - vf->fifo_slot) / 2; // lower bound of FIFO ents \r
  if ((pv->status & PVS_CPUWR) && vf->fifo_total > 4 + x)\r
    burn = PicoVideoFIFODrain(4, lc, 0);\r
\r
  return burn;\r
}\r
\r
// at HINT, advance FIFO to new scanline\r
int PicoVideoFIFOHint(void)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
  int burn = 0;\r
\r
  // reset slot to start of scanline\r
  vf->fifo_slot = 0;\r
  // only need to refresh sprite position if we are synced\r
  if (Pico.est.DrawScanline == Pico.m.scanline && !(pv->status & SR_VB))\r
    PicoDrawRefreshSprites();\r
 \r
  // if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
  if (pv->status & PVS_CPUWR)\r
    burn = PicoVideoFIFODrain(4, lc, 0);\r
  else if (pv->status & PVS_CPURD)\r
    burn = PicoVideoFIFORead();\r
\r
  return burn;\r
}\r
\r
// switch FIFO mode between active/inactive display\r
void PicoVideoFIFOMode(int active, int h40)\r
{\r
  static const unsigned short *vdpcyc2sl[2][2] =\r
      { {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl},{vdpcyc2sl_32_ac, vdpcyc2sl_40_ac} };\r
  static const unsigned short *vdpsl2cyc[2][2] =\r
      { {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl},{vdpsl2cyc_32_ac, vdpsl2cyc_40_ac} };\r
  static const unsigned char *vdphcounts[2] =\r
      { hcounts_32, hcounts_40 };\r
\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int lc = SekCyclesDone() - Pico.t.m68c_line_start;\r
  active = active && !(pv->status & PVS_VB2);\r
\r
  if (vf->fifo_maxslot)\r
    PicoVideoFIFOSync(lc);\r
  else\r
    lc = 0;\r
\r
  vf->fifo_cyc2sl = vdpcyc2sl[active][h40];\r
  vf->fifo_sl2cyc = vdpsl2cyc[active][h40];\r
  vf->fifo_hcounts = vdphcounts[h40];\r
  // recalculate FIFO slot for new mode\r
  vf->fifo_slot = Cyc2Sl(vf, lc);\r
  vf->fifo_maxslot = Cyc2Sl(vf, slcpu);\r
}\r
\r
// VDP memory rd/wr\r
\r
static __inline void AutoIncrement(void)\r
{\r
  struct PicoVideo *pvid = &Pico.video;\r
  pvid->addr=(unsigned short)(pvid->addr+pvid->reg[0xf]);\r
  if (pvid->addr < pvid->reg[0xf]) pvid->addr_u ^= 1;\r
}\r
\r
static NOINLINE void VideoWriteVRAM128(u32 a, u16 d)\r
{\r
  // nasty\r
  u32 b = ((a & 2) >> 1) | ((a & 0x400) >> 9) | (a & 0x3FC) | ((a & 0x1F800) >> 1);\r
\r
  ((u8 *)PicoMem.vram)[b] = d;\r
  if (!(u16)((b^SATaddr) & SATmask))\r
    Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
\r
  if (((a^SATaddr) & SATmask) == 0)\r
    UpdateSAT(a, d);\r
}\r
\r
static void VideoWrite(u16 d)\r
{\r
  struct PicoVideo *pvid = &Pico.video;\r
  unsigned int a = pvid->addr;\r
\r
  switch (pvid->type)\r
  {\r
    case 1: if (a & 1)\r
              d = (u16)((d << 8) | (d >> 8));\r
            a |= pvid->addr_u << 16;\r
            VideoWriteVRAM(a, d);\r
            break;\r
    case 3: if (PicoMem.cram [(a >> 1) & 0x3f] != (d & 0xeee)) Pico.m.dirtyPal = 1;\r
            PicoMem.cram [(a >> 1) & 0x3f] = d & 0xeee; break;\r
    case 5: PicoMem.vsram[(a >> 1) & 0x3f] = d & 0x7ff; break;\r
    case 0x81:\r
            a |= pvid->addr_u << 16;\r
            VideoWriteVRAM128(a, d);\r
            break;\r
    //default:elprintf(EL_ANOMALY, "VDP write %04x with bad type %i", d, pvid->type); break;\r
  }\r
\r
  AutoIncrement();\r
}\r
\r
static unsigned int VideoRead(int is_from_z80)\r
{\r
  struct PicoVideo *pvid = &Pico.video;\r
  unsigned int a, d = VdpFIFO.fifo_data[(VdpFIFO.fifo_dx+1)&3];\r
\r
  a=pvid->addr; a>>=1;\r
\r
  if (!is_from_z80)\r
    SekCyclesBurnRun(PicoVideoFIFORead());\r
  switch (pvid->type)\r
  {\r
    case 0: d=PicoMem.vram [a & 0x7fff]; break;\r
    case 8: d=PicoMem.cram [a & 0x003f] | (d & ~0x0eee); break;\r
    case 4: if ((a & 0x3f) >= 0x28) a = 0;\r
            d=PicoMem.vsram [a & 0x003f] | (d & ~0x07ff); break;\r
    case 12:a=PicoMem.vram [a & 0x7fff]; if (pvid->addr&1) a >>= 8;\r
            d=(a & 0x00ff) | (d & ~0x00ff); break;\r
    default:elprintf(EL_ANOMALY, "VDP read with bad type %i", pvid->type); break;\r
  }\r
\r
  AutoIncrement();\r
  return d;\r
}\r
\r
// VDP DMA\r
\r
static int GetDmaLength(void)\r
{\r
  struct PicoVideo *pvid=&Pico.video;\r
  int len=0;\r
  // 16-bit words to transfer:\r
  len =pvid->reg[0x13];\r
  len|=pvid->reg[0x14]<<8;\r
  len = ((len - 1) & 0xffff) + 1;\r
  return len;\r
}\r
\r
static void DmaSlow(int len, u32 source)\r
{\r
  struct PicoVideo *pvid=&Pico.video;\r
  u32 inc = pvid->reg[0xf];\r
  u32 a = pvid->addr | (pvid->addr_u << 16), e;\r
  u16 *r, *base = NULL;\r
  u32 mask = 0x1ffff;\r
  int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
\r
  elprintf(EL_VDPDMA, "DmaSlow[%i] %06x->%04x len %i inc=%i blank %i [%u] @ %06x",\r
    pvid->type, source, a, len, inc, (pvid->status&SR_VB)||!(pvid->reg[1]&0x40),\r
    SekCyclesDone(), SekPc);\r
\r
  SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (pvid->type == 1),\r
                              PVS_DMABG, SR_DMA | PVS_CPUWR));\r
  // short transfers might have been completely conveyed to FIFO, adjust state\r
  if ((pvid->status & SR_DMA) && VdpFIFO.fifo_total <= 4)\r
    SetFIFOState(&VdpFIFO, pvid);\r
\r
  if ((source & 0xe00000) == 0xe00000) { // Ram\r
    base = (u16 *)PicoMem.ram;\r
    mask = 0xffff;\r
  }\r
  else if (PicoIn.AHW & PAHW_MCD)\r
  {\r
    u8 r3 = Pico_mcd->s68k_regs[3];\r
    elprintf(EL_VDPDMA, "DmaSlow CD, r3=%02x", r3);\r
    if (source < Pico.romsize /*0x20000*/) { // Bios area\r
      base = (u16 *)(Pico.rom + (source & 0xfe0000));\r
    } else if ((source & 0xfc0000) == pcd_base_address+0x200000) { // Word Ram\r
      if (!(r3 & 4)) { // 2M mode\r
        base = (u16 *)(Pico_mcd->word_ram2M + (source & 0x20000));\r
      } else {\r
        if ((source & 0xfe0000) < pcd_base_address+0x220000) { // 1M mode\r
          int bank = r3 & 1;\r
          base = (u16 *)(Pico_mcd->word_ram1M[bank]);\r
        } else {\r
          DmaSlowCell(source - 2, a, len, inc);\r
          return;\r
        }\r
      }\r
      source -= 2;\r
    } else if ((source & 0xfe0000) == pcd_base_address+0x020000) { // Prg Ram\r
      base = (u16 *)Pico_mcd->prg_ram_b[r3 >> 6];\r
      source -= 2; // XXX: test\r
    }\r
  }\r
  else\r
  {\r
    // if we have DmaHook, let it handle ROM because of possible DMA delay\r
    u32 source2;\r
    if (PicoDmaHook && (source2 = PicoDmaHook(source, len, &base, &mask)))\r
      source = source2;\r
    else // Rom\r
      base = m68k_dma_source(source);\r
  }\r
  if (!base) {\r
    elprintf(EL_VDPDMA|EL_ANOMALY, "DmaSlow[%i] %06x->%04x: invalid src", pvid->type, source, a);\r
    return;\r
  }\r
\r
  // operate in words\r
  source >>= 1;\r
  mask >>= 1;\r
\r
  switch (pvid->type)\r
  {\r
    case 1: // vram\r
      e = a + len*2-1;\r
      r = PicoMem.vram;\r
      if (inc == 2 && !(a & 1) && !((a ^ e) >> 16) &&\r
          ((a >= SATaddr + 0x280) | (e < SATaddr)) &&\r
          !((source ^ (source + len-1)) & ~mask))\r
      {\r
        // most used DMA mode\r
        memcpy((char *)r + a, base + (source & mask), len * 2);\r
        a += len * 2;\r
        break;\r
      }\r
      for(; len; len--)\r
      {\r
        u16 d = base[source++ & mask];\r
        if(a & 1) d=(d<<8)|(d>>8);\r
        VideoWriteVRAM(a, d);\r
        // AutoIncrement\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
\r
    case 3: // cram\r
      Pico.m.dirtyPal = 1;\r
      r = PicoMem.cram;\r
      if (inc == 0 && !(pvid->reg[1] & 0x40) &&\r
            (pvid->reg[7] & 0x3f) == ((a/2) & 0x3f)) { // bg color DMA\r
        PicoVideoSync(1);\r
        int sl = VdpFIFO.fifo_hcounts[lc/clkdiv];\r
        if (sl > VdpFIFO.fifo_hcounts[0]-5) // hint delay is 5 slots\r
          sl = (s8)sl;\r
        // TODO this is needed to cover timing inaccuracies\r
        if (sl <= 12) sl = -3;\r
        else if (sl <= 40) sl = 30;\r
        PicoDrawBgcDMA(base, source, mask, len, sl);\r
        // do last DMA cycle since it's all going to the same cram location\r
        source = source+len-1;\r
        len = 1;\r
      }\r
      for (; len; len--)\r
      {\r
        r[(a / 2) & 0x3f] = base[source++ & mask] & 0xeee;\r
        // AutoIncrement\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
\r
    case 5: // vsram\r
      r = PicoMem.vsram;\r
      for (; len; len--)\r
      {\r
        r[(a / 2) & 0x3f] = base[source++ & mask] & 0x7ff;\r
        // AutoIncrement\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
\r
    case 0x81: // vram 128k\r
      for(; len; len--)\r
      {\r
        u16 d = base[source++ & mask];\r
        VideoWriteVRAM128(a, d);\r
        // AutoIncrement\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
\r
    default:\r
      if (pvid->type != 0 || (EL_LOGMASK & EL_VDPDMA))\r
        elprintf(EL_VDPDMA|EL_ANOMALY, "DMA with bad type %i", pvid->type);\r
      break;\r
  }\r
  // remember addr\r
  pvid->addr = a;\r
  pvid->addr_u = a >> 16;\r
}\r
\r
static void DmaCopy(int len)\r
{\r
  struct PicoVideo *pvid=&Pico.video;\r
  u32 a = pvid->addr | (pvid->addr_u << 16);\r
  u8 *vr = (u8 *)PicoMem.vram;\r
  u8 inc = pvid->reg[0xf];\r
  int source;\r
  elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());\r
\r
  // XXX implement VRAM 128k? Is this even working? xfer/count still in bytes?\r
  SekCyclesBurnRun(PicoVideoFIFOWrite(2*len, FQ_BGDMA, // 2 slots each (rd+wr)\r
                              PVS_CPUWR, SR_DMA | PVS_DMABG));\r
\r
  source =pvid->reg[0x15];\r
  source|=pvid->reg[0x16]<<8;\r
\r
  for (; len; len--)\r
  {\r
    vr[(u16)a] = vr[(u16)(source++)];\r
    if (((a^SATaddr) & SATmask) == 0)\r
      UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);\r
    // AutoIncrement\r
    a = (a+inc) & ~0x20000;\r
  }\r
  // remember addr\r
  pvid->addr = a;\r
  pvid->addr_u = a >> 16;\r
}\r
\r
static NOINLINE void DmaFill(int data)\r
{\r
  struct PicoVideo *pvid=&Pico.video;\r
  u32 a = pvid->addr | (pvid->addr_u << 16), e;\r
  u8 *vr = (u8 *)PicoMem.vram;\r
  u8 high = (u8)(data >> 8);\r
  u8 inc = pvid->reg[0xf];\r
  int source;\r
  int len, l;\r
\r
  len = GetDmaLength();\r
  elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());\r
\r
  SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA, // 1 slot each (wr)\r
                              PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));\r
\r
  switch (pvid->type)\r
  {\r
    case 1: // vram\r
      e = a + len-1;\r
      if (inc == 1 && !((a ^ e) >> 16) &&\r
          ((a >= SATaddr + 0x280) | (e < SATaddr)))\r
      {\r
        // most used DMA mode\r
        memset(vr + (u16)a, high, len);\r
        a += len;\r
        break;\r
      }\r
      for (l = len; l; l--) {\r
        // Write upper byte to adjacent address\r
        // (here we are byteswapped, so address is already 'adjacent')\r
        vr[(u16)a] = high;\r
        if (((a^SATaddr) & SATmask) == 0)\r
          UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);\r
\r
        // Increment address register\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
    case 3:   // cram\r
      Pico.m.dirtyPal = 1;\r
      data &= 0xeee;\r
      for (l = len; l; l--) {\r
        PicoMem.cram[(a/2) & 0x3f] = data;\r
\r
        // Increment address register\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
    case 5: { // vsram\r
      data &= 0x7ff;\r
      for (l = len; l; l--) {\r
        PicoMem.vsram[(a/2) & 0x3f] = data;\r
\r
        // Increment address register\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
    }\r
    case 0x81: // vram 128k\r
      for (l = len; l; l--) {\r
        VideoWriteVRAM128(a, data);\r
\r
        // Increment address register\r
        a = (a+inc) & ~0x20000;\r
      }\r
      break;\r
    default:\r
      a += len * inc;\r
      break;\r
  }\r
\r
  // remember addr\r
  pvid->addr = a;\r
  pvid->addr_u = a >> 16;\r
  // register update\r
  pvid->reg[0x13] = pvid->reg[0x14] = 0;\r
  source  = pvid->reg[0x15];\r
  source |= pvid->reg[0x16] << 8;\r
  source += len;\r
  pvid->reg[0x15] = source;\r
  pvid->reg[0x16] = source >> 8;\r
}\r
\r
// VDP command handling\r
\r
static NOINLINE void CommandDma(void)\r
{\r
  struct PicoVideo *pvid = &Pico.video;\r
  u32 len, method;\r
  u32 source;\r
\r
  PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);\r
  if (pvid->status & SR_DMA) {\r
    elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",\r
             VdpFIFO.fifo_total, SekPc);\r
    VdpFIFO.fifo_total = VdpFIFO.fifo_ql = 0;\r
    pvid->status &= ~PVS_DMAFILL;\r
  }\r
\r
  len = GetDmaLength();\r
  source  = pvid->reg[0x15];\r
  source |= pvid->reg[0x16] << 8;\r
  source |= pvid->reg[0x17] << 16;\r
\r
  method=pvid->reg[0x17]>>6;\r
  if (method < 2)\r
    DmaSlow(len, source << 1); // 68000 to VDP\r
  else if (method == 3)\r
    DmaCopy(len); // VRAM Copy\r
  else {\r
    pvid->status |= SR_DMA|PVS_DMAFILL;\r
    return;\r
  }\r
  source += len;\r
  pvid->reg[0x13] = pvid->reg[0x14] = 0;\r
  pvid->reg[0x15] = source;\r
  pvid->reg[0x16] = source >> 8;\r
}\r
\r
static NOINLINE void CommandChange(struct PicoVideo *pvid)\r
{\r
  unsigned int cmd, addr;\r
\r
  cmd = pvid->command;\r
\r
  // Get type of transfer 0xc0000030 (v/c/vsram read/write)\r
  pvid->type = (u8)(((cmd >> 2) & 0xc) | (cmd >> 30));\r
  if (pvid->type == 1) // vram\r
    pvid->type |= pvid->reg[1] & 0x80; // 128k\r
\r
  // Get address 0x3fff0003\r
  addr  = (cmd >> 16) & 0x3fff;\r
  addr |= (cmd << 14) & 0xc000;\r
  pvid->addr = (u16)addr;\r
  pvid->addr_u = (u8)((cmd >> 2) & 1);\r
}\r
\r
// VDP interface\r
 \r
static inline int InHblank(int offs)\r
{\r
  // check if in left border (14 pixels) or HBLANK (86 pixels), 116 68k cycles\r
  return SekCyclesDone() - Pico.t.m68c_line_start <= offs;\r
}\r
\r
void PicoVideoSync(int skip)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  int lines = Pico.video.reg[1]&0x08 ? 240 : 224;\r
  int last = Pico.m.scanline - (skip > 0);\r
\r
  if (!(PicoIn.opt & POPT_ALT_RENDERER) && !PicoIn.skipFrame) {\r
    if (last >= lines)\r
      last = lines-1;\r
    else // in active display, need to sync next frame as well\r
      Pico.est.rendstatus |= PDRAW_SYNC_NEXT;\r
\r
    //elprintf(EL_ANOMALY, "sync");\r
    if (unlikely(linedisabled >= 0 && linedisabled <= last)) {\r
      if (Pico.est.DrawScanline <= linedisabled) {\r
        int sl = vf->fifo_hcounts[lineoffset/clkdiv];\r
        PicoDrawSync(linedisabled, sl ? sl : 1, 0);\r
      }\r
      linedisabled = -1;\r
    }\r
    if (unlikely(lineenabled >= 0 && lineenabled <= last)) {\r
      if (Pico.est.DrawScanline <= lineenabled) {\r
        int sl = vf->fifo_hcounts[lineoffset/clkdiv];\r
        PicoDrawSync(lineenabled, 0, sl ? sl : 1);\r
      }\r
      lineenabled = -1;\r
    }\r
    if (Pico.est.DrawScanline <= last)\r
      PicoDrawSync(last, 0, 0);\r
  }\r
  if (skip >= 0)\r
    Pico.est.rendstatus |= PDRAW_SYNC_NEEDED;\r
}\r
\r
PICO_INTERNAL_ASM void PicoVideoWrite(u32 a,unsigned short d)\r
{\r
  struct PicoVideo *pvid=&Pico.video;\r
\r
  //elprintf(EL_STATUS, "PicoVideoWrite [%06x] %04x [%u] @ %06x",\r
  //  a, d, SekCyclesDone(), SekPc);\r
\r
  a &= 0x1c;\r
  switch (a)\r
  {\r
  case 0x00: // Data port 0 or 2\r
    if (pvid->pending) {\r
      CommandChange(pvid);\r
      pvid->pending=0;\r
    }\r
\r
    // try avoiding the sync if the data doesn't change.\r
    // Writes to the SAT in VRAM are special since they update the SAT cache.\r
    if ((pvid->reg[1]&0x40) &&\r
        !(pvid->type == 1 && !(pvid->addr&1) && ((pvid->addr^SATaddr)&SATmask) && PicoMem.vram[pvid->addr>>1] == d) &&\r
        !(pvid->type == 3 && PicoMem.cram[(pvid->addr>>1) & 0x3f] == (d & 0xeee)) &&\r
        !(pvid->type == 5 && PicoMem.vsram[(pvid->addr>>1) & 0x3f] == (d & 0x7ff)))\r
      // the vertical scroll value for this line must be read from VSRAM early,\r
      // since the A/B tile row to be read depends on it. E.g. Skitchin, OD2\r
      // in contrast, CRAM writes would have an immediate effect on the current\r
      // pixel, so sync can be closer to start of actual image data\r
      PicoVideoSync(InHblank(pvid->type == 3 ? 103 : 30)); // cram in Toy Story\r
\r
    if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))\r
    {\r
      VdpFIFO.fifo_data[++VdpFIFO.fifo_dx&3] = d;\r
      SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));\r
\r
      elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",\r
        pvid->addr, d, SekCyclesDone(), pvid->type, SekPc);\r
    }\r
    VideoWrite(d);\r
\r
    // start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.\r
    if (pvid->status & PVS_DMAFILL)\r
      DmaFill(VdpFIFO.fifo_data[(VdpFIFO.fifo_dx + !!(pvid->type&~0x81))&3]);\r
\r
    break;\r
\r
  case 0x04: // Control (command) port 4 or 6\r
    if (pvid->status & SR_DMA)\r
      SekCyclesBurnRun(PicoVideoFIFORead()); // kludge, flush out running DMA\r
    if (pvid->pending)\r
    {\r
      // Low word of command:\r
      if (!(pvid->reg[1]&0x10))\r
        d = (d&~0x80)|(pvid->command&0x80);\r
      pvid->command &= 0xffff0000;\r
      pvid->command |= d;\r
      pvid->pending = 0;\r
      CommandChange(pvid);\r
      // Check for dma:\r
      if (d & 0x80) {\r
        PicoVideoSync(InHblank(93));\r
        CommandDma();\r
      }\r
    }\r
    else\r
    {\r
      if ((d&0xc000)==0x8000)\r
      {\r
        // Register write:\r
        int num=(d>>8)&0x1f;\r
        int dold=pvid->reg[num];\r
        pvid->type=0; // register writes clear command (else no Sega logo in Golden Axe II)\r
        if (num > 0x0a && !(pvid->reg[1]&4)) {\r
          elprintf(EL_ANOMALY, "%02x written to reg %02x in SMS mode @ %06x", d, num, SekPc);\r
          return;\r
        }\r
\r
        d &= 0xff;\r
\r
        if (num == 1 && ((pvid->reg[1]^d)&0x40)) {\r
          // handle line blanking before line rendering. Only the last switch\r
          // before the 1st sync for other reasons is honoured. Switching after\r
          // active area is on next line\r
          int skip = InHblank(470); // Deadly Moves\r
          PicoVideoSync(skip);\r
          lineenabled = (d&0x40) ? Pico.m.scanline + !skip: -1;\r
          linedisabled = (d&0x40) ? -1 : Pico.m.scanline + !skip;\r
          lineoffset = (skip ? SekCyclesDone() - Pico.t.m68c_line_start : 0);\r
        } else if (((1<<num) & 0x738ff) && pvid->reg[num] != d)\r
          // VDP regs 0-7,11-13,16-18 influence rendering, ignore all others\r
          PicoVideoSync(InHblank(93)); // Toy Story\r
        pvid->reg[num] = d;\r
\r
        switch (num)\r
        {\r
          case 0x00:\r
            if ((~dold&d)&2) {\r
              unsigned c = SekCyclesDone() - Pico.t.m68c_line_start;\r
              pvid->hv_latch = VdpFIFO.fifo_hcounts[c/clkdiv] | (pvid->v_counter << 8);\r
            }\r
            elprintf(EL_INTSW, "hint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x10)>>4,\r
                    (d&0x10)>>4, SekCyclesDone(), (pvid->pending_ints&0x10)>>4, SekPc);\r
            goto update_irq;\r
          case 0x01:\r
            if ((d^dold)&0x40)\r
              PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);\r
            if (!(pvid->status & PVS_VB2))\r
              pvid->status &= ~SR_VB;\r
            pvid->status |= ((d >> 3) ^ SR_VB) & SR_VB; // forced blanking\r
            elprintf(EL_INTSW, "vint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x20)>>5,\r
                    (d&0x20)>>5, SekCyclesDone(), (pvid->pending_ints&0x20)>>5, SekPc);\r
            goto update_irq;\r
          case 0x05:\r
          case 0x06:\r
            if (d^dold) Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
            break;\r
          case 0x0c:\r
            // renderers should update their palettes if sh/hi mode is changed\r
            if ((d^dold)&8) Pico.m.dirtyPal = 1;\r
            if ((d^dold)&1) {\r
              PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);\r
              Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
            }\r
            break;\r
          default:\r
            return;\r
        }\r
        if (Pico.est.rendstatus & PDRAW_DIRTY_SPRITES) {\r
          SATaddr = ((pvid->reg[5]&0x7f) << 9) | ((pvid->reg[6]&0x20) << 11);\r
          SATmask = ~0x1ff;\r
          if (pvid->reg[12]&1)\r
            SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit\r
          //elprintf(EL_STATUS, "spritep moved to %04x", SATaddr);\r
        }\r
        return;\r
\r
update_irq:\r
#ifndef EMU_CORE_DEBUG\r
        // update IRQ level; TODO hack, still fire irq if disabling now\r
        if (!SekShouldInterrupt() || SekIrqLevel < pvid->hint_irq)\r
        {\r
          int lines, pints, irq = 0;\r
          lines = (pvid->reg[1] & 0x20) | (pvid->reg[0] & 0x10);\r
          pints = pvid->pending_ints & lines;\r
               if (pints & 0x20) irq = 6;\r
          else if (pints & 0x10) irq = pvid->hint_irq;\r
\r
          if (irq) {\r
            // VDP irqs have highest prio, just overwrite old level\r
            SekInterrupt(irq); // update line\r
\r
            // TODO this is broken because cost of current insn isn't known here\r
            SekEndRun(21); // make it delayed\r
          } else if (SekIrqLevel >= pvid->hint_irq) {\r
            // no VDP irq, query lower irqs\r
            SekInterrupt(PicoIn.AHW & PAHW_PICO ? PicoPicoIrqAck(0) : 0);\r
          }\r
        }\r
#endif\r
      }\r
      else\r
      {\r
        // High word of command:\r
        pvid->command&=0x0000ffff;\r
        pvid->command|=d<<16;\r
        pvid->pending=1;\r
      }\r
    }\r
    break;\r
\r
  // case 0x08: // 08 0a - HV counter - lock up\r
  // case 0x0c: // 0c 0e - HV counter - lock up\r
  // case 0x10: // 10 12 - PSG - handled by caller\r
  // case 0x14: // 14 16 - PSG - handled by caller\r
  // case 0x18: // 18 1a - no effect?\r
  case 0x1c: // 1c 1e - debug\r
    pvid->debug = d;\r
    pvid->debug_p = 0;\r
    if (d & (1 << 6)) {\r
      pvid->debug_p |= PVD_KILL_A | PVD_KILL_B;\r
      pvid->debug_p |= PVD_KILL_S_LO | PVD_KILL_S_HI;\r
    }\r
    switch ((d >> 7) & 3) {\r
      case 1:\r
        pvid->debug_p &= ~(PVD_KILL_S_LO | PVD_KILL_S_HI);\r
        pvid->debug_p |= PVD_FORCE_S;\r
        break;\r
      case 2:\r
        pvid->debug_p &= ~PVD_KILL_A;\r
        pvid->debug_p |= PVD_FORCE_A;\r
        break;\r
      case 3:\r
        pvid->debug_p &= ~PVD_KILL_B;\r
        pvid->debug_p |= PVD_FORCE_B;\r
        break;\r
    }\r
    break;\r
  }\r
}\r
\r
static u32 VideoSr(const struct PicoVideo *pv)\r
{\r
  unsigned int hp = pv->reg[12]&1 ? hboff40*488.5/slots40 : hboff32*488.5/slots32;\r
  unsigned int hl = pv->reg[12]&1 ? hblen40*488.5/slots40 : hblen32*488.5/slots32;\r
  unsigned int c = SekCyclesDone() - Pico.t.m68c_line_start;\r
  u32 d;\r
\r
  PicoVideoFIFOSync(c);\r
  d = (u16)pv->status;\r
\r
  if (c - hp < hl)\r
    d |= SR_HB;\r
\r
  if (VdpFIFO.fifo_total >= 4)\r
    d |= SR_FULL;\r
  else if (!VdpFIFO.fifo_total)\r
    d |= SR_EMPT;\r
  return d;\r
}\r
\r
PICO_INTERNAL_ASM u32 PicoVideoRead(u32 a)\r
{\r
  struct PicoVideo *pv = &Pico.video;\r
  a &= 0x1c;\r
\r
  if (a == 0x04) // control port\r
  {\r
    u32 d = VideoSr(pv);\r
    if (pv->pending) {\r
      CommandChange(pv);\r
      pv->pending = 0;\r
    }\r
    elprintf(EL_SR, "SR read: %04x [%u] @ %06x", d, SekCyclesDone(), SekPc);\r
    return d;\r
  }\r
\r
  if (a == 0x08)\r
  {\r
    unsigned int c;\r
    u32 d;\r
\r
    c = SekCyclesDone() - Pico.t.m68c_line_start;\r
    if (pv->reg[0]&2)\r
         d = pv->hv_latch;\r
    else d = VdpFIFO.fifo_hcounts[c/clkdiv] | (pv->v_counter << 8);\r
\r
    elprintf(EL_HVCNT, "hv: %02x %02x [%u] @ %06x", d, pv->v_counter, SekCyclesDone(), SekPc);\r
    return d;\r
  }\r
\r
  if (a==0x00) // data port\r
  {\r
    return VideoRead(0);\r
  }\r
\r
  return PicoRead16_floating(a | 0xc00000);\r
}\r
\r
unsigned char PicoVideoRead8DataH(int is_from_z80)\r
{\r
  return VideoRead(is_from_z80) >> 8;\r
}\r
\r
unsigned char PicoVideoRead8DataL(int is_from_z80)\r
{\r
  return VideoRead(is_from_z80);\r
}\r
\r
unsigned char PicoVideoRead8CtlH(int is_from_z80)\r
{\r
  struct PicoVideo *pv = &Pico.video;\r
  u8 d = VideoSr(pv) >> 8;\r
  if (pv->pending) {\r
    CommandChange(pv);\r
    pv->pending = 0;\r
  }\r
  elprintf(EL_SR, "SR read (h): %02x @ %06x", d, SekPc);\r
  return d;\r
}\r
\r
unsigned char PicoVideoRead8CtlL(int is_from_z80)\r
{\r
  struct PicoVideo *pv = &Pico.video;\r
  u8 d = VideoSr(pv);\r
  if (pv->pending) {\r
    CommandChange(pv);\r
    pv->pending = 0;\r
  }\r
  elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);\r
  return d;\r
}\r
\r
unsigned char PicoVideoRead8HV_H(int is_from_z80)\r
{\r
  u32 d = Pico.video.v_counter;\r
  if (Pico.video.reg[0]&2)\r
    d = Pico.video.hv_latch >> 8;\r
  elprintf(EL_HVCNT, "vcounter: %02x [%u] @ %06x", d, SekCyclesDone(), SekPc);\r
  return d;\r
}\r
\r
// FIXME: broken\r
unsigned char PicoVideoRead8HV_L(int is_from_z80)\r
{\r
  u32 d = SekCyclesDone() - Pico.t.m68c_line_start;\r
  if (Pico.video.reg[0]&2)\r
       d = Pico.video.hv_latch;\r
  else d = VdpFIFO.fifo_hcounts[d/clkdiv];\r
  elprintf(EL_HVCNT, "hcounter: %02x [%u] @ %06x", d, SekCyclesDone(), SekPc);\r
  return d;\r
}\r
\r
void PicoVideoReset(void)\r
{\r
  Pico.video.pending_ints=0;\r
  Pico.video.reg[1] &= ~0x40; // TODO verify display disabled after reset\r
  Pico.video.reg[10] = 0xff; // HINT is turned off after reset\r
  Pico.video.status = 0x3428 | Pico.m.pal; // 'always set' bits | vblank | collision | pal\r
\r
  memset(&VdpFIFO, 0, sizeof(VdpFIFO));\r
  Pico.m.dirtyPal = 1;\r
\r
  PicoDrawBgcDMA(NULL, 0, 0, 0, 0);\r
  PicoVideoFIFOMode(Pico.video.reg[1]&0x40, Pico.video.reg[12]&1);\r
}\r
\r
void PicoVideoCacheSAT(int load)\r
{\r
  struct PicoVideo *pv = &Pico.video;\r
  int l;\r
\r
  SATaddr = ((pv->reg[5]&0x7f) << 9) | ((pv->reg[6]&0x20) << 11);\r
  SATmask = ~0x1ff;\r
  if (pv->reg[12]&1)\r
    SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit\r
\r
  // rebuild SAT cache XXX wrong since cache and memory can differ\r
  for (l = 0; load && l < 2*80; l ++) {\r
    u16 addr = SATaddr + l*4;\r
    ((u16 *)VdpSATCache)[l*2    ] = PicoMem.vram[(addr>>1)    ];\r
    ((u16 *)VdpSATCache)[l*2 + 1] = PicoMem.vram[(addr>>1) + 1];\r
  }\r
\r
  Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
}\r
\r
void PicoVideoSave(void)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int l, x;\r
\r
  // account for all outstanding xfers XXX kludge, entry attr's not saved\r
  pv->fifo_cnt = pv->fifo_bgcnt = 0;\r
  for (l = vf->fifo_ql, x = vf->fifo_qx + l-1; l > 0; l--, x--) {\r
    int cnt = (vf->fifo_queue[x&7] >> 3);\r
    if (vf->fifo_queue[x&7] & FQ_BGDMA)\r
      pv->fifo_bgcnt += cnt;\r
    else\r
      pv->fifo_cnt += cnt;\r
  }\r
}\r
\r
void PicoVideoLoad(void)\r
{\r
  struct VdpFIFO *vf = &VdpFIFO;\r
  struct PicoVideo *pv = &Pico.video;\r
  int b = pv->type == 1;\r
\r
  // convert former dma_xfers (why was this in PicoMisc anyway?)\r
  if (Pico.m.dma_xfers) {\r
    pv->fifo_cnt = Pico.m.dma_xfers << b;\r
    Pico.m.dma_xfers = 0;\r
  }\r
\r
  // fake entries in the FIFO if there are outstanding transfers\r
  vf->fifo_ql = vf->fifo_qx = vf->fifo_total = 0;\r
  if (pv->fifo_cnt) {\r
    int wc = pv->fifo_cnt;\r
    vf->fifo_total = (wc+b) >> b;\r
    vf->fifo_queue[vf->fifo_qx + vf->fifo_ql] = (wc << 3) | b | FQ_FGDMA;\r
    vf->fifo_ql ++;\r
    if (vf->fifo_total > 4 && !(pv->status & (PVS_CPUWR|PVS_CPURD)))\r
      pv->status |= PVS_CPUWR;\r
  }\r
  if (pv->fifo_bgcnt) {\r
    int wc = pv->fifo_bgcnt;\r
    if (!vf->fifo_ql)\r
      pv->status |= PVS_DMABG;\r
    vf->fifo_queue[vf->fifo_qx + vf->fifo_ql] = (wc << 3)     | FQ_BGDMA;\r
    vf->fifo_ql ++;\r
  }\r
  PicoVideoCacheSAT(1);\r
  vf->fifo_maxslot = 0;\r
}\r
// vim:shiftwidth=2:ts=2:expandtab\r