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1 | @ vim:filetype=armasm |
2 | |
3 | |
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4 | .global vidCpy8to16 @ void *dest, void *src, short *pal, int lines|(is32col<<8) |
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5 | |
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6 | vidCpy8to16: |
7 | stmfd sp!, {r4-r8,lr} |
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8 | |
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9 | tst r3, #0x100 |
10 | and r3, r3, #0xff |
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11 | mov r3, r3, lsr #1 |
12 | orr r3, r3, r3, lsl #8 |
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13 | orreq r3, r3, #(320/8-1)<<24 @ 40 col mode |
14 | orrne r3, r3, #(256/8-1)<<24 @ 32 col mode |
15 | orrne r3, r3, #0x10000 |
16 | addne r0, r0, #32*2 |
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17 | add r1, r1, #8 |
18 | mov lr, #0xff |
19 | mov lr, lr, lsl #1 |
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20 | |
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21 | @ even lines first |
22 | vcloop_aligned: |
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23 | ldr r12, [r1], #4 |
24 | ldr r7, [r1], #4 |
25 | |
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26 | and r4, lr, r12,lsl #1 |
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27 | ldrh r4, [r2, r4] |
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28 | and r5, lr, r12,lsr #7 |
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29 | ldrh r5, [r2, r5] |
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30 | and r6, lr, r12,lsr #15 |
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31 | ldrh r6, [r2, r6] |
32 | orr r4, r4, r5, lsl #16 |
33 | |
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34 | and r5, lr, r12,lsr #23 |
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35 | ldrh r5, [r2, r5] |
36 | and r8, lr, r7, lsl #1 |
37 | ldrh r8, [r2, r8] |
38 | orr r5, r6, r5, lsl #16 |
39 | |
40 | and r6, lr, r7, lsr #7 |
41 | ldrh r6, [r2, r6] |
42 | and r12,lr, r7, lsr #15 |
43 | ldrh r12,[r2, r12] |
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44 | and r7, lr, r7, lsr #23 |
45 | ldrh r7, [r2, r7] |
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46 | orr r8, r8, r6, lsl #16 |
47 | |
48 | subs r3, r3, #1<<24 |
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49 | orr r12,r12, r7, lsl #16 |
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50 | |
51 | stmia r0!, {r4,r5,r8,r12} |
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52 | bpl vcloop_aligned |
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53 | |
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54 | tst r3, #0x10000 |
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55 | add r1, r1, #336 @ skip a line and 1 col |
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56 | addne r1, r1, #64 @ skip more for 32col mode |
57 | add r0, r0, #(320+2)*2 |
58 | addne r0, r0, #64*2 |
59 | addeq r3, r3, #(320/8)<<24 |
60 | addne r3, r3, #(256/8)<<24 |
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61 | sub r3, r3, #1 |
62 | tst r3, #0xff |
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63 | bne vcloop_aligned |
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64 | |
65 | and r4, r3, #0xff00 |
66 | orr r3, r3, r4, lsr #8 |
67 | mov r4, r4, lsr #7 |
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68 | sub r6, r4, #1 |
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69 | mov r5, #320*2 |
70 | add r5, r5, #2 |
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71 | mul r4, r5, r6 |
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72 | sub r0, r0, r4 |
73 | mov r5, #328 |
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74 | mul r4, r5, r6 |
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75 | sub r1, r1, r4 |
76 | |
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77 | sub r0, r0, #2 |
78 | mov r8, #0 |
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79 | |
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80 | vcloop_unaligned: |
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81 | ldr r12, [r1], #4 |
82 | ldr r7, [r1], #4 |
83 | |
84 | and r6, lr, r12, lsl #1 |
85 | ldrh r6, [r2, r6] |
86 | and r5, lr, r12, lsr #7 |
87 | ldrh r5, [r2, r5] |
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88 | orr r4, r8, r6, lsl #16 |
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89 | |
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90 | and r6, lr, r12, lsr #15 |
91 | ldrh r6, [r2, r6] |
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92 | and r8, lr, r12, lsr #23 |
93 | ldrh r8, [r2, r8] |
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94 | orr r5, r5, r6, lsl #16 |
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95 | |
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96 | and r6, lr, r7, lsl #1 |
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97 | ldrh r6, [r2, r6] |
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98 | and r12,lr, r7, lsr #7 |
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99 | ldrh r12,[r2, r12] |
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100 | orr r6, r8, r6, lsl #16 |
101 | |
102 | and r8, lr, r7, lsr #15 |
103 | ldrh r8, [r2, r8] |
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104 | |
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105 | subs r3, r3, #1<<24 |
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106 | and r7, lr, r7, lsr #23 |
107 | orr r12,r12,r8, lsl #16 |
108 | |
109 | ldrh r8, [r2, r7] |
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110 | |
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111 | stmia r0!, {r4,r5,r6,r12} |
112 | bpl vcloop_unaligned |
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113 | |
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114 | strh r8, [r0] |
115 | mov r8, #0 |
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116 | |
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117 | tst r3, #0x10000 |
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118 | add r1, r1, #336 @ skip a line and 1 col |
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119 | addne r1, r1, #64 @ skip more for 32col mode |
120 | add r0, r0, #(320+2)*2 |
121 | addne r0, r0, #64*2 |
122 | addeq r3, r3, #(320/8)<<24 |
123 | addne r3, r3, #(256/8)<<24 |
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124 | sub r3, r3, #1 |
125 | tst r3, #0xff |
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126 | bne vcloop_unaligned |
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127 | |
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128 | ldmfd sp!, {r4-r8,lr} |
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129 | bx lr |
130 | |
131 | |