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1 | @ vim:filetype=armasm:\r |
2 | \r |
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3 | @ ARM940 initialization.\r |
4 | @ Based on ogg940 code by Dzz.\r |
5 | @ (c) Copyright 2007, Grazvydas "notaz" Ignotas\r |
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6 | \r |
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7 | .equ mmsp2_regs, (0xc0000000-0x02000000) @ assume we live @ 0x2000000 bank\r |
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8 | .equ shared_ctl, 0x00200000 @ this is where shared_ctl struncture is located\r |
9 | \r |
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10 | \r |
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11 | @ exception table:\r |
12 | .global code940\r |
13 | code940:\r |
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14 | b .b_reset @ reset\r |
15 | b .b_undef @ undefined instructions\r |
16 | b .b_swi @ software interrupt\r |
17 | b .b_pabort @ prefetch abort\r |
18 | b .b_dabort @ data abort\r |
19 | b .b_reserved @ reserved\r |
20 | b .b_irq @ IRQ\r |
21 | b .b_fiq @ FIQ\r |
22 | \r |
23 | @ test\r |
24 | .b_reset:\r |
25 | mov r12, #0\r |
26 | b .Begin\r |
27 | .b_undef:\r |
28 | mov r12, #1\r |
29 | b .Begin\r |
30 | .b_swi:\r |
31 | mov r12, #2\r |
32 | b .Begin\r |
33 | .b_pabort:\r |
34 | mov r12, #3\r |
35 | b .Begin\r |
36 | .b_dabort:\r |
37 | mov r12, #4\r |
38 | b .Begin\r |
39 | .b_reserved:\r |
40 | mov r12, #5\r |
41 | b .Begin\r |
42 | .b_irq:\r |
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43 | mov sp, #0x100000 @ reset stack\r |
44 | sub sp, sp, #4\r |
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45 | mov r0, #shared_ctl @ remember where we were when interrupt happened\r |
46 | add r0, r0, #0x20\r |
47 | str lr, [r0]\r |
48 | mov r0, #shared_ctl @ increment exception counter (for debug)\r |
49 | add r0, r0, #(6*4)\r |
50 | ldr r1, [r0]\r |
51 | add r1, r1, #1\r |
52 | str r1, [r0]\r |
53 | \r |
54 | bl Main940\r |
55 | \r |
56 | @ we should never get here\r |
57 | b .b_reserved\r |
58 | \r |
59 | \r |
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60 | .b_fiq:\r |
61 | mov r12, #7\r |
62 | b .Begin\r |
63 | \r |
64 | .Begin:\r |
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65 | mov sp, #0x100000 @ set the stack top (1M)\r |
66 | sub sp, sp, #4 @ minus 4\r |
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67 | \r |
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68 | @ set up memory region 0 -- the whole 4GB address space\r |
69 | mov r0, #(0x1f<<1)|1 @ region data\r |
70 | mcr p15, 0, r0, c6, c0, 0 @ opcode2 ~ data/instr\r |
71 | mcr p15, 0, r0, c6, c0, 1\r |
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72 | \r |
73 | @ set up region 1 which is the first 2 megabytes.\r |
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74 | mov r0, #(0x14<<1)|1 @ region data\r |
75 | mcr p15, 0, r0, c6, c1, 0\r |
76 | mcr p15, 0, r0, c6, c1, 1\r |
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77 | \r |
78 | @ set up region 2: 64k 0x200000-0x210000\r |
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79 | mov r0, #(0x0f<<1)|1\r |
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80 | orr r0, r0, #0x200000\r |
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81 | mcr p15, 0, r0, c6, c2, 0\r |
82 | mcr p15, 0, r0, c6, c2, 1\r |
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83 | \r |
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84 | @ set up region 3: 64k 0xbe000000-0xbe010000 (hw control registers)\r |
85 | mov r0, #(0x0f<<1)|1\r |
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86 | orr r0, r0, #mmsp2_regs\r |
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87 | mcr p15, 0, r0, c6, c3, 0\r |
88 | mcr p15, 0, r0, c6, c3, 1\r |
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89 | \r |
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90 | @ set up region 4: 16M 0x01000000-0x02000000 (mp3 area)\r |
91 | mov r0, #(0x17<<1)|1\r |
92 | orr r0, r0, #0x01000000\r |
93 | mcr p15, 0, r0, c6, c4, 0\r |
94 | mcr p15, 0, r0, c6, c4, 1\r |
95 | \r |
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96 | @ region 5: 4K 0x00000000-0x00001000 (boot code protection region)\r |
97 | mov r0, #(0x0b<<1)|1\r |
98 | mcr p15, 0, r0, c6, c5, 0\r |
99 | mcr p15, 0, r0, c6, c5, 1\r |
100 | \r |
101 | @ set regions 1, 4 and 5 to be cacheable (so the first 2M and mp3 area will be cacheable)\r |
102 | mov r0, #(1<<1)|(1<<4)|(1<<5)\r |
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103 | mcr p15, 0, r0, c2, c0, 0\r |
104 | mcr p15, 0, r0, c2, c0, 1\r |
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105 | \r |
106 | @ set region 1 to be bufferable too (only data)\r |
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107 | mov r0, #(1<<1)\r |
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108 | mcr p15, 0, r0, c3, c0, 0\r |
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109 | \r |
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110 | @ set access protection\r |
111 | @ data: [no, full, full, full, full, no access] for regions [5 4 3 2 1 0]\r |
112 | mov r0, #(0<<10)|(3<<8)|(3<<6)|(3<<4)|(3<<2)|(0)\r |
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113 | mcr p15, 0, r0, c5, c0, 0\r |
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114 | @ instructions: [full, no access, no, no, full, no]\r |
115 | mov r0, #(0<< 6)|(0<<4)|(3<<2)|(0)\r |
116 | orr r0, r0, #(3<<10)|(0<<8)\r |
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117 | mcr p15, 0, r0, c5, c0, 1\r |
118 | \r |
119 | mrc p15, 0, r0, c1, c0, 0 @ fetch current control reg\r |
120 | orr r0, r0, #1 @ 0x00000001: enable protection unit\r |
121 | orr r0, r0, #4 @ 0x00000004: enable D cache\r |
122 | orr r0, r0, #0x1000 @ 0x00001000: enable I cache\r |
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123 | @ bic r0, r0, #0xC0000000\r |
124 | @ orr r0, r0, #0x40000000 @ 0x40000000: synchronous, faster?\r |
125 | orr r0, r0, #0xC0000000 @ 0xC0000000: async\r |
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126 | mcr p15, 0, r0, c1, c0, 0 @ set control reg\r |
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127 | \r |
128 | @ flush (invalidate) the cache (just in case)\r |
129 | mov r0, #0\r |
130 | mcr p15, 0, r0, c7, c6, 0\r |
131 | \r |
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132 | @ remember which exception vector we came from (increment counter for debug)\r |
133 | mov r0, #shared_ctl\r |
134 | add r0, r0, r12, lsl #2\r |
135 | ldr r1, [r0]\r |
136 | add r1, r1, #1\r |
137 | str r1, [r0]\r |
138 | \r |
139 | @ remember last lr (for debug)\r |
140 | mov r0, #shared_ctl\r |
141 | add r0, r0, #0x20\r |
142 | str lr, [r0]\r |
143 | \r |
144 | @ ready to take first job-interrupt\r |
145 | wait_for_irq:\r |
146 | mrs r0, cpsr\r |
147 | bic r0, r0, #0x80\r |
148 | msr cpsr_c, r0 @ enable interrupts\r |
149 | \r |
150 | mov r0, #0\r |
151 | mcr p15, 0, r0, c7, c0, 4 @ wait for IRQ\r |
152 | @ mcr p15, 0, r0, c15, c8, 2\r |
153 | nop\r |
154 | nop\r |
155 | b .b_reserved\r |
156 | \r |
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157 | \r |
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158 | \r |
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159 | @ next job getter\r |
160 | .global wait_get_job @ int oldjob\r |
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161 | \r |
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162 | wait_get_job:\r |
163 | mov r3, #mmsp2_regs\r |
164 | orr r2, r3, #0x3B00\r |
165 | orr r2, r2, #0x0046 @ DUALPEND940 register\r |
166 | ldrh r12,[r2]\r |
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167 | \r |
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168 | tst r0, r0\r |
169 | beq wgj_no_old\r |
170 | sub r0, r0, #1\r |
171 | mov r1, #1\r |
172 | mov r1, r1, lsl r0\r |
173 | strh r1, [r2] @ clear finished job's pending bit\r |
174 | bic r12,r12,r1\r |
175 | \r |
176 | wgj_no_old:\r |
177 | tst r12,r12\r |
178 | beq wgj_no_jobs\r |
179 | mov r0, #0\r |
180 | wgj_loop:\r |
181 | add r0, r0, #1\r |
182 | movs r12,r12,lsr #1\r |
183 | bxcs lr\r |
184 | b wgj_loop\r |
185 | \r |
186 | wgj_no_jobs:\r |
187 | mvn r0, #0\r |
188 | orr r2, r3, #0x4500\r |
189 | str r0, [r2] @ clear all pending interrupts in irq controller's SRCPND register\r |
190 | orr r2, r2, #0x0010\r |
191 | str r0, [r2] @ clear all pending interrupts in irq controller's INTPND register\r |
192 | b wait_for_irq\r |
193 | \r |
194 | .pool\r |
195 | \r |
196 | \r |
197 | \r |
198 | \r |
199 | @ some asm utils are also defined here:\r |
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200 | .global spend_cycles @ c\r |
201 | \r |
202 | spend_cycles:\r |
203 | mov r0, r0, lsr #2 @ 4 cycles/iteration\r |
204 | sub r0, r0, #2 @ entry/exit/init\r |
205 | .sc_loop:\r |
206 | subs r0, r0, #1\r |
207 | bpl .sc_loop\r |
208 | \r |
209 | bx lr\r |
210 | \r |
211 | \r |
212 | @ clean-flush function from ARM940T technical reference manual\r |
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213 | .global dcache_clean_flush\r |
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214 | \r |
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215 | dcache_clean_flush:\r |
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216 | mov r1, #0 @ init line counter\r |
217 | ccf_outer_loop:\r |
218 | mov r0, #0 @ segment counter\r |
219 | ccf_inner_loop:\r |
220 | orr r2, r1, r0 @ make segment and line address\r |
221 | mcr p15, 0, r2, c7, c14, 2 @ clean and flush that line\r |
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222 | add r0, r0, #0x10 @ incremet segment counter\r |
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223 | cmp r0, #0x40 @ complete all 4 segments?\r |
224 | bne ccf_inner_loop\r |
225 | add r1, r1, #0x04000000 @ increment line counter\r |
226 | cmp r1, #0 @ complete all lines?\r |
227 | bne ccf_outer_loop\r |
228 | bx lr\r |
229 | \r |
230 | \r |
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231 | \r |
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232 | @ clean-only version\r |
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233 | .global dcache_clean\r |
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234 | \r |
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235 | dcache_clean:\r |
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236 | mov r1, #0 @ init line counter\r |
237 | cf_outer_loop:\r |
238 | mov r0, #0 @ segment counter\r |
239 | cf_inner_loop:\r |
240 | orr r2, r1, r0 @ make segment and line address\r |
241 | mcr p15, 0, r2, c7, c10, 2 @ clean that line\r |
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242 | add r0, r0, #0x10 @ incremet segment counter\r |
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243 | cmp r0, #0x40 @ complete all 4 segments?\r |
244 | bne cf_inner_loop\r |
245 | add r1, r1, #0x04000000 @ increment line counter\r |
246 | cmp r1, #0 @ complete all lines?\r |
247 | bne cf_outer_loop\r |
248 | bx lr\r |
249 | \r |
250 | \r |
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251 | @ drain write buffer\r |
252 | .global drain_wb\r |
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253 | \r |
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254 | drain_wb:\r |
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255 | mov r0, #0\r |
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256 | mcr p15, 0, r0, c7, c10, 4\r |
257 | bx lr\r |
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258 | \r |
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259 | \r |
260 | .global set_if_not_changed @ int *val, int oldval, int newval\r |
261 | \r |
262 | set_if_not_changed:\r |
263 | swp r3, r2, [r0]\r |
264 | cmp r1, r3\r |
265 | bxeq lr\r |
266 | strne r3, [r0] @ restore value which was changed there by other core\r |
267 | bx lr\r |
268 | \r |
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269 | \r |
270 | \r |
271 | @ pad the protected region.\r |
272 | .rept 1024\r |
273 | .long 0\r |
274 | .endr\r |
275 | \r |