cc68a136 |
1 | /* cpuctrl for GP2X |
2 | Copyright (C) 2005 Hermes/PS2Reality |
3 | the gamma-routine was provided by theoddbot |
4 | parts (c) Rlyehs Work & (C) 2006 god_at_hell |
5 | |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by |
8 | the Free Software Foundation; either version 2 of the License, or |
9 | (at your option) any later version. |
10 | |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | GNU General Public License for more details. |
15 | |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software |
18 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
19 | |
20 | */ |
21 | |
22 | |
23 | #include <sys/mman.h> |
24 | #include <math.h> |
25 | #include "cpuctrl.h" |
26 | |
27 | |
28 | /* system registers */ |
29 | static struct |
30 | { |
31 | unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,MEMTIMEX0,MEMTIMEX1; |
32 | } |
33 | system_reg; |
34 | |
35 | static unsigned short dispclockdiv; |
36 | |
37 | static volatile unsigned short *MEM_REG; |
38 | |
39 | #define SYS_CLK_FREQ 7372800 |
40 | |
41 | |
42 | void cpuctrl_init(void) |
43 | { |
44 | extern volatile unsigned short *gp2x_memregs; /* from minimal library rlyeh */ |
45 | MEM_REG=&gp2x_memregs[0]; |
46 | system_reg.SYSCSETREG=MEM_REG[0x91c>>1]; |
47 | system_reg.FPLLVSETREG=MEM_REG[0x912>>1]; |
48 | system_reg.SYSCLKENREG=MEM_REG[0x904>>1]; |
49 | system_reg.DUALINT920=MEM_REG[0x3B40>>1]; |
50 | system_reg.DUALINT940=MEM_REG[0x3B42>>1]; |
51 | system_reg.DUALCTRL940=MEM_REG[0x3B48>>1]; |
52 | system_reg.MEMTIMEX0=MEM_REG[0x3802>>1]; |
53 | system_reg.MEMTIMEX1=MEM_REG[0x3804>>1]; |
54 | dispclockdiv=MEM_REG[0x924>>1]; |
55 | } |
56 | |
57 | |
58 | void cpuctrl_deinit(void) |
59 | { |
60 | MEM_REG[0x91c>>1]=system_reg.SYSCSETREG; |
61 | MEM_REG[0x910>>1]=system_reg.FPLLVSETREG; |
62 | MEM_REG[0x3B40>>1]=system_reg.DUALINT920; |
63 | MEM_REG[0x3B42>>1]=system_reg.DUALINT940; |
64 | MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940; |
65 | MEM_REG[0x904>>1]=system_reg.SYSCLKENREG; |
66 | MEM_REG[0x924>>1]=dispclockdiv; |
67 | MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0; |
68 | MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1 /*| 0x9000*/; |
69 | } |
70 | |
71 | |
72 | void set_display_clock_div(unsigned div) |
73 | { |
74 | div=((div & 63) | 64)<<8; |
75 | MEM_REG[0x924>>1]=(MEM_REG[0x924>>1] & ~(255<<8)) | div; |
76 | } |
77 | |
78 | |
79 | void set_FCLK(unsigned MHZ) |
80 | { |
81 | unsigned v; |
82 | unsigned mdiv,pdiv=3,scale=0; |
83 | MHZ*=1000000; |
84 | mdiv=(MHZ*pdiv)/SYS_CLK_FREQ; |
85 | mdiv=((mdiv-8)<<8) & 0xff00; |
86 | pdiv=((pdiv-2)<<2) & 0xfc; |
87 | scale&=3; |
88 | v=mdiv | pdiv | scale; |
89 | MEM_REG[0x910>>1]=v; |
90 | } |
91 | |
92 | |
93 | void set_920_Div(unsigned short div) |
94 | { |
95 | unsigned short v; |
96 | v = MEM_REG[0x91c>>1] & (~0x3); |
97 | MEM_REG[0x91c>>1] = (div & 0x7) | v; |
98 | } |
99 | |
100 | |
101 | void set_DCLK_Div( unsigned short div ) |
102 | { |
103 | unsigned short v; |
104 | v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)) ); |
105 | MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v; |
106 | } |
107 | |
108 | /* |
109 | void Disable_940(void) |
110 | { |
111 | MEM_REG[0x3B42>>1]; |
112 | MEM_REG[0x3B42>>1]=0; |
113 | MEM_REG[0x3B46>>1]=0xffff; |
114 | MEM_REG[0x3B48>>1]|= (1 << 7); |
115 | MEM_REG[0x904>>1]&=0xfffe; |
116 | } |
117 | */ |
118 | |
119 | void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD) |
120 | { |
121 | tRC -= 1; tRAS -= 1; tWR -= 1; tMRD -= 1; tRFC -= 1; tRP -= 1; tRCD -= 1; // ??? |
122 | MEM_REG[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF); |
123 | MEM_REG[0x3804>>1] = /*0x9000 |*/ ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF); |
124 | } |
125 | |
126 | |
127 | /* |
128 | void gp2x_video_wait_vsync(void) |
129 | { |
130 | MEM_REG[0x2846>>1]=(MEM_REG[0x2846>>1] | 0x20) & ~2; |
131 | while(!(MEM_REG[0x2846>>1] & 2)); |
132 | } |
133 | */ |
134 | |
135 | void set_gamma(int g100) |
136 | { |
137 | float gamma = (float) g100 / 100; |
138 | int i; |
139 | //printf ("set gamma = %f\r\n",gamma); |
140 | gamma = 1/gamma; |
141 | |
142 | //enable gamma |
143 | MEM_REG[0x2880>>1]&=~(1<<12); |
144 | |
145 | MEM_REG[0x295C>>1]=0; |
146 | for(i=0; i<256; i++) |
147 | { |
148 | unsigned char g; |
149 | unsigned short s; |
150 | g =(unsigned char)(255.0*pow(i/255.0,gamma)); |
151 | s = (g<<8) | g; |
152 | MEM_REG[0x295E>>1]= s; |
153 | MEM_REG[0x295E>>1]= g; |
154 | } |
155 | } |
156 | |