c5c73e2f |
1 | /* |
2 | * <random_info=mem_map> |
3 | * 00000000-029fffff linux (42MB) |
4 | * 02a00000-02dfffff fb (4MB, 153600B really used) |
5 | * 02e00000-02ffffff sound dma (2MB) |
6 | * 03000000-03ffffff MPEGDEC (?, 16MB) |
7 | * </random_info> |
8 | */ |
ee2a3bdf |
9 | #include <stdio.h> |
10 | #include <stdlib.h> |
11 | #include <string.h> |
12 | #include <math.h> |
13 | #include <sys/types.h> |
14 | #include <sys/stat.h> |
15 | #include <fcntl.h> |
16 | #include <sys/mman.h> |
17 | #include <unistd.h> |
18 | #include <sys/ioctl.h> |
19 | #include <linux/fb.h> |
20 | |
21 | #include "soc.h" |
22 | #include "plat_gp2x.h" |
23 | #include "../common/emu.h" |
f4750ee0 |
24 | #include "../common/plat.h" |
ee2a3bdf |
25 | #include "../common/arm_utils.h" |
26 | #include "pollux_set.h" |
27 | |
28 | static volatile unsigned short *memregs; |
f4750ee0 |
29 | static volatile unsigned int *memregl; |
ee2a3bdf |
30 | static int memdev = -1; |
61753a67 |
31 | static int battdev = -1; |
ee2a3bdf |
32 | |
33 | extern void *gp2x_screens[4]; |
34 | |
35 | #define fb_buf_count 4 |
36 | static unsigned int fb_paddr[fb_buf_count]; |
37 | static int fb_work_buf; |
38 | static int fbdev = -1; |
39 | |
2275c676 |
40 | static char cpuclk_was_changed = 0; |
41 | static unsigned short memtimex_old[2]; |
42 | static unsigned int pllsetreg0; |
cc41eb4f |
43 | static int last_pal_setting = 0; |
2275c676 |
44 | |
ee2a3bdf |
45 | |
7b436906 |
46 | /* misc */ |
47 | static void pollux_set_fromenv(const char *env_var) |
48 | { |
49 | const char *set_string; |
50 | set_string = getenv(env_var); |
51 | if (set_string) |
52 | pollux_set(memregs, set_string); |
53 | else |
54 | printf("env var %s not defined.\n", env_var); |
55 | } |
56 | |
ee2a3bdf |
57 | /* video stuff */ |
58 | static void pollux_video_flip(int buf_count) |
59 | { |
60 | memregl[0x406C>>2] = fb_paddr[fb_work_buf]; |
61 | memregl[0x4058>>2] |= 0x10; |
62 | fb_work_buf++; |
63 | if (fb_work_buf >= buf_count) |
64 | fb_work_buf = 0; |
65 | g_screen_ptr = gp2x_screens[fb_work_buf]; |
66 | } |
67 | |
68 | static void gp2x_video_flip_(void) |
69 | { |
70 | pollux_video_flip(fb_buf_count); |
71 | } |
72 | |
73 | /* doulblebuffered flip */ |
74 | static void gp2x_video_flip2_(void) |
75 | { |
76 | pollux_video_flip(2); |
77 | } |
78 | |
79 | static void gp2x_video_changemode_ll_(int bpp) |
80 | { |
cc41eb4f |
81 | static int prev_bpp = 0; |
ee2a3bdf |
82 | int code = 0, bytes = 2; |
cc41eb4f |
83 | int rot_cmd[2] = { 0, 0 }; |
ee2a3bdf |
84 | unsigned int r; |
7b436906 |
85 | char buff[32]; |
cc41eb4f |
86 | int ret; |
87 | |
88 | if (bpp == prev_bpp) |
89 | return; |
90 | prev_bpp = bpp; |
91 | |
92 | printf("changemode: %dbpp rot=%d\n", abs(bpp), bpp < 0); |
93 | |
94 | /* negative bpp means rotated mode */ |
95 | rot_cmd[0] = (bpp < 0) ? 6 : 5; |
96 | ret = ioctl(fbdev, _IOW('D', 90, int[2]), rot_cmd); |
97 | if (ret < 0) |
98 | perror("rot ioctl failed"); |
99 | memregl[0x4004>>2] = (bpp < 0) ? 0x013f00ef : 0x00ef013f; |
100 | memregl[0x4000>>2] |= 1 << 3; |
101 | |
102 | /* the above ioctl resets LCD timings, so set them here */ |
7b436906 |
103 | snprintf(buff, sizeof(buff), "POLLUX_LCD_TIMINGS_%s", last_pal_setting ? "PAL" : "NTSC"); |
104 | pollux_set_fromenv(buff); |
cc41eb4f |
105 | |
106 | switch (abs(bpp)) |
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107 | { |
108 | case 8: |
109 | code = 0x443a; |
110 | bytes = 1; |
111 | break; |
112 | |
113 | case 15: |
114 | case 16: |
115 | code = 0x4432; |
116 | bytes = 2; |
117 | break; |
118 | |
119 | default: |
cc41eb4f |
120 | printf("unhandled bpp request: %d\n", abs(bpp)); |
ee2a3bdf |
121 | return; |
122 | } |
123 | |
124 | memregl[0x405c>>2] = bytes; |
cc41eb4f |
125 | memregl[0x4060>>2] = bytes * (bpp < 0 ? 240 : 320); |
ee2a3bdf |
126 | |
127 | r = memregl[0x4058>>2]; |
128 | r = (r & 0xffff) | (code << 16) | 0x10; |
129 | memregl[0x4058>>2] = r; |
130 | } |
131 | |
132 | static void gp2x_video_setpalette_(int *pal, int len) |
133 | { |
134 | /* pollux palette is 16bpp only.. */ |
135 | int i; |
136 | for (i = 0; i < len; i++) |
137 | { |
138 | int c = pal[i]; |
139 | c = ((c >> 8) & 0xf800) | ((c >> 5) & 0x07c0) | ((c >> 3) & 0x001f); |
140 | memregl[0x4070>>2] = (i << 24) | c; |
141 | } |
142 | } |
143 | |
144 | static void gp2x_video_RGB_setscaling_(int ln_offs, int W, int H) |
145 | { |
146 | /* maybe a job for 3d hardware? */ |
147 | } |
148 | |
149 | static void gp2x_video_wait_vsync_(void) |
150 | { |
151 | while (!(memregl[0x308c>>2] & (1 << 10))); |
152 | spend_cycles(128); |
153 | memregl[0x308c>>2] |= 1 << 10; |
154 | } |
155 | |
156 | /* CPU clock */ |
157 | static void gp2x_set_cpuclk_(unsigned int mhz) |
158 | { |
159 | char buff[24]; |
160 | snprintf(buff, sizeof(buff), "cpuclk=%u", mhz); |
161 | pollux_set(memregs, buff); |
2275c676 |
162 | |
163 | cpuclk_was_changed = 1; |
ee2a3bdf |
164 | } |
165 | |
ee2a3bdf |
166 | /* RAM timings */ |
ee2a3bdf |
167 | static void set_ram_timings_(void) |
168 | { |
169 | pollux_set_fromenv("POLLUX_RAM_TIMINGS"); |
170 | } |
171 | |
172 | static void unset_ram_timings_(void) |
173 | { |
174 | int i; |
175 | |
2275c676 |
176 | memregs[0x14802>>1] = memtimex_old[0]; |
177 | memregs[0x14804>>1] = memtimex_old[1] | 0x8000; |
ee2a3bdf |
178 | |
179 | for (i = 0; i < 0x100000; i++) |
180 | if (!(memregs[0x14804>>1] & 0x8000)) |
181 | break; |
182 | |
183 | printf("RAM timings reset to startup values.\n"); |
184 | } |
185 | |
186 | /* LCD refresh */ |
187 | static void set_lcd_custom_rate_(int is_pal) |
188 | { |
7b436906 |
189 | /* just remember PAL/NTSC. We always set timings in _changemode_ll() */ |
cc41eb4f |
190 | last_pal_setting = is_pal; |
ee2a3bdf |
191 | } |
192 | |
193 | static void unset_lcd_custom_rate_(void) |
194 | { |
195 | } |
196 | |
197 | static void set_lcd_gamma_(int g100, int A_SNs_curve) |
198 | { |
199 | /* hm, the LCD possibly can do it (but not POLLUX) */ |
200 | } |
42171343 |
201 | |
61753a67 |
202 | static int gp2x_read_battery_(void) |
203 | { |
204 | unsigned short magic_val = 0; |
205 | |
206 | if (battdev < 0) |
207 | return -1; |
208 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
209 | return -1; |
210 | switch (magic_val) { |
211 | default: |
212 | case 1: return 100; |
213 | case 2: return 66; |
214 | case 3: return 40; |
215 | case 4: return 0; |
216 | } |
217 | } |
218 | |
b24e0f6c |
219 | #define TIMER_BASE3 0x1980 |
220 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
221 | |
222 | unsigned int gp2x_get_ticks_us_(void) |
223 | { |
224 | TIMER_REG(0x08) = 0x4b; /* run timer, latch value */ |
225 | return TIMER_REG(0); |
226 | } |
227 | |
228 | unsigned int gp2x_get_ticks_ms_(void) |
229 | { |
3328d53b |
230 | /* approximate /= 1000 */ |
b24e0f6c |
231 | unsigned long long v64; |
3328d53b |
232 | v64 = (unsigned long long)gp2x_get_ticks_us_() * 4294968; |
233 | return v64 >> 32; |
b24e0f6c |
234 | } |
235 | |
236 | static void timer_cleanup(void) |
237 | { |
238 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
239 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
240 | TIMER_REG(0x00) = 0; /* clear counter */ |
241 | TIMER_REG(0x40) = 0; /* clocks off */ |
242 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
243 | } |
244 | |
f4750ee0 |
245 | /* note: both PLLs are programmed the same way, |
246 | * the databook incorrectly states that PLL1 differs */ |
247 | static int decode_pll(unsigned int reg) |
248 | { |
249 | long long v; |
250 | int p, m, s; |
251 | |
252 | p = (reg >> 18) & 0x3f; |
253 | m = (reg >> 8) & 0x3ff; |
254 | s = reg & 0xff; |
255 | |
256 | if (p == 0) |
257 | p = 1; |
258 | |
259 | v = 27000000; // master clock |
260 | v = v * m / (p << s); |
261 | return v; |
262 | } |
263 | |
42171343 |
264 | void pollux_init(void) |
265 | { |
ee2a3bdf |
266 | struct fb_fix_screeninfo fbfix; |
f4750ee0 |
267 | int i, ret, rate; |
ee2a3bdf |
268 | |
269 | memdev = open("/dev/mem", O_RDWR); |
270 | if (memdev == -1) { |
271 | perror("open(/dev/mem) failed"); |
272 | exit(1); |
273 | } |
274 | |
275 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000); |
276 | if (memregs == MAP_FAILED) { |
277 | perror("mmap(memregs) failed"); |
278 | exit(1); |
279 | } |
280 | memregl = (volatile void *)memregs; |
281 | |
282 | fbdev = open("/dev/fb0", O_RDWR); |
283 | if (fbdev < 0) { |
284 | perror("can't open fbdev"); |
285 | exit(1); |
286 | } |
287 | |
288 | ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix); |
289 | if (ret == -1) { |
290 | perror("ioctl(fbdev) failed"); |
291 | exit(1); |
292 | } |
293 | |
294 | printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start); |
295 | fb_paddr[0] = fbfix.smem_start; |
296 | |
297 | gp2x_screens[0] = mmap(0, 320*240*2*fb_buf_count, PROT_READ|PROT_WRITE, |
298 | MAP_SHARED, memdev, fb_paddr[0]); |
299 | if (gp2x_screens[0] == MAP_FAILED) |
300 | { |
301 | perror("mmap(gp2x_screens) failed"); |
302 | exit(1); |
303 | } |
304 | memset(gp2x_screens[0], 0, 320*240*2*fb_buf_count); |
305 | |
306 | printf(" %p -> %08x\n", gp2x_screens[0], fb_paddr[0]); |
307 | for (i = 1; i < fb_buf_count; i++) |
308 | { |
309 | fb_paddr[i] = fb_paddr[i-1] + 320*240*2; |
310 | gp2x_screens[i] = (char *)gp2x_screens[i-1] + 320*240*2; |
311 | printf(" %p -> %08x\n", gp2x_screens[i], fb_paddr[i]); |
312 | } |
313 | fb_work_buf = 0; |
314 | g_screen_ptr = gp2x_screens[0]; |
315 | |
61753a67 |
316 | battdev = open("/dev/pollux_batt", O_RDONLY); |
317 | if (battdev < 0) |
318 | perror("Warning: could't open pollux_batt"); |
319 | |
f4750ee0 |
320 | /* find what PLL1 runs at, for the timer */ |
321 | rate = decode_pll(memregl[0xf008>>2]); |
322 | printf("PLL1 @ %dHz\n", rate); |
323 | rate /= 1000000; |
324 | |
b24e0f6c |
325 | /* setup timer */ |
f4750ee0 |
326 | if (1 <= rate && rate <= 256) { |
327 | if (TIMER_REG(0x08) & 8) { |
328 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
329 | timer_cleanup(); |
330 | } |
331 | |
332 | TIMER_REG(0x44) = ((rate - 1) << 4) | 2; /* using PLL1, divide by it's rate */ |
333 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
334 | TIMER_REG(0x08) = 0x6b; /* run timer, clear irq, latch value */ |
335 | |
336 | gp2x_get_ticks_ms = gp2x_get_ticks_ms_; |
337 | gp2x_get_ticks_us = gp2x_get_ticks_us_; |
338 | } |
339 | else { |
340 | fprintf(stderr, "warning: could not make use of timer\n"); |
b24e0f6c |
341 | |
f4750ee0 |
342 | // those functions are actually not good at all on Wiz kernel |
343 | gp2x_get_ticks_ms = plat_get_ticks_ms_good; |
344 | gp2x_get_ticks_us = plat_get_ticks_us_good; |
345 | } |
b24e0f6c |
346 | |
61753a67 |
347 | pllsetreg0 = memregl[0xf004>>2]; |
2275c676 |
348 | memtimex_old[0] = memregs[0x14802>>1]; |
349 | memtimex_old[1] = memregs[0x14804>>1]; |
ee2a3bdf |
350 | |
351 | gp2x_video_flip = gp2x_video_flip_; |
352 | gp2x_video_flip2 = gp2x_video_flip2_; |
353 | gp2x_video_changemode_ll = gp2x_video_changemode_ll_; |
354 | gp2x_video_setpalette = gp2x_video_setpalette_; |
355 | gp2x_video_RGB_setscaling = gp2x_video_RGB_setscaling_; |
356 | gp2x_video_wait_vsync = gp2x_video_wait_vsync_; |
357 | |
f4750ee0 |
358 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
359 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
360 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
361 | gp2x_set_cpuclk = gp2x_set_cpuclk_; |
362 | else { |
363 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
364 | memregl[0xf000>>2]); |
365 | gp2x_set_cpuclk = NULL; |
366 | } |
ee2a3bdf |
367 | |
368 | set_lcd_custom_rate = set_lcd_custom_rate_; |
369 | unset_lcd_custom_rate = unset_lcd_custom_rate_; |
370 | set_lcd_gamma = set_lcd_gamma_; |
371 | |
372 | set_ram_timings = set_ram_timings_; |
373 | unset_ram_timings = unset_ram_timings_; |
61753a67 |
374 | gp2x_read_battery = gp2x_read_battery_; |
42171343 |
375 | } |
376 | |
377 | void pollux_finish(void) |
378 | { |
ee2a3bdf |
379 | /* switch to default fb mem, turn portrait off */ |
380 | memregl[0x406C>>2] = fb_paddr[0]; |
381 | memregl[0x4058>>2] |= 0x10; |
ee2a3bdf |
382 | close(fbdev); |
383 | |
2275c676 |
384 | gp2x_video_changemode_ll_(16); |
385 | unset_ram_timings_(); |
386 | if (cpuclk_was_changed) { |
387 | memregl[0xf004>>2] = pllsetreg0; |
388 | memregl[0xf07c>>2] |= 0x8000; |
389 | } |
45285368 |
390 | timer_cleanup(); |
2275c676 |
391 | |
ee2a3bdf |
392 | munmap((void *)memregs, 0x20000); |
393 | close(memdev); |
61753a67 |
394 | if (battdev >= 0) |
395 | close(battdev); |
42171343 |
396 | } |
397 | |