notaz.gp2x.de / pcsx_rearmed.git / blame
| Commit | Line | Data |
|---|---|---|
| ef79bbde P |
1 | /***************************************************************************\r |
| 2 | registers.h - description\r | |
| 3 | -------------------\r | |
| 4 | begin : Wed May 15 2002\r | |
| 5 | copyright : (C) 2002 by Pete Bernert\r | |
| 6 | email : BlackDove@addcom.de\r | |
| 7 | ***************************************************************************/\r | |
| 8 | /***************************************************************************\r | |
| 9 | * *\r | |
| 10 | * This program is free software; you can redistribute it and/or modify *\r | |
| 11 | * it under the terms of the GNU General Public License as published by *\r | |
| 12 | * the Free Software Foundation; either version 2 of the License, or *\r | |
| 13 | * (at your option) any later version. See also the license.txt file for *\r | |
| 14 | * additional informations. *\r | |
| 15 | * *\r | |
| 16 | ***************************************************************************/\r | |
| 17 | \r | |
| 18 | #define H_SPUReverbAddr 0x0da2\r | |
| 19 | #define H_SPUirqAddr 0x0da4\r | |
| 20 | #define H_SPUaddr 0x0da6\r | |
| 21 | #define H_SPUdata 0x0da8\r | |
| 22 | #define H_SPUctrl 0x0daa\r | |
| 23 | #define H_SPUstat 0x0dae\r | |
| 24 | #define H_SPUmvolL 0x0d80\r | |
| 25 | #define H_SPUmvolR 0x0d82\r | |
| 26 | #define H_SPUrvolL 0x0d84\r | |
| 27 | #define H_SPUrvolR 0x0d86\r | |
| 28 | #define H_SPUon1 0x0d88\r | |
| 29 | #define H_SPUon2 0x0d8a\r | |
| 30 | #define H_SPUoff1 0x0d8c\r | |
| 31 | #define H_SPUoff2 0x0d8e\r | |
| 32 | #define H_FMod1 0x0d90\r | |
| 33 | #define H_FMod2 0x0d92\r | |
| 34 | #define H_Noise1 0x0d94\r | |
| 35 | #define H_Noise2 0x0d96\r | |
| 36 | #define H_RVBon1 0x0d98\r | |
| 37 | #define H_RVBon2 0x0d9a\r | |
| 38 | #define H_SPUMute1 0x0d9c\r | |
| 39 | #define H_SPUMute2 0x0d9e\r | |
| 40 | #define H_CDLeft 0x0db0\r | |
| 41 | #define H_CDRight 0x0db2\r | |
| 42 | #define H_ExtLeft 0x0db4\r | |
| 43 | #define H_ExtRight 0x0db6\r | |
| 44 | #define H_Reverb 0x0dc0\r | |
| 45 | #define H_SPUPitch0 0x0c04\r | |
| 46 | #define H_SPUPitch1 0x0c14\r | |
| 47 | #define H_SPUPitch2 0x0c24\r | |
| 48 | #define H_SPUPitch3 0x0c34\r | |
| 49 | #define H_SPUPitch4 0x0c44\r | |
| 50 | #define H_SPUPitch5 0x0c54\r | |
| 51 | #define H_SPUPitch6 0x0c64\r | |
| 52 | #define H_SPUPitch7 0x0c74\r | |
| 53 | #define H_SPUPitch8 0x0c84\r | |
| 54 | #define H_SPUPitch9 0x0c94\r | |
| 55 | #define H_SPUPitch10 0x0ca4\r | |
| 56 | #define H_SPUPitch11 0x0cb4\r | |
| 57 | #define H_SPUPitch12 0x0cc4\r | |
| 58 | #define H_SPUPitch13 0x0cd4\r | |
| 59 | #define H_SPUPitch14 0x0ce4\r | |
| 60 | #define H_SPUPitch15 0x0cf4\r | |
| 61 | #define H_SPUPitch16 0x0d04\r | |
| 62 | #define H_SPUPitch17 0x0d14\r | |
| 63 | #define H_SPUPitch18 0x0d24\r | |
| 64 | #define H_SPUPitch19 0x0d34\r | |
| 65 | #define H_SPUPitch20 0x0d44\r | |
| 66 | #define H_SPUPitch21 0x0d54\r | |
| 67 | #define H_SPUPitch22 0x0d64\r | |
| 68 | #define H_SPUPitch23 0x0d74\r | |
| 69 | \r | |
| 70 | #define H_SPUStartAdr0 0x0c06\r | |
| 71 | #define H_SPUStartAdr1 0x0c16\r | |
| 72 | #define H_SPUStartAdr2 0x0c26\r | |
| 73 | #define H_SPUStartAdr3 0x0c36\r | |
| 74 | #define H_SPUStartAdr4 0x0c46\r | |
| 75 | #define H_SPUStartAdr5 0x0c56\r | |
| 76 | #define H_SPUStartAdr6 0x0c66\r | |
| 77 | #define H_SPUStartAdr7 0x0c76\r | |
| 78 | #define H_SPUStartAdr8 0x0c86\r | |
| 79 | #define H_SPUStartAdr9 0x0c96\r | |
| 80 | #define H_SPUStartAdr10 0x0ca6\r | |
| 81 | #define H_SPUStartAdr11 0x0cb6\r | |
| 82 | #define H_SPUStartAdr12 0x0cc6\r | |
| 83 | #define H_SPUStartAdr13 0x0cd6\r | |
| 84 | #define H_SPUStartAdr14 0x0ce6\r | |
| 85 | #define H_SPUStartAdr15 0x0cf6\r | |
| 86 | #define H_SPUStartAdr16 0x0d06\r | |
| 87 | #define H_SPUStartAdr17 0x0d16\r | |
| 88 | #define H_SPUStartAdr18 0x0d26\r | |
| 89 | #define H_SPUStartAdr19 0x0d36\r | |
| 90 | #define H_SPUStartAdr20 0x0d46\r | |
| 91 | #define H_SPUStartAdr21 0x0d56\r | |
| 92 | #define H_SPUStartAdr22 0x0d66\r | |
| 93 | #define H_SPUStartAdr23 0x0d76\r | |
| 94 | \r | |
| 95 | #define H_SPULoopAdr0 0x0c0e\r | |
| 96 | #define H_SPULoopAdr1 0x0c1e\r | |
| 97 | #define H_SPULoopAdr2 0x0c2e\r | |
| 98 | #define H_SPULoopAdr3 0x0c3e\r | |
| 99 | #define H_SPULoopAdr4 0x0c4e\r | |
| 100 | #define H_SPULoopAdr5 0x0c5e\r | |
| 101 | #define H_SPULoopAdr6 0x0c6e\r | |
| 102 | #define H_SPULoopAdr7 0x0c7e\r | |
| 103 | #define H_SPULoopAdr8 0x0c8e\r | |
| 104 | #define H_SPULoopAdr9 0x0c9e\r | |
| 105 | #define H_SPULoopAdr10 0x0cae\r | |
| 106 | #define H_SPULoopAdr11 0x0cbe\r | |
| 107 | #define H_SPULoopAdr12 0x0cce\r | |
| 108 | #define H_SPULoopAdr13 0x0cde\r | |
| 109 | #define H_SPULoopAdr14 0x0cee\r | |
| 110 | #define H_SPULoopAdr15 0x0cfe\r | |
| 111 | #define H_SPULoopAdr16 0x0d0e\r | |
| 112 | #define H_SPULoopAdr17 0x0d1e\r | |
| 113 | #define H_SPULoopAdr18 0x0d2e\r | |
| 114 | #define H_SPULoopAdr19 0x0d3e\r | |
| 115 | #define H_SPULoopAdr20 0x0d4e\r | |
| 116 | #define H_SPULoopAdr21 0x0d5e\r | |
| 117 | #define H_SPULoopAdr22 0x0d6e\r | |
| 118 | #define H_SPULoopAdr23 0x0d7e\r | |
| 119 | \r | |
| 120 | #define H_SPU_ADSRLevel0 0x0c08\r | |
| 121 | #define H_SPU_ADSRLevel1 0x0c18\r | |
| 122 | #define H_SPU_ADSRLevel2 0x0c28\r | |
| 123 | #define H_SPU_ADSRLevel3 0x0c38\r | |
| 124 | #define H_SPU_ADSRLevel4 0x0c48\r | |
| 125 | #define H_SPU_ADSRLevel5 0x0c58\r | |
| 126 | #define H_SPU_ADSRLevel6 0x0c68\r | |
| 127 | #define H_SPU_ADSRLevel7 0x0c78\r | |
| 128 | #define H_SPU_ADSRLevel8 0x0c88\r | |
| 129 | #define H_SPU_ADSRLevel9 0x0c98\r | |
| 130 | #define H_SPU_ADSRLevel10 0x0ca8\r | |
| 131 | #define H_SPU_ADSRLevel11 0x0cb8\r | |
| 132 | #define H_SPU_ADSRLevel12 0x0cc8\r | |
| 133 | #define H_SPU_ADSRLevel13 0x0cd8\r | |
| 134 | #define H_SPU_ADSRLevel14 0x0ce8\r | |
| 135 | #define H_SPU_ADSRLevel15 0x0cf8\r | |
| 136 | #define H_SPU_ADSRLevel16 0x0d08\r | |
| 137 | #define H_SPU_ADSRLevel17 0x0d18\r | |
| 138 | #define H_SPU_ADSRLevel18 0x0d28\r | |
| 139 | #define H_SPU_ADSRLevel19 0x0d38\r | |
| 140 | #define H_SPU_ADSRLevel20 0x0d48\r | |
| 141 | #define H_SPU_ADSRLevel21 0x0d58\r | |
| 142 | #define H_SPU_ADSRLevel22 0x0d68\r | |
| 143 | #define H_SPU_ADSRLevel23 0x0d78\r | |
| 144 | \r | |
| 3fc2a4c2 | 145 | #define CTRL_IRQ 0x40\r |
| 146 | #define CTRL_REVERB 0x80\r | |
| 147 | #define CTRL_NOISE 0x3f00\r | |
| 148 | #define CTRL_MUTE 0x4000\r | |
| 149 | #define CTRL_ON 0x8000\r | |
| 150 | \r | |
| 151 | #define STAT_IRQ 0x40\r | |
| 152 | \r | |
| 7e44d49d | 153 | ///////////////////////////////////////////////////////////\r |
| 154 | \r | |
| 650adfd2 | 155 | void CALLBACK SPUwriteRegister(unsigned long reg, unsigned short val, unsigned int cycles);\r |
| 7e44d49d | 156 | \r |