| 1 | #include "../pico_int.h" |
| 2 | #include "../sound/ym2612.h" |
| 3 | |
| 4 | struct Pico32x Pico32x; |
| 5 | SH2 sh2s[2]; |
| 6 | |
| 7 | static void sh2_irq_cb(int id, int level) |
| 8 | { |
| 9 | // diagnostic for now |
| 10 | elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id)); |
| 11 | } |
| 12 | |
| 13 | void p32x_update_irls(void) |
| 14 | { |
| 15 | int irqs, mlvl = 0, slvl = 0; |
| 16 | |
| 17 | // msh2 |
| 18 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
| 19 | while ((irqs >>= 1)) |
| 20 | mlvl++; |
| 21 | mlvl *= 2; |
| 22 | |
| 23 | // ssh2 |
| 24 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
| 25 | while ((irqs >>= 1)) |
| 26 | slvl++; |
| 27 | slvl *= 2; |
| 28 | |
| 29 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
| 30 | sh2_irl_irq(&msh2, mlvl); |
| 31 | sh2_irl_irq(&ssh2, slvl); |
| 32 | mlvl = mlvl ? 1 : 0; |
| 33 | slvl = slvl ? 1 : 0; |
| 34 | p32x_poll_event(mlvl | (slvl << 1), 0); |
| 35 | } |
| 36 | |
| 37 | void Pico32xStartup(void) |
| 38 | { |
| 39 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
| 40 | |
| 41 | PicoAHW |= PAHW_32X; |
| 42 | sh2_init(&msh2, 0); |
| 43 | msh2.irq_callback = sh2_irq_cb; |
| 44 | sh2_init(&ssh2, 1); |
| 45 | ssh2.irq_callback = sh2_irq_cb; |
| 46 | |
| 47 | PicoMemSetup32x(); |
| 48 | |
| 49 | if (!Pico.m.pal) |
| 50 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
| 51 | |
| 52 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
| 53 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
| 54 | |
| 55 | emu_32x_startup(); |
| 56 | } |
| 57 | |
| 58 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
| 59 | void p32x_reset_sh2s(void) |
| 60 | { |
| 61 | elprintf(EL_32X, "sh2 reset"); |
| 62 | |
| 63 | sh2_reset(&msh2); |
| 64 | sh2_reset(&ssh2); |
| 65 | |
| 66 | // if we don't have BIOS set, perform it's work here. |
| 67 | // MSH2 |
| 68 | if (p32x_bios_m == NULL) { |
| 69 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
| 70 | unsigned int vbr; |
| 71 | |
| 72 | // initial data |
| 73 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
| 74 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
| 75 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
| 76 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
| 77 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
| 78 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
| 79 | idl_src, idl_dst, idl_size); |
| 80 | } |
| 81 | else |
| 82 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
| 83 | |
| 84 | // GBR/VBR |
| 85 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
| 86 | sh2_set_gbr(0, 0x20004000); |
| 87 | sh2_set_vbr(0, vbr); |
| 88 | |
| 89 | // checksum and M_OK |
| 90 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
| 91 | // program will set M_OK |
| 92 | } |
| 93 | |
| 94 | // SSH2 |
| 95 | if (p32x_bios_s == NULL) { |
| 96 | unsigned int vbr; |
| 97 | |
| 98 | // GBR/VBR |
| 99 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
| 100 | sh2_set_gbr(1, 0x20004000); |
| 101 | sh2_set_vbr(1, vbr); |
| 102 | // program will set S_OK |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | void Pico32xInit(void) |
| 107 | { |
| 108 | } |
| 109 | |
| 110 | void PicoPower32x(void) |
| 111 | { |
| 112 | memset(&Pico32x, 0, sizeof(Pico32x)); |
| 113 | |
| 114 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
| 115 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
| 116 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
| 117 | } |
| 118 | |
| 119 | void PicoUnload32x(void) |
| 120 | { |
| 121 | if (Pico32xMem != NULL) |
| 122 | free(Pico32xMem); |
| 123 | Pico32xMem = NULL; |
| 124 | |
| 125 | PicoAHW &= ~PAHW_32X; |
| 126 | } |
| 127 | |
| 128 | void PicoReset32x(void) |
| 129 | { |
| 130 | if (PicoAHW & PAHW_32X) { |
| 131 | Pico32x.sh2irqs |= P32XI_VRES; |
| 132 | p32x_update_irls(); |
| 133 | p32x_poll_event(3, 0); |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | static void p32x_start_blank(void) |
| 138 | { |
| 139 | // enter vblank |
| 140 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
| 141 | |
| 142 | // FB swap waits until vblank |
| 143 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
| 144 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
| 145 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
| 146 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
| 147 | } |
| 148 | |
| 149 | Pico32x.sh2irqs |= P32XI_VINT; |
| 150 | p32x_update_irls(); |
| 151 | p32x_poll_event(3, 1); |
| 152 | } |
| 153 | |
| 154 | static __inline void run_m68k(int cyc) |
| 155 | { |
| 156 | #if defined(EMU_C68K) |
| 157 | PicoCpuCM68k.cycles = cyc; |
| 158 | CycloneRun(&PicoCpuCM68k); |
| 159 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
| 160 | #elif defined(EMU_M68K) |
| 161 | SekCycleCnt += m68k_execute(cyc); |
| 162 | #elif defined(EMU_F68K) |
| 163 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
| 164 | #endif |
| 165 | } |
| 166 | |
| 167 | // ~1463.8, but due to cache misses and slow mem |
| 168 | // it's much lower than that |
| 169 | //#define SH2_LINE_CYCLES 735 |
| 170 | #define CYCLES_M68K2SH2(x) ((x) * 6 / 4) |
| 171 | |
| 172 | #define PICO_32X |
| 173 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
| 174 | { \ |
| 175 | int slice; \ |
| 176 | SekCycleAim += m68k_cycles; \ |
| 177 | while (SekCycleCnt < SekCycleAim) { \ |
| 178 | slice = SekCycleCnt; \ |
| 179 | run_m68k(SekCycleAim - SekCycleCnt); \ |
| 180 | if (!(Pico32x.regs[0] & P32XS_nRES)) \ |
| 181 | continue; /* SH2s reseting */ \ |
| 182 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
| 183 | if (SekCycleCnt < SekCycleAim) \ |
| 184 | elprintf(EL_32X, "slice %d", slice); \ |
| 185 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
| 186 | sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \ |
| 187 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
| 188 | sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \ |
| 189 | } \ |
| 190 | } |
| 191 | |
| 192 | #define STEP_68K 24 |
| 193 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
| 194 | { \ |
| 195 | int i; \ |
| 196 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
| 197 | run_m68k(STEP_68K); \ |
| 198 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
| 199 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
| 200 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
| 201 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
| 202 | } \ |
| 203 | /* last step */ \ |
| 204 | i = (m68k_cycles) - i; \ |
| 205 | run_m68k(i); \ |
| 206 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
| 207 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
| 208 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
| 209 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
| 210 | } |
| 211 | |
| 212 | #define CPUS_RUN CPUS_RUN_SIMPLE |
| 213 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
| 214 | |
| 215 | #include "../pico_cmn.c" |
| 216 | |
| 217 | void PicoFrame32x(void) |
| 218 | { |
| 219 | pwm_frame_smp_cnt = 0; |
| 220 | |
| 221 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
| 222 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
| 223 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
| 224 | |
| 225 | p32x_poll_event(3, 1); |
| 226 | |
| 227 | PicoFrameStart(); |
| 228 | PicoFrameHints(); |
| 229 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
| 230 | } |
| 231 | |