| 1 | /* |
| 2 | * PicoDrive |
| 3 | * (C) notaz, 2009,2010,2013 |
| 4 | * |
| 5 | * This work is licensed under the terms of MAME license. |
| 6 | * See COPYING file in the top-level directory. |
| 7 | */ |
| 8 | #include "../pico_int.h" |
| 9 | #include "../sound/ym2612.h" |
| 10 | #include "../../cpu/sh2/compiler.h" |
| 11 | |
| 12 | struct Pico32x Pico32x; |
| 13 | SH2 sh2s[2]; |
| 14 | |
| 15 | #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP) |
| 16 | |
| 17 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
| 18 | { |
| 19 | if (sh2->pending_irl > sh2->pending_int_irq) { |
| 20 | elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x", |
| 21 | level, sh2_pc(sh2)); |
| 22 | return 64 + sh2->pending_irl / 2; |
| 23 | } else { |
| 24 | elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x", |
| 25 | level, sh2->pending_int_vector, sh2_pc(sh2)); |
| 26 | sh2->pending_int_irq = 0; // auto-clear |
| 27 | sh2->pending_level = sh2->pending_irl; |
| 28 | return sh2->pending_int_vector; |
| 29 | } |
| 30 | } |
| 31 | |
| 32 | // MUST specify active_sh2 when called from sh2 memhandlers |
| 33 | void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) |
| 34 | { |
| 35 | int irqs, mlvl = 0, slvl = 0; |
| 36 | int mrun, srun; |
| 37 | |
| 38 | if (active_sh2 != NULL) |
| 39 | m68k_cycles = sh2_cycles_done_m68k(active_sh2); |
| 40 | |
| 41 | // msh2 |
| 42 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0]; |
| 43 | while ((irqs >>= 1)) |
| 44 | mlvl++; |
| 45 | mlvl *= 2; |
| 46 | |
| 47 | // ssh2 |
| 48 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1]; |
| 49 | while ((irqs >>= 1)) |
| 50 | slvl++; |
| 51 | slvl *= 2; |
| 52 | |
| 53 | mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2); |
| 54 | if (mrun) { |
| 55 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles); |
| 56 | if (active_sh2 == &msh2) |
| 57 | sh2_end_run(active_sh2, 1); |
| 58 | } |
| 59 | |
| 60 | srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2); |
| 61 | if (srun) { |
| 62 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles); |
| 63 | if (active_sh2 == &ssh2) |
| 64 | sh2_end_run(active_sh2, 1); |
| 65 | } |
| 66 | |
| 67 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
| 68 | } |
| 69 | |
| 70 | // the mask register is inconsistent, CMD is supposed to be a mask, |
| 71 | // while others are actually irq trigger enables? |
| 72 | // TODO: test on hw.. |
| 73 | void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask) |
| 74 | { |
| 75 | Pico32x.sh2irqs |= mask & P32XI_VRES; |
| 76 | Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3); |
| 77 | Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3); |
| 78 | |
| 79 | p32x_update_irls(sh2, m68k_cycles); |
| 80 | } |
| 81 | |
| 82 | void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles) |
| 83 | { |
| 84 | if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1)) |
| 85 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
| 86 | else |
| 87 | Pico32x.sh2irqi[0] &= ~P32XI_CMD; |
| 88 | |
| 89 | if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2)) |
| 90 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
| 91 | else |
| 92 | Pico32x.sh2irqi[1] &= ~P32XI_CMD; |
| 93 | |
| 94 | p32x_update_irls(sh2, m68k_cycles); |
| 95 | } |
| 96 | |
| 97 | void Pico32xStartup(void) |
| 98 | { |
| 99 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
| 100 | |
| 101 | // TODO: OOM handling |
| 102 | PicoAHW |= PAHW_32X; |
| 103 | sh2_init(&msh2, 0, &ssh2); |
| 104 | msh2.irq_callback = sh2_irq_cb; |
| 105 | sh2_init(&ssh2, 1, &msh2); |
| 106 | ssh2.irq_callback = sh2_irq_cb; |
| 107 | |
| 108 | PicoMemSetup32x(); |
| 109 | p32x_pwm_ctl_changed(); |
| 110 | p32x_timers_recalc(); |
| 111 | |
| 112 | if (!Pico.m.pal) |
| 113 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
| 114 | |
| 115 | rendstatus_old = -1; |
| 116 | |
| 117 | emu_32x_startup(); |
| 118 | } |
| 119 | |
| 120 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
| 121 | void p32x_reset_sh2s(void) |
| 122 | { |
| 123 | elprintf(EL_32X, "sh2 reset"); |
| 124 | |
| 125 | sh2_reset(&msh2); |
| 126 | sh2_reset(&ssh2); |
| 127 | sh2_peripheral_reset(&msh2); |
| 128 | sh2_peripheral_reset(&ssh2); |
| 129 | |
| 130 | // if we don't have BIOS set, perform it's work here. |
| 131 | // MSH2 |
| 132 | if (p32x_bios_m == NULL) { |
| 133 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
| 134 | unsigned int vbr; |
| 135 | |
| 136 | // initial data |
| 137 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
| 138 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
| 139 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
| 140 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
| 141 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
| 142 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
| 143 | idl_src, idl_dst, idl_size); |
| 144 | } |
| 145 | else |
| 146 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
| 147 | |
| 148 | // GBR/VBR |
| 149 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
| 150 | sh2_set_gbr(0, 0x20004000); |
| 151 | sh2_set_vbr(0, vbr); |
| 152 | |
| 153 | // checksum and M_OK |
| 154 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
| 155 | // program will set M_OK |
| 156 | } |
| 157 | |
| 158 | // SSH2 |
| 159 | if (p32x_bios_s == NULL) { |
| 160 | unsigned int vbr; |
| 161 | |
| 162 | // GBR/VBR |
| 163 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
| 164 | sh2_set_gbr(1, 0x20004000); |
| 165 | sh2_set_vbr(1, vbr); |
| 166 | // program will set S_OK |
| 167 | } |
| 168 | |
| 169 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone(); |
| 170 | } |
| 171 | |
| 172 | void Pico32xInit(void) |
| 173 | { |
| 174 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
| 175 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
| 176 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
| 177 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
| 178 | } |
| 179 | |
| 180 | void PicoPower32x(void) |
| 181 | { |
| 182 | memset(&Pico32x, 0, sizeof(Pico32x)); |
| 183 | |
| 184 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
| 185 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN; |
| 186 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
| 187 | } |
| 188 | |
| 189 | void PicoUnload32x(void) |
| 190 | { |
| 191 | if (Pico32xMem != NULL) |
| 192 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
| 193 | Pico32xMem = NULL; |
| 194 | sh2_finish(&msh2); |
| 195 | sh2_finish(&ssh2); |
| 196 | |
| 197 | PicoAHW &= ~PAHW_32X; |
| 198 | } |
| 199 | |
| 200 | void PicoReset32x(void) |
| 201 | { |
| 202 | if (PicoAHW & PAHW_32X) { |
| 203 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone(); |
| 204 | p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES); |
| 205 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); |
| 206 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); |
| 207 | p32x_pwm_ctl_changed(); |
| 208 | p32x_timers_recalc(); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | static void p32x_start_blank(void) |
| 213 | { |
| 214 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
| 215 | int offs, lines; |
| 216 | |
| 217 | pprof_start(draw); |
| 218 | |
| 219 | offs = 8; lines = 224; |
| 220 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
| 221 | offs = 0; |
| 222 | lines = 240; |
| 223 | } |
| 224 | |
| 225 | // XXX: no proper handling of 32col mode.. |
| 226 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
| 227 | (Pico.video.reg[12] & 1) && // 40col mode |
| 228 | (PicoDrawMask & PDRAW_32X_ON)) |
| 229 | { |
| 230 | int md_bg = Pico.video.reg[7] & 0x3f; |
| 231 | |
| 232 | // we draw full layer (not line-by-line) |
| 233 | PicoDraw32xLayer(offs, lines, md_bg); |
| 234 | } |
| 235 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
| 236 | PicoDraw32xLayerMdOnly(offs, lines); |
| 237 | |
| 238 | pprof_end(draw); |
| 239 | } |
| 240 | |
| 241 | // enter vblank |
| 242 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
| 243 | |
| 244 | // FB swap waits until vblank |
| 245 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
| 246 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
| 247 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
| 248 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
| 249 | } |
| 250 | |
| 251 | p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT); |
| 252 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
| 253 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
| 254 | } |
| 255 | |
| 256 | void p32x_schedule_hint(SH2 *sh2, int m68k_cycles) |
| 257 | { |
| 258 | // rather rough, 32x hint is useless in practice |
| 259 | int after; |
| 260 | |
| 261 | if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4)) |
| 262 | return; // nobody cares |
| 263 | // note: when Pico.m.scanline is 224, SH2s might |
| 264 | // still be at scanline 93 (or so) |
| 265 | if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224) |
| 266 | return; |
| 267 | |
| 268 | after = (Pico32x.sh2_regs[4 / 2] + 1) * 488; |
| 269 | if (sh2 != NULL) |
| 270 | p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after); |
| 271 | else |
| 272 | p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after); |
| 273 | } |
| 274 | |
| 275 | /* events */ |
| 276 | static void fillend_event(unsigned int now) |
| 277 | { |
| 278 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
| 279 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now); |
| 280 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now); |
| 281 | } |
| 282 | |
| 283 | static void hint_event(unsigned int now) |
| 284 | { |
| 285 | p32x_trigger_irq(NULL, now, P32XI_HINT); |
| 286 | p32x_schedule_hint(NULL, now); |
| 287 | } |
| 288 | |
| 289 | typedef void (event_cb)(unsigned int now); |
| 290 | |
| 291 | /* times are in m68k (7.6MHz) cycles */ |
| 292 | unsigned int p32x_event_times[P32X_EVENT_COUNT]; |
| 293 | static unsigned int event_time_next; |
| 294 | static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = { |
| 295 | [P32X_EVENT_PWM] = p32x_pwm_irq_event, |
| 296 | [P32X_EVENT_FILLEND] = fillend_event, |
| 297 | [P32X_EVENT_HINT] = hint_event, |
| 298 | }; |
| 299 | |
| 300 | // schedule event at some time 'after', in m68k clocks |
| 301 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after) |
| 302 | { |
| 303 | unsigned int when; |
| 304 | |
| 305 | when = (now + after) | 1; |
| 306 | |
| 307 | elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when); |
| 308 | p32x_event_times[event] = when; |
| 309 | |
| 310 | if (event_time_next == 0 || CYCLES_GT(event_time_next, when)) |
| 311 | event_time_next = when; |
| 312 | } |
| 313 | |
| 314 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after) |
| 315 | { |
| 316 | unsigned int now = sh2_cycles_done_m68k(sh2); |
| 317 | int left_to_next; |
| 318 | |
| 319 | p32x_event_schedule(now, event, after); |
| 320 | |
| 321 | left_to_next = (event_time_next - now) * 3; |
| 322 | sh2_end_run(sh2, left_to_next); |
| 323 | } |
| 324 | |
| 325 | static void p32x_run_events(unsigned int until) |
| 326 | { |
| 327 | int oldest, oldest_diff, time; |
| 328 | int i, diff; |
| 329 | |
| 330 | while (1) { |
| 331 | oldest = -1, oldest_diff = 0x7fffffff; |
| 332 | |
| 333 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
| 334 | if (p32x_event_times[i]) { |
| 335 | diff = p32x_event_times[i] - until; |
| 336 | if (diff < oldest_diff) { |
| 337 | oldest_diff = diff; |
| 338 | oldest = i; |
| 339 | } |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | if (oldest_diff <= 0) { |
| 344 | time = p32x_event_times[oldest]; |
| 345 | p32x_event_times[oldest] = 0; |
| 346 | elprintf(EL_32X, "32x: run event #%d %u", oldest, time); |
| 347 | p32x_event_cbs[oldest](time); |
| 348 | } |
| 349 | else if (oldest_diff < 0x7fffffff) { |
| 350 | event_time_next = p32x_event_times[oldest]; |
| 351 | break; |
| 352 | } |
| 353 | else { |
| 354 | event_time_next = 0; |
| 355 | break; |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | if (oldest != -1) |
| 360 | elprintf(EL_32X, "32x: next event #%d at %u", |
| 361 | oldest, event_time_next); |
| 362 | } |
| 363 | |
| 364 | static inline void run_sh2(SH2 *sh2, int m68k_cycles) |
| 365 | { |
| 366 | int cycles, done; |
| 367 | |
| 368 | pevt_log_sh2_o(sh2, EVT_RUN_START); |
| 369 | sh2->state |= SH2_STATE_RUN; |
| 370 | cycles = C_M68K_TO_SH2(*sh2, m68k_cycles); |
| 371 | elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x", |
| 372 | sh2->m68krcycles_done, cycles, sh2->pc); |
| 373 | |
| 374 | done = sh2_execute(sh2, cycles); |
| 375 | |
| 376 | sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done); |
| 377 | sh2->state &= ~SH2_STATE_RUN; |
| 378 | pevt_log_sh2_o(sh2, EVT_RUN_END); |
| 379 | elprintf_sh2(sh2, EL_32X, "-run %u %d", |
| 380 | sh2->m68krcycles_done, done); |
| 381 | } |
| 382 | |
| 383 | // sync other sh2 to this one |
| 384 | // note: recursive call |
| 385 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target) |
| 386 | { |
| 387 | SH2 *osh2 = sh2->other_sh2; |
| 388 | int left_to_event; |
| 389 | int m68k_cycles; |
| 390 | |
| 391 | if (osh2->state & SH2_STATE_RUN) |
| 392 | return; |
| 393 | |
| 394 | m68k_cycles = m68k_target - osh2->m68krcycles_done; |
| 395 | if (m68k_cycles < 200) |
| 396 | return; |
| 397 | |
| 398 | if (osh2->state & SH2_IDLE_STATES) { |
| 399 | osh2->m68krcycles_done = m68k_target; |
| 400 | return; |
| 401 | } |
| 402 | |
| 403 | elprintf_sh2(osh2, EL_32X, "sync to %u %d", |
| 404 | m68k_target, m68k_cycles); |
| 405 | |
| 406 | run_sh2(osh2, m68k_cycles); |
| 407 | |
| 408 | // there might be new event to schedule current sh2 to |
| 409 | if (event_time_next) { |
| 410 | left_to_event = event_time_next - m68k_target; |
| 411 | left_to_event *= 3; |
| 412 | if (sh2_cycles_left(sh2) > left_to_event) { |
| 413 | if (left_to_event < 1) |
| 414 | left_to_event = 1; |
| 415 | sh2_end_run(sh2, left_to_event); |
| 416 | } |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | #define sync_sh2s_normal p32x_sync_sh2s |
| 421 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
| 422 | |
| 423 | /* most timing is in 68k clock */ |
| 424 | void sync_sh2s_normal(unsigned int m68k_target) |
| 425 | { |
| 426 | unsigned int now, target, timer_cycles; |
| 427 | int cycles; |
| 428 | |
| 429 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
| 430 | |
| 431 | if (!(Pico32x.regs[0] & P32XS_nRES)) { |
| 432 | msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target; |
| 433 | return; // rare |
| 434 | } |
| 435 | |
| 436 | now = msh2.m68krcycles_done; |
| 437 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
| 438 | now = ssh2.m68krcycles_done; |
| 439 | timer_cycles = now; |
| 440 | |
| 441 | while (CYCLES_GT(m68k_target, now)) |
| 442 | { |
| 443 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
| 444 | p32x_run_events(now); |
| 445 | |
| 446 | target = m68k_target; |
| 447 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
| 448 | target = event_time_next; |
| 449 | |
| 450 | while (CYCLES_GT(target, now)) |
| 451 | { |
| 452 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
| 453 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
| 454 | m68k_target - now, Pico32x.emu_flags); |
| 455 | |
| 456 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
| 457 | cycles = target - ssh2.m68krcycles_done; |
| 458 | if (cycles > 0) { |
| 459 | run_sh2(&ssh2, cycles); |
| 460 | |
| 461 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
| 462 | target = event_time_next; |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | if (!(msh2.state & SH2_IDLE_STATES)) { |
| 467 | cycles = target - msh2.m68krcycles_done; |
| 468 | if (cycles > 0) { |
| 469 | run_sh2(&msh2, cycles); |
| 470 | |
| 471 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
| 472 | target = event_time_next; |
| 473 | } |
| 474 | } |
| 475 | |
| 476 | now = target; |
| 477 | if (!(msh2.state & SH2_IDLE_STATES)) { |
| 478 | if (CYCLES_GT(now, msh2.m68krcycles_done)) |
| 479 | now = msh2.m68krcycles_done; |
| 480 | } |
| 481 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
| 482 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
| 483 | now = ssh2.m68krcycles_done; |
| 484 | } |
| 485 | } |
| 486 | |
| 487 | p32x_timers_do(now - timer_cycles); |
| 488 | timer_cycles = now; |
| 489 | } |
| 490 | |
| 491 | // advance idle CPUs |
| 492 | if (msh2.state & SH2_IDLE_STATES) { |
| 493 | if (CYCLES_GT(m68k_target, msh2.m68krcycles_done)) |
| 494 | msh2.m68krcycles_done = m68k_target; |
| 495 | } |
| 496 | if (ssh2.state & SH2_IDLE_STATES) { |
| 497 | if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done)) |
| 498 | ssh2.m68krcycles_done = m68k_target; |
| 499 | } |
| 500 | } |
| 501 | |
| 502 | #define STEP_68K 24 |
| 503 | |
| 504 | void sync_sh2s_lockstep(unsigned int m68k_target) |
| 505 | { |
| 506 | unsigned int mcycles; |
| 507 | |
| 508 | mcycles = msh2.m68krcycles_done; |
| 509 | if (ssh2.m68krcycles_done < mcycles) |
| 510 | mcycles = ssh2.m68krcycles_done; |
| 511 | |
| 512 | while (mcycles < m68k_target) { |
| 513 | mcycles += STEP_68K; |
| 514 | sync_sh2s_normal(mcycles); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | #define CPUS_RUN(m68k_cycles) do { \ |
| 519 | SekRunM68k(m68k_cycles); \ |
| 520 | if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \ |
| 521 | && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \ |
| 522 | PicoSyncZ80(SekCyclesDone()); \ |
| 523 | if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \ |
| 524 | p32x_sync_sh2s(SekCyclesDone()); \ |
| 525 | } while (0) |
| 526 | |
| 527 | #define PICO_32X |
| 528 | #include "../pico_cmn.c" |
| 529 | |
| 530 | void PicoFrame32x(void) |
| 531 | { |
| 532 | Pico.m.scanline = 0; |
| 533 | |
| 534 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
| 535 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
| 536 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
| 537 | |
| 538 | if (!(Pico32x.sh2_regs[0] & 0x80)) |
| 539 | p32x_schedule_hint(NULL, SekCyclesDone()); |
| 540 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
| 541 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
| 542 | |
| 543 | PicoFrameStart(); |
| 544 | PicoFrameHints(); |
| 545 | sh2_drc_frame(); |
| 546 | |
| 547 | elprintf(EL_32X, "poll: %02x %02x %02x", |
| 548 | Pico32x.emu_flags & 3, msh2.state, ssh2.state); |
| 549 | } |
| 550 | |
| 551 | // calculate multipliers against 68k clock (7670442) |
| 552 | // normally * 3, but effectively slower due to high latencies everywhere |
| 553 | // however using something lower breaks MK2 animations |
| 554 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
| 555 | { |
| 556 | float m68k_clk = (float)(OSC_NTSC / 7); |
| 557 | if (msh2_hz > 0) { |
| 558 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
| 559 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
| 560 | } |
| 561 | if (ssh2_hz > 0) { |
| 562 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
| 563 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | void Pico32xStateLoaded(int is_early) |
| 568 | { |
| 569 | if (is_early) { |
| 570 | Pico32xMemStateLoaded(); |
| 571 | return; |
| 572 | } |
| 573 | |
| 574 | sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone(); |
| 575 | p32x_update_irls(NULL, SekCyclesDone()); |
| 576 | p32x_pwm_state_loaded(); |
| 577 | p32x_run_events(SekCyclesDone()); |
| 578 | } |
| 579 | |
| 580 | // vim:shiftwidth=2:ts=2:expandtab |