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1// Pico Library - Header File\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006 notaz, All rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9\r
10#include <stdio.h>\r
11#include <stdlib.h>\r
12#include <string.h>\r
13#include "Pico.h"\r
14\r
15\r
16// to select core, define EMU_C68K, EMU_M68K or EMU_A68K in your makefile\r
17\r
18#ifdef __cplusplus\r
19extern "C" {\r
20#endif\r
21\r
22\r
23// ----------------------- 68000 CPU -----------------------\r
24#ifdef EMU_C68K\r
25#include "../cpu/Cyclone/Cyclone.h"\r
26extern struct Cyclone PicoCpu;\r
27#define SekCyclesLeft PicoCpu.cycles // cycles left for this run\r
28#define SekSetCyclesLeft(c) PicoCpu.cycles=c\r
29#define SekPc (PicoCpu.pc-PicoCpu.membase)\r
30#endif\r
31\r
32#ifdef EMU_A68K\r
33void __cdecl M68000_RUN();\r
34// The format of the data in a68k.asm (at the _M68000_regs location)\r
35struct A68KContext\r
36{\r
37 unsigned int d[8],a[8];\r
38 unsigned int isp,srh,ccr,xc,pc,irq,sr;\r
39 int (*IrqCallback) (int nIrq);\r
40 unsigned int ppc;\r
41 void *pResetCallback;\r
42 unsigned int sfc,dfc,usp,vbr;\r
43 unsigned int AsmBank,CpuVersion;\r
44};\r
45struct A68KContext M68000_regs;\r
46extern int m68k_ICount;\r
47#define SekCyclesLeft m68k_ICount\r
48#define SekSetCyclesLeft(c) m68k_ICount=c\r
49#define SekPc M68000_regs.pc\r
50#endif\r
51\r
52#ifdef EMU_M68K\r
53#include "../cpu/musashi/m68kcpu.h"\r
54extern m68ki_cpu_core PicoM68kCPU; // MD's CPU\r
55extern m68ki_cpu_core PicoS68kCPU; // Mega CD's CPU\r
56#ifndef SekCyclesLeft\r
57#define SekCyclesLeft m68k_cycles_remaining()\r
58#define SekSetCyclesLeft(c) SET_CYCLES(c)\r
59#define SekPc m68k_get_reg(&PicoM68kCPU, M68K_REG_PC)\r
60#define SekPcS68k m68k_get_reg(&PicoS68kCPU, M68K_REG_PC)\r
61#endif\r
62#endif\r
63\r
64extern int SekCycleCnt; // cycles done in this frame\r
65extern int SekCycleAim; // cycle aim\r
66extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
67\r
68#define SekCyclesReset() {SekCycleCntT+=SekCycleCnt;SekCycleCnt=SekCycleAim=0;}\r
69#define SekCyclesBurn(c) SekCycleCnt+=c\r
70#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
71#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
72\r
73#define SekEndRun(after) { \\r
74 SekCycleCnt -= SekCyclesLeft - after; \\r
75 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
76 SekSetCyclesLeft(after); \\r
77}\r
78\r
79extern int SekCycleCntS68k;\r
80extern int SekCycleAimS68k;\r
81\r
82#define SekCyclesResetS68k() {SekCycleCntS68k=SekCycleAimS68k=0;}\r
83\r
84// does not work as expected\r
85//extern int z80ExtraCycles; // extra z80 cycles, used when z80 is [en|dis]abled\r
86\r
87extern int PicoMCD;\r
88\r
89// ---------------------------------------------------------\r
90\r
91// main oscillator clock which controls timing\r
92#define OSC_NTSC 53693100\r
93#define OSC_PAL 53203424 // not accurate\r
94\r
95struct PicoVideo\r
96{\r
97 unsigned char reg[0x20];\r
98 unsigned int command; // 32-bit Command\r
99 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
100 unsigned char type; // Command type (v/c/vsram read/write)\r
101 unsigned short addr; // Read/Write address\r
102 int status; // Status bits\r
103 unsigned char pending_ints; // pending interrupts: ??VH????\r
104 unsigned char pad[0x13];\r
105};\r
106\r
107struct PicoMisc\r
108{\r
109 unsigned char rotate;\r
110 unsigned char z80Run;\r
111 unsigned char padTHPhase[2]; // phase of gamepad TH switches\r
112 short scanline; // 0 to 261||311; -1 in fast mode\r
113 char dirtyPal; // Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
114 unsigned char hardware; // Hardware value for country\r
115 unsigned char pal; // 1=PAL 0=NTSC\r
116 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM?\r
117 unsigned short z80_bank68k;\r
118 unsigned short z80_lastaddr; // this is for Z80 faking\r
119 unsigned char z80_fakeval;\r
120 unsigned char pad0;\r
121 unsigned char padDelay[2]; // gamepad phase time outs, so we count a delay\r
122 unsigned short sram_addr; // EEPROM address register\r
123 unsigned char sram_cycle; // EEPROM SRAM cycle number\r
124 unsigned char sram_slave; // EEPROM slave word for X24C02 and better SRAMs\r
125 unsigned char prot_bytes[2]; // simple protection fakeing\r
126 unsigned short dma_bytes; //\r
127 unsigned char pad[2];\r
128 unsigned int frame_count; // mainly for movies\r
129};\r
130\r
131// some assembly stuff depend on these, do not touch!\r
132struct Pico\r
133{\r
134 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
135 unsigned short vram[0x8000]; // 0x10000\r
136 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
137 unsigned char ioports[0x10];\r
138 unsigned int pad[0x3c]; // unused\r
139 unsigned short cram[0x40]; // 0x22100\r
140 unsigned short vsram[0x40]; // 0x22180\r
141\r
142 unsigned char *rom; // 0x22200\r
143 unsigned int romsize; // 0x22204\r
144\r
145 struct PicoMisc m;\r
146 struct PicoVideo video;\r
147};\r
148\r
149// sram\r
150struct PicoSRAM\r
151{\r
152 unsigned char *data; // actual data\r
153 unsigned int start; // start address in 68k address space\r
154 unsigned int end;\r
155 unsigned char resize; // 1=SRAM size changed and needs to be reallocated on PicoReset\r
156 unsigned char reg_back; // copy of Pico.m.sram_reg to set after reset\r
157 unsigned char changed;\r
158 unsigned char pad;\r
159};\r
160\r
161// MCD\r
162#include "cd/cd_sys.h"\r
163#include "cd/LC89510.h"\r
164\r
165struct mcd_misc\r
166{\r
167 unsigned short hint_vector;\r
168 unsigned char busreq;\r
169 unsigned char pad0;\r
170\r
171};\r
172\r
173typedef struct\r
174{\r
175 unsigned char bios[0x20000];\r
176 union {\r
177 unsigned char prg_ram[0x80000];\r
178 unsigned char prg_ram_b[4][0x20000];\r
179 };\r
180 unsigned char word_ram[0x40000];\r
181 unsigned char s68k_regs[0x200];\r
182 CDD cdd;\r
183 CDC cdc;\r
184 _scd scd;\r
185 struct mcd_misc m;\r
186} mcd_state;\r
187\r
188#define Pico_mcd ((mcd_state *)Pico.rom)\r
189\r
190\r
191// Draw.c\r
192int PicoLine(int scan);\r
193void PicoFrameStart();\r
194\r
195// Draw2.c\r
196void PicoFrameFull();\r
197\r
198// Memory.c\r
199int PicoInitPc(unsigned int pc);\r
200unsigned int CPU_CALL PicoRead32(unsigned int a);\r
201int PicoMemInit();\r
202void PicoMemReset();\r
203void PicoDasm(int start,int len);\r
204unsigned char z80_read(unsigned short a);\r
205unsigned short z80_read16(unsigned short a);\r
206void z80_write(unsigned char data, unsigned short a);\r
207void z80_write16(unsigned short data, unsigned short a);\r
208\r
209// cd/Memory.c\r
210unsigned char PicoReadCD8 (unsigned int a);\r
211unsigned short PicoReadCD16(unsigned int a);\r
212unsigned int PicoReadCD32(unsigned int a);\r
213void PicoWriteCD8 (unsigned int a, unsigned char d);\r
214void PicoWriteCD16(unsigned int a, unsigned short d);\r
215void PicoWriteCD32(unsigned int a, unsigned int d);\r
216\r
217// Pico.c\r
218extern struct Pico Pico;\r
219extern struct PicoSRAM SRam;\r
220extern int emustatus;\r
221int CheckDMA(void);\r
222\r
223// cd/Pico.c\r
224int PicoInitMCD(void);\r
225void PicoExitMCD(void);\r
226int PicoResetMCD(int hard);\r
227\r
228// Sek.c\r
229int SekInit(void);\r
230int SekReset(void);\r
231int SekInterrupt(int irq);\r
232void SekState(unsigned char *data);\r
233\r
234// cd/Sek.c\r
235int SekInitS68k(void);\r
236int SekResetS68k(void);\r
237int SekInterruptS68k(int irq);\r
238\r
239// VideoPort.c\r
240void PicoVideoWrite(unsigned int a,unsigned short d);\r
241unsigned int PicoVideoRead(unsigned int a);\r
242\r
243// Misc.c\r
244void SRAMWriteEEPROM(unsigned int d);\r
245unsigned int SRAMReadEEPROM();\r
246void SRAMUpdPending(unsigned int a, unsigned int d);\r
247\r
248\r
249#ifdef __cplusplus\r
250} // End of extern "C"\r
251#endif\r