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hint-less mode updated for SVP, state load callback, etc
[picodrive.git] / Pico / carthw / svp / ssp16.c
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1// basic, incomplete SSP160x (SSP1601?) interpreter
2// with SVP memory controller emu
3
4// (c) Copyright 2008, Grazvydas "notaz" Ignotas
5// Free for non-commercial use.
6
7// For commercial use, separate licencing terms must be obtained.
8
9
10//#define USE_DEBUGGER
11/* detect ops with unimplemented/invalid fields.
12 * Useful for homebrew or if a new VR revision pops up. */
13//#define DO_CHECKS
14
15#include "../../PicoInt.h"
16
17/*
18 * Register info
19 *
20 * 0. "-"
21 * size: 16
22 * desc: Constant register with all bits set (0xffff).
23 *
24 * 1. "X"
25 * size: 16
26 * desc: Generic register. When set, updates P (P = X * Y * 2)
27 *
28 * 2. "Y"
29 * size: 16
30 * desc: Generic register. When set, updates P (P = X * Y * 2)
31 *
32 * 3. "A"
33 * size: 32
34 * desc: Accumulator.
35 *
36 * 4. "ST"
37 * size: 16
38 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
39 * fedc ba98 7654 3210
40 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
41 * modulo-increment and modulo-decrement. The value shows which
42 * power of 2 to use, i.e. 4 means modulo by 16.
43 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
44 * 43 - RB (?)
45 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
46 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
47 * datasheet says these (5,6) bits correspond to hardware pins.
48 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
49 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
50 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
51 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
52 * a - GPI_0 Interrupt 0 enable/status?
53 * b - GPI_1 Interrupt 1 enable/status?
54 * c - L L flag. Carry?
55 * d - Z Zero flag.
56 * e - OV Overflow flag.
57 * f - N Negative flag.
58 * seen directly changing code sequences:
59 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
60 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
61 * ld ST, A ld ST, A ori 3
62 * ld ST, A
63 *
64 * 5. "STACK"
65 * size: 16
66 * desc: hw stack of 6 levels (according to datasheet)
67 *
68 * 6. "PC"
69 * size: 16
70 * desc: Program counter.
71 *
72 * 7. "P"
73 * size: 32
74 * desc: multiply result register. P = X * Y * 2
75 * probably affected by MACS bit in ST.
76 *
77 * 8. "PM0" (PM from PMAR name from Tasco's docs)
78 * size: 16?
79 * desc: Programmable Memory access register.
80 * On reset, or when one (both?) GP0 bits are clear,
81 * acts as status for XST, mapped at 015004 at 68k side:
82 * bit0: ssp has written something to XST (cleared when 015004 is read)
83 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
84 *
85 * 9. "PM1"
86 * size: 16?
87 * desc: Programmable Memory access register.
88 * This reg. is only used as PMAR.
89 *
90 * 10. "PM2"
91 * size: 16?
92 * desc: Programmable Memory access register.
93 * This reg. is only used as PMAR.
94 *
95 * 11. "XST"
96 * size: 16?
97 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
98 * Can be programmed as PMAR? (only seen in test mode code)
99 * Affects PM0 when written to?
100 *
101 * 12. "PM4"
102 * size: 16?
103 * desc: Programmable Memory access register.
104 * This reg. is only used as PMAR. The most used PMAR by VR.
105 *
106 * 13. (unused by VR)
107 *
108 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
109 * size: 32?
110 * desc: Programmable Memory access Control. Set using 2 16bit writes,
111 * first address, then mode word. After setting PMAC, PMAR sould
112 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
113 * reading and writing respectively.
114 * Reading the register also shifts it's state (from "waiting for
115 * address" to "waiting for mode" and back). Reads always return
116 * address related to last PMx register accressed.
117 * (note: addresses do not wrap).
118 *
119 * 15. "AL"
120 * size: 16
121 * desc: Accumulator Low. 16 least significant bits of accumulator.
122 * (normally reading acc (ld X, A) you get 16 most significant bits).
123 *
124 *
125 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
126 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
127 * which work similar to * and ** operators in C, only they use different memory banks and
128 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
129 * program memory at address read from (rX), and increments value in (rX).
130 *
131 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
132 * 3 modifiers can be applied (optional):
133 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
134 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
135 * +!: post-increment, unaffected by RPL (probably).
136 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
137 * ar probably invalid.
138 *
139 * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do).
140 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
141 * Samsung's old DSP page claims that).
142 * 1 of these 4 modifiers must be used (short form direct addressing?):
143 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
144 * |01: RAMx[1]
145 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
146 * |11: RAMx[3]
147 *
148 *
149 * Instruction notes
150 *
151 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
152 *
153 * mld (rj), (ri) [, b]
154 * operation: A = 0; P = (rj) * (ri)
155 * notes: based on IIR_4B.SC sample. flags? what is b???
156 *
157 * mpya (rj), (ri) [, b]
158 * name: multiply and add?
159 * operation: A += P; P = (rj) * (ri)
160 *
161 * mpys (rj), (ri), b
162 * name: multiply and subtract?
163 * notes: not used by VR code.
164 *
165 * mod cond, op
166 * mod cond, shr does arithmetic shift
167 *
168 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
169 *
170 * memory map:
171 * 000000 - 1fffff ROM, accessable by both
172 * 200000 - 2fffff unused?
173 * 300000 - 31ffff DRAM, both
174 * 320000 - 38ffff unused?
175 * 390000 - 3907ff IRAM. can only be accessed by ssp?
176 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
177 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
178 *
179 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
180 * 30fe06 - also sync related.
181 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR.
182 *
183 * Assumptions and limitations in this code
184 * only Z and N status flags are emulated (others unused by VR)
185 * so all condition checks except N and Z are ignored (not used by VR)
186 * modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR)
187 * loop repeat mode when (ri) is destination is ignored
188 * ops not used by VR are not implemented
189 */
190
191#include "../../PicoInt.h"
192
193#define u32 unsigned int
194
195// 0
196#define rX ssp->gr[SSP_X].h
197#define rY ssp->gr[SSP_Y].h
198#define rA ssp->gr[SSP_A].h
199#define rST ssp->gr[SSP_ST].h // 4
200#define rSTACK ssp->gr[SSP_STACK].h
201#define rPC ssp->gr[SSP_PC].h
202#define rP ssp->gr[SSP_P]
203#define rPM0 ssp->gr[SSP_PM0].h // 8
204#define rPM1 ssp->gr[SSP_PM1].h
205#define rPM2 ssp->gr[SSP_PM2].h
206#define rXST ssp->gr[SSP_XST].h
207#define rPM4 ssp->gr[SSP_PM4].h // 12
208// 13
209#define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
210#define rAL ssp->gr[SSP_A].l
211
212#define rA32 ssp->gr[SSP_A].v
213#define rIJ ssp->r
214
215#define IJind (((op>>6)&4)|(op&3))
216
217#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
218#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
219#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
220
221#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
222#define REG_WRITE(r,d) { \
223 int r1 = r; \
224 if (r1 >= 4) write_handlers[r1](d); \
225 else if (r1 > 0) ssp->gr[r1].h = d; \
226}
227
228// flags
229#define SSP_FLAG_L (1<<0xc)
230#define SSP_FLAG_Z (1<<0xd)
231#define SSP_FLAG_V (1<<0xe)
232#define SSP_FLAG_N (1<<0xf)
233
234// update ZN according to 32bit ACC.
235#define UPD_ACC_ZN \
236 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
237 if (!rA32) rST |= SSP_FLAG_Z; \
238 else rST |= (rA32>>16)&SSP_FLAG_N;
239
240// it seems SVP code never checks for L and OV, so we leave them out.
241// rST |= (t>>4)&SSP_FLAG_L;
242#define UPD_LZVN \
243 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
244 if (!rA32) rST |= SSP_FLAG_Z; \
245 else rST |= (rA32>>16)&SSP_FLAG_N;
246
247// standard cond processing.
248// again, only Z and N is checked, as VR doesn't seem to use any other conds.
249#define COND_CHECK \
250 switch (op&0xf0) { \
251 case 0x00: cond = 1; break; /* always true */ \
252 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
253 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
254 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
255 }
256
257// ops with accumulator.
258// how is low word really affected by these?
259// nearly sure 'ld A' doesn't affect flags
260#define OP_LDA(x) \
261 ssp->gr[SSP_A].h = x
262
263#define OP_LDA32(x) \
264 rA32 = x
265
266#define OP_SUBA(x) { \
267 rA32 -= (x) << 16; \
268 UPD_LZVN \
269}
270
271#define OP_SUBA32(x) { \
272 rA32 -= (x); \
273 UPD_LZVN \
274}
275
276#define OP_CMPA(x) { \
277 u32 t = rA32 - ((x) << 16); \
278 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
279 if (!t) rST |= SSP_FLAG_Z; \
280 else rST |= (t>>16)&SSP_FLAG_N; \
281}
282
283#define OP_CMPA32(x) { \
284 u32 t = rA32 - (x); \
285 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
286 if (!t) rST |= SSP_FLAG_Z; \
287 else rST |= (t>>16)&SSP_FLAG_N; \
288}
289
290#define OP_ADDA(x) { \
291 rA32 += (x) << 16; \
292 UPD_LZVN \
293}
294
295#define OP_ADDA32(x) { \
296 rA32 += (x); \
297 UPD_LZVN \
298}
299
300#define OP_ANDA(x) \
301 rA32 &= (x) << 16; \
302 UPD_ACC_ZN
303
304#define OP_ANDA32(x) \
305 rA32 &= (x); \
306 UPD_ACC_ZN
307
308#define OP_ORA(x) \
309 rA32 |= (x) << 16; \
310 UPD_ACC_ZN
311
312#define OP_ORA32(x) \
313 rA32 |= (x); \
314 UPD_ACC_ZN
315
316#define OP_EORA(x) \
317 rA32 ^= (x) << 16; \
318 UPD_ACC_ZN
319
320#define OP_EORA32(x) \
321 rA32 ^= (x); \
322 UPD_ACC_ZN
323
324
325#define OP_CHECK32(OP) { \
326 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
327 read_P(); /* update P */ \
328 OP(rP.v); \
329 break; \
330 } \
331 if ((op & 0x0f) == SSP_A) { /* A <- A */ \
332 OP(rA32); \
333 break; \
334 } \
335}
336
337
338#ifdef DO_CHECKS
339#define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS())
340#define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS())
341#define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS())
342#define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS())
343#define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS())
344#define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS())
345#define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS())
346#define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS())
347#define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS())
348#define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS())
349#define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS())
350#else
351#define CHECK_IMM16()
352#define CHECK_B_SET()
353#define CHECK_B_CLEAR()
354#define CHECK_MOD()
355#define CHECK_10f()
356#define CHECK_008()
357#define CHECK_00f()
358#define CHECK_0f0()
359#define CHECK_1f0()
360#define CHECK_RPL()
361#define CHECK_ST(d)
362#endif
363
364ssp1601_t *ssp = NULL;
365static unsigned short *PC;
366static int g_cycles;
367
368#ifdef USE_DEBUGGER
369static int running = 0;
370static int last_iram = 0;
371#endif
372
373// -----------------------------------------------------
374// register i/o handlers
375
376// 0-4, 13
377static u32 read_unknown(void)
378{
379 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
380 return 0;
381}
382
383static void write_unknown(u32 d)
384{
385 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
386}
387
388// 4
389static void write_ST(u32 d)
390{
391 CHECK_ST(d);
392 rST = d;
393}
394
395// 5
396static u32 read_STACK(void)
397{
398 --rSTACK;
399 if ((short)rSTACK < 0) {
400 rSTACK = 5;
401 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
402 }
403 return ssp->stack[rSTACK];
404}
405
406static void write_STACK(u32 d)
407{
408 if (rSTACK >= 6) {
409 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
410 rSTACK = 0;
411 }
412 ssp->stack[rSTACK++] = d;
413}
414
415// 6
416static u32 read_PC(void)
417{
418 return GET_PC();
419}
420
421static void write_PC(u32 d)
422{
423 SET_PC(d);
424 g_cycles--;
425}
426
427// 7
428static u32 read_P(void)
429{
430 int m1 = (signed short)rX;
431 int m2 = (signed short)rY;
432 rP.v = (m1 * m2 * 2);
433 return rP.h;
434}
435
436// -----------------------------------------------------
437
438static int get_inc(int mode)
439{
440 int inc = (mode >> 11) & 7;
441 if (inc != 0) {
442 if (inc != 7) inc--;
443 inc = 1 << inc; // 0 1 2 4 8 16 32 128
444 if (mode & 0x8000) inc = -inc; // decrement mode
445 }
446 return inc;
447}
448
449#define overwrite_write(dst, d) \
450{ \
451 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
452 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
453 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
454 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
455}
456
457static u32 pm_io(int reg, int write, u32 d)
458{
459 if (ssp->emu_status & SSP_PMC_SET)
460 {
461 // this MUST be blind r or w
462 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
463 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
464 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
465 ssp->emu_status &= ~SSP_PMC_SET;
466 return 0;
467 }
468 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
469 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
470 ssp->emu_status &= ~SSP_PMC_SET;
471 if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
472 elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1);
473#ifdef USE_DEBUGGER
474 last_iram = (ssp->RAM1[0]-1)<<1;
475#endif
476 }
477 return 0;
478 }
479
480 // just in case
481 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
482 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
483 reg, write ? 'w' : 'r', GET_PPC_OFFS());
484 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
485 }
486
487 if (reg == 4 || (rST & 0x60))
488 {
489 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
490 unsigned short *dram = (unsigned short *)svp->dram;
491 if (write)
492 {
493 int mode = ssp->pmac_write[reg]>>16;
494 int addr = ssp->pmac_write[reg]&0xffff;
495 if ((mode & 0xb800) == 0xb800)
496 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
497 if ((mode & 0x43ff) == 0x0018) // DRAM
498 {
499 int inc = get_inc(mode);
500 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
501 reg, CADDR, d, inc, (mode>>10)&1);
502 if (mode & 0x0400) {
503 overwrite_write(dram[addr], d);
504 } else dram[addr] = d;
505 ssp->pmac_write[reg] += inc;
506 }
507 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
508 {
509 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
510 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
511 if (mode & 0x0400) {
512 overwrite_write(dram[addr], d);
513 } else dram[addr] = d;
514 ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
515 }
516 else if ((mode & 0x47ff) == 0x001c) // IRAM
517 {
518 int inc = get_inc(mode);
519 if ((addr&0xfc00) != 0x8000)
520 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
521 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
522 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
523 ssp->pmac_write[reg] += inc;
524 }
525 else
526 {
527 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
528 reg, mode, CADDR, d, GET_PPC_OFFS());
529 }
530 }
531 else
532 {
533 int mode = ssp->pmac_read[reg]>>16;
534 int addr = ssp->pmac_read[reg]&0xffff;
535 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
536 {
537 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
538 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
539 ssp->pmac_read[reg] += 1;
540 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
541 }
542 else if ((mode & 0x47ff) == 0x0018) // DRAM
543 {
544 int inc = get_inc(mode);
545 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
546 d = dram[addr];
547 ssp->pmac_read[reg] += inc;
548 }
549 else
550 {
551 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
552 reg, mode, CADDR, GET_PPC_OFFS());
553 d = 0;
554 }
555 }
556
557 // PMC value corresponds to last PMR accessed (not sure).
558 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
559
560 return d;
561 }
562
563 return (u32)-1;
564}
565
566// 8
567static u32 read_PM0(void)
568{
569 u32 d = pm_io(0, 0, 0);
570 if (d != (u32)-1) return d;
571 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
572 d = rPM0;
573 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
574 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
575 }
576 rPM0 &= ~2; // ?
577 return d;
578}
579
580static void write_PM0(u32 d)
581{
582 u32 r = pm_io(0, 1, d);
583 if (r != (u32)-1) return;
584 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
585 rPM0 = d;
586}
587
588// 9
589static u32 read_PM1(void)
590{
591 u32 d = pm_io(1, 0, 0);
592 if (d != (u32)-1) return d;
593 // can be removed?
594 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
595 return rPM1;
596}
597
598static void write_PM1(u32 d)
599{
600 u32 r = pm_io(1, 1, d);
601 if (r != (u32)-1) return;
602 // can be removed?
603 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
604 rPM1 = d;
605}
606
607// 10
608static u32 read_PM2(void)
609{
610 u32 d = pm_io(2, 0, 0);
611 if (d != (u32)-1) return d;
612 // can be removed?
613 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
614 return rPM2;
615}
616
617static void write_PM2(u32 d)
618{
619 u32 r = pm_io(2, 1, d);
620 if (r != (u32)-1) return;
621 // can be removed?
622 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
623 rPM2 = d;
624}
625
626// 11
627static u32 read_XST(void)
628{
629 // can be removed?
630 u32 d = pm_io(3, 0, 0);
631 if (d != (u32)-1) return d;
632
633 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
634 return rXST;
635}
636
637static void write_XST(u32 d)
638{
639 // can be removed?
640 u32 r = pm_io(3, 1, d);
641 if (r != (u32)-1) return;
642
643 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
644 rPM0 |= 1;
645 rXST = d;
646}
647
648// 12
649static u32 read_PM4(void)
650{
651 u32 d = pm_io(4, 0, 0);
652 if (d == 0) {
653 switch (GET_PPC_OFFS()) {
654 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
655 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
656 }
657 }
658 if (d != (u32)-1) return d;
659 // can be removed?
660 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
661 return rPM4;
662}
663
664static void write_PM4(u32 d)
665{
666 u32 r = pm_io(4, 1, d);
667 if (r != (u32)-1) return;
668 // can be removed?
669 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
670 rPM4 = d;
671}
672
673// 14
674static u32 read_PMC(void)
675{
676 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
677 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
678 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
679 //if (ssp->emu_status & SSP_PMC_SET)
680 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
681 ssp->emu_status |= SSP_PMC_SET;
682 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
683 return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
684 } else {
685 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
686 return rPMC.l;
687 }
688}
689
690static void write_PMC(u32 d)
691{
692 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
693 //if (ssp->emu_status & SSP_PMC_SET)
694 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
695 ssp->emu_status |= SSP_PMC_SET;
696 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
697 rPMC.h = d;
698 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
699 } else {
700 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
701 rPMC.l = d;
702 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
703 }
704}
705
706// 15
707static u32 read_AL(void)
708{
709 if (*(PC-1) == 0x000f)
710 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
711 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
712 return rAL;
713}
714
715static void write_AL(u32 d)
716{
717 rAL = d;
718}
719
720
721typedef u32 (*read_func_t)(void);
722typedef void (*write_func_t)(u32 d);
723
724static read_func_t read_handlers[16] =
725{
726 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
727 read_unknown, // 4 ST
728 read_STACK,
729 read_PC,
730 read_P,
731 read_PM0, // 8
732 read_PM1,
733 read_PM2,
734 read_XST,
735 read_PM4, // 12
736 read_unknown, // 13 gr13
737 read_PMC,
738 read_AL
739};
740
741static write_func_t write_handlers[16] =
742{
743 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
744// write_unknown, // 4 ST
745 write_ST, // 4 ST (debug hook)
746 write_STACK,
747 write_PC,
748 write_unknown, // 7 P
749 write_PM0, // 8
750 write_PM1,
751 write_PM2,
752 write_XST,
753 write_PM4, // 12
754 write_unknown, // 13 gr13
755 write_PMC,
756 write_AL
757};
758
759// -----------------------------------------------------
760// pointer register handlers
761
762//
763#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
764
765static u32 ptr1_read_(int ri, int isj2, int modi3)
766{
767 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
768 u32 mask, add = 0, t = ri | isj2 | modi3;
769 unsigned char *rp = NULL;
770 switch (t)
771 {
772 // mod=0 (00)
773 case 0x00:
774 case 0x01:
775 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
776 case 0x03: return ssp->RAM0[0];
777 case 0x04:
778 case 0x05:
779 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
780 case 0x07: return ssp->RAM1[0];
781 // mod=1 (01), "+!"
782 case 0x08:
783 case 0x09:
784 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
785 case 0x0b: return ssp->RAM0[1];
786 case 0x0c:
787 case 0x0d:
788 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
789 case 0x0f: return ssp->RAM1[1];
790 // mod=2 (10), "-"
791 case 0x10:
792 case 0x11:
793 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
794 if (!(rST&7)) { (*rp)--; return t; }
795 add = -1; goto modulo;
796 case 0x13: return ssp->RAM0[2];
797 case 0x14:
798 case 0x15:
799 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
800 if (!(rST&7)) { (*rp)--; return t; }
801 add = -1; goto modulo;
802 case 0x17: return ssp->RAM1[2];
803 // mod=3 (11), "+"
804 case 0x18:
805 case 0x19:
806 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
807 if (!(rST&7)) { (*rp)++; return t; }
808 add = 1; goto modulo;
809 case 0x1b: return ssp->RAM0[3];
810 case 0x1c:
811 case 0x1d:
812 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
813 if (!(rST&7)) { (*rp)++; return t; }
814 add = 1; goto modulo;
815 case 0x1f: return ssp->RAM1[3];
816 }
817
818 return 0;
819
820modulo:
821 mask = (1 << (rST&7)) - 1;
822 *rp = (*rp & ~mask) | ((*rp + add) & mask);
823 return t;
824}
825
826static void ptr1_write(int op, u32 d)
827{
828 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
829 switch (t)
830 {
831 // mod=0 (00)
832 case 0x00:
833 case 0x01:
834 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
835 case 0x03: ssp->RAM0[0] = d; return;
836 case 0x04:
837 case 0x05:
838 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
839 case 0x07: ssp->RAM1[0] = d; return;
840 // mod=1 (01), "+!"
841 // mod=3, "+"
842 case 0x08:
843 case 0x09:
844 case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
845 case 0x0b: ssp->RAM0[1] = d; return;
846 case 0x0c:
847 case 0x0d:
848 case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
849 case 0x0f: ssp->RAM1[1] = d; return;
850 // mod=2 (10), "-"
851 case 0x10:
852 case 0x11:
853 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return;
854 case 0x13: ssp->RAM0[2] = d; return;
855 case 0x14:
856 case 0x15:
857 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return;
858 case 0x17: ssp->RAM1[2] = d; return;
859 // mod=3 (11), "+"
860 case 0x18:
861 case 0x19:
862 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return;
863 case 0x1b: ssp->RAM0[3] = d; return;
864 case 0x1c:
865 case 0x1d:
866 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return;
867 case 0x1f: ssp->RAM1[3] = d; return;
868 }
869}
870
871static u32 ptr2_read(int op)
872{
873 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
874 switch (t)
875 {
876 // mod=0 (00)
877 case 0x00:
878 case 0x01:
879 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
880 case 0x03: mv = ssp->RAM0[0]++; break;
881 case 0x04:
882 case 0x05:
883 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
884 case 0x07: mv = ssp->RAM1[0]++; break;
885 // mod=1 (01)
886 case 0x0b: mv = ssp->RAM0[1]++; break;
887 case 0x0f: mv = ssp->RAM1[1]++; break;
888 // mod=2 (10)
889 case 0x13: mv = ssp->RAM0[2]++; break;
890 case 0x17: mv = ssp->RAM1[2]++; break;
891 // mod=3 (11)
892 case 0x1b: mv = ssp->RAM0[3]++; break;
893 case 0x1f: mv = ssp->RAM1[3]++; break;
894 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
895 return 0;
896 }
897
898 return ((unsigned short *)svp->iram_rom)[mv];
899}
900
901
902// -----------------------------------------------------
903
904#if defined(USE_DEBUGGER)
905static void debug_dump2file(const char *fname, void *mem, int len)
906{
907 FILE *f = fopen(fname, "wb");
908 unsigned short *p = mem;
909 int i;
910 if (f) {
911 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
912 fwrite(mem, 1, len, f);
913 fclose(f);
914 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
915 printf("dumped to %s\n", fname);
916 }
917 else
918 printf("dump failed\n");
919}
920#endif
921
922#ifdef USE_DEBUGGER
923static void debug_dump(void)
924{
925 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
926 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
927 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
928 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
929 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
930 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
931 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
932 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
933 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
934 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
935}
936
937static void debug_dump_mem(void)
938{
939 int h, i;
940 printf("RAM0\n");
941 for (h = 0; h < 32; h++)
942 {
943 if (h == 16) printf("RAM1\n");
944 printf("%03x:", h*16);
945 for (i = 0; i < 16; i++)
946 printf(" %04x", ssp->RAM[h*16+i]);
947 printf("\n");
948 }
949}
950
951static int bpts[10] = { 0, };
952
953static void debug(unsigned int pc, unsigned int op)
954{
955 static char buffo[64] = {0,};
956 char buff[64] = {0,};
957 int i;
958
959 if (running) {
960 for (i = 0; i < 10; i++)
961 if (pc != 0 && bpts[i] == pc) {
962 printf("breakpoint %i\n", i);
963 running = 0;
964 break;
965 }
966 }
967 if (running) return;
968
969 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
970
971 while (1)
972 {
973 printf("dbg> ");
974 fflush(stdout);
975 fgets(buff, sizeof(buff), stdin);
976 if (buff[0] == '\n') strcpy(buff, buffo);
977 else strcpy(buffo, buff);
978
979 switch (buff[0]) {
980 case 0: exit(0);
981 case 'c':
982 case 'r': running = 1; return;
983 case 's':
984 case 'n': return;
985 case 'x': debug_dump(); break;
986 case 'm': debug_dump_mem(); break;
987 case 'b': {
988 char *baddr = buff + 2;
989 i = 0;
990 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
991 bpts[i] = strtol(baddr, NULL, 16) >> 1;
992 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
993 break;
994 }
995 case 'd':
996 sprintf(buff, "iramrom_%04x.bin", last_iram);
997 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
998 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
999 break;
1000 default: printf("unknown command\n"); break;
1001 }
1002 }
1003}
1004#endif // USE_DEBUGGER
1005
1006
1007void ssp1601_reset(ssp1601_t *l_ssp)
1008{
1009 ssp = l_ssp;
1010 ssp->emu_status = 0;
1011 ssp->gr[SSP_GR0].v = 0xffff0000;
1012 rPC = 0x400;
1013 rSTACK = 0; // ? using ascending stack
1014 rST = 0;
1015}
1016
1017
1018void ssp1601_run(int cycles)
1019{
1020 SET_PC(rPC);
1021
1022 g_cycles = cycles;
1023
1024 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
1025 {
1026 int op;
1027 u32 tmpv;
1028
1029 op = *PC++;
1030#ifdef USE_DEBUGGER
1031 debug(GET_PC()-1, op);
1032#endif
1033 switch (op >> 9)
1034 {
1035 // ld d, s
1036 case 0x00:
1037 CHECK_B_SET();
1038 if (op == 0) break; // nop
1039 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1040 read_P(); // update P
1041 rA32 = rP.v;
1042 }
1043 else
1044 {
1045 tmpv = REG_READ(op & 0x0f);
1046 REG_WRITE((op & 0xf0) >> 4, tmpv);
1047 }
1048 break;
1049
1050 // ld d, (ri)
1051 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1052
1053 // ld (ri), s
1054 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1055
1056 // ldi d, imm
1057 case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break;
1058
1059 // ld d, ((ri))
1060 case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break;
1061
1062 // ldi (ri), imm
1063 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break;
1064
1065 // ld adr, a
1066 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1067
1068 // ld d, ri
1069 case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1070
1071 // ld ri, s
1072 case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1073
1074 // ldi ri, simm
1075 case 0x0c:
1076 case 0x0d:
1077 case 0x0e:
1078 case 0x0f: rIJ[(op>>8)&7] = op; break;
1079
1080 // call cond, addr
1081 case 0x24: {
1082 int cond = 0;
1083 CHECK_00f();
1084 COND_CHECK
1085 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); }
1086 else PC++;
1087 g_cycles--; // always 2 cycles
1088 break;
1089 }
1090
1091 // ld d, (a)
1092 case 0x25:
1093 CHECK_10f();
1094 tmpv = ((unsigned short *)svp->iram_rom)[rA];
1095 REG_WRITE((op & 0xf0) >> 4, tmpv);
1096 g_cycles -= 2; // 3 cycles total
1097 break;
1098
1099 // bra cond, addr
1100 case 0x26: {
1101 int cond = 0;
1102 CHECK_00f();
1103 COND_CHECK
1104 if (cond) { int new_PC = *PC++; SET_PC(new_PC); }
1105 else PC++;
1106 g_cycles--;
1107 break;
1108 }
1109
1110 // mod cond, op
1111 case 0x48: {
1112 int cond = 0;
1113 CHECK_008();
1114 COND_CHECK
1115 if (cond) {
1116 switch (op & 7) {
1117 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1118 case 3: rA32 <<= 1; break; // shl
1119 case 6: rA32 = -(signed int)rA32; break; // neg
1120 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1121 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1122 op&7, GET_PPC_OFFS());
1123 }
1124 UPD_ACC_ZN
1125 }
1126 break;
1127 }
1128
1129 // mpys?
1130 case 0x1b:
1131 CHECK_B_CLEAR();
1132 read_P(); // update P
1133 rA32 -= rP.v;
1134 UPD_ACC_ZN
1135 rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
1136 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
1137 break;
1138
1139 // mpya (rj), (ri), b
1140 case 0x4b:
1141 CHECK_B_CLEAR();
1142 read_P(); // update P
1143 rA32 += rP.v;
1144 UPD_ACC_ZN
1145 rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
1146 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
1147 break;
1148
1149 // mld (rj), (ri), b
1150 case 0x5b:
1151 CHECK_B_CLEAR();
1152 rA32 = 0;
1153 rST &= 0x0fff;
1154 rST |= SSP_FLAG_Z;
1155 rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
1156 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
1157 break;
1158
1159 // OP a, s
1160 case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1161 case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1162 case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1163 case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1164 case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1165 case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1166
1167 // OP a, (ri)
1168 case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1169 case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1170 case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1171 case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1172 case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1173 case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1174
1175 // OP a, adr
1176 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1177 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1178 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1179 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1180 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1181 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1182 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1183
1184 // OP a, imm
1185 case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break;
1186 case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break;
1187 case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break;
1188 case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break;
1189 case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break;
1190 case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break;
1191
1192 // OP a, ((ri))
1193 case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break;
1194 case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break;
1195 case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break;
1196 case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break;
1197 case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break;
1198 case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break;
1199
1200 // OP a, ri
1201 case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1202 case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1203 case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1204 case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1205 case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1206 case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1207
1208 // OP simm
1209 case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break;
1210 case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break;
1211 case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break;
1212 case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break;
1213 case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break;
1214 case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break;
1215
1216 default:
1217 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1218 break;
1219 }
1220 g_cycles--;
1221 }
1222
1223 rPC = GET_PC();
1224 read_P(); // update P
1225}
1226
fast MegaDrive/MegaCD/32X emulator