| | 1 | // basic, incomplete SSP160x (SSP1601?) interpreter |
| | 2 | // with SVP memory controller emu |
| | 3 | |
| | 4 | // (c) Copyright 2008, Grazvydas "notaz" Ignotas |
| | 5 | // Free for non-commercial use. |
| | 6 | |
| | 7 | // For commercial use, separate licencing terms must be obtained. |
| | 8 | |
| | 9 | |
| | 10 | //#define USE_DEBUGGER |
| | 11 | /* detect ops with unimplemented/invalid fields. |
| | 12 | * Useful for homebrew or if a new VR revision pops up. */ |
| | 13 | //#define DO_CHECKS |
| | 14 | |
| | 15 | #include "../../PicoInt.h" |
| | 16 | |
| | 17 | /* |
| | 18 | * Register info |
| | 19 | * |
| | 20 | * 0. "-" |
| | 21 | * size: 16 |
| | 22 | * desc: Constant register with all bits set (0xffff). |
| | 23 | * |
| | 24 | * 1. "X" |
| | 25 | * size: 16 |
| | 26 | * desc: Generic register. When set, updates P (P = X * Y * 2) |
| | 27 | * |
| | 28 | * 2. "Y" |
| | 29 | * size: 16 |
| | 30 | * desc: Generic register. When set, updates P (P = X * Y * 2) |
| | 31 | * |
| | 32 | * 3. "A" |
| | 33 | * size: 32 |
| | 34 | * desc: Accumulator. |
| | 35 | * |
| | 36 | * 4. "ST" |
| | 37 | * size: 16 |
| | 38 | * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG |
| | 39 | * fedc ba98 7654 3210 |
| | 40 | * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively |
| | 41 | * modulo-increment and modulo-decrement. The value shows which |
| | 42 | * power of 2 to use, i.e. 4 means modulo by 16. |
| | 43 | * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC) |
| | 44 | * 43 - RB (?) |
| | 45 | * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?). |
| | 46 | * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after. |
| | 47 | * datasheet says these (5,6) bits correspond to hardware pins. |
| | 48 | * 7 - IE (?) Not directly used by SVP code (never set, but preserved)? |
| | 49 | * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value |
| | 50 | * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff)) |
| | 51 | * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift") |
| | 52 | * a - GPI_0 Interrupt 0 enable/status? |
| | 53 | * b - GPI_1 Interrupt 1 enable/status? |
| | 54 | * c - L L flag. Carry? |
| | 55 | * d - Z Zero flag. |
| | 56 | * e - OV Overflow flag. |
| | 57 | * f - N Negative flag. |
| | 58 | * seen directly changing code sequences: |
| | 59 | * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h |
| | 60 | * ldi ST, 60h ori A, 60h and A, E8h and A, E8h |
| | 61 | * ld ST, A ld ST, A ori 3 |
| | 62 | * ld ST, A |
| | 63 | * |
| | 64 | * 5. "STACK" |
| | 65 | * size: 16 |
| | 66 | * desc: hw stack of 6 levels (according to datasheet) |
| | 67 | * |
| | 68 | * 6. "PC" |
| | 69 | * size: 16 |
| | 70 | * desc: Program counter. |
| | 71 | * |
| | 72 | * 7. "P" |
| | 73 | * size: 32 |
| | 74 | * desc: multiply result register. P = X * Y * 2 |
| | 75 | * probably affected by MACS bit in ST. |
| | 76 | * |
| | 77 | * 8. "PM0" (PM from PMAR name from Tasco's docs) |
| | 78 | * size: 16? |
| | 79 | * desc: Programmable Memory access register. |
| | 80 | * On reset, or when one (both?) GP0 bits are clear, |
| | 81 | * acts as status for XST, mapped at 015004 at 68k side: |
| | 82 | * bit0: ssp has written something to XST (cleared when 015004 is read) |
| | 83 | * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read) |
| | 84 | * |
| | 85 | * 9. "PM1" |
| | 86 | * size: 16? |
| | 87 | * desc: Programmable Memory access register. |
| | 88 | * This reg. is only used as PMAR. |
| | 89 | * |
| | 90 | * 10. "PM2" |
| | 91 | * size: 16? |
| | 92 | * desc: Programmable Memory access register. |
| | 93 | * This reg. is only used as PMAR. |
| | 94 | * |
| | 95 | * 11. "XST" |
| | 96 | * size: 16? |
| | 97 | * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side. |
| | 98 | * Can be programmed as PMAR? (only seen in test mode code) |
| | 99 | * Affects PM0 when written to? |
| | 100 | * |
| | 101 | * 12. "PM4" |
| | 102 | * size: 16? |
| | 103 | * desc: Programmable Memory access register. |
| | 104 | * This reg. is only used as PMAR. The most used PMAR by VR. |
| | 105 | * |
| | 106 | * 13. (unused by VR) |
| | 107 | * |
| | 108 | * 14. "PMC" (PMC from PMAC name from Tasco's docs) |
| | 109 | * size: 32? |
| | 110 | * desc: Programmable Memory access Control. Set using 2 16bit writes, |
| | 111 | * first address, then mode word. After setting PMAC, PMAR sould |
| | 112 | * be blind accessed (ld -, PMx or ld PMx, -) to program it for |
| | 113 | * reading and writing respectively. |
| | 114 | * Reading the register also shifts it's state (from "waiting for |
| | 115 | * address" to "waiting for mode" and back). Reads always return |
| | 116 | * address related to last PMx register accressed. |
| | 117 | * (note: addresses do not wrap). |
| | 118 | * |
| | 119 | * 15. "AL" |
| | 120 | * size: 16 |
| | 121 | * desc: Accumulator Low. 16 least significant bits of accumulator. |
| | 122 | * (normally reading acc (ld X, A) you get 16 most significant bits). |
| | 123 | * |
| | 124 | * |
| | 125 | * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1. |
| | 126 | * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ], |
| | 127 | * which work similar to * and ** operators in C, only they use different memory banks and |
| | 128 | * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses |
| | 129 | * program memory at address read from (rX), and increments value in (rX). |
| | 130 | * |
| | 131 | * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5]. |
| | 132 | * 3 modifiers can be applied (optional): |
| | 133 | * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST. |
| | 134 | * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure). |
| | 135 | * +!: post-increment, unaffected by RPL (probably). |
| | 136 | * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-] |
| | 137 | * ar probably invalid. |
| | 138 | * |
| | 139 | * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do). |
| | 140 | * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+, |
| | 141 | * Samsung's old DSP page claims that). |
| | 142 | * 1 of these 4 modifiers must be used (short form direct addressing?): |
| | 143 | * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code) |
| | 144 | * |01: RAMx[1] |
| | 145 | * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2 |
| | 146 | * |11: RAMx[3] |
| | 147 | * |
| | 148 | * |
| | 149 | * Instruction notes |
| | 150 | * |
| | 151 | * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc) |
| | 152 | * |
| | 153 | * mld (rj), (ri) [, b] |
| | 154 | * operation: A = 0; P = (rj) * (ri) |
| | 155 | * notes: based on IIR_4B.SC sample. flags? what is b??? |
| | 156 | * |
| | 157 | * mpya (rj), (ri) [, b] |
| | 158 | * name: multiply and add? |
| | 159 | * operation: A += P; P = (rj) * (ri) |
| | 160 | * |
| | 161 | * mpys (rj), (ri), b |
| | 162 | * name: multiply and subtract? |
| | 163 | * notes: not used by VR code. |
| | 164 | * |
| | 165 | * mod cond, op |
| | 166 | * mod cond, shr does arithmetic shift |
| | 167 | * |
| | 168 | * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns |
| | 169 | * |
| | 170 | * memory map: |
| | 171 | * 000000 - 1fffff ROM, accessable by both |
| | 172 | * 200000 - 2fffff unused? |
| | 173 | * 300000 - 31ffff DRAM, both |
| | 174 | * 320000 - 38ffff unused? |
| | 175 | * 390000 - 3907ff IRAM. can only be accessed by ssp? |
| | 176 | * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only? |
| | 177 | * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different |
| | 178 | * |
| | 179 | * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k) |
| | 180 | * 30fe06 - also sync related. |
| | 181 | * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR. |
| | 182 | * |
| | 183 | * Assumptions and limitations in this code |
| | 184 | * only Z and N status flags are emulated (others unused by VR) |
| | 185 | * so all condition checks except N and Z are ignored (not used by VR) |
| | 186 | * modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR) |
| | 187 | * loop repeat mode when (ri) is destination is ignored |
| | 188 | * ops not used by VR are not implemented |
| | 189 | */ |
| | 190 | |
| | 191 | #include "../../PicoInt.h" |
| | 192 | |
| | 193 | #define u32 unsigned int |
| | 194 | |
| | 195 | // 0 |
| | 196 | #define rX ssp->gr[SSP_X].h |
| | 197 | #define rY ssp->gr[SSP_Y].h |
| | 198 | #define rA ssp->gr[SSP_A].h |
| | 199 | #define rST ssp->gr[SSP_ST].h // 4 |
| | 200 | #define rSTACK ssp->gr[SSP_STACK].h |
| | 201 | #define rPC ssp->gr[SSP_PC].h |
| | 202 | #define rP ssp->gr[SSP_P] |
| | 203 | #define rPM0 ssp->gr[SSP_PM0].h // 8 |
| | 204 | #define rPM1 ssp->gr[SSP_PM1].h |
| | 205 | #define rPM2 ssp->gr[SSP_PM2].h |
| | 206 | #define rXST ssp->gr[SSP_XST].h |
| | 207 | #define rPM4 ssp->gr[SSP_PM4].h // 12 |
| | 208 | // 13 |
| | 209 | #define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h |
| | 210 | #define rAL ssp->gr[SSP_A].l |
| | 211 | |
| | 212 | #define rA32 ssp->gr[SSP_A].v |
| | 213 | #define rIJ ssp->r |
| | 214 | |
| | 215 | #define IJind (((op>>6)&4)|(op&3)) |
| | 216 | |
| | 217 | #ifndef EMBED_INTERPRETER |
| | 218 | #define GET_PC() (PC - (unsigned short *)svp->iram_rom) |
| | 219 | #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2) |
| | 220 | #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d |
| | 221 | #endif |
| | 222 | |
| | 223 | #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]()) |
| | 224 | #define REG_WRITE(r,d) { \ |
| | 225 | int r1 = r; \ |
| | 226 | if (r1 >= 4) write_handlers[r1](d); \ |
| | 227 | else if (r1 > 0) ssp->gr[r1].h = d; \ |
| | 228 | } |
| | 229 | |
| | 230 | // flags |
| | 231 | #define SSP_FLAG_L (1<<0xc) |
| | 232 | #define SSP_FLAG_Z (1<<0xd) |
| | 233 | #define SSP_FLAG_V (1<<0xe) |
| | 234 | #define SSP_FLAG_N (1<<0xf) |
| | 235 | |
| | 236 | // update ZN according to 32bit ACC. |
| | 237 | #define UPD_ACC_ZN \ |
| | 238 | rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \ |
| | 239 | if (!rA32) rST |= SSP_FLAG_Z; \ |
| | 240 | else rST |= (rA32>>16)&SSP_FLAG_N; |
| | 241 | |
| | 242 | // it seems SVP code never checks for L and OV, so we leave them out. |
| | 243 | // rST |= (t>>4)&SSP_FLAG_L; |
| | 244 | #define UPD_LZVN \ |
| | 245 | rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \ |
| | 246 | if (!rA32) rST |= SSP_FLAG_Z; \ |
| | 247 | else rST |= (rA32>>16)&SSP_FLAG_N; |
| | 248 | |
| | 249 | // standard cond processing. |
| | 250 | // again, only Z and N is checked, as VR doesn't seem to use any other conds. |
| | 251 | #define COND_CHECK \ |
| | 252 | switch (op&0xf0) { \ |
| | 253 | case 0x00: cond = 1; break; /* always true */ \ |
| | 254 | case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \ |
| | 255 | case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \ |
| | 256 | default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \ |
| | 257 | } |
| | 258 | |
| | 259 | // ops with accumulator. |
| | 260 | // how is low word really affected by these? |
| | 261 | // nearly sure 'ld A' doesn't affect flags |
| | 262 | #define OP_LDA(x) \ |
| | 263 | ssp->gr[SSP_A].h = x |
| | 264 | |
| | 265 | #define OP_LDA32(x) \ |
| | 266 | rA32 = x |
| | 267 | |
| | 268 | #define OP_SUBA(x) { \ |
| | 269 | rA32 -= (x) << 16; \ |
| | 270 | UPD_LZVN \ |
| | 271 | } |
| | 272 | |
| | 273 | #define OP_SUBA32(x) { \ |
| | 274 | rA32 -= (x); \ |
| | 275 | UPD_LZVN \ |
| | 276 | } |
| | 277 | |
| | 278 | #define OP_CMPA(x) { \ |
| | 279 | u32 t = rA32 - ((x) << 16); \ |
| | 280 | rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \ |
| | 281 | if (!t) rST |= SSP_FLAG_Z; \ |
| | 282 | else rST |= (t>>16)&SSP_FLAG_N; \ |
| | 283 | } |
| | 284 | |
| | 285 | #define OP_CMPA32(x) { \ |
| | 286 | u32 t = rA32 - (x); \ |
| | 287 | rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \ |
| | 288 | if (!t) rST |= SSP_FLAG_Z; \ |
| | 289 | else rST |= (t>>16)&SSP_FLAG_N; \ |
| | 290 | } |
| | 291 | |
| | 292 | #define OP_ADDA(x) { \ |
| | 293 | rA32 += (x) << 16; \ |
| | 294 | UPD_LZVN \ |
| | 295 | } |
| | 296 | |
| | 297 | #define OP_ADDA32(x) { \ |
| | 298 | rA32 += (x); \ |
| | 299 | UPD_LZVN \ |
| | 300 | } |
| | 301 | |
| | 302 | #define OP_ANDA(x) \ |
| | 303 | rA32 &= (x) << 16; \ |
| | 304 | UPD_ACC_ZN |
| | 305 | |
| | 306 | #define OP_ANDA32(x) \ |
| | 307 | rA32 &= (x); \ |
| | 308 | UPD_ACC_ZN |
| | 309 | |
| | 310 | #define OP_ORA(x) \ |
| | 311 | rA32 |= (x) << 16; \ |
| | 312 | UPD_ACC_ZN |
| | 313 | |
| | 314 | #define OP_ORA32(x) \ |
| | 315 | rA32 |= (x); \ |
| | 316 | UPD_ACC_ZN |
| | 317 | |
| | 318 | #define OP_EORA(x) \ |
| | 319 | rA32 ^= (x) << 16; \ |
| | 320 | UPD_ACC_ZN |
| | 321 | |
| | 322 | #define OP_EORA32(x) \ |
| | 323 | rA32 ^= (x); \ |
| | 324 | UPD_ACC_ZN |
| | 325 | |
| | 326 | |
| | 327 | #define OP_CHECK32(OP) { \ |
| | 328 | if ((op & 0x0f) == SSP_P) { /* A <- P */ \ |
| | 329 | read_P(); /* update P */ \ |
| | 330 | OP(rP.v); \ |
| | 331 | break; \ |
| | 332 | } \ |
| | 333 | if ((op & 0x0f) == SSP_A) { /* A <- A */ \ |
| | 334 | OP(rA32); \ |
| | 335 | break; \ |
| | 336 | } \ |
| | 337 | } |
| | 338 | |
| | 339 | |
| | 340 | #ifdef DO_CHECKS |
| | 341 | #define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 342 | #define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 343 | #define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 344 | #define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 345 | #define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 346 | #define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 347 | #define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 348 | #define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 349 | #define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 350 | #define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS()) |
| | 351 | #define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS()) |
| | 352 | #else |
| | 353 | #define CHECK_IMM16() |
| | 354 | #define CHECK_B_SET() |
| | 355 | #define CHECK_B_CLEAR() |
| | 356 | #define CHECK_MOD() |
| | 357 | #define CHECK_10f() |
| | 358 | #define CHECK_008() |
| | 359 | #define CHECK_00f() |
| | 360 | #define CHECK_0f0() |
| | 361 | #define CHECK_1f0() |
| | 362 | #define CHECK_RPL() |
| | 363 | #define CHECK_ST(d) |
| | 364 | #endif |
| | 365 | |
| | 366 | #ifndef EMBED_INTERPRETER |
| | 367 | static |
| | 368 | #endif |
| | 369 | ssp1601_t *ssp = NULL; |
| | 370 | static unsigned short *PC; |
| | 371 | static int g_cycles; |
| | 372 | |
| | 373 | #ifdef USE_DEBUGGER |
| | 374 | static int running = 0; |
| | 375 | static int last_iram = 0; |
| | 376 | #endif |
| | 377 | |
| | 378 | // ----------------------------------------------------- |
| | 379 | // register i/o handlers |
| | 380 | |
| | 381 | // 0-4, 13 |
| | 382 | static u32 read_unknown(void) |
| | 383 | { |
| | 384 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS()); |
| | 385 | return 0; |
| | 386 | } |
| | 387 | |
| | 388 | static void write_unknown(u32 d) |
| | 389 | { |
| | 390 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS()); |
| | 391 | } |
| | 392 | |
| | 393 | // 4 |
| | 394 | static void write_ST(u32 d) |
| | 395 | { |
| | 396 | CHECK_ST(d); |
| | 397 | rST = d; |
| | 398 | } |
| | 399 | |
| | 400 | // 5 |
| | 401 | static u32 read_STACK(void) |
| | 402 | { |
| | 403 | --rSTACK; |
| | 404 | if ((short)rSTACK < 0) { |
| | 405 | rSTACK = 5; |
| | 406 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS()); |
| | 407 | } |
| | 408 | return ssp->stack[rSTACK]; |
| | 409 | } |
| | 410 | |
| | 411 | static void write_STACK(u32 d) |
| | 412 | { |
| | 413 | if (rSTACK >= 6) { |
| | 414 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS()); |
| | 415 | rSTACK = 0; |
| | 416 | } |
| | 417 | ssp->stack[rSTACK++] = d; |
| | 418 | } |
| | 419 | |
| | 420 | // 6 |
| | 421 | static u32 read_PC(void) |
| | 422 | { |
| | 423 | return GET_PC(); |
| | 424 | } |
| | 425 | |
| | 426 | static void write_PC(u32 d) |
| | 427 | { |
| | 428 | SET_PC(d); |
| | 429 | g_cycles--; |
| | 430 | } |
| | 431 | |
| | 432 | // 7 |
| | 433 | static u32 read_P(void) |
| | 434 | { |
| | 435 | int m1 = (signed short)rX; |
| | 436 | int m2 = (signed short)rY; |
| | 437 | rP.v = (m1 * m2 * 2); |
| | 438 | return rP.h; |
| | 439 | } |
| | 440 | |
| | 441 | // ----------------------------------------------------- |
| | 442 | |
| | 443 | static int get_inc(int mode) |
| | 444 | { |
| | 445 | int inc = (mode >> 11) & 7; |
| | 446 | if (inc != 0) { |
| | 447 | if (inc != 7) inc--; |
| | 448 | inc = 1 << inc; // 0 1 2 4 8 16 32 128 |
| | 449 | if (mode & 0x8000) inc = -inc; // decrement mode |
| | 450 | } |
| | 451 | return inc; |
| | 452 | } |
| | 453 | |
| | 454 | #define overwrite_write(dst, d) \ |
| | 455 | { \ |
| | 456 | if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \ |
| | 457 | if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \ |
| | 458 | if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \ |
| | 459 | if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \ |
| | 460 | } |
| | 461 | |
| | 462 | static u32 pm_io(int reg, int write, u32 d) |
| | 463 | { |
| | 464 | if (ssp->emu_status & SSP_PMC_SET) |
| | 465 | { |
| | 466 | // this MUST be blind r or w |
| | 467 | if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) { |
| | 468 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x", |
| | 469 | reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS()); |
| | 470 | ssp->emu_status &= ~SSP_PMC_SET; |
| | 471 | return 0; |
| | 472 | } |
| | 473 | elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS()); |
| | 474 | ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v; |
| | 475 | ssp->emu_status &= ~SSP_PMC_SET; |
| | 476 | if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) { |
| | 477 | elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1); |
| | 478 | #ifdef USE_DEBUGGER |
| | 479 | last_iram = (ssp->RAM1[0]-1)<<1; |
| | 480 | #endif |
| | 481 | } |
| | 482 | return 0; |
| | 483 | } |
| | 484 | |
| | 485 | // just in case |
| | 486 | if (ssp->emu_status & SSP_PMC_HAVE_ADDR) { |
| | 487 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x", |
| | 488 | reg, write ? 'w' : 'r', GET_PPC_OFFS()); |
| | 489 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
| | 490 | } |
| | 491 | |
| | 492 | if (reg == 4 || (rST & 0x60)) |
| | 493 | { |
| | 494 | #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1) |
| | 495 | unsigned short *dram = (unsigned short *)svp->dram; |
| | 496 | if (write) |
| | 497 | { |
| | 498 | int mode = ssp->pmac_write[reg]>>16; |
| | 499 | int addr = ssp->pmac_write[reg]&0xffff; |
| | 500 | if ((mode & 0xb800) == 0xb800) |
| | 501 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode); |
| | 502 | if ((mode & 0x43ff) == 0x0018) // DRAM |
| | 503 | { |
| | 504 | int inc = get_inc(mode); |
| | 505 | elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)", |
| | 506 | reg, CADDR, d, inc, (mode>>10)&1); |
| | 507 | if (mode & 0x0400) { |
| | 508 | overwrite_write(dram[addr], d); |
| | 509 | } else dram[addr] = d; |
| | 510 | ssp->pmac_write[reg] += inc; |
| | 511 | } |
| | 512 | else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc |
| | 513 | { |
| | 514 | elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x", |
| | 515 | reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS()); |
| | 516 | if (mode & 0x0400) { |
| | 517 | overwrite_write(dram[addr], d); |
| | 518 | } else dram[addr] = d; |
| | 519 | ssp->pmac_write[reg] += (addr&1) ? 31 : 1; |
| | 520 | } |
| | 521 | else if ((mode & 0x47ff) == 0x001c) // IRAM |
| | 522 | { |
| | 523 | int inc = get_inc(mode); |
| | 524 | if ((addr&0xfc00) != 0x8000) |
| | 525 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1); |
| | 526 | elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc); |
| | 527 | ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d; |
| | 528 | ssp->pmac_write[reg] += inc; |
| | 529 | #ifdef EMBED_INTERPRETER |
| | 530 | ssp->drc.iram_dirty = 1; |
| | 531 | #endif |
| | 532 | } |
| | 533 | else |
| | 534 | { |
| | 535 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x", |
| | 536 | reg, mode, CADDR, d, GET_PPC_OFFS()); |
| | 537 | } |
| | 538 | } |
| | 539 | else |
| | 540 | { |
| | 541 | int mode = ssp->pmac_read[reg]>>16; |
| | 542 | int addr = ssp->pmac_read[reg]&0xffff; |
| | 543 | if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct |
| | 544 | { |
| | 545 | elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR, |
| | 546 | ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]); |
| | 547 | ssp->pmac_read[reg] += 1; |
| | 548 | d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]; |
| | 549 | } |
| | 550 | else if ((mode & 0x47ff) == 0x0018) // DRAM |
| | 551 | { |
| | 552 | int inc = get_inc(mode); |
| | 553 | elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]); |
| | 554 | d = dram[addr]; |
| | 555 | ssp->pmac_read[reg] += inc; |
| | 556 | } |
| | 557 | else |
| | 558 | { |
| | 559 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x", |
| | 560 | reg, mode, CADDR, GET_PPC_OFFS()); |
| | 561 | d = 0; |
| | 562 | } |
| | 563 | } |
| | 564 | |
| | 565 | // PMC value corresponds to last PMR accessed (not sure). |
| | 566 | rPMC.v = ssp->pmac_read[write ? reg + 6 : reg]; |
| | 567 | |
| | 568 | return d; |
| | 569 | } |
| | 570 | |
| | 571 | return (u32)-1; |
| | 572 | } |
| | 573 | |
| | 574 | // 8 |
| | 575 | static u32 read_PM0(void) |
| | 576 | { |
| | 577 | u32 d = pm_io(0, 0, 0); |
| | 578 | if (d != (u32)-1) return d; |
| | 579 | elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS()); |
| | 580 | d = rPM0; |
| | 581 | #ifndef EMBED_INTERPRETER |
| | 582 | if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) { |
| | 583 | ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0"); |
| | 584 | } |
| | 585 | #endif |
| | 586 | rPM0 &= ~2; // ? |
| | 587 | return d; |
| | 588 | } |
| | 589 | |
| | 590 | static void write_PM0(u32 d) |
| | 591 | { |
| | 592 | u32 r = pm_io(0, 1, d); |
| | 593 | if (r != (u32)-1) return; |
| | 594 | elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
| | 595 | rPM0 = d; |
| | 596 | } |
| | 597 | |
| | 598 | // 9 |
| | 599 | static u32 read_PM1(void) |
| | 600 | { |
| | 601 | u32 d = pm_io(1, 0, 0); |
| | 602 | if (d != (u32)-1) return d; |
| | 603 | // can be removed? |
| | 604 | elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS()); |
| | 605 | return rPM1; |
| | 606 | } |
| | 607 | |
| | 608 | static void write_PM1(u32 d) |
| | 609 | { |
| | 610 | u32 r = pm_io(1, 1, d); |
| | 611 | if (r != (u32)-1) return; |
| | 612 | // can be removed? |
| | 613 | elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
| | 614 | rPM1 = d; |
| | 615 | } |
| | 616 | |
| | 617 | // 10 |
| | 618 | static u32 read_PM2(void) |
| | 619 | { |
| | 620 | u32 d = pm_io(2, 0, 0); |
| | 621 | if (d != (u32)-1) return d; |
| | 622 | // can be removed? |
| | 623 | elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS()); |
| | 624 | return rPM2; |
| | 625 | } |
| | 626 | |
| | 627 | static void write_PM2(u32 d) |
| | 628 | { |
| | 629 | u32 r = pm_io(2, 1, d); |
| | 630 | if (r != (u32)-1) return; |
| | 631 | // can be removed? |
| | 632 | elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
| | 633 | rPM2 = d; |
| | 634 | } |
| | 635 | |
| | 636 | // 11 |
| | 637 | static u32 read_XST(void) |
| | 638 | { |
| | 639 | // can be removed? |
| | 640 | u32 d = pm_io(3, 0, 0); |
| | 641 | if (d != (u32)-1) return d; |
| | 642 | |
| | 643 | elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS()); |
| | 644 | return rXST; |
| | 645 | } |
| | 646 | |
| | 647 | static void write_XST(u32 d) |
| | 648 | { |
| | 649 | // can be removed? |
| | 650 | u32 r = pm_io(3, 1, d); |
| | 651 | if (r != (u32)-1) return; |
| | 652 | |
| | 653 | elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS()); |
| | 654 | rPM0 |= 1; |
| | 655 | rXST = d; |
| | 656 | } |
| | 657 | |
| | 658 | // 12 |
| | 659 | static u32 read_PM4(void) |
| | 660 | { |
| | 661 | u32 d = pm_io(4, 0, 0); |
| | 662 | #ifndef EMBED_INTERPRETER |
| | 663 | if (d == 0) { |
| | 664 | switch (GET_PPC_OFFS()) { |
| | 665 | case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break; |
| | 666 | case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break; |
| | 667 | } |
| | 668 | } |
| | 669 | #endif |
| | 670 | if (d != (u32)-1) return d; |
| | 671 | // can be removed? |
| | 672 | elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS()); |
| | 673 | return rPM4; |
| | 674 | } |
| | 675 | |
| | 676 | static void write_PM4(u32 d) |
| | 677 | { |
| | 678 | u32 r = pm_io(4, 1, d); |
| | 679 | if (r != (u32)-1) return; |
| | 680 | // can be removed? |
| | 681 | elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
| | 682 | rPM4 = d; |
| | 683 | } |
| | 684 | |
| | 685 | // 14 |
| | 686 | static u32 read_PMC(void) |
| | 687 | { |
| | 688 | elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l, |
| | 689 | (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS()); |
| | 690 | if (ssp->emu_status & SSP_PMC_HAVE_ADDR) { |
| | 691 | //if (ssp->emu_status & SSP_PMC_SET) |
| | 692 | // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS()); |
| | 693 | ssp->emu_status |= SSP_PMC_SET; |
| | 694 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
| | 695 | return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf); |
| | 696 | } else { |
| | 697 | ssp->emu_status |= SSP_PMC_HAVE_ADDR; |
| | 698 | return rPMC.l; |
| | 699 | } |
| | 700 | } |
| | 701 | |
| | 702 | static void write_PMC(u32 d) |
| | 703 | { |
| | 704 | if (ssp->emu_status & SSP_PMC_HAVE_ADDR) { |
| | 705 | //if (ssp->emu_status & SSP_PMC_SET) |
| | 706 | // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS()); |
| | 707 | ssp->emu_status |= SSP_PMC_SET; |
| | 708 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
| | 709 | rPMC.h = d; |
| | 710 | elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS()); |
| | 711 | } else { |
| | 712 | ssp->emu_status |= SSP_PMC_HAVE_ADDR; |
| | 713 | rPMC.l = d; |
| | 714 | elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS()); |
| | 715 | } |
| | 716 | } |
| | 717 | |
| | 718 | // 15 |
| | 719 | static u32 read_AL(void) |
| | 720 | { |
| | 721 | if (*(PC-1) == 0x000f) |
| | 722 | elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS()); |
| | 723 | ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ? |
| | 724 | return rAL; |
| | 725 | } |
| | 726 | |
| | 727 | static void write_AL(u32 d) |
| | 728 | { |
| | 729 | rAL = d; |
| | 730 | } |
| | 731 | |
| | 732 | |
| | 733 | typedef u32 (*read_func_t)(void); |
| | 734 | typedef void (*write_func_t)(u32 d); |
| | 735 | |
| | 736 | static read_func_t read_handlers[16] = |
| | 737 | { |
| | 738 | read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A |
| | 739 | read_unknown, // 4 ST |
| | 740 | read_STACK, |
| | 741 | read_PC, |
| | 742 | read_P, |
| | 743 | read_PM0, // 8 |
| | 744 | read_PM1, |
| | 745 | read_PM2, |
| | 746 | read_XST, |
| | 747 | read_PM4, // 12 |
| | 748 | read_unknown, // 13 gr13 |
| | 749 | read_PMC, |
| | 750 | read_AL |
| | 751 | }; |
| | 752 | |
| | 753 | static write_func_t write_handlers[16] = |
| | 754 | { |
| | 755 | write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A |
| | 756 | // write_unknown, // 4 ST |
| | 757 | write_ST, // 4 ST (debug hook) |
| | 758 | write_STACK, |
| | 759 | write_PC, |
| | 760 | write_unknown, // 7 P |
| | 761 | write_PM0, // 8 |
| | 762 | write_PM1, |
| | 763 | write_PM2, |
| | 764 | write_XST, |
| | 765 | write_PM4, // 12 |
| | 766 | write_unknown, // 13 gr13 |
| | 767 | write_PMC, |
| | 768 | write_AL |
| | 769 | }; |
| | 770 | |
| | 771 | // ----------------------------------------------------- |
| | 772 | // pointer register handlers |
| | 773 | |
| | 774 | // |
| | 775 | #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18) |
| | 776 | |
| | 777 | static u32 ptr1_read_(int ri, int isj2, int modi3) |
| | 778 | { |
| | 779 | //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18); |
| | 780 | u32 mask, add = 0, t = ri | isj2 | modi3; |
| | 781 | unsigned char *rp = NULL; |
| | 782 | switch (t) |
| | 783 | { |
| | 784 | // mod=0 (00) |
| | 785 | case 0x00: |
| | 786 | case 0x01: |
| | 787 | case 0x02: return ssp->RAM0[ssp->r0[t&3]]; |
| | 788 | case 0x03: return ssp->RAM0[0]; |
| | 789 | case 0x04: |
| | 790 | case 0x05: |
| | 791 | case 0x06: return ssp->RAM1[ssp->r1[t&3]]; |
| | 792 | case 0x07: return ssp->RAM1[0]; |
| | 793 | // mod=1 (01), "+!" |
| | 794 | case 0x08: |
| | 795 | case 0x09: |
| | 796 | case 0x0a: return ssp->RAM0[ssp->r0[t&3]++]; |
| | 797 | case 0x0b: return ssp->RAM0[1]; |
| | 798 | case 0x0c: |
| | 799 | case 0x0d: |
| | 800 | case 0x0e: return ssp->RAM1[ssp->r1[t&3]++]; |
| | 801 | case 0x0f: return ssp->RAM1[1]; |
| | 802 | // mod=2 (10), "-" |
| | 803 | case 0x10: |
| | 804 | case 0x11: |
| | 805 | case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp]; |
| | 806 | if (!(rST&7)) { (*rp)--; return t; } |
| | 807 | add = -1; goto modulo; |
| | 808 | case 0x13: return ssp->RAM0[2]; |
| | 809 | case 0x14: |
| | 810 | case 0x15: |
| | 811 | case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp]; |
| | 812 | if (!(rST&7)) { (*rp)--; return t; } |
| | 813 | add = -1; goto modulo; |
| | 814 | case 0x17: return ssp->RAM1[2]; |
| | 815 | // mod=3 (11), "+" |
| | 816 | case 0x18: |
| | 817 | case 0x19: |
| | 818 | case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp]; |
| | 819 | if (!(rST&7)) { (*rp)++; return t; } |
| | 820 | add = 1; goto modulo; |
| | 821 | case 0x1b: return ssp->RAM0[3]; |
| | 822 | case 0x1c: |
| | 823 | case 0x1d: |
| | 824 | case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp]; |
| | 825 | if (!(rST&7)) { (*rp)++; return t; } |
| | 826 | add = 1; goto modulo; |
| | 827 | case 0x1f: return ssp->RAM1[3]; |
| | 828 | } |
| | 829 | |
| | 830 | return 0; |
| | 831 | |
| | 832 | modulo: |
| | 833 | mask = (1 << (rST&7)) - 1; |
| | 834 | *rp = (*rp & ~mask) | ((*rp + add) & mask); |
| | 835 | return t; |
| | 836 | } |
| | 837 | |
| | 838 | static void ptr1_write(int op, u32 d) |
| | 839 | { |
| | 840 | int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18); |
| | 841 | switch (t) |
| | 842 | { |
| | 843 | // mod=0 (00) |
| | 844 | case 0x00: |
| | 845 | case 0x01: |
| | 846 | case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return; |
| | 847 | case 0x03: ssp->RAM0[0] = d; return; |
| | 848 | case 0x04: |
| | 849 | case 0x05: |
| | 850 | case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return; |
| | 851 | case 0x07: ssp->RAM1[0] = d; return; |
| | 852 | // mod=1 (01), "+!" |
| | 853 | // mod=3, "+" |
| | 854 | case 0x08: |
| | 855 | case 0x09: |
| | 856 | case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return; |
| | 857 | case 0x0b: ssp->RAM0[1] = d; return; |
| | 858 | case 0x0c: |
| | 859 | case 0x0d: |
| | 860 | case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return; |
| | 861 | case 0x0f: ssp->RAM1[1] = d; return; |
| | 862 | // mod=2 (10), "-" |
| | 863 | case 0x10: |
| | 864 | case 0x11: |
| | 865 | case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return; |
| | 866 | case 0x13: ssp->RAM0[2] = d; return; |
| | 867 | case 0x14: |
| | 868 | case 0x15: |
| | 869 | case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return; |
| | 870 | case 0x17: ssp->RAM1[2] = d; return; |
| | 871 | // mod=3 (11), "+" |
| | 872 | case 0x18: |
| | 873 | case 0x19: |
| | 874 | case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return; |
| | 875 | case 0x1b: ssp->RAM0[3] = d; return; |
| | 876 | case 0x1c: |
| | 877 | case 0x1d: |
| | 878 | case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return; |
| | 879 | case 0x1f: ssp->RAM1[3] = d; return; |
| | 880 | } |
| | 881 | } |
| | 882 | |
| | 883 | static u32 ptr2_read(int op) |
| | 884 | { |
| | 885 | int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18); |
| | 886 | switch (t) |
| | 887 | { |
| | 888 | // mod=0 (00) |
| | 889 | case 0x00: |
| | 890 | case 0x01: |
| | 891 | case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break; |
| | 892 | case 0x03: mv = ssp->RAM0[0]++; break; |
| | 893 | case 0x04: |
| | 894 | case 0x05: |
| | 895 | case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break; |
| | 896 | case 0x07: mv = ssp->RAM1[0]++; break; |
| | 897 | // mod=1 (01) |
| | 898 | case 0x0b: mv = ssp->RAM0[1]++; break; |
| | 899 | case 0x0f: mv = ssp->RAM1[1]++; break; |
| | 900 | // mod=2 (10) |
| | 901 | case 0x13: mv = ssp->RAM0[2]++; break; |
| | 902 | case 0x17: mv = ssp->RAM1[2]++; break; |
| | 903 | // mod=3 (11) |
| | 904 | case 0x1b: mv = ssp->RAM0[3]++; break; |
| | 905 | case 0x1f: mv = ssp->RAM1[3]++; break; |
| | 906 | default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS()); |
| | 907 | return 0; |
| | 908 | } |
| | 909 | |
| | 910 | return ((unsigned short *)svp->iram_rom)[mv]; |
| | 911 | } |
| | 912 | |
| | 913 | |
| | 914 | // ----------------------------------------------------- |
| | 915 | |
| | 916 | #if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER) |
| | 917 | static void debug_dump2file(const char *fname, void *mem, int len) |
| | 918 | { |
| | 919 | FILE *f = fopen(fname, "wb"); |
| | 920 | unsigned short *p = mem; |
| | 921 | int i; |
| | 922 | if (f) { |
| | 923 | for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8); |
| | 924 | fwrite(mem, 1, len, f); |
| | 925 | fclose(f); |
| | 926 | for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8); |
| | 927 | printf("dumped to %s\n", fname); |
| | 928 | } |
| | 929 | else |
| | 930 | printf("dump failed\n"); |
| | 931 | } |
| | 932 | #endif |
| | 933 | |
| | 934 | #ifdef USE_DEBUGGER |
| | 935 | static void debug_dump(void) |
| | 936 | { |
| | 937 | printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v); |
| | 938 | printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v); |
| | 939 | printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2); |
| | 940 | printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v); |
| | 941 | printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v', |
| | 942 | rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1); |
| | 943 | printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1], |
| | 944 | ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]); |
| | 945 | printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]); |
| | 946 | elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status); |
| | 947 | } |
| | 948 | |
| | 949 | static void debug_dump_mem(void) |
| | 950 | { |
| | 951 | int h, i; |
| | 952 | printf("RAM0\n"); |
| | 953 | for (h = 0; h < 32; h++) |
| | 954 | { |
| | 955 | if (h == 16) printf("RAM1\n"); |
| | 956 | printf("%03x:", h*16); |
| | 957 | for (i = 0; i < 16; i++) |
| | 958 | printf(" %04x", ssp->RAM[h*16+i]); |
| | 959 | printf("\n"); |
| | 960 | } |
| | 961 | } |
| | 962 | |
| | 963 | static int bpts[10] = { 0, }; |
| | 964 | |
| | 965 | static void debug(unsigned int pc, unsigned int op) |
| | 966 | { |
| | 967 | static char buffo[64] = {0,}; |
| | 968 | char buff[64] = {0,}; |
| | 969 | int i; |
| | 970 | |
| | 971 | if (running) { |
| | 972 | for (i = 0; i < 10; i++) |
| | 973 | if (pc != 0 && bpts[i] == pc) { |
| | 974 | printf("breakpoint %i\n", i); |
| | 975 | running = 0; |
| | 976 | break; |
| | 977 | } |
| | 978 | } |
| | 979 | if (running) return; |
| | 980 | |
| | 981 | printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1); |
| | 982 | |
| | 983 | while (1) |
| | 984 | { |
| | 985 | printf("dbg> "); |
| | 986 | fflush(stdout); |
| | 987 | fgets(buff, sizeof(buff), stdin); |
| | 988 | if (buff[0] == '\n') strcpy(buff, buffo); |
| | 989 | else strcpy(buffo, buff); |
| | 990 | |
| | 991 | switch (buff[0]) { |
| | 992 | case 0: exit(0); |
| | 993 | case 'c': |
| | 994 | case 'r': running = 1; return; |
| | 995 | case 's': |
| | 996 | case 'n': return; |
| | 997 | case 'x': debug_dump(); break; |
| | 998 | case 'm': debug_dump_mem(); break; |
| | 999 | case 'b': { |
| | 1000 | char *baddr = buff + 2; |
| | 1001 | i = 0; |
| | 1002 | if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; } |
| | 1003 | bpts[i] = strtol(baddr, NULL, 16) >> 1; |
| | 1004 | printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1); |
| | 1005 | break; |
| | 1006 | } |
| | 1007 | case 'd': |
| | 1008 | sprintf(buff, "iramrom_%04x.bin", last_iram); |
| | 1009 | debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom)); |
| | 1010 | debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram)); |
| | 1011 | break; |
| | 1012 | default: printf("unknown command\n"); break; |
| | 1013 | } |
| | 1014 | } |
| | 1015 | } |
| | 1016 | #endif // USE_DEBUGGER |
| | 1017 | |
| | 1018 | |
| | 1019 | void ssp1601_reset(ssp1601_t *l_ssp) |
| | 1020 | { |
| | 1021 | ssp = l_ssp; |
| | 1022 | ssp->emu_status = 0; |
| | 1023 | ssp->gr[SSP_GR0].v = 0xffff0000; |
| | 1024 | rPC = 0x400; |
| | 1025 | rSTACK = 0; // ? using ascending stack |
| | 1026 | rST = 0; |
| | 1027 | } |
| | 1028 | |
| | 1029 | |
| | 1030 | void ssp1601_run(int cycles) |
| | 1031 | { |
| | 1032 | #ifndef EMBED_INTERPRETER |
| | 1033 | SET_PC(rPC); |
| | 1034 | #endif |
| | 1035 | g_cycles = cycles; |
| | 1036 | |
| | 1037 | while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK)) |
| | 1038 | { |
| | 1039 | int op; |
| | 1040 | u32 tmpv; |
| | 1041 | |
| | 1042 | op = *PC++; |
| | 1043 | #ifdef USE_DEBUGGER |
| | 1044 | debug(GET_PC()-1, op); |
| | 1045 | #endif |
| | 1046 | switch (op >> 9) |
| | 1047 | { |
| | 1048 | // ld d, s |
| | 1049 | case 0x00: |
| | 1050 | CHECK_B_SET(); |
| | 1051 | if (op == 0) break; // nop |
| | 1052 | if (op == ((SSP_A<<4)|SSP_P)) { // A <- P |
| | 1053 | // not sure. MAME claims that only hi word is transfered. |
| | 1054 | read_P(); // update P |
| | 1055 | rA32 = rP.v; |
| | 1056 | } |
| | 1057 | else |
| | 1058 | { |
| | 1059 | tmpv = REG_READ(op & 0x0f); |
| | 1060 | REG_WRITE((op & 0xf0) >> 4, tmpv); |
| | 1061 | } |
| | 1062 | break; |
| | 1063 | |
| | 1064 | // ld d, (ri) |
| | 1065 | case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break; |
| | 1066 | |
| | 1067 | // ld (ri), s |
| | 1068 | case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break; |
| | 1069 | |
| | 1070 | // ldi d, imm |
| | 1071 | case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break; |
| | 1072 | |
| | 1073 | // ld d, ((ri)) |
| | 1074 | case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break; |
| | 1075 | |
| | 1076 | // ldi (ri), imm |
| | 1077 | case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break; |
| | 1078 | |
| | 1079 | // ld adr, a |
| | 1080 | case 0x07: ssp->RAM[op & 0x1ff] = rA; break; |
| | 1081 | |
| | 1082 | // ld d, ri |
| | 1083 | case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break; |
| | 1084 | |
| | 1085 | // ld ri, s |
| | 1086 | case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break; |
| | 1087 | |
| | 1088 | // ldi ri, simm |
| | 1089 | case 0x0c: |
| | 1090 | case 0x0d: |
| | 1091 | case 0x0e: |
| | 1092 | case 0x0f: rIJ[(op>>8)&7] = op; break; |
| | 1093 | |
| | 1094 | // call cond, addr |
| | 1095 | case 0x24: { |
| | 1096 | int cond = 0; |
| | 1097 | CHECK_00f(); |
| | 1098 | COND_CHECK |
| | 1099 | if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); } |
| | 1100 | else PC++; |
| | 1101 | g_cycles--; // always 2 cycles |
| | 1102 | break; |
| | 1103 | } |
| | 1104 | |
| | 1105 | // ld d, (a) |
| | 1106 | case 0x25: |
| | 1107 | CHECK_10f(); |
| | 1108 | tmpv = ((unsigned short *)svp->iram_rom)[rA]; |
| | 1109 | REG_WRITE((op & 0xf0) >> 4, tmpv); |
| | 1110 | g_cycles -= 2; // 3 cycles total |
| | 1111 | break; |
| | 1112 | |
| | 1113 | // bra cond, addr |
| | 1114 | case 0x26: { |
| | 1115 | int cond = 0; |
| | 1116 | CHECK_00f(); |
| | 1117 | COND_CHECK |
| | 1118 | if (cond) { int new_PC = *PC++; SET_PC(new_PC); } |
| | 1119 | else PC++; |
| | 1120 | g_cycles--; |
| | 1121 | break; |
| | 1122 | } |
| | 1123 | |
| | 1124 | // mod cond, op |
| | 1125 | case 0x48: { |
| | 1126 | int cond = 0; |
| | 1127 | CHECK_008(); |
| | 1128 | COND_CHECK |
| | 1129 | if (cond) { |
| | 1130 | switch (op & 7) { |
| | 1131 | case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic) |
| | 1132 | case 3: rA32 <<= 1; break; // shl |
| | 1133 | case 6: rA32 = -(signed int)rA32; break; // neg |
| | 1134 | case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs |
| | 1135 | default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x", |
| | 1136 | op&7, GET_PPC_OFFS()); |
| | 1137 | } |
| | 1138 | UPD_ACC_ZN |
| | 1139 | } |
| | 1140 | break; |
| | 1141 | } |
| | 1142 | |
| | 1143 | // mpys? |
| | 1144 | case 0x1b: |
| | 1145 | CHECK_B_CLEAR(); |
| | 1146 | read_P(); // update P |
| | 1147 | rA32 -= rP.v; |
| | 1148 | UPD_ACC_ZN |
| | 1149 | rX = ptr1_read_(op&3, 0, (op<<1)&0x18); |
| | 1150 | rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); |
| | 1151 | break; |
| | 1152 | |
| | 1153 | // mpya (rj), (ri), b |
| | 1154 | case 0x4b: |
| | 1155 | CHECK_B_CLEAR(); |
| | 1156 | read_P(); // update P |
| | 1157 | rA32 += rP.v; |
| | 1158 | UPD_ACC_ZN |
| | 1159 | rX = ptr1_read_(op&3, 0, (op<<1)&0x18); |
| | 1160 | rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); |
| | 1161 | break; |
| | 1162 | |
| | 1163 | // mld (rj), (ri), b |
| | 1164 | case 0x5b: |
| | 1165 | CHECK_B_CLEAR(); |
| | 1166 | rA32 = 0; |
| | 1167 | rST &= 0x0fff; |
| | 1168 | rST |= SSP_FLAG_Z; |
| | 1169 | rX = ptr1_read_(op&3, 0, (op<<1)&0x18); |
| | 1170 | rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); |
| | 1171 | break; |
| | 1172 | |
| | 1173 | // OP a, s |
| | 1174 | case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break; |
| | 1175 | case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break; |
| | 1176 | case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break; |
| | 1177 | case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break; |
| | 1178 | case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break; |
| | 1179 | case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break; |
| | 1180 | |
| | 1181 | // OP a, (ri) |
| | 1182 | case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break; |
| | 1183 | case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break; |
| | 1184 | case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break; |
| | 1185 | case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break; |
| | 1186 | case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break; |
| | 1187 | case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break; |
| | 1188 | |
| | 1189 | // OP a, adr |
| | 1190 | case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break; |
| | 1191 | case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break; |
| | 1192 | case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break; |
| | 1193 | case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break; |
| | 1194 | case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break; |
| | 1195 | case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break; |
| | 1196 | case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break; |
| | 1197 | |
| | 1198 | // OP a, imm |
| | 1199 | case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break; |
| | 1200 | case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break; |
| | 1201 | case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break; |
| | 1202 | case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break; |
| | 1203 | case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break; |
| | 1204 | case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break; |
| | 1205 | |
| | 1206 | // OP a, ((ri)) |
| | 1207 | case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break; |
| | 1208 | case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break; |
| | 1209 | case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break; |
| | 1210 | case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break; |
| | 1211 | case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break; |
| | 1212 | case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break; |
| | 1213 | |
| | 1214 | // OP a, ri |
| | 1215 | case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break; |
| | 1216 | case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break; |
| | 1217 | case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break; |
| | 1218 | case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break; |
| | 1219 | case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break; |
| | 1220 | case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break; |
| | 1221 | |
| | 1222 | // OP simm |
| | 1223 | case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break; |
| | 1224 | case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break; |
| | 1225 | case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break; |
| | 1226 | case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break; |
| | 1227 | case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break; |
| | 1228 | case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break; |
| | 1229 | |
| | 1230 | default: |
| | 1231 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS()); |
| | 1232 | break; |
| | 1233 | } |
| | 1234 | g_cycles--; |
| | 1235 | } |
| | 1236 | |
| | 1237 | rPC = GET_PC(); |
| | 1238 | read_P(); // update P |
| | 1239 | } |
| | 1240 | |
notaz.gp2x.de / picodrive.git / blame_incremental