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SVP save support
[picodrive.git] / Pico / carthw / svp / ssp16.c
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1// basic, incomplete SSP160x (SSP1601?) interpreter
2// with SVP memory controller emu
3
4// (c) Copyright 2008, Grazvydas "notaz" Ignotas
5// Free for non-commercial use.
6
7// For commercial use, separate licencing terms must be obtained.
8
9
10#include "../../PicoInt.h"
11
12/*
13 * Register info
14 *
15 * 0. "-"
16 * size: 16
17 * desc: Constant register with all bits set (0xffff).
18 *
19 * 1. "X"
20 * size: 16
21 * desc: Generic register. When set, updates P (P = X * Y * 2)
22 *
23 * 2. "Y"
24 * size: 16
25 * desc: Generic register. When set, updates P (P = X * Y * 2)
26 *
27 * 3. "A"
28 * size: 32
29 * desc: Accumulator.
30 *
31 * 4. "ST"
32 * size: 16
33 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
34 * fedc ba98 7654 3210
35 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
36 * modulo-increment and modulo-decrement. The value shows which
37 * power of 2 to use, i.e. 4 means modulo by 16.
38 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
39 * 43 - RB (?)
40 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
41 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
42 * datasheet says these (5,6) bits correspond to hardware pins.
43 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
44 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
45 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
46 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
47 * a - GPI_0 Interrupt 0 enable/status?
48 * b - GPI_1 Interrupt 1 enable/status?
49 * c - L L flag. Carry?
50 * d - Z Zero flag.
51 * e - OV Overflow flag.
52 * f - N Negative flag.
53 * seen directly changing code sequences:
54 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
55 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
56 * ld ST, A ld ST, A ori 3
57 * ld ST, A
58 *
59 * 5. "STACK"
60 * size: 16
61 * desc: hw stack of 6 levels (according to datasheet)
62 *
63 * 6. "PC"
64 * size: 16
65 * desc: Program counter.
66 *
67 * 7. "P"
68 * size: 32
69 * desc: multiply result register. P = X * Y * 2
70 * probably affected by MACS bit in ST.
71 *
72 * 8. "PM0" (PM from PMAR name from Tasco's docs)
73 * size: 16?
74 * desc: Programmable Memory access register.
75 * On reset, or when one (both?) GP0 bits are clear,
76 * acts as status for XST, mapped at 015004 at 68k side:
77 * bit0: ssp has written something to XST (cleared when 015004 is read)
78 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
79 *
80 * 9. "PM1"
81 * size: 16?
82 * desc: Programmable Memory access register.
83 * This reg. is only used as PMAR.
84 *
85 * 10. "PM2"
86 * size: 16?
87 * desc: Programmable Memory access register.
88 * This reg. is only used as PMAR.
89 *
90 * 11. "XST"
91 * size: 16?
92 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
93 * Can be programmed as PMAR? (only seen in test mode code)
94 * Affects PM0 when written to?
95 *
96 * 12. "PM4"
97 * size: 16?
98 * desc: Programmable Memory access register.
99 * This reg. is only used as PMAR. The most used PMAR by VR.
100 *
101 * 13. (unused by VR)
102 *
103 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
104 * size: 32?
105 * desc: Programmable Memory access Control. Set using 2 16bit writes,
106 * first address, then mode word. After setting PMAC, PMAR sould
107 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
108 * reading and writing respectively.
109 * Reading the register also shifts it's state (from "waiting for
110 * address" to "waiting for mode" and back). Reads always return
111 * address related to last PMx register accressed.
112 * (note: addresses do not wrap).
113 *
114 * 15. "AL"
115 * size: 16
116 * desc: Accumulator Low. 16 least significant bits of accumulator.
117 * (normally reading acc (ld X, A) you get 16 most significant bits).
118 *
119 *
120 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
121 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
122 * which work similar to * and ** operators in C, only they use different memory banks and
123 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
124 * program memory at address read from (rX), and increments value in (rX).
125 *
126 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
127 * 3 modifiers can be applied (optional):
128 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
129 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
130 * +!: post-increment, unaffected by RPL (probably).
131 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
132 * ar probably invalid.
133 *
134 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
135 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
136 * Samsung's old DSP page claims that).
137 * 1 of these 4 modifiers must be used (short form direct addressing?):
138 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
139 * |01: RAMx[1]
140 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
141 * |11: RAMx[3]
142 *
143 *
144 * Instruction notes
145 *
146 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
147 *
148 * mld (rj), (ri) [, b]
149 * operation: A = 0; P = (rj) * (ri)
150 * notes: based on IIR_4B.SC sample. flags? what is b???
151 *
152 * mpya (rj), (ri) [, b]
153 * name: multiply and add?
154 * operation: A += P; P = (rj) * (ri)
155 *
156 * mpys (rj), (ri), b
157 * name: multiply and subtract?
158 * notes: not used by VR code.
159 *
160 * mod cond, op
161 * mod cond, shr does arithmetic shift
162 *
163 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
164 *
165 * memory map:
166 * 000000 - 1fffff ROM, accessable by both
167 * 200000 - 2fffff unused?
168 * 300000 - 31ffff DRAM, both
169 * 320000 - 38ffff unused?
170 * 390000 - 3907ff IRAM. can only be accessed by ssp?
171 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
172 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
173 *
174 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
175 * 30fe06 - also sync related.
176 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
177 *
178 * + figure out if 'op A, P' is 32bit (nearly sure it is)
179 * * does mld, mpya load their operands into X and Y?
180 * * OP simm
181 *
182 * Assumptions in this code
183 * P is not directly writeable
184 * flags correspond to full 32bit accumulator
185 * only Z and N status flags are emulated (others unused by SVP)
186 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
187 * 'ld d, (a)' loads from program ROM
188 */
189
190#include "../../PicoInt.h"
191
192#define u32 unsigned int
193
194//#define USE_DEBUGGER
195
196// 0
197#define rX ssp->gr[SSP_X].h
198#define rY ssp->gr[SSP_Y].h
199#define rA ssp->gr[SSP_A].h
200#define rST ssp->gr[SSP_ST].h // 4
201#define rSTACK ssp->gr[SSP_STACK].h
202#define rPC ssp->gr[SSP_PC].h
203#define rP ssp->gr[SSP_P]
204#define rPM0 ssp->gr[SSP_PM0].h // 8
205#define rPM1 ssp->gr[SSP_PM1].h
206#define rPM2 ssp->gr[SSP_PM2].h
207#define rXST ssp->gr[SSP_XST].h
208#define rPM4 ssp->gr[SSP_PM4].h // 12
209// 13
210#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
211#define rAL ssp->gr[SSP_A].l
212
213#define rA32 ssp->gr[SSP_A].v
214#define rIJ ssp->r
215
216#define IJind (((op>>6)&4)|(op&3))
217
218#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
219#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
220#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
221
222#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
223#define REG_WRITE(r,d) { \
224 int r1 = r; \
225 if (r1 >= 4) write_handlers[r1](d); \
226 else if (r1 > 0) ssp->gr[r1].h = d; \
227}
228
229// flags
230#define SSP_FLAG_L (1<<0xc)
231#define SSP_FLAG_Z (1<<0xd)
232#define SSP_FLAG_V (1<<0xe)
233#define SSP_FLAG_N (1<<0xf)
234
235// update ZN according to 32bit ACC.
236#define UPD_ACC_ZN \
237 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
238 if (!rA32) rST |= SSP_FLAG_Z; \
239 else rST |= (rA32>>16)&SSP_FLAG_N;
240
241// it seems SVP code never checks for L and OV, so we leave them out.
242// rST |= (t>>4)&SSP_FLAG_L;
243#define UPD_LZVN \
244 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
245 if (!rA32) rST |= SSP_FLAG_Z; \
246 else rST |= (rA32>>16)&SSP_FLAG_N;
247
248// standard cond processing.
249// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
250#define COND_CHECK \
251 switch (op&0xf0) { \
252 case 0x00: cond = 1; break; /* always true */ \
253 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
254 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
255 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
256 }
257
258// ops with accumulator.
259// how is low word really affected by these?
260// nearly sure 'ld A' doesn't affect flags
261#define OP_LDA(x) \
262 ssp->gr[SSP_A].h = x
263
264#define OP_LDA32(x) \
265 rA32 = x
266
267#define OP_SUBA(x) { \
268 rA32 -= (x) << 16; \
269 UPD_LZVN \
270}
271
272#define OP_SUBA32(x) { \
273 rA32 -= (x); \
274 UPD_LZVN \
275}
276
277#define OP_CMPA(x) { \
278 u32 t = rA32 - ((x) << 16); \
279 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
280 if (!t) rST |= SSP_FLAG_Z; \
281 else rST |= (t>>16)&SSP_FLAG_N; \
282}
283
284#define OP_CMPA32(x) { \
285 u32 t = rA32 - (x); \
286 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
287 if (!t) rST |= SSP_FLAG_Z; \
288 else rST |= (t>>16)&SSP_FLAG_N; \
289}
290
291#define OP_ADDA(x) { \
292 rA32 += (x) << 16; \
293 UPD_LZVN \
294}
295
296#define OP_ADDA32(x) { \
297 rA32 += (x); \
298 UPD_LZVN \
299}
300
301#define OP_ANDA(x) \
302 rA32 &= (x) << 16; \
303 UPD_ACC_ZN
304
305#define OP_ANDA32(x) \
306 rA32 &= (x); \
307 UPD_ACC_ZN
308
309#define OP_ORA(x) \
310 rA32 |= (x) << 16; \
311 UPD_ACC_ZN
312
313#define OP_ORA32(x) \
314 rA32 |= (x); \
315 UPD_ACC_ZN
316
317#define OP_EORA(x) \
318 rA32 ^= (x) << 16; \
319 UPD_ACC_ZN
320
321#define OP_EORA32(x) \
322 rA32 ^= (x); \
323 UPD_ACC_ZN
324
325
326#define OP_CHECK32(OP) \
327 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
328 read_P(); /* update P */ \
329 OP(ssp->gr[SSP_P].v); \
330 break; \
331}
332
333
334static ssp1601_t *ssp = NULL;
335static unsigned short *PC;
336static int g_cycles;
337
338#ifdef USE_DEBUGGER
339static int running = 0;
340static int last_iram = 0;
341#endif
342
343// -----------------------------------------------------
344// register i/o handlers
345
346// 0-4, 13
347static u32 read_unknown(void)
348{
349 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
350 return 0;
351}
352
353static void write_unknown(u32 d)
354{
355 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
356}
357
358// 4
359static void write_ST(u32 d)
360{
361 //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
362 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
363 rST = d;
364}
365
366// 5
367static u32 read_STACK(void)
368{
369 --rSTACK;
370 if ((short)rSTACK < 0) {
371 rSTACK = 5;
372 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
373 }
374 return ssp->stack[rSTACK];
375}
376
377static void write_STACK(u32 d)
378{
379 if (rSTACK >= 6) {
380 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
381 rSTACK = 0;
382 }
383 ssp->stack[rSTACK++] = d;
384}
385
386// 6
387static u32 read_PC(void)
388{
389 return GET_PC();
390}
391
392static void write_PC(u32 d)
393{
394 SET_PC(d);
395 g_cycles--;
396}
397
398// 7
399static u32 read_P(void)
400{
401 int m1 = (signed short)rX;
402 int m2 = (signed short)rY;
403 rP.v = (m1 * m2 * 2);
404 return rP.h;
405}
406
407// -----------------------------------------------------
408
409static int get_inc(int mode)
410{
411 int inc = (mode >> 11) & 7;
412 if (inc != 0) {
413 if (inc != 7) inc--;
414 inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
415 if (mode & 0x8000) inc = -inc; // decrement mode
416 }
417 return inc;
418}
419
420#define overwite_write(dst, d) \
421{ \
422 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
423 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
424 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
425 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
426}
427
428static u32 pm_io(int reg, int write, u32 d)
429{
430 if (ssp->emu_status & SSP_PMC_SET)
431 {
432 // this MUST be blind r or w
433 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
434 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
435 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
436 ssp->emu_status &= ~SSP_PMC_SET;
437 return 0;
438 }
439 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
440 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
441 ssp->emu_status &= ~SSP_PMC_SET;
442 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
443 elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
444#ifdef USE_DEBUGGER
445 last_iram = (ssp->RAM1[0]-1)<<1;
446#endif
447 }
448 return 0;
449 }
450
451 // just in case
452 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
453 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
454 reg, write ? 'w' : 'r', GET_PPC_OFFS());
455 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
456 }
457
458 if (reg == 4 || (rST & 0x60))
459 {
460 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
461 unsigned short *dram = (unsigned short *)svp->dram;
462 if (write)
463 {
464 int mode = ssp->pmac_write[reg]&0xffff;
465 int addr = ssp->pmac_write[reg]>>16;
466 if ((mode & 0xb800) == 0xb800)
467 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
468 if ((mode & 0x43ff) == 0x0018) // DRAM
469 {
470 int inc = get_inc(mode);
471 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
472 reg, CADDR, d, inc >> 16, (mode>>10)&1);
473 if (mode & 0x0400) {
474 overwite_write(dram[addr], d);
475 } else dram[addr] = d;
476 ssp->pmac_write[reg] += inc;
477 }
478 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
479 {
480 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
481 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
482 if (mode & 0x0400) {
483 overwite_write(dram[addr], d);
484 } else dram[addr] = d;
485 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
486 }
487 else if ((mode & 0x47ff) == 0x001c) // IRAM
488 {
489 int inc = get_inc(mode);
490 if ((addr&0xfc00) != 0x8000)
491 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
492 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
493 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
494 ssp->pmac_write[reg] += inc;
495 }
496 else
497 {
498 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
499 reg, mode, CADDR, d, GET_PPC_OFFS());
500 }
501 }
502 else
503 {
504 int mode = ssp->pmac_read[reg]&0xffff;
505 int addr = ssp->pmac_read[reg]>>16;
506 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
507 {
508 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
509 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
510 if ((signed int)ssp->pmac_read[reg] >> 16 == -1)
511 ssp->pmac_read[reg]++;
512 ssp->pmac_read[reg] += 1<<16;
513 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
514 }
515 else if ((mode & 0x47ff) == 0x0018) // DRAM
516 {
517 int inc = get_inc(mode);
518 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
519 d = dram[addr];
520 ssp->pmac_read[reg] += inc;
521 }
522 else
523 {
524 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
525 reg, mode, CADDR, GET_PPC_OFFS());
526 d = 0;
527 }
528 }
529
530 // PMC value corresponds to last PMR accessed (not sure).
531 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
532
533 return d;
534 }
535
536 return (u32)-1;
537}
538
539// 8
540static u32 read_PM0(void)
541{
542 u32 d = pm_io(0, 0, 0);
543 if (d != (u32)-1) return d;
544 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
545 d = rPM0;
546 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
547 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
548 }
549 rPM0 &= ~2; // ?
550 return d;
551}
552
553static void write_PM0(u32 d)
554{
555 u32 r = pm_io(0, 1, d);
556 if (r != (u32)-1) return;
557 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
558 rPM0 = d;
559}
560
561// 9
562static u32 read_PM1(void)
563{
564 u32 d = pm_io(1, 0, 0);
565 if (d != (u32)-1) return d;
566 // can be removed?
567 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
568 return rPM1;
569}
570
571static void write_PM1(u32 d)
572{
573 u32 r = pm_io(1, 1, d);
574 if (r != (u32)-1) return;
575 // can be removed?
576 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
577 rPM1 = d;
578}
579
580// 10
581static u32 read_PM2(void)
582{
583 u32 d = pm_io(2, 0, 0);
584 if (d != (u32)-1) return d;
585 // can be removed?
586 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
587 return rPM2;
588}
589
590static void write_PM2(u32 d)
591{
592 u32 r = pm_io(2, 1, d);
593 if (r != (u32)-1) return;
594 // can be removed?
595 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
596 rPM2 = d;
597}
598
599// 11
600static u32 read_XST(void)
601{
602 // can be removed?
603 u32 d = pm_io(3, 0, 0);
604 if (d != (u32)-1) return d;
605
606 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
607 return rXST;
608}
609
610static void write_XST(u32 d)
611{
612 // can be removed?
613 u32 r = pm_io(3, 1, d);
614 if (r != (u32)-1) return;
615
616 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
617 rPM0 |= 1;
618 rXST = d;
619}
620
621// 12
622static u32 read_PM4(void)
623{
624 u32 d = pm_io(4, 0, 0);
625 if (d == 0) {
626 switch (GET_PPC_OFFS()) {
627 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
628 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
629 }
630 }
631 if (d != (u32)-1) return d;
632 // can be removed?
633 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
634 return rPM4;
635}
636
637static void write_PM4(u32 d)
638{
639 u32 r = pm_io(4, 1, d);
640 if (r != (u32)-1) return;
641 // can be removed?
642 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
643 rPM4 = d;
644}
645
646// 14
647static u32 read_PMC(void)
648{
649 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
650 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
651 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
652 //if (ssp->emu_status & SSP_PMC_SET)
653 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
654 ssp->emu_status |= SSP_PMC_SET;
655 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
656 return ((rPMC.h << 4) & 0xfff0) | ((rPMC.h >> 4) & 0xf);
657 } else {
658 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
659 return rPMC.h;
660 }
661}
662
663static void write_PMC(u32 d)
664{
665 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
666 //if (ssp->emu_status & SSP_PMC_SET)
667 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
668 ssp->emu_status |= SSP_PMC_SET;
669 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
670 rPMC.l = d;
671 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
672 } else {
673 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
674 rPMC.h = d;
675 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
676 }
677}
678
679// 15
680static u32 read_AL(void)
681{
682 if (*(PC-1) == 0x000f) {
683 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
684 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
685 }
686 return rAL;
687}
688
689static void write_AL(u32 d)
690{
691 rAL = d;
692}
693
694
695typedef u32 (*read_func_t)(void);
696typedef void (*write_func_t)(u32 d);
697
698static read_func_t read_handlers[16] =
699{
700 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
701 read_unknown, // 4 ST
702 read_STACK,
703 read_PC,
704 read_P,
705 read_PM0, // 8
706 read_PM1,
707 read_PM2,
708 read_XST,
709 read_PM4, // 12
710 read_unknown, // 13 gr13
711 read_PMC,
712 read_AL
713};
714
715static write_func_t write_handlers[16] =
716{
717 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
718// write_unknown, // 4 ST
719 write_ST, // 4 ST (debug hook)
720 write_STACK,
721 write_PC,
722 write_unknown, // 7 P
723 write_PM0, // 8
724 write_PM1,
725 write_PM2,
726 write_XST,
727 write_PM4, // 12
728 write_unknown, // 13 gr13
729 write_PMC,
730 write_AL
731};
732
733// -----------------------------------------------------
734// pointer register handlers
735
736//
737#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
738
739static u32 ptr1_read_(int ri, int isj2, int modi3)
740{
741 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
742 u32 mask, add = 0, t = ri | isj2 | modi3;
743 unsigned char *rp = NULL;
744 switch (t)
745 {
746 // mod=0 (00)
747 case 0x00:
748 case 0x01:
749 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
750 case 0x03: return ssp->RAM0[0];
751 case 0x04:
752 case 0x05:
753 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
754 case 0x07: return ssp->RAM1[0];
755 // mod=1 (01), "+!"
756 case 0x08:
757 case 0x09:
758 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
759 case 0x0b: return ssp->RAM0[1];
760 case 0x0c:
761 case 0x0d:
762 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
763 case 0x0f: return ssp->RAM1[1];
764 // mod=2 (10), "-"
765 case 0x10:
766 case 0x11:
767 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
768 if (!(rST&7)) { (*rp)--; return t; }
769 add = -1; goto modulo;
770 case 0x13: return ssp->RAM0[2];
771 case 0x14:
772 case 0x15:
773 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
774 if (!(rST&7)) { (*rp)--; return t; }
775 add = -1; goto modulo;
776 case 0x17: return ssp->RAM1[2];
777 // mod=3 (11), "+"
778 case 0x18:
779 case 0x19:
780 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
781 if (!(rST&7)) { (*rp)++; return t; }
782 add = 1; goto modulo;
783 case 0x1b: return ssp->RAM0[3];
784 case 0x1c:
785 case 0x1d:
786 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
787 if (!(rST&7)) { (*rp)++; return t; }
788 add = 1; goto modulo;
789 case 0x1f: return ssp->RAM1[3];
790 }
791
792 return 0;
793
794modulo:
795 mask = (1 << (rST&7)) - 1;
796 *rp = (*rp & ~mask) | ((*rp + add) & mask);
797 return t;
798}
799
800static void ptr1_write(int op, u32 d)
801{
802 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
803 switch (t)
804 {
805 // mod=0 (00)
806 case 0x00:
807 case 0x01:
808 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
809 case 0x03: ssp->RAM0[0] = d; return;
810 case 0x04:
811 case 0x05:
812 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
813 case 0x07: ssp->RAM1[0] = d; return;
814 // mod=1 (01), "+!"
815 // mod=3, "+"
816 case 0x08:
817 case 0x18:
818 case 0x09:
819 case 0x19:
820 case 0x0a:
821 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
822 case 0x0b: ssp->RAM0[1] = d; return;
823 case 0x0c:
824 case 0x1c:
825 case 0x0d:
826 case 0x1d:
827 case 0x0e:
828 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
829 case 0x0f: ssp->RAM1[1] = d; return;
830 // mod=2 (10), "-"
831 case 0x10:
832 case 0x11:
833 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
834 case 0x13: ssp->RAM0[2] = d; return;
835 case 0x14:
836 case 0x15:
837 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
838 case 0x17: ssp->RAM1[2] = d; return;
839 // mod=3 (11)
840 case 0x1b: ssp->RAM0[3] = d; return;
841 case 0x1f: ssp->RAM1[3] = d; return;
842 }
843}
844
845static u32 ptr2_read(int op)
846{
847 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
848 switch (t)
849 {
850 // mod=0 (00)
851 case 0x00:
852 case 0x01:
853 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
854 case 0x03: mv = ssp->RAM0[0]++; break;
855 case 0x04:
856 case 0x05:
857 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
858 case 0x07: mv = ssp->RAM1[0]++; break;
859 // mod=1 (01)
860 case 0x0b: mv = ssp->RAM0[1]++; break;
861 case 0x0f: mv = ssp->RAM1[1]++; break;
862 // mod=2 (10)
863 case 0x13: mv = ssp->RAM0[2]++; break;
864 case 0x17: mv = ssp->RAM1[2]++; break;
865 // mod=3 (11)
866 case 0x1b: mv = ssp->RAM0[3]++; break;
867 case 0x1f: mv = ssp->RAM1[3]++; break;
868 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
869 return 0;
870 }
871
872 return ((unsigned short *)svp->iram_rom)[mv];
873}
874
875
876// -----------------------------------------------------
877
878void ssp1601_reset(ssp1601_t *l_ssp)
879{
880 ssp = l_ssp;
881 ssp->emu_status = 0;
882 ssp->gr[SSP_GR0].v = 0xffff0000;
883 rPC = 0x400;
884 rSTACK = 0; // ? using ascending stack
885 rST = 0;
886}
887
888
889#ifdef USE_DEBUGGER
890static void debug_dump(void)
891{
892 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
893 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
894 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
895 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
896 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
897 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
898 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
899 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
900 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
901 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
902}
903
904static void debug_dump_mem(void)
905{
906 int h, i;
907 printf("RAM0\n");
908 for (h = 0; h < 32; h++)
909 {
910 if (h == 16) printf("RAM1\n");
911 printf("%03x:", h*16);
912 for (i = 0; i < 16; i++)
913 printf(" %04x", ssp->RAM[h*16+i]);
914 printf("\n");
915 }
916}
917
918static void debug_dump2file(const char *fname, void *mem, int len)
919{
920 FILE *f = fopen(fname, "wb");
921 unsigned short *p = mem;
922 int i;
923 if (f) {
924 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
925 fwrite(mem, 1, len, f);
926 fclose(f);
927 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
928 printf("dumped to %s\n", fname);
929 }
930 else
931 printf("dump failed\n");
932}
933
934static int bpts[10] = { 0, };
935
936static void debug(unsigned int pc, unsigned int op)
937{
938 static char buffo[64] = {0,};
939 char buff[64] = {0,};
940 int i;
941
942 if (running) {
943 for (i = 0; i < 10; i++)
944 if (pc != 0 && bpts[i] == pc) {
945 printf("breakpoint %i\n", i);
946 running = 0;
947 break;
948 }
949 }
950 if (running) return;
951
952 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
953
954 while (1)
955 {
956 printf("dbg> ");
957 fflush(stdout);
958 fgets(buff, sizeof(buff), stdin);
959 if (buff[0] == '\n') strcpy(buff, buffo);
960 else strcpy(buffo, buff);
961
962 switch (buff[0]) {
963 case 0: exit(0);
964 case 'c':
965 case 'r': running = 1; return;
966 case 's':
967 case 'n': return;
968 case 'x': debug_dump(); break;
969 case 'm': debug_dump_mem(); break;
970 case 'b': {
971 char *baddr = buff + 2;
972 i = 0;
973 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
974 bpts[i] = strtol(baddr, NULL, 16) >> 1;
975 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
976 break;
977 }
978 case 'd':
979 sprintf(buff, "iramrom_%04x.bin", last_iram);
980 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
981 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
982 break;
983 default: printf("unknown command\n"); break;
984 }
985 }
986}
987#endif // USE_DEBUGGER
988
989
990void ssp1601_run(int cycles)
991{
992 SET_PC(rPC);
993 g_cycles = cycles;
994
995 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
996 {
997 int op;
998 u32 tmpv;
999
1000 op = *PC++;
1001#ifdef USE_DEBUGGER
1002 debug(GET_PC()-1, op);
1003#endif
1004 switch (op >> 9)
1005 {
1006 // ld d, s
1007 case 0x00:
1008 if (op == 0) break; // nop
1009 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1010 // not sure. MAME claims that only hi word is transfered.
1011 read_P(); // update P
1012 rA32 = ssp->gr[SSP_P].v;
1013 }
1014 else
1015 {
1016 tmpv = REG_READ(op & 0x0f);
1017 REG_WRITE((op & 0xf0) >> 4, tmpv);
1018 }
1019 break;
1020
1021 // ld d, (ri)
1022 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1023
1024 // ld (ri), s
1025 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1026
1027 // ldi d, imm
1028 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1029
1030 // ld d, ((ri))
1031 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1032
1033 // ldi (ri), imm
1034 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1035
1036 // ld adr, a
1037 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1038
1039 // ld d, ri
1040 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1041
1042 // ld ri, s
1043 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1044
1045 // ldi ri, simm
1046 case 0x0c:
1047 case 0x0d:
1048 case 0x0e:
1049 case 0x0f: rIJ[(op>>8)&7] = op; break;
1050
1051 // call cond, addr
1052 case 0x24: {
1053 int cond = 0;
1054 COND_CHECK
1055 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1056 else PC++;
1057 break;
1058 }
1059
1060 // ld d, (a)
1061 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1062
1063 // bra cond, addr
1064 case 0x26: {
1065 int cond = 0;
1066 COND_CHECK
1067 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1068 else PC++;
1069 break;
1070 }
1071
1072 // mod cond, op
1073 case 0x48: {
1074 int cond = 0;
1075 COND_CHECK
1076 if (cond) {
1077 switch (op & 7) {
1078 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1079 case 3: rA32 <<= 1; break; // shl
1080 case 6: rA32 = -(signed int)rA32; break; // neg
1081 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1082 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1083 op&7, GET_PPC_OFFS());
1084 }
1085 UPD_ACC_ZN // ?
1086 }
1087 break;
1088 }
1089
1090 // mpys?
1091 case 0x1b:
1092 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1093 read_P(); // update P
1094 rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
1095 UPD_ACC_ZN // there checking flags after this
1096 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1097 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1098 break;
1099
1100 // mpya (rj), (ri), b
1101 case 0x4b:
1102 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1103 read_P(); // update P
1104 rA32 += ssp->gr[SSP_P].v; // confirmed to be 32bit
1105 UPD_ACC_ZN // ?
1106 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1107 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1108 break;
1109
1110 // mld (rj), (ri), b
1111 case 0x5b:
1112 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1113 rA32 = 0;
1114 rST &= 0x0fff; // ?
1115 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1116 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1117 break;
1118
1119 // OP a, s
1120 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1121 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1122 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1123 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1124 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1125 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1126
1127 // OP a, (ri)
1128 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1129 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1130 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1131 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1132 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1133 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1134
1135 // OP a, adr
1136 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1137 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1138 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1139 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1140 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1141 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1142 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1143
1144 // OP a, imm
1145 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1146 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1147 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1148 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1149 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1150 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1151
1152 // OP a, ((ri))
1153 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1154 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1155 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1156 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1157 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1158 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1159
1160 // OP a, ri
1161 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1162 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1163 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1164 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1165 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1166 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1167
1168 // OP simm
1169 case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1170 case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1171 case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1172 // MAME code only does LSB of top word, but this looks wrong to me.
1173 case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1174 case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1175 case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1176
1177 default:
1178 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1179 break;
1180 }
1181 g_cycles--;
1182 }
1183
1184 read_P(); // update P
1185 rPC = GET_PC();
1186
1187 if (ssp->gr[SSP_GR0].v != 0xffff0000)
1188 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
1189}
1190
fast MegaDrive/MegaCD/32X emulator