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svp. does some output now
[picodrive.git] / Pico / carthw / svp / ssp16.c
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1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
31 * 43 - RB (?)
32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
72 *
73 * 9. "PM1"
74 * size: 16?
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
77 *
78 * 10. "PM2"
79 * size: 16?
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
82 *
83 * 11. "XST"
84 * size: 16?
85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
86 * Can be programmed as PMAR? (only seen in test mode code)
87 * Affects PM0 when written to?
88 *
89 * 12. "PM4"
90 * size: 16?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
93 *
94 * 13. (unused by VR)
95 *
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
97 * size: 32?
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
100 * be accessed to program it.
101 *
102 * 15. "AL"
103 * size: 16
104 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
105 * (normally reading acc (ld X, A) you get 16 most significant bits).
106 *
107 *
108 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
109 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
110 * which work similar to * and ** operators in C, only they use different memory banks and
111 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
112 * program memory at address read from (rX), and increments value in (rX).
113 *
114 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
115 * 3 modifiers can be applied (optional):
116 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
117 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
118 * +!: post-increment, unaffected by RPL (probably).
119 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
120 * ar probably invalid.
121 *
122 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
123 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
124 * Samsung's old DSP page claims that).
125 * 1 of these 4 modifiers must be used (short form direct addressing?):
126 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
127 * |01: RAMx[1]
128 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
129 * |11: RAMx[3]
130 *
131 *
132 * Instruction notes
133 *
134 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
135 *
136 * mld (rj), (ri) [, b]
137 * operation: A = 0; P = (rj) * (ri)
138 * notes: based on IIR_4B.SC sample. flags? what is b???
139 * TODO: figure out if (rj) and (ri) get loaded in X and Y
140 *
141 * mpya (rj), (ri) [, b]
142 * name: multiply and add?
143 * operation: A += P; P = (rj) * (ri)
144 *
145 * mpys (rj), (ri), b
146 * name: multiply and subtract?
147 * notes: not used by VR code.
148 *
149 * mod cond, op
150 * mod cond, shr does arithmetic shift
151 *
152 * memory map:
153 * 000000 - 1fffff ROM, accessable by both
154 * 200000 - 2fffff unused?
155 * 300000 - 31ffff DRAM, both
156 * 320000 - 38ffff unused?
157 * 390000 - 3907ff IRAM. can only be accessed by ssp?
158 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
159 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
160 *
161 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
162 * 30fe06 - also sync related.
163 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
164 *
165 * misc:
166 * pressing all buttons while resetting game will kick into test mode
167 *
168 * Assumptions in this code
169 * P is not directly writeable
170 * flags correspond to full 32bit accumulator
171 * only Z and N status flags are emulated (others unused by SVP)
172 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
173 * modifiers '+' and '+!' act the same (this is most likely wrong)
174 * 'ld d, (a)' loads from program ROM
175 */
176
177#include "../../PicoInt.h"
178
179#define u32 unsigned int
180
181// 0
182#define rX ssp->gr[SSP_X].h
183#define rY ssp->gr[SSP_Y].h
184#define rA ssp->gr[SSP_A].h
185#define rST ssp->gr[SSP_ST].h // 4
186#define rSTACK ssp->gr[SSP_STACK].h
187#define rPC ssp->gr[SSP_PC].h
188#define rP ssp->gr[SSP_P]
189#define rPM0 ssp->gr[SSP_PM0].h // 8
190#define rPM1 ssp->gr[SSP_PM1].h
191#define rPM2 ssp->gr[SSP_PM2].h
192#define rXST ssp->gr[SSP_XST].h
193#define rPM4 ssp->gr[SSP_PM4].h // 12
194// 13
195#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
196#define rAL ssp->gr[SSP_A].l
197
198#define rA32 ssp->gr[SSP_A].v
199#define rIJ ssp->r
200
201#define IJind (((op>>6)&4)|(op&3))
202
203#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
204#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
205#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
206
207#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
208#define REG_WRITE(r,d) { \
209 int r1 = r; \
210 if (r1 >= 4) write_handlers[r1](d); \
211 else if (r1 > 0) ssp->gr[r1].h = d; \
212}
213
214// flags
215#define SSP_FLAG_L (1<<0xc)
216#define SSP_FLAG_Z (1<<0xd)
217#define SSP_FLAG_V (1<<0xe)
218#define SSP_FLAG_N (1<<0xf)
219
220// update ZN according to 32bit ACC.
221#define UPD_ACC_ZN \
222 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
223 if (!rA32) rST |= SSP_FLAG_Z; \
224 else rST |= (rA32>>16)&SSP_FLAG_N;
225
226// it seems SVP code never checks for L and OV, so we leave them out.
227// rST |= (t>>4)&SSP_FLAG_L;
228#define UPD_t_LZVN \
229 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
230 if (!t) rST |= SSP_FLAG_Z; \
231 else rST |= t&SSP_FLAG_N; \
232
233// standard cond processing.
234// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
235#define COND_CHECK \
236 switch (op&0xf0) { \
237 case 0x00: cond = 1; break; /* always true */ \
238 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
239 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
240 default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
241 }
242
243// ops with accumulator.
244// how is low word really affected by these?
245// nearly sure 'ld A' doesn't affect flags
246#define OP_LDA(x) \
247 ssp->gr[SSP_A].h = x
248
249#define OP_SUBA(x) { \
250 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
251 UPD_t_LZVN \
252 ssp->gr[SSP_A].h = t; \
253}
254
255#define OP_CMPA(x) { \
256 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
257 UPD_t_LZVN \
258}
259
260#define OP_ADDA(x) { \
261 u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
262 UPD_t_LZVN \
263 ssp->gr[SSP_A].h = t; \
264}
265
266#define OP_ANDA(x) \
267 ssp->gr[SSP_A].v &= (x) << 16; \
268 UPD_ACC_ZN
269
270#define OP_ORA(x) \
271 ssp->gr[SSP_A].v |= (x) << 16; \
272 UPD_ACC_ZN
273
274#define OP_EORA(x) \
275 ssp->gr[SSP_A].v ^= (x) << 16; \
276 UPD_ACC_ZN
277
278
279static ssp1601_t *ssp = NULL;
280static unsigned short *PC;
281static int g_cycles;
282// debug
283static int running = 0;
284static int last_iram = 0;
285
286// -----------------------------------------------------
287// register i/o handlers
288
289// 0-4, 13
290static u32 read_unknown(void)
291{
292 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
293 return 0;
294}
295
296static void write_unknown(u32 d)
297{
298 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
299}
300
301// 4
302static void write_ST(u32 d)
303{
304 if ((rST ^ d) & 7) {
305 elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
306// running = 0;
307 }
308 rST = d;
309}
310
311// 5
312static u32 read_STACK(void)
313{
314 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
315 --rSTACK;
316 if ((short)rSTACK < 0) {
317 rSTACK = 5;
318 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
319 }
320 return ssp->stack[rSTACK];
321}
322
323static void write_STACK(u32 d)
324{
325 if (rSTACK >= 6) {
326 running = 0;
327 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
328 rSTACK = 0;
329 }
330 ssp->stack[rSTACK++] = d;
331}
332
333// 6
334static u32 read_PC(void)
335{
336 return GET_PC();
337}
338
339static void write_PC(u32 d)
340{
341 SET_PC(d);
342 g_cycles--;
343}
344
345// 7
346static u32 read_P(void)
347{
348 rP.v = (u32)rX * rY * 2;
349 return rP.h;
350}
351
352// -----------------------------------------------------
353
354static void iram_write(int addr, u32 d, int reg, int inc)
355{
356 if ((addr&0xfc00) != 0x8000)
357 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
358 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
359 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
360 ssp->pmac_write[reg] += inc<<16;
361}
362
363int lil[32] = { 0, }, lilp = 0;
364
365static void debug_dump2file(const char *fname, void *mem, int len);
366
367#define overwite_write(dst, d) \
368{ \
369 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
370 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
371 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
372 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
373}
374
375static u32 pm_io(int reg, int write, u32 d)
376{
377 if (ssp->emu_status & SSP_PMC_SET) {
378 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
379 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
380 ssp->emu_status &= ~SSP_PMC_SET;
381 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
382 elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
383/*
384 {
385 int i;
386 char buff[64];
387 for (i = 0; i < 32; i++) {
388 if (lil[i] == last_iram) break;
389 if (lil[i] == 0) {
390 lil[i] = last_iram;
391 sprintf(buff, "iramrom_%04x.bin", last_iram);
392 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
393 break;
394 }
395 }
396 }
397*/
398 last_iram = (ssp->RAM1[0]-1)<<1;
399 }
400 return 0;
401 }
402
403 // just in case
404 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
405
406// if (ssp->pmac_read[reg] != 0)
407 if (reg == 4 || (rST & 0x60))
408 {
409 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
410 unsigned short *dram = (unsigned short *)svp->dram;
411 if (write)
412 {
413 /* TODO: 0c18 mode? */
414 int mode = ssp->pmac_write[reg]&0xffff;
415 int addr = ssp->pmac_write[reg]>>16;
416 switch (mode) {
417 case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", CADDR, d);
418 dram[addr] = d;
419 break;
420 case 0x0418: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (overwr)", CADDR, d);
421 overwite_write(dram[addr], d);
422 break;
423 case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", CADDR, d);
424 dram[addr] = d;
425 ssp->pmac_write[reg] += 1<<16;
426 break;
427 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
428 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
429 case 0x4018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (cell inc)", CADDR, d);
430 dram[addr] = d;
431 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
432 break;
433 case 0x4418: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (overwr, cell inc)", CADDR, d);
434 overwite_write(dram[addr], d);
435 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
436 break;
437 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
438 reg, mode, CADDR, d, GET_PPC_OFFS()); break;
439 }
440 }
441 else
442 {
443 int mode = ssp->pmac_read[reg]&0xffff;
444 int addr = ssp->pmac_read[reg]>>16;
445 if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
446 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
447 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
448 ssp->pmac_read[reg] += 1<<16;
449 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
450 goto ext_io_end;
451 }
452
453 switch (mode) {
454 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
455 d = dram[addr]; // checked
456 break;
457 case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", CADDR, dram[addr]);
458 ssp->pmac_read[reg] += 1<<16;
459 d = dram[addr];
460 break;
461 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
462 ssp->pmac_read[reg] += 32<<16;
463 d = dram[addr];
464 break;
465 case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
466 ssp->pmac_read[reg] -= 16<<16;
467 d = dram[addr];
468 break;
469 case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
470 ssp->pmac_read[reg] -= 128<<16;
471 d = dram[addr];
472 break;
473 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
474 reg, mode, CADDR, GET_PPC_OFFS());
475 d = 0;
476 break;
477 }
478 }
479
480ext_io_end:
481 // PMC value corresponds to last PMR accessed (not sure).
482 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
483
484 return d;
485 }
486
487 return (u32)-1;
488}
489
490// 8
491static u32 read_PM0(void)
492{
493 u32 d = pm_io(0, 0, 0);
494 if (d != (u32)-1) return d;
495 if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
496 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
497 d = rPM0;
498 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
499 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
500 }
501 rPM0 &= ~2; // ?
502 return d;
503}
504
505static void write_PM0(u32 d)
506{
507 u32 r = pm_io(0, 1, d);
508 if (r != (u32)-1) return;
509 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
510 rPM0 = d;
511}
512
513// 9
514static u32 read_PM1(void)
515{
516 u32 d = pm_io(1, 0, 0);
517 if (d != (u32)-1) return d;
518 // can be removed?
519 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
520 return rPM1;
521}
522
523static void write_PM1(u32 d)
524{
525 u32 r = pm_io(1, 1, d);
526 if (r != (u32)-1) return;
527 // can be removed?
528 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
529 rPM1 = d;
530}
531
532// 10
533static u32 read_PM2(void)
534{
535 u32 d = pm_io(2, 0, 0);
536 if (d != (u32)-1) return d;
537 // can be removed?
538 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
539 return rPM2;
540}
541
542static void write_PM2(u32 d)
543{
544 u32 r = pm_io(2, 1, d);
545 if (r != (u32)-1) return;
546 // can be removed?
547 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
548 rPM2 = d;
549}
550
551// 11
552static u32 read_XST(void)
553{
554 // can be removed?
555 u32 d = pm_io(3, 0, 0);
556 if (d != (u32)-1) return d;
557
558 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
559 return rXST;
560}
561
562static void write_XST(u32 d)
563{
564 // can be removed?
565 u32 r = pm_io(3, 1, d);
566 if (r != (u32)-1) return;
567
568 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
569 rPM0 |= 1;
570 rXST = d;
571}
572
573// 12
574static u32 read_PM4(void)
575{
576 u32 d = pm_io(4, 0, 0);
577 if (d == 0) {
578 switch (GET_PPC_OFFS()) {
579 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
580 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
581 }
582 }
583 if (d != (u32)-1) return d;
584 // can be removed?
585 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
586 return rPM4;
587}
588
589static void write_PM4(u32 d)
590{
591 u32 r = pm_io(4, 1, d);
592 if (r != (u32)-1) return;
593 // can be removed?
594 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
595 rPM4 = d;
596}
597
598// 14
599static u32 read_PMC(void)
600{
601 elprintf(EL_SVP, "PMC r %08x @ %04x", rPMC.v, GET_PPC_OFFS());
602 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
603 if (ssp->emu_status & SSP_PMC_SET)
604 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
605 ssp->emu_status |= SSP_PMC_SET;
606 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
607 return rPMC.l;
608 } else {
609 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
610 return rPMC.h;
611 }
612}
613
614static void write_PMC(u32 d)
615{
616 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
617 if (ssp->emu_status & SSP_PMC_SET)
618 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
619 ssp->emu_status |= SSP_PMC_SET;
620 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
621 rPMC.l = d;
622 } else {
623 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
624 rPMC.h = d;
625 }
626}
627
628// 15
629static u32 read_AL(void)
630{
631 // TODO: figure out what's up with those blind reads..
632 if (*(PC-1) == 0x000f)
633 elprintf(EL_SVP|EL_ANOMALY, "ssp unhandled AL blind read..");
634 return rAL;
635}
636
637static void write_AL(u32 d)
638{
639 rAL = d;
640}
641
642
643typedef u32 (*read_func_t)(void);
644typedef void (*write_func_t)(u32 d);
645
646static read_func_t read_handlers[16] =
647{
648 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
649 read_unknown, // 4 ST
650 read_STACK,
651 read_PC,
652 read_P,
653 read_PM0, // 8
654 read_PM1,
655 read_PM2,
656 read_XST,
657 read_PM4, // 12
658 read_unknown, // 13 gr13
659 read_PMC,
660 read_AL
661};
662
663static write_func_t write_handlers[16] =
664{
665 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
666// write_unknown, // 4 ST
667 write_ST, // 4 ST (debug hook)
668 write_STACK,
669 write_PC,
670 write_unknown, // 7 P
671 write_PM0, // 8
672 write_PM1,
673 write_PM2,
674 write_XST,
675 write_PM4, // 12
676 write_unknown, // 13 gr13
677 write_PMC,
678 write_AL
679};
680
681// -----------------------------------------------------
682// pointer register handlers
683
684//
685#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
686
687static u32 ptr1_read_(int ri, int isj2, int modi3)
688{
689 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
690 u32 mask, add = 0, t = ri | isj2 | modi3;
691 unsigned char *rp = NULL;
692 switch (t)
693 {
694 // mod=0 (00)
695 case 0x00:
696 case 0x01:
697 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
698 case 0x03: return ssp->RAM0[0];
699 case 0x04:
700 case 0x05:
701 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
702 case 0x07: return ssp->RAM1[0];
703 // mod=1 (01), "+!"
704 case 0x08:
705 case 0x09:
706 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
707 case 0x0b: return ssp->RAM0[1];
708 case 0x0c:
709 case 0x0d:
710 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
711 case 0x0f: return ssp->RAM1[1];
712 // mod=2 (10), "-"
713 case 0x10:
714 case 0x11:
715 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
716 if (!(rST&7)) { (*rp)--; return t; }
717 add = -1; goto modulo;
718 case 0x13: return ssp->RAM0[2];
719 case 0x14:
720 case 0x15:
721 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
722 if (!(rST&7)) { (*rp)--; return t; }
723 add = -1; goto modulo;
724 case 0x17: return ssp->RAM1[2];
725 // mod=3 (11), "+"
726 case 0x18:
727 case 0x19:
728 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
729 if (!(rST&7)) { (*rp)++; return t; }
730 add = 1; goto modulo;
731 case 0x1b: return ssp->RAM0[3];
732 case 0x1c:
733 case 0x1d:
734 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
735 if (!(rST&7)) { (*rp)++; return t; }
736 add = 1; goto modulo;
737 case 0x1f: return ssp->RAM1[3];
738 }
739
740 return 0;
741
742modulo:
743 mask = (1 << (rST&7)) - 1;
744 *rp = (*rp & ~mask) | ((*rp + add) & mask);
745 return t;
746}
747
748static void ptr1_write(int op, u32 d)
749{
750 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
751 switch (t)
752 {
753 // mod=0 (00)
754 case 0x00:
755 case 0x01:
756 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
757 case 0x03: ssp->RAM0[0] = d; return;
758 case 0x04:
759 case 0x05:
760 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
761 case 0x07: ssp->RAM1[0] = d; return;
762 // mod=1 (01), "+!"
763 // mod=3, "+"
764 case 0x08:
765 case 0x18:
766 case 0x09:
767 case 0x19:
768 case 0x0a:
769 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
770 case 0x0b: ssp->RAM0[1] = d; return;
771 case 0x0c:
772 case 0x1c:
773 case 0x0d:
774 case 0x1d:
775 case 0x0e:
776 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
777 case 0x0f: ssp->RAM1[1] = d; return;
778 // mod=2 (10), "-"
779 case 0x10:
780 case 0x11:
781 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
782 case 0x13: ssp->RAM0[2] = d; return;
783 case 0x14:
784 case 0x15:
785 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
786 case 0x17: ssp->RAM1[2] = d; return;
787 // mod=3 (11)
788 case 0x1b: ssp->RAM0[3] = d; return;
789 case 0x1f: ssp->RAM1[3] = d; return;
790 }
791}
792
793static u32 ptr2_read(int op)
794{
795 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
796 switch (t)
797 {
798 // mod=0 (00)
799 case 0x00:
800 case 0x01:
801 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
802 case 0x03: mv = ssp->RAM0[0]++; break;
803 case 0x04:
804 case 0x05:
805 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
806 case 0x07: mv = ssp->RAM1[0]++; break;
807 // mod=1 (01)
808 case 0x0b: mv = ssp->RAM0[1]++; break;
809 case 0x0f: mv = ssp->RAM1[1]++; break;
810 // mod=2 (10)
811 case 0x13: mv = ssp->RAM0[2]++; break;
812 case 0x17: mv = ssp->RAM1[2]++; break;
813 // mod=3 (11)
814 case 0x1b: mv = ssp->RAM0[3]++; break;
815 case 0x1f: mv = ssp->RAM1[3]++; break;
816 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
817 return 0;
818 }
819
820 return ((unsigned short *)svp->iram_rom)[mv];
821}
822
823
824// -----------------------------------------------------
825
826void ssp1601_reset(ssp1601_t *l_ssp)
827{
828 ssp = l_ssp;
829 ssp->emu_status = 0;
830 ssp->gr[SSP_GR0].v = 0xffff0000;
831 rPC = 0x400;
832 rSTACK = 0; // ? using ascending stack
833 rST = 0;
834}
835
836
837static void debug_dump(void)
838{
839 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
840 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
841 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
842 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
843 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
844 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
845 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
846 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
847 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
848 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
849}
850
851static void debug_dump_mem(void)
852{
853 int h, i;
854 printf("RAM0\n");
855 for (h = 0; h < 32; h++)
856 {
857 if (h == 16) printf("RAM1\n");
858 printf("%03x:", h*16);
859 for (i = 0; i < 16; i++)
860 printf(" %04x", ssp->RAM[h*16+i]);
861 printf("\n");
862 }
863}
864
865static void debug_dump2file(const char *fname, void *mem, int len)
866{
867 FILE *f = fopen(fname, "wb");
868 unsigned short *p = mem;
869 int i;
870 if (f) {
871 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
872 fwrite(mem, 1, len, f);
873 fclose(f);
874 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
875 printf("dumped to %s\n", fname);
876 }
877 else
878 printf("dump failed\n");
879}
880
881static int bpts[10] = { 0, };
882
883static void debug(unsigned int pc, unsigned int op)
884{
885 static char buffo[64] = {0,};
886 char buff[64] = {0,};
887 int i;
888
889 if (running) {
890 for (i = 0; i < 10; i++)
891 if (pc != 0 && bpts[i] == pc) {
892 printf("breakpoint %i\n", i);
893 running = 0;
894 break;
895 }
896 }
897 if (running) return;
898
899 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
900
901 while (1)
902 {
903 printf("dbg> ");
904 fflush(stdout);
905 fgets(buff, sizeof(buff), stdin);
906 if (buff[0] == '\n') strcpy(buff, buffo);
907 else strcpy(buffo, buff);
908
909 switch (buff[0]) {
910 case 0: exit(0);
911 case 'c':
912 case 'r': running = 1; return;
913 case 's':
914 case 'n': return;
915 case 'x': debug_dump(); break;
916 case 'm': debug_dump_mem(); break;
917 case 'b': {
918 char *baddr = buff + 2;
919 i = 0;
920 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
921 bpts[i] = strtol(baddr, NULL, 16) >> 1;
922 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
923 break;
924 }
925 case 'd':
926 sprintf(buff, "iramrom_%04x.bin", last_iram);
927 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
928 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
929 break;
930 default: printf("unknown command\n"); break;
931 }
932 }
933}
934
935void ssp1601_run(int cycles)
936{
937 SET_PC(rPC);
938 g_cycles = cycles;
939
940//if (Pico.m.frame_count == 480) running = 0;
941
942 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
943 {
944 int op;
945 u32 tmpv;
946
947 op = *PC++;
948 debug(GET_PC()-1, op);
949 switch (op >> 9)
950 {
951 // ld d, s
952 case 0x00:
953 if (op == 0) break; // nop
954 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
955 // not sure. MAME claims that only hi word is transfered.
956 read_P(); // update P
957 ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
958 }
959 else
960 {
961 tmpv = REG_READ(op & 0x0f);
962 REG_WRITE((op & 0xf0) >> 4, tmpv);
963 }
964 break;
965
966 // ld d, (ri)
967 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
968
969 // ld (ri), s
970 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
971
972 // ldi d, imm
973 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
974
975 // ld d, ((ri))
976 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
977
978 // ldi (ri), imm
979 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
980
981 // ld adr, a
982 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
983
984 // ld d, ri
985 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
986
987 // ld ri, s
988 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
989
990 // ldi ri, simm
991 case 0x0c:
992 case 0x0d:
993 case 0x0e:
994 case 0x0f: rIJ[(op>>8)&7] = op; break;
995
996 // call cond, addr
997 case 0x24: {
998 int cond = 0;
999 COND_CHECK
1000 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1001 else PC++;
1002 break;
1003 }
1004
1005 // ld d, (a)
1006 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1007
1008 // bra cond, addr
1009 case 0x26: {
1010 int cond = 0;
1011 COND_CHECK
1012 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1013 else PC++;
1014 break;
1015 }
1016
1017 // mod cond, op
1018 case 0x48: {
1019 int cond = 0;
1020 COND_CHECK
1021 if (cond) {
1022 switch (op & 7) {
1023 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1024 case 3: rA32 <<= 1; break; // shl
1025 case 6: rA32 = -(signed int)rA32; break; // neg
1026 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1027 default: elprintf(EL_SVP, "ssp16: FIXME unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
1028 }
1029 UPD_ACC_ZN // ?
1030 }
1031 break;
1032 }
1033
1034#if 1
1035 // mpys?
1036 case 0x1b:
1037 // very uncertain about this one. What about b?
1038 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1039 read_P(); // update P
1040 ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
1041// UPD_ACC_ZN // I've seen code checking flags after this
1042 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1043 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1044 break;
1045#endif
1046 // mpya (rj), (ri), b
1047 case 0x4b:
1048 // dunno if this is correct. What about b?
1049 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1050 read_P(); // update P
1051 ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
1052 UPD_ACC_ZN // ?
1053 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1054 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1055 break;
1056
1057 // mld (rj), (ri), b
1058 case 0x5b:
1059 // dunno if this is correct. What about b?
1060 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1061 ssp->gr[SSP_A].v = 0; // maybe only upper word?
1062 // UPD_t_LZVN // ?
1063 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1064 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1065 break;
1066
1067 // OP a, s
1068 case 0x10: tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1069 case 0x30: tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1070 case 0x40: tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1071 case 0x50: tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1072 case 0x60: tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1073 case 0x70: tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1074
1075 // OP a, (ri)
1076 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1077 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1078 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1079 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1080 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1081 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1082
1083 // OP a, adr
1084 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1085 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1086 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1087 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1088 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1089 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1090 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1091
1092 // OP a, imm
1093 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1094 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1095 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1096 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1097 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1098 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1099
1100 // OP a, ((ri))
1101 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1102 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1103 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1104 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1105 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1106 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1107
1108 // OP a, ri
1109 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1110 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1111 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1112 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1113 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1114 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1115
1116 // OP simm
1117 case 0x1c: OP_SUBA(op & 0xff); break;
1118 case 0x3c: OP_CMPA(op & 0xff); break;
1119 case 0x4c: OP_ADDA(op & 0xff); break;
1120 // MAME code only does LSB of top word, but this looks wrong to me.
1121 case 0x5c: OP_ANDA(op & 0xff); break;
1122 case 0x6c: OP_ORA (op & 0xff); break;
1123 case 0x7c: OP_EORA(op & 0xff); break;
1124
1125 default:
1126 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1127 break;
1128 }
1129 g_cycles--;
1130 }
1131
1132 read_P(); // update P
1133 rPC = GET_PC();
1134
1135 if (ssp->gr[SSP_GR0].v != 0xffff0000)
1136 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
1137}
1138
fast MegaDrive/MegaCD/32X emulator