hint-less mode updated for SVP, state load callback, etc
[picodrive.git] / Pico / carthw / svp / stub_arm.S
... / ...
CommitLineData
1@ vim:filetype=armasm
2
3.if 0
4#include "compiler.h"
5.endif
6
7.global tcache
8
9.global flush_inval_caches
10.global ssp_regfile_load
11.global ssp_regfile_store
12.global ssp_drc_entry
13.global ssp_drc_next
14.global ssp_hle_800
15
16@ translation cache buffer
17.text
18.align 12 @ 4096
19.size tcache, TCACHE_SIZE
20tcache:
21 .space TCACHE_SIZE
22
23
24.text
25.align 2
26
27
28flush_inval_caches:
29 mov r2, #0x0 @ must be 0
30 swi 0x9f0002
31 bx lr
32
33
34@ SSP_GR0, SSP_X, SSP_Y, SSP_A,
35@ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
36@ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
37@ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
38
39@ register map:
40@ r4: XXYY
41@ r5: A
42@ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
43@ r7: SSP context
44@ r8: r0-r2 (.210)
45@ r9: r4-r6 (.654)
46@ r10: P
47@ r11: cycles
48
49@ trashes r2,r3
50
51ssp_regfile_load:
52 ldr r7, =ssp
53 ldr r7, [r7]
54 add r2, r7, #0x400
55 add r2, r2, #4
56 ldmia r2, {r3,r4,r5,r6,r8}
57 mov r3, r3, lsr #16
58 mov r3, r3, lsl #16
59 orr r4, r3, r4, lsr #16 @ XXYY
60
61 and r8, r8, #0x0f0000
62 mov r8, r8, lsl #13 @ sss0 *
63 and r9, r6, #0x670000
64 tst r6, #0x80000000
65 orrne r8, r8, #0x8
66 tst r6, #0x20000000
67 orrne r8, r8, #0x4 @ sss0 * NZ..
68 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
69
70 ldr r8, [r7, #0x440] @ r0-r2
71 ldr r9, [r7, #0x444] @ r4-r6
72 ldr r10,[r7, #(0x400+7*4)] @ P
73 bx lr
74
75
76ssp_regfile_store:
77 str r10,[r7, #(0x400+7*4)] @ P
78 str r8, [r7, #0x440] @ r0-r2
79 str r9, [r7, #0x444] @ r4-r6
80
81 mov r9, r6, lsr #13
82 and r9, r9, #(7<<16) @ STACK
83 mov r3, r6, lsl #28
84 msr cpsr_flg, r3 @ to to ARM PSR
85 and r6, r6, #0x670
86 mov r6, r6, lsl #12
87 orrmi r6, r6, #0x80000000 @ N
88 orreq r6, r6, #0x20000000 @ Z
89
90 mov r3, r4, lsl #16 @ Y
91 mov r2, r4, lsr #16
92 mov r2, r2, lsl #16 @ X
93 add r8, r7, #0x400
94 add r8, r8, #4
95 stmia r8, {r2,r3,r5,r6,r9}
96 bx lr
97
98
99#define SSP_OFFS_GR 0x400
100#define SSP_PM0 8
101#define SSP_PC 6
102#define SSP_OFFS_EMUSTAT 0x484 // emu_status
103#define SSP_OFFS_IRAM_DIRTY 0x494
104#define SSP_OFFS_IRAM_CTX 0x498 // iram_context
105#define SSP_OFFS_BLTAB 0x49c // block_table
106#define SSP_OFFS_BLTAB_IRAM 0x4a0
107#define SSP_OFFS_TMP0 0x4a4
108#define SSP_WAIT_PM0 0x2000
109
110
111ssp_drc_entry:
112 stmfd sp!, {r4-r11, lr}
113 mov r11, r0
114 bl ssp_regfile_load
115
116ssp_drc_next:
117 cmp r11, #0
118 bmi ssp_drc_end
119
120 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
121 mov r0, r0, lsr #16
122 str r0, [r7, #SSP_OFFS_TMP0]
123 cmp r0, #0x400
124 blt ssp_de_iram
125
126 ldr r1, [r7, #SSP_OFFS_BLTAB]
127 ldr r1, [r1, r0, lsl #2]
128 tst r1, r1
129 bxne r1
130 bl ssp_translate_block
131 ldr r2, [r7, #SSP_OFFS_TMP0] @ entry PC
132 ldr r1, [r7, #SSP_OFFS_BLTAB]
133 str r0, [r1, r2, lsl #2]
134 bx r0
135
136ssp_de_iram:
137 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
138 tst r1, r1
139 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
140 beq ssp_de_iram_ctx
141
142 bl ssp_get_iram_context
143 mov r1, #0
144 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
145 mov r1, r0
146 str r1, [r7, #SSP_OFFS_IRAM_CTX]
147 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
148
149ssp_de_iram_ctx:
150 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
151 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
152 add r2, r2, r0, lsl #2
153 ldr r1, [r2]
154 tst r1, r1
155 bxne r1
156 str r2, [r7, #SSP_OFFS_TMP0]
157 bl ssp_translate_block
158 ldr r2, [r7, #SSP_OFFS_TMP0] @ &block_table_iram[iram_context][rPC]
159 str r0, [r2]
160 bx r0
161
162ssp_drc_end:
163 bl ssp_regfile_store
164 mov r0, r11
165 ldmfd sp!, {r4-r11, lr}
166 bx lr
167
168
169
170@ ld A, PM0
171@ andi 2
172@ bra z=1, gloc_0800
173ssp_hle_800:
174 @ block prologue
175@ stmfd sp!, {r4-r11, lr}
176@ bl regfile_load
177@ mov r11, #0
178
179 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
180 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
181 tst r0, #0x20000
182 orreq r1, r1, #SSP_WAIT_PM0
183 addeq r11,r11, #1024
184 streq r1, [r7, #SSP_OFFS_EMUSTAT]
185 movne r0, #0x04000000
186 orrne r0, r0, #0x00040000
187 strne r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
188
189 bl ssp_drc_next
190@ bl regfile_store
191@ add r0, r11, #3
192@ ldmfd sp!, {r4-r11, lr}
193@ bx lr
194
195