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dualcore integration in famc, bram cart C code, psp bugfixes
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1// Memory I/O handlers for Sega/Mega CD.\r
2// Loosely based on Gens code.\r
3// (c) Copyright 2007, Grazvydas "notaz" Ignotas\r
4\r
5\r
6//#define __debug_io\r
7\r
8#include "../PicoInt.h"\r
9\r
10#include "../sound/ym2612.h"\r
11#include "../sound/sn76496.h"\r
12\r
13#include "gfx_cd.h"\r
14#include "pcm.h"\r
15\r
16#ifndef UTYPES_DEFINED\r
17typedef unsigned char u8;\r
18typedef unsigned short u16;\r
19typedef unsigned int u32;\r
20#define UTYPES_DEFINED\r
21#endif\r
22\r
23//#define __debug_io\r
24//#define __debug_io2\r
25\r
26//#define rdprintf dprintf\r
27#define rdprintf(...)\r
28//#define wrdprintf dprintf\r
29#define wrdprintf(...)\r
30#define plprintf dprintf\r
31//#define plprintf(...)\r
32\r
33#ifdef EMU_CORE_DEBUG\r
34extern u32 lastread_a, lastread_d[16], lastwrite_cyc_d[16];\r
35extern int lrp_cyc, lwp_cyc;\r
36#undef USE_POLL_DETECT\r
37#endif\r
38\r
39// -----------------------------------------------------------------\r
40\r
41// poller detection\r
42#define POLL_LIMIT 16\r
43#define POLL_CYCLES 124\r
44// int m68k_poll_addr, m68k_poll_cnt;\r
45unsigned int s68k_poll_adclk, s68k_poll_cnt;\r
46\r
47#ifndef _ASM_CD_MEMORY_C\r
48static u32 m68k_reg_read16(u32 a)\r
49{\r
50 u32 d=0;\r
51 a &= 0x3e;\r
52 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);\r
53\r
54 switch (a) {\r
55 case 0:\r
56 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens\r
57 goto end;\r
58 case 2:\r
59 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
60 // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)\r
61 if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }\r
62 //printf("m68k_regs r3: %02x @%06x\n", (u8)d, SekPc);\r
63 goto end;\r
64 case 4:\r
65 d = Pico_mcd->s68k_regs[4]<<8;\r
66 goto end;\r
67 case 6:\r
68 d = *(u16 *)(Pico_mcd->bios + 0x72);\r
69 goto end;\r
70 case 8:\r
71 d = Read_CDC_Host(0);\r
72 goto end;\r
73 case 0xA:\r
74 dprintf("m68k FIXME: reserved read");\r
75 goto end;\r
76 case 0xC:\r
77 d = Pico_mcd->m.timer_stopwatch >> 16;\r
78 dprintf("m68k stopwatch timer read (%04x)", d);\r
79 goto end;\r
80 }\r
81\r
82 if (a < 0x30) {\r
83 // comm flag/cmd/status (0xE-0x2F)\r
84 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
85 goto end;\r
86 }\r
87\r
88 dprintf("m68k_regs FIXME invalid read @ %02x", a);\r
89\r
90end:\r
91\r
92 // dprintf("ret = %04x", d);\r
93 return d;\r
94}\r
95#endif\r
96\r
97#ifndef _ASM_CD_MEMORY_C\r
98static\r
99#endif\r
100void m68k_reg_write8(u32 a, u32 d)\r
101{\r
102 a &= 0x3f;\r
103 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);\r
104\r
105 switch (a) {\r
106 case 0:\r
107 d &= 1;\r
108 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }\r
109 return;\r
110 case 1:\r
111 d &= 3;\r
112 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset\r
113 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
114 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
115 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {\r
116 SekResetS68k(); // S68k comes out of RESET or BRQ state\r
117 Pico_mcd->m.state_flags&=~1;\r
118 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r
119 }\r
120 Pico_mcd->m.busreq = d;\r
121 return;\r
122 case 2:\r
123 dprintf("m68k: prg wp=%02x", d);\r
124 Pico_mcd->s68k_regs[2] = d; // really use s68k side register\r
125 return;\r
126 case 3: {\r
127 u32 dold = Pico_mcd->s68k_regs[3]&0x1f;\r
128 //printf("m68k_regs w3: %02x @%06x\n", (u8)d, SekPc);\r
129 d &= 0xc2;\r
130 if ((dold>>6) != ((d>>6)&3))\r
131 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
132 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
133 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
134 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
135 if (dold & 4) {\r
136 d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
137 } else {\r
138 //dold &= ~2; // ??\r
139#if 1\r
140 if ((d & 2) && !(dold & 2)) {\r
141 Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)\r
142 d &= ~2;\r
143 }\r
144#else\r
145 if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode\r
146#endif\r
147 }\r
148 Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register\r
149#ifdef USE_POLL_DETECT\r
150 if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {\r
151 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
152 plprintf("s68k poll release, a=%02x\n", a);\r
153 }\r
154#endif\r
155 return;\r
156 }\r
157 case 6:\r
158 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer\r
159 return;\r
160 case 7:\r
161 Pico_mcd->bios[0x72] = d;\r
162 dprintf("hint vector set to %08x", PicoRead32(0x70));\r
163 return;\r
164 case 0xf:\r
165 d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)\r
166 case 0xe:\r
167 //dprintf("m68k: comm flag: %02x", d);\r
168 Pico_mcd->s68k_regs[0xe] = d;\r
169#ifdef USE_POLL_DETECT\r
170 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {\r
171 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
172 plprintf("s68k poll release, a=%02x\n", a);\r
173 }\r
174#endif\r
175 return;\r
176 }\r
177\r
178 if ((a&0xf0) == 0x10) {\r
179 Pico_mcd->s68k_regs[a] = d;\r
180#ifdef USE_POLL_DETECT\r
181 if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {\r
182 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
183 plprintf("s68k poll release, a=%02x\n", a);\r
184 }\r
185#endif\r
186 return;\r
187 }\r
188\r
189 dprintf("m68k FIXME: invalid write? [%02x] %02x", a, d);\r
190}\r
191\r
192#ifndef _ASM_CD_MEMORY_C\r
193static\r
194#endif\r
195u32 s68k_poll_detect(u32 a, u32 d)\r
196{\r
197#ifdef USE_POLL_DETECT\r
198 // polling detection\r
199 if (a == (s68k_poll_adclk&0xff)) {\r
200 unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);\r
201 if (clkdiff <= POLL_CYCLES) {\r
202 s68k_poll_cnt++;\r
203 //printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);\r
204 if (s68k_poll_cnt > POLL_LIMIT) {\r
205 SekSetStopS68k(1);\r
206 plprintf("s68k poll detected @ %06x, a=%02x\n", SekPcS68k, a);\r
207 }\r
208 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;\r
209 return d;\r
210 }\r
211 }\r
212 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;\r
213 s68k_poll_cnt = 0;\r
214#endif\r
215 return d;\r
216}\r
217\r
218#define READ_FONT_DATA(basemask) \\r
219{ \\r
220 unsigned int fnt = *(unsigned int *)(Pico_mcd->s68k_regs + 0x4c); \\r
221 unsigned int col0 = (fnt >> 8) & 0x0f, col1 = (fnt >> 12) & 0x0f; \\r
222 if (fnt & (basemask << 0)) d = col1 ; else d = col0; \\r
223 if (fnt & (basemask << 1)) d |= col1 << 4; else d |= col0 << 4; \\r
224 if (fnt & (basemask << 2)) d |= col1 << 8; else d |= col0 << 8; \\r
225 if (fnt & (basemask << 3)) d |= col1 << 12; else d |= col0 << 12; \\r
226}\r
227\r
228\r
229#ifndef _ASM_CD_MEMORY_C\r
230static\r
231#endif\r
232u32 s68k_reg_read16(u32 a)\r
233{\r
234 u32 d=0;\r
235\r
236 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);\r
237\r
238 switch (a) {\r
239 case 0:\r
240 return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r
241 case 2:\r
242 d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);\r
243 //printf("s68k_regs r3: %02x @%06x\n", (u8)d, SekPcS68k);\r
244 return s68k_poll_detect(a, d);\r
245 case 6:\r
246 return CDC_Read_Reg();\r
247 case 8:\r
248 return Read_CDC_Host(1); // Gens returns 0 here on byte reads\r
249 case 0xC:\r
250 d = Pico_mcd->m.timer_stopwatch >> 16;\r
251 dprintf("s68k stopwatch timer read (%04x)", d);\r
252 return d;\r
253 case 0x30:\r
254 dprintf("s68k int3 timer read (%02x)", Pico_mcd->s68k_regs[31]);\r
255 return Pico_mcd->s68k_regs[31];\r
256 case 0x34: // fader\r
257 return 0; // no busy bit\r
258 case 0x50: // font data (check: Lunar 2, Silpheed)\r
259 READ_FONT_DATA(0x00100000);\r
260 return d;\r
261 case 0x52:\r
262 READ_FONT_DATA(0x00010000);\r
263 return d;\r
264 case 0x54:\r
265 READ_FONT_DATA(0x10000000);\r
266 return d;\r
267 case 0x56:\r
268 READ_FONT_DATA(0x01000000);\r
269 return d;\r
270 }\r
271\r
272 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
273\r
274 if (a >= 0x0e && a < 0x30)\r
275 return s68k_poll_detect(a, d);\r
276\r
277 return d;\r
278}\r
279\r
280#ifndef _ASM_CD_MEMORY_C\r
281static\r
282#endif\r
283void s68k_reg_write8(u32 a, u32 d)\r
284{\r
285 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);\r
286\r
287 // Warning: d might have upper bits set\r
288 switch (a) {\r
289 case 2:\r
290 return; // only m68k can change WP\r
291 case 3: {\r
292 int dold = Pico_mcd->s68k_regs[3];\r
293 //printf("s68k_regs w3: %02x @%06x\n", (u8)d, SekPcS68k);\r
294 d &= 0x1d;\r
295 d |= dold&0xc2;\r
296 if (d&4) {\r
297 if ((d ^ dold) & 5) {\r
298 d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
299 PicoMemResetCD(d);\r
300 }\r
301#ifdef _ASM_CD_MEMORY_C\r
302 if ((d ^ dold) & 0x1d)\r
303 PicoMemResetCDdecode(d);\r
304#endif\r
305 if (!(dold & 4)) {\r
306 dprintf("wram mode 2M->1M");\r
307 wram_2M_to_1M(Pico_mcd->word_ram2M);\r
308 }\r
309 } else {\r
310 if (dold & 4) {\r
311 dprintf("wram mode 1M->2M");\r
312 if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k\r
313 d &= ~3;\r
314 d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode\r
315 }\r
316 wram_1M_to_2M(Pico_mcd->word_ram2M);\r
317 PicoMemResetCD(d);\r
318 }\r
319 else\r
320 d |= dold&1;\r
321 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
322 }\r
323 break;\r
324 }\r
325 case 4:\r
326 dprintf("s68k CDC dest: %x", d&7);\r
327 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode\r
328 return;\r
329 case 5:\r
330 //dprintf("s68k CDC reg addr: %x", d&0xf);\r
331 break;\r
332 case 7:\r
333 CDC_Write_Reg(d);\r
334 return;\r
335 case 0xa:\r
336 dprintf("s68k set CDC dma addr");\r
337 break;\r
338 case 0xc:\r
339 case 0xd:\r
340 dprintf("s68k set stopwatch timer");\r
341 Pico_mcd->m.timer_stopwatch = 0;\r
342 return;\r
343 case 0xe:\r
344 Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair\r
345 return;\r
346 case 0x31:\r
347 dprintf("s68k set int3 timer: %02x", d);\r
348 Pico_mcd->m.timer_int3 = (d & 0xff) << 16;\r
349 break;\r
350 case 0x33: // IRQ mask\r
351 dprintf("s68k irq mask: %02x", d);\r
352 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r
353 CDD_Export_Status();\r
354 }\r
355 break;\r
356 case 0x34: // fader\r
357 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;\r
358 return;\r
359 case 0x36:\r
360 return; // d/m bit is unsetable\r
361 case 0x37: {\r
362 u32 d_old = Pico_mcd->s68k_regs[0x37];\r
363 Pico_mcd->s68k_regs[0x37] = d&7;\r
364 if ((d&4) && !(d_old&4)) {\r
365 CDD_Export_Status();\r
366 }\r
367 return;\r
368 }\r
369 case 0x4b:\r
370 Pico_mcd->s68k_regs[a] = (u8) d;\r
371 CDD_Import_Command();\r
372 return;\r
373 }\r
374\r
375 if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))\r
376 {\r
377 dprintf("s68k FIXME: invalid write @ %02x?", a);\r
378 return;\r
379 }\r
380\r
381 Pico_mcd->s68k_regs[a] = (u8) d;\r
382}\r
383\r
384\r
385#ifndef _ASM_CD_MEMORY_C\r
386static u32 OtherRead16End(u32 a, int realsize)\r
387{\r
388 u32 d=0;\r
389\r
390 if ((a&0xffffc0)==0xa12000) {\r
391 d=m68k_reg_read16(a);\r
392 goto end;\r
393 }\r
394\r
395 if (a==0x400000) {\r
396 if (SRam.data != NULL) d=3; // 64k cart\r
397 goto end;\r
398 }\r
399\r
400 if ((a&0xfe0000)==0x600000) {\r
401 if (SRam.data != NULL) {\r
402 d=SRam.data[((a>>1)&0xffff)+0x2000];\r
403 if (realsize == 8) d|=d<<8;\r
404 }\r
405 goto end;\r
406 }\r
407\r
408 if (a==0x7ffffe) {\r
409 d=Pico_mcd->m.bcram_reg;\r
410 goto end;\r
411 }\r
412\r
413 dprintf("m68k FIXME: unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);\r
414\r
415end:\r
416 return d;\r
417}\r
418\r
419\r
420static void OtherWrite8End(u32 a, u32 d, int realsize)\r
421{\r
422 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }\r
423\r
424 if ((a&0xfe0000)==0x600000) {\r
425 if (SRam.data != NULL && (Pico_mcd->m.bcram_reg&1)) {\r
426 SRam.data[((a>>1)&0xffff)+0x2000]=d;\r
427 SRam.changed = 1;\r
428 }\r
429 return;\r
430 }\r
431\r
432 if (a==0x7fffff) {\r
433 Pico_mcd->m.bcram_reg=d;\r
434 return;\r
435 }\r
436\r
437 dprintf("m68k FIXME: strange w%i: [%06x], %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
438}\r
439\r
440#define _CD_MEMORY_C\r
441#undef _ASM_MEMORY_C\r
442#include "../MemoryCmn.c"\r
443#include "cell_map.c"\r
444#endif // !def _ASM_CD_MEMORY_C\r
445\r
446\r
447// -----------------------------------------------------------------\r
448// Read Rom and read Ram\r
449\r
450#ifdef _ASM_CD_MEMORY_C\r
451u32 PicoReadM68k8(u32 a);\r
452#else\r
453static u32 PicoReadM68k8(u32 a)\r
454{\r
455 u32 d=0;\r
456\r
457 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r
458\r
459 a&=0xffffff;\r
460\r
461 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios\r
462\r
463 // prg RAM\r
464 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
465 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
466 d = *(prg_bank+((a^1)&0x1ffff));\r
467 goto end;\r
468 }\r
469\r
470 // word RAM\r
471 if ((a&0xfc0000)==0x200000) {\r
472 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);\r
473 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
474 int bank = Pico_mcd->s68k_regs[3]&1;\r
475 if (a >= 0x220000)\r
476 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged\r
477 else a &= 0x1ffff;\r
478 d = Pico_mcd->word_ram1M[bank][a^1];\r
479 } else {\r
480 // allow access in any mode, like Gens does\r
481 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];\r
482 }\r
483 wrdprintf("ret = %02x", (u8)d);\r
484 goto end;\r
485 }\r
486\r
487 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
488\r
489 if ((a&0xffffc0)==0xa12000)\r
490 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);\r
491\r
492 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;\r
493\r
494 if ((a&0xffffc0)==0xa12000)\r
495 rdprintf("ret = %02x", (u8)d);\r
496\r
497 end:\r
498\r
499#ifdef __debug_io\r
500 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
501#endif\r
502#ifdef EMU_CORE_DEBUG\r
503 if (a>=Pico.romsize) {\r
504 lastread_a = a;\r
505 lastread_d[lrp_cyc++&15] = d;\r
506 }\r
507#endif\r
508 return d;\r
509}\r
510#endif\r
511\r
512\r
513#ifdef _ASM_CD_MEMORY_C\r
514u32 PicoReadM68k16(u32 a);\r
515#else\r
516static u32 PicoReadM68k16(u32 a)\r
517{\r
518 u32 d=0;\r
519\r
520 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
521\r
522 a&=0xfffffe;\r
523\r
524 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios\r
525\r
526 // prg RAM\r
527 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
528 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
529 wrdprintf("m68k_prgram r16: [%i,%06x] @%06x", Pico_mcd->s68k_regs[3]>>6, a, SekPc);\r
530 d = *(u16 *)(prg_bank+(a&0x1fffe));\r
531 wrdprintf("ret = %04x", d);\r
532 goto end;\r
533 }\r
534\r
535 // word RAM\r
536 if ((a&0xfc0000)==0x200000) {\r
537 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);\r
538 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
539 int bank = Pico_mcd->s68k_regs[3]&1;\r
540 if (a >= 0x220000)\r
541 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged\r
542 else a &= 0x1fffe;\r
543 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);\r
544 } else {\r
545 // allow access in any mode, like Gens does\r
546 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
547 }\r
548 wrdprintf("ret = %04x", d);\r
549 goto end;\r
550 }\r
551\r
552 if ((a&0xffffc0)==0xa12000)\r
553 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);\r
554\r
555 d = OtherRead16(a, 16);\r
556\r
557 if ((a&0xffffc0)==0xa12000)\r
558 rdprintf("ret = %04x", d);\r
559\r
560 end:\r
561\r
562#ifdef __debug_io\r
563 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
564#endif\r
565#ifdef EMU_CORE_DEBUG\r
566 if (a>=Pico.romsize) {\r
567 lastread_a = a;\r
568 lastread_d[lrp_cyc++&15] = d;\r
569 }\r
570#endif\r
571 return d;\r
572}\r
573#endif\r
574\r
575\r
576#ifdef _ASM_CD_MEMORY_C\r
577u32 PicoReadM68k32(u32 a);\r
578#else\r
579static u32 PicoReadM68k32(u32 a)\r
580{\r
581 u32 d=0;\r
582\r
583 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r
584\r
585 a&=0xfffffe;\r
586\r
587 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios\r
588\r
589 // prg RAM\r
590 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
591 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
592 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
593 d = (pm[0]<<16)|pm[1];\r
594 goto end;\r
595 }\r
596\r
597 // word RAM\r
598 if ((a&0xfc0000)==0x200000) {\r
599 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);\r
600 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
601 int bank = Pico_mcd->s68k_regs[3]&1;\r
602 if (a >= 0x220000) { // cell arranged\r
603 u32 a1, a2;\r
604 a1 = (a&2) | (cell_map(a >> 2) << 2);\r
605 if (a&2) a2 = cell_map((a+2) >> 2) << 2;\r
606 else a2 = a1 + 2;\r
607 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) << 16;\r
608 d |= *(u16 *)(Pico_mcd->word_ram1M[bank]+a2);\r
609 } else {\r
610 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];\r
611 }\r
612 } else {\r
613 // allow access in any mode, like Gens does\r
614 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
615 }\r
616 wrdprintf("ret = %08x", d);\r
617 goto end;\r
618 }\r
619\r
620 if ((a&0xffffc0)==0xa12000)\r
621 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);\r
622\r
623 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
624\r
625 if ((a&0xffffc0)==0xa12000)\r
626 rdprintf("ret = %08x", d);\r
627\r
628 end:\r
629#ifdef __debug_io\r
630 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
631#endif\r
632#ifdef EMU_CORE_DEBUG\r
633 if (a>=Pico.romsize) {\r
634 lastread_a = a;\r
635 lastread_d[lrp_cyc++&15] = d;\r
636 }\r
637#endif\r
638 return d;\r
639}\r
640#endif\r
641\r
642\r
643// -----------------------------------------------------------------\r
644\r
645#ifdef _ASM_CD_MEMORY_C\r
646void PicoWriteM68k8(u32 a,u8 d);\r
647#else\r
648static void PicoWriteM68k8(u32 a,u8 d)\r
649{\r
650#ifdef __debug_io\r
651 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
652#endif\r
653#ifdef EMU_CORE_DEBUG\r
654 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
655#endif\r
656\r
657 if ((a&0xe00000)==0xe00000) { // Ram\r
658 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;\r
659 return;\r
660 }\r
661\r
662 a&=0xffffff;\r
663\r
664 // prg RAM\r
665 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
666 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
667 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;\r
668 return;\r
669 }\r
670\r
671 // word RAM\r
672 if ((a&0xfc0000)==0x200000) {\r
673 wrdprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);\r
674 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
675 int bank = Pico_mcd->s68k_regs[3]&1;\r
676 if (a >= 0x220000)\r
677 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged\r
678 else a &= 0x1ffff;\r
679 *(u8 *)(Pico_mcd->word_ram1M[bank]+(a^1))=d;\r
680 } else {\r
681 // allow access in any mode, like Gens does\r
682 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;\r
683 }\r
684 return;\r
685 }\r
686\r
687 if ((a&0xffffc0)==0xa12000) {\r
688 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);\r
689 m68k_reg_write8(a, d);\r
690 return;\r
691 }\r
692\r
693 OtherWrite8(a,d);\r
694}\r
695#endif\r
696\r
697\r
698#ifdef _ASM_CD_MEMORY_C\r
699void PicoWriteM68k16(u32 a,u16 d);\r
700#else\r
701static void PicoWriteM68k16(u32 a,u16 d)\r
702{\r
703#ifdef __debug_io\r
704 dprintf("w16: %06x, %04x", a&0xffffff, d);\r
705#endif\r
706#ifdef EMU_CORE_DEBUG\r
707 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
708#endif\r
709\r
710 if ((a&0xe00000)==0xe00000) { // Ram\r
711 *(u16 *)(Pico.ram+(a&0xfffe))=d;\r
712 return;\r
713 }\r
714\r
715 a&=0xfffffe;\r
716\r
717 // prg RAM\r
718 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
719 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
720 wrdprintf("m68k_prgram w16: [%i,%06x] %04x @%06x", Pico_mcd->s68k_regs[3]>>6, a, d, SekPc);\r
721 *(u16 *)(prg_bank+(a&0x1fffe))=d;\r
722 return;\r
723 }\r
724\r
725 // word RAM\r
726 if ((a&0xfc0000)==0x200000) {\r
727 wrdprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);\r
728 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
729 int bank = Pico_mcd->s68k_regs[3]&1;\r
730 if (a >= 0x220000)\r
731 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged\r
732 else a &= 0x1fffe;\r
733 *(u16 *)(Pico_mcd->word_ram1M[bank]+a)=d;\r
734 } else {\r
735 // allow access in any mode, like Gens does\r
736 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;\r
737 }\r
738 return;\r
739 }\r
740\r
741 // regs\r
742 if ((a&0xffffc0)==0xa12000) {\r
743 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);\r
744 if (a == 0xe) { // special case, 2 byte writes would be handled differently\r
745 Pico_mcd->s68k_regs[0xe] = d >> 8;\r
746#ifdef USE_POLL_DETECT\r
747 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {\r
748 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
749 plprintf("s68k poll release, a=%02x\n", a);\r
750 }\r
751#endif\r
752 return;\r
753 }\r
754 m68k_reg_write8(a, d>>8);\r
755 m68k_reg_write8(a+1,d&0xff);\r
756 return;\r
757 }\r
758\r
759 OtherWrite16(a,d);\r
760}\r
761#endif\r
762\r
763\r
764#ifdef _ASM_CD_MEMORY_C\r
765void PicoWriteM68k32(u32 a,u32 d);\r
766#else\r
767static void PicoWriteM68k32(u32 a,u32 d)\r
768{\r
769#ifdef __debug_io\r
770 dprintf("w32: %06x, %08x", a&0xffffff, d);\r
771#endif\r
772#ifdef EMU_CORE_DEBUG\r
773 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
774#endif\r
775\r
776 if ((a&0xe00000)==0xe00000)\r
777 {\r
778 // Ram:\r
779 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
780 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
781 return;\r
782 }\r
783\r
784 a&=0xfffffe;\r
785\r
786 // prg RAM\r
787 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
788 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
789 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
790 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
791 return;\r
792 }\r
793\r
794 // word RAM\r
795 if ((a&0xfc0000)==0x200000) {\r
796 if (d != 0) // don't log clears\r
797 wrdprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);\r
798 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
799 int bank = Pico_mcd->s68k_regs[3]&1;\r
800 if (a >= 0x220000) { // cell arranged\r
801 u32 a1, a2;\r
802 a1 = (a&2) | (cell_map(a >> 2) << 2);\r
803 if (a&2) a2 = cell_map((a+2) >> 2) << 2;\r
804 else a2 = a1 + 2;\r
805 *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) = d >> 16;\r
806 *(u16 *)(Pico_mcd->word_ram1M[bank]+a2) = d;\r
807 } else {\r
808 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
809 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
810 }\r
811 } else {\r
812 // allow access in any mode, like Gens does\r
813 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
814 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
815 }\r
816 return;\r
817 }\r
818\r
819 if ((a&0xffffc0)==0xa12000) {\r
820 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);\r
821 if ((a&0x3e) == 0xe) dprintf("m68k FIXME: w32 [%02x]", a&0x3f);\r
822 }\r
823\r
824 OtherWrite16(a, (u16)(d>>16));\r
825 OtherWrite16(a+2,(u16)d);\r
826}\r
827#endif\r
828\r
829\r
830// -----------------------------------------------------------------\r
831// S68k\r
832// -----------------------------------------------------------------\r
833\r
834#ifdef _ASM_CD_MEMORY_C\r
835u32 PicoReadS68k8(u32 a);\r
836#else\r
837static u32 PicoReadS68k8(u32 a)\r
838{\r
839 u32 d=0;\r
840\r
841#ifdef EMU_CORE_DEBUG\r
842 u32 ab=a&0xfffffe;\r
843#endif\r
844 a&=0xffffff;\r
845\r
846 // prg RAM\r
847 if (a < 0x80000) {\r
848 d = *(Pico_mcd->prg_ram+(a^1));\r
849 goto end;\r
850 }\r
851\r
852 // regs\r
853 if ((a&0xfffe00) == 0xff8000) {\r
854 a &= 0x1ff;\r
855 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);\r
856 if (a >= 0x0e && a < 0x30) {\r
857 d = Pico_mcd->s68k_regs[a];\r
858 s68k_poll_detect(a, d);\r
859 rdprintf("ret = %02x", (u8)d);\r
860 goto end;\r
861 }\r
862 else if (a >= 0x58 && a < 0x68)\r
863 d = gfx_cd_read(a&~1);\r
864 else d = s68k_reg_read16(a&~1);\r
865 if ((a&1)==0) d>>=8;\r
866 rdprintf("ret = %02x", (u8)d);\r
867 goto end;\r
868 }\r
869\r
870 // word RAM (2M area)\r
871 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
872 // test: batman returns\r
873 wrdprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPcS68k);\r
874 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?\r
875 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
876 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];\r
877 if (a&1) d &= 0x0f;\r
878 else d >>= 4;\r
879 dprintf("FIXME: decode");\r
880 } else {\r
881 // allow access in any mode, like Gens does\r
882 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];\r
883 }\r
884 wrdprintf("ret = %02x", (u8)d);\r
885 goto end;\r
886 }\r
887\r
888 // word RAM (1M area)\r
889 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
890 int bank;\r
891 wrdprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPcS68k);\r
892// if (!(Pico_mcd->s68k_regs[3]&4))\r
893// dprintf("s68k_wram1M FIXME: wrong mode");\r
894 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
895 d = Pico_mcd->word_ram1M[bank][(a^1)&0x1ffff];\r
896 wrdprintf("ret = %02x", (u8)d);\r
897 goto end;\r
898 }\r
899\r
900 // PCM\r
901 if ((a&0xff8000)==0xff0000) {\r
902 dprintf("s68k_pcm r8: [%06x] @%06x", a, SekPcS68k);\r
903 a &= 0x7fff;\r
904 if (a >= 0x2000)\r
905 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];\r
906 else if (a >= 0x20) {\r
907 a &= 0x1e;\r
908 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
909 if (a & 2) d >>= 8;\r
910 }\r
911 dprintf("ret = %02x", (u8)d);\r
912 goto end;\r
913 }\r
914\r
915 // bram\r
916 if ((a&0xff0000)==0xfe0000) {\r
917 d = Pico_mcd->bram[(a>>1)&0x1fff];\r
918 goto end;\r
919 }\r
920\r
921 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
922\r
923 end:\r
924\r
925#ifdef __debug_io2\r
926 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
927#endif\r
928#ifdef EMU_CORE_DEBUG\r
929 lastread_a = ab;\r
930 lastread_d[lrp_cyc++&15] = d;\r
931#endif\r
932 return d;\r
933}\r
934#endif\r
935\r
936\r
937#ifdef _ASM_CD_MEMORY_C\r
938u32 PicoReadS68k16(u32 a);\r
939#else\r
940static u32 PicoReadS68k16(u32 a)\r
941{\r
942 u32 d=0;\r
943\r
944#ifdef EMU_CORE_DEBUG\r
945 u32 ab=a&0xfffffe;\r
946#endif\r
947 a&=0xfffffe;\r
948\r
949 // prg RAM\r
950 if (a < 0x80000) {\r
951 wrdprintf("s68k_prgram r16: [%06x] @%06x", a, SekPcS68k);\r
952 d = *(u16 *)(Pico_mcd->prg_ram+a);\r
953 wrdprintf("ret = %04x", d);\r
954 goto end;\r
955 }\r
956\r
957 // regs\r
958 if ((a&0xfffe00) == 0xff8000) {\r
959 a &= 0x1fe;\r
960 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);\r
961 if (a >= 0x58 && a < 0x68)\r
962 d = gfx_cd_read(a);\r
963 else d = s68k_reg_read16(a);\r
964 rdprintf("ret = %04x", d);\r
965 goto end;\r
966 }\r
967\r
968 // word RAM (2M area)\r
969 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
970 wrdprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPcS68k);\r
971 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?\r
972 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
973 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];\r
974 d |= d << 4; d &= ~0xf0;\r
975 dprintf("FIXME: decode");\r
976 } else {\r
977 // allow access in any mode, like Gens does\r
978 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
979 }\r
980 wrdprintf("ret = %04x", d);\r
981 goto end;\r
982 }\r
983\r
984 // word RAM (1M area)\r
985 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
986 int bank;\r
987 wrdprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPcS68k);\r
988// if (!(Pico_mcd->s68k_regs[3]&4))\r
989// dprintf("s68k_wram1M FIXME: wrong mode");\r
990 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
991 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
992 wrdprintf("ret = %04x", d);\r
993 goto end;\r
994 }\r
995\r
996 // bram\r
997 if ((a&0xff0000)==0xfe0000) {\r
998 dprintf("FIXME: s68k_bram r16: [%06x] @%06x", a, SekPcS68k);\r
999 a = (a>>1)&0x1fff;\r
1000 d = Pico_mcd->bram[a++]; // Gens does little endian here, and so do we..\r
1001 d|= Pico_mcd->bram[a++] << 8; // This is most likely wrong\r
1002 dprintf("ret = %04x", d);\r
1003 goto end;\r
1004 }\r
1005\r
1006 // PCM\r
1007 if ((a&0xff8000)==0xff0000) {\r
1008 dprintf("FIXME: s68k_pcm r16: [%06x] @%06x", a, SekPcS68k);\r
1009 a &= 0x7fff;\r
1010 if (a >= 0x2000)\r
1011 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];\r
1012 else if (a >= 0x20) {\r
1013 a &= 0x1e;\r
1014 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
1015 if (a & 2) d >>= 8;\r
1016 }\r
1017 dprintf("ret = %04x", d);\r
1018 goto end;\r
1019 }\r
1020\r
1021 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1022\r
1023 end:\r
1024\r
1025#ifdef __debug_io2\r
1026 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1027#endif\r
1028#ifdef EMU_CORE_DEBUG\r
1029 lastread_a = ab;\r
1030 lastread_d[lrp_cyc++&15] = d;\r
1031#endif\r
1032 return d;\r
1033}\r
1034#endif\r
1035\r
1036\r
1037#ifdef _ASM_CD_MEMORY_C\r
1038u32 PicoReadS68k32(u32 a);\r
1039#else\r
1040static u32 PicoReadS68k32(u32 a)\r
1041{\r
1042 u32 d=0;\r
1043\r
1044#ifdef EMU_CORE_DEBUG\r
1045 u32 ab=a&0xfffffe;\r
1046#endif\r
1047 a&=0xfffffe;\r
1048\r
1049 // prg RAM\r
1050 if (a < 0x80000) {\r
1051 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
1052 d = (pm[0]<<16)|pm[1];\r
1053 goto end;\r
1054 }\r
1055\r
1056 // regs\r
1057 if ((a&0xfffe00) == 0xff8000) {\r
1058 a &= 0x1fe;\r
1059 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);\r
1060 if (a >= 0x58 && a < 0x68)\r
1061 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);\r
1062 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);\r
1063 rdprintf("ret = %08x", d);\r
1064 goto end;\r
1065 }\r
1066\r
1067 // word RAM (2M area)\r
1068 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1069 wrdprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPcS68k);\r
1070 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?\r
1071 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1072 a >>= 1;\r
1073 d = Pico_mcd->word_ram1M[bank][((a+0)^1)&0x1ffff] << 16;\r
1074 d |= Pico_mcd->word_ram1M[bank][((a+1)^1)&0x1ffff];\r
1075 d |= d << 4; d &= 0x0f0f0f0f;\r
1076 } else {\r
1077 // allow access in any mode, like Gens does\r
1078 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
1079 }\r
1080 wrdprintf("ret = %08x", d);\r
1081 goto end;\r
1082 }\r
1083\r
1084 // word RAM (1M area)\r
1085 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1086 int bank;\r
1087 wrdprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPcS68k);\r
1088// if (!(Pico_mcd->s68k_regs[3]&4))\r
1089// dprintf("s68k_wram1M FIXME: wrong mode");\r
1090 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1091 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];\r
1092 wrdprintf("ret = %08x", d);\r
1093 goto end;\r
1094 }\r
1095\r
1096 // PCM\r
1097 if ((a&0xff8000)==0xff0000) {\r
1098 dprintf("s68k_pcm r32: [%06x] @%06x", a, SekPcS68k);\r
1099 a &= 0x7fff;\r
1100 if (a >= 0x2000) {\r
1101 a >>= 1;\r
1102 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] << 16;\r
1103 d |= Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff];\r
1104 } else if (a >= 0x20) {\r
1105 a &= 0x1e;\r
1106 if (a & 2) {\r
1107 a >>= 2;\r
1108 d = (Pico_mcd->pcm.ch[a].addr >> (PCM_STEP_SHIFT-8)) & 0xff0000;\r
1109 d |= (Pico_mcd->pcm.ch[(a+1)&7].addr >> PCM_STEP_SHIFT) & 0xff;\r
1110 } else {\r
1111 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
1112 d = ((d<<16)&0xff0000) | ((d>>8)&0xff); // PCM chip is LE\r
1113 }\r
1114 }\r
1115 dprintf("ret = %08x", d);\r
1116 goto end;\r
1117 }\r
1118\r
1119 // bram\r
1120 if ((a&0xff0000)==0xfe0000) {\r
1121 dprintf("FIXME: s68k_bram r32: [%06x] @%06x", a, SekPcS68k);\r
1122 a = (a>>1)&0x1fff;\r
1123 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..\r
1124 d|= Pico_mcd->bram[a++] << 24;\r
1125 d|= Pico_mcd->bram[a++];\r
1126 d|= Pico_mcd->bram[a++] << 8;\r
1127 dprintf("ret = %08x", d);\r
1128 goto end;\r
1129 }\r
1130\r
1131 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1132\r
1133 end:\r
1134\r
1135#ifdef __debug_io2\r
1136 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1137#endif\r
1138#ifdef EMU_CORE_DEBUG\r
1139 if (ab > 0x78) { // not vectors and stuff\r
1140 lastread_a = ab;\r
1141 lastread_d[lrp_cyc++&15] = d;\r
1142 }\r
1143#endif\r
1144 return d;\r
1145}\r
1146#endif\r
1147\r
1148\r
1149#ifndef _ASM_CD_MEMORY_C\r
1150/* check: jaguar xj 220 (draws entire world using decode) */\r
1151static void decode_write8(u32 a, u8 d, int r3)\r
1152{\r
1153 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);\r
1154 u8 oldmask = (a&1) ? 0xf0 : 0x0f;\r
1155\r
1156 r3 &= 0x18;\r
1157 d &= 0x0f;\r
1158 if (!(a&1)) d <<= 4;\r
1159\r
1160 if (r3 == 8) {\r
1161 if ((!(*pd & (~oldmask))) && d) goto do_it;\r
1162 } else if (r3 > 8) {\r
1163 if (d) goto do_it;\r
1164 } else {\r
1165 goto do_it;\r
1166 }\r
1167\r
1168 return;\r
1169do_it:\r
1170 *pd = d | (*pd & oldmask);\r
1171}\r
1172\r
1173\r
1174static void decode_write16(u32 a, u16 d, int r3)\r
1175{\r
1176 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);\r
1177\r
1178 //if ((a & 0x3ffff) < 0x28000) return;\r
1179\r
1180 r3 &= 0x18;\r
1181 d &= 0x0f0f;\r
1182 d |= d >> 4;\r
1183\r
1184 if (r3 == 8) {\r
1185 u8 dold = *pd;\r
1186 if (!(dold & 0xf0)) dold |= d & 0xf0;\r
1187 if (!(dold & 0x0f)) dold |= d & 0x0f;\r
1188 *pd = dold;\r
1189 } else if (r3 > 8) {\r
1190 u8 dold = *pd;\r
1191 if (!(d & 0xf0)) d |= dold & 0xf0;\r
1192 if (!(d & 0x0f)) d |= dold & 0x0f;\r
1193 *pd = d;\r
1194 } else {\r
1195 *pd = d;\r
1196 }\r
1197}\r
1198#endif\r
1199\r
1200// -----------------------------------------------------------------\r
1201\r
1202#ifdef _ASM_CD_MEMORY_C\r
1203void PicoWriteS68k8(u32 a,u8 d);\r
1204#else\r
1205static void PicoWriteS68k8(u32 a,u8 d)\r
1206{\r
1207#ifdef __debug_io2\r
1208 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
1209#endif\r
1210\r
1211 a&=0xffffff;\r
1212\r
1213#ifdef EMU_CORE_DEBUG\r
1214 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
1215#endif\r
1216\r
1217 // prg RAM\r
1218 if (a < 0x80000) {\r
1219 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));\r
1220 if (a >= (Pico_mcd->s68k_regs[2]<<8)) *pm=d;\r
1221 return;\r
1222 }\r
1223\r
1224 // regs\r
1225 if ((a&0xfffe00) == 0xff8000) {\r
1226 a &= 0x1ff;\r
1227 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);\r
1228 if (a >= 0x58 && a < 0x68)\r
1229 gfx_cd_write16(a&~1, (d<<8)|d);\r
1230 else s68k_reg_write8(a,d);\r
1231 return;\r
1232 }\r
1233\r
1234 // word RAM (2M area)\r
1235 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1236 int r3 = Pico_mcd->s68k_regs[3];\r
1237 wrdprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPcS68k);\r
1238 if (r3 & 4) { // 1M decode mode?\r
1239 decode_write8(a, d, r3);\r
1240 } else {\r
1241 // allow access in any mode, like Gens does\r
1242 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;\r
1243 }\r
1244 return;\r
1245 }\r
1246\r
1247 // word RAM (1M area)\r
1248 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1249 // Wing Commander tries to write here in wrong mode\r
1250 int bank;\r
1251 if (d)\r
1252 wrdprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPcS68k);\r
1253// if (!(Pico_mcd->s68k_regs[3]&4))\r
1254// dprintf("s68k_wram1M FIXME: wrong mode");\r
1255 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1256 *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff))=d;\r
1257 return;\r
1258 }\r
1259\r
1260 // PCM\r
1261 if ((a&0xff8000)==0xff0000) {\r
1262 a &= 0x7fff;\r
1263 if (a >= 0x2000)\r
1264 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
1265 else if (a < 0x12)\r
1266 pcm_write(a>>1, d);\r
1267 return;\r
1268 }\r
1269\r
1270 // bram\r
1271 if ((a&0xff0000)==0xfe0000) {\r
1272 Pico_mcd->bram[(a>>1)&0x1fff] = d;\r
1273 SRam.changed = 1;\r
1274 return;\r
1275 }\r
1276\r
1277 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
1278}\r
1279#endif\r
1280\r
1281\r
1282#ifdef _ASM_CD_MEMORY_C\r
1283void PicoWriteS68k16(u32 a,u16 d);\r
1284#else\r
1285static void PicoWriteS68k16(u32 a,u16 d)\r
1286{\r
1287#ifdef __debug_io2\r
1288 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1289#endif\r
1290\r
1291 a&=0xfffffe;\r
1292\r
1293#ifdef EMU_CORE_DEBUG\r
1294 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
1295#endif\r
1296\r
1297 // prg RAM\r
1298 if (a < 0x80000) {\r
1299 wrdprintf("s68k_prgram w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
1300 if (a >= (Pico_mcd->s68k_regs[2]<<8)) // needed for Dungeon Explorer\r
1301 *(u16 *)(Pico_mcd->prg_ram+a)=d;\r
1302 return;\r
1303 }\r
1304\r
1305 // regs\r
1306 if ((a&0xfffe00) == 0xff8000) {\r
1307 a &= 0x1fe;\r
1308 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);\r
1309 if (a >= 0x58 && a < 0x68)\r
1310 gfx_cd_write16(a, d);\r
1311 else {\r
1312 if (a == 0xe) { // special case, 2 byte writes would be handled differently\r
1313 Pico_mcd->s68k_regs[0xf] = d;\r
1314 return;\r
1315 }\r
1316 s68k_reg_write8(a, d>>8);\r
1317 s68k_reg_write8(a+1,d&0xff);\r
1318 }\r
1319 return;\r
1320 }\r
1321\r
1322 // word RAM (2M area)\r
1323 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1324 int r3 = Pico_mcd->s68k_regs[3];\r
1325 wrdprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
1326 if (r3 & 4) { // 1M decode mode?\r
1327 decode_write16(a, d, r3);\r
1328 } else {\r
1329 // allow access in any mode, like Gens does\r
1330 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;\r
1331 }\r
1332 return;\r
1333 }\r
1334\r
1335 // word RAM (1M area)\r
1336 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1337 int bank;\r
1338 if (d)\r
1339 wrdprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
1340// if (!(Pico_mcd->s68k_regs[3]&4))\r
1341// dprintf("s68k_wram1M FIXME: wrong mode");\r
1342 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1343 *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe))=d;\r
1344 return;\r
1345 }\r
1346\r
1347 // PCM\r
1348 if ((a&0xff8000)==0xff0000) {\r
1349 a &= 0x7fff;\r
1350 if (a >= 0x2000)\r
1351 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
1352 else if (a < 0x12)\r
1353 pcm_write(a>>1, d & 0xff);\r
1354 return;\r
1355 }\r
1356\r
1357 // bram\r
1358 if ((a&0xff0000)==0xfe0000) {\r
1359 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
1360 a = (a>>1)&0x1fff;\r
1361 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..\r
1362 Pico_mcd->bram[a++] = d >> 8;\r
1363 SRam.changed = 1;\r
1364 return;\r
1365 }\r
1366\r
1367 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1368}\r
1369#endif\r
1370\r
1371\r
1372#ifdef _ASM_CD_MEMORY_C\r
1373void PicoWriteS68k32(u32 a,u32 d);\r
1374#else\r
1375static void PicoWriteS68k32(u32 a,u32 d)\r
1376{\r
1377#ifdef __debug_io2\r
1378 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1379#endif\r
1380\r
1381 a&=0xfffffe;\r
1382\r
1383#ifdef EMU_CORE_DEBUG\r
1384 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
1385#endif\r
1386\r
1387 // prg RAM\r
1388 if (a < 0x80000) {\r
1389 if (a >= (Pico_mcd->s68k_regs[2]<<8)) {\r
1390 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
1391 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1392 }\r
1393 return;\r
1394 }\r
1395\r
1396 // regs\r
1397 if ((a&0xfffe00) == 0xff8000) {\r
1398 a &= 0x1fe;\r
1399 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);\r
1400 if (a >= 0x58 && a < 0x68) {\r
1401 gfx_cd_write16(a, d>>16);\r
1402 gfx_cd_write16(a+2, d&0xffff);\r
1403 } else {\r
1404 if ((a&0x1fe) == 0xe) dprintf("s68k FIXME: w32 [%02x]", a&0x3f);\r
1405 s68k_reg_write8(a, d>>24);\r
1406 s68k_reg_write8(a+1,(d>>16)&0xff);\r
1407 s68k_reg_write8(a+2,(d>>8) &0xff);\r
1408 s68k_reg_write8(a+3, d &0xff);\r
1409 }\r
1410 return;\r
1411 }\r
1412\r
1413 // word RAM (2M area)\r
1414 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1415 int r3 = Pico_mcd->s68k_regs[3];\r
1416 wrdprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPcS68k);\r
1417 if (r3 & 4) { // 1M decode mode?\r
1418 decode_write16(a , d >> 16, r3);\r
1419 decode_write16(a+2, d , r3);\r
1420 } else {\r
1421 // allow access in any mode, like Gens does\r
1422 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
1423 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1424 }\r
1425 return;\r
1426 }\r
1427\r
1428 // word RAM (1M area)\r
1429 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1430 int bank;\r
1431 u16 *pm;\r
1432 if (d)\r
1433 wrdprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPcS68k);\r
1434// if (!(Pico_mcd->s68k_regs[3]&4))\r
1435// dprintf("s68k_wram1M FIXME: wrong mode");\r
1436 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1437 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1438 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1439 return;\r
1440 }\r
1441\r
1442 // PCM\r
1443 if ((a&0xff8000)==0xff0000) {\r
1444 a &= 0x7fff;\r
1445 if (a >= 0x2000) {\r
1446 a >>= 1;\r
1447 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] = (d >> 16);\r
1448 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff] = d;\r
1449 } else if (a < 0x12) {\r
1450 a >>= 1;\r
1451 pcm_write(a, (d>>16) & 0xff);\r
1452 pcm_write(a+1, d & 0xff);\r
1453 }\r
1454 return;\r
1455 }\r
1456\r
1457 // bram\r
1458 if ((a&0xff0000)==0xfe0000) {\r
1459 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPcS68k);\r
1460 a = (a>>1)&0x1fff;\r
1461 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?\r
1462 Pico_mcd->bram[a++] = d >> 24;\r
1463 Pico_mcd->bram[a++] = d;\r
1464 Pico_mcd->bram[a++] = d >> 8;\r
1465 SRam.changed = 1;\r
1466 return;\r
1467 }\r
1468\r
1469 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1470}\r
1471#endif\r
1472\r
1473\r
1474// -----------------------------------------------------------------\r
1475\r
1476\r
1477#ifdef EMU_C68K\r
1478static __inline int PicoMemBaseM68k(u32 pc)\r
1479{\r
1480 if ((pc&0xe00000)==0xe00000)\r
1481 return (int)Pico.ram-(pc&0xff0000); // Program Counter in Ram\r
1482\r
1483 if (pc < 0x20000)\r
1484 return (int)Pico_mcd->bios; // Program Counter in BIOS\r
1485\r
1486 if ((pc&0xfc0000)==0x200000)\r
1487 {\r
1488 if (!(Pico_mcd->s68k_regs[3]&4))\r
1489 return (int)Pico_mcd->word_ram2M - 0x200000; // Program Counter in Word Ram\r
1490 if (pc < 0x220000) {\r
1491 int bank = Pico_mcd->s68k_regs[3]&1;\r
1492 return (int)Pico_mcd->word_ram1M[bank] - 0x200000;\r
1493 }\r
1494 }\r
1495\r
1496 // Error - Program Counter is invalid\r
1497 dprintf("m68k FIXME: unhandled jump to %06x", pc);\r
1498\r
1499 return (int)Pico_mcd->bios;\r
1500}\r
1501\r
1502\r
1503static u32 PicoCheckPcM68k(u32 pc)\r
1504{\r
1505 pc-=PicoCpuCM68k.membase; // Get real pc\r
1506 pc&=0xfffffe;\r
1507\r
1508 PicoCpuCM68k.membase=PicoMemBaseM68k(pc);\r
1509\r
1510 return PicoCpuCM68k.membase+pc;\r
1511}\r
1512\r
1513\r
1514static __inline int PicoMemBaseS68k(u32 pc)\r
1515{\r
1516 if (pc < 0x80000) // PRG RAM\r
1517 return (int)Pico_mcd->prg_ram;\r
1518\r
1519 if ((pc&0xfc0000)==0x080000) // WORD RAM 2M area (assume we are in the right mode..)\r
1520 return (int)Pico_mcd->word_ram2M - 0x080000;\r
1521\r
1522 if ((pc&0xfe0000)==0x0c0000) { // word RAM 1M area\r
1523 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1524 return (int)Pico_mcd->word_ram1M[bank] - 0x0c0000;\r
1525 }\r
1526\r
1527 // Error - Program Counter is invalid\r
1528 dprintf("s68k FIXME: unhandled jump to %06x", pc);\r
1529\r
1530 return (int)Pico_mcd->prg_ram;\r
1531}\r
1532\r
1533\r
1534static u32 PicoCheckPcS68k(u32 pc)\r
1535{\r
1536 pc-=PicoCpuCS68k.membase; // Get real pc\r
1537 pc&=0xfffffe;\r
1538\r
1539 PicoCpuCS68k.membase=PicoMemBaseS68k(pc);\r
1540\r
1541 return PicoCpuCS68k.membase+pc;\r
1542}\r
1543#endif\r
1544\r
1545#ifndef _ASM_CD_MEMORY_C\r
1546void PicoMemResetCD(int r3)\r
1547{\r
1548#ifdef EMU_F68K\r
1549 // update fetchmap..\r
1550 int i;\r
1551 if (!(r3 & 4))\r
1552 {\r
1553 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x240000; i++)\r
1554 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x200000;\r
1555 }\r
1556 else\r
1557 {\r
1558 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x220000; i++)\r
1559 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[r3 & 1] - 0x200000;\r
1560 for (i = M68K_FETCHBANK1*0x0c/0x100; (i<<(24-FAMEC_FETCHBITS)) < 0x0e0000; i++)\r
1561 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[(r3&1)^1] - 0x0c0000;\r
1562 }\r
1563#endif\r
1564}\r
1565#endif\r
1566\r
1567PICO_INTERNAL void PicoMemSetupCD(void)\r
1568{\r
1569 dprintf("PicoMemSetupCD()");\r
1570#ifdef EMU_C68K\r
1571 // Setup m68k memory callbacks:\r
1572 PicoCpuCM68k.checkpc=PicoCheckPcM68k;\r
1573 PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoReadM68k8;\r
1574 PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoReadM68k16;\r
1575 PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoReadM68k32;\r
1576 PicoCpuCM68k.write8 =PicoWriteM68k8;\r
1577 PicoCpuCM68k.write16=PicoWriteM68k16;\r
1578 PicoCpuCM68k.write32=PicoWriteM68k32;\r
1579 // s68k\r
1580 PicoCpuCS68k.checkpc=PicoCheckPcS68k;\r
1581 PicoCpuCS68k.fetch8 =PicoCpuCS68k.read8 =PicoReadS68k8;\r
1582 PicoCpuCS68k.fetch16=PicoCpuCS68k.read16=PicoReadS68k16;\r
1583 PicoCpuCS68k.fetch32=PicoCpuCS68k.read32=PicoReadS68k32;\r
1584 PicoCpuCS68k.write8 =PicoWriteS68k8;\r
1585 PicoCpuCS68k.write16=PicoWriteS68k16;\r
1586 PicoCpuCS68k.write32=PicoWriteS68k32;\r
1587#endif\r
1588#ifdef EMU_F68K\r
1589 // m68k\r
1590 PicoCpuFM68k.read_byte =PicoReadM68k8;\r
1591 PicoCpuFM68k.read_word =PicoReadM68k16;\r
1592 PicoCpuFM68k.read_long =PicoReadM68k32;\r
1593 PicoCpuFM68k.write_byte=PicoWriteM68k8;\r
1594 PicoCpuFM68k.write_word=PicoWriteM68k16;\r
1595 PicoCpuFM68k.write_long=PicoWriteM68k32;\r
1596 // s68k\r
1597 PicoCpuFS68k.read_byte =PicoReadS68k8;\r
1598 PicoCpuFS68k.read_word =PicoReadS68k16;\r
1599 PicoCpuFS68k.read_long =PicoReadS68k32;\r
1600 PicoCpuFS68k.write_byte=PicoWriteS68k8;\r
1601 PicoCpuFS68k.write_word=PicoWriteS68k16;\r
1602 PicoCpuFS68k.write_long=PicoWriteS68k32;\r
1603\r
1604 // setup FAME fetchmap\r
1605 {\r
1606 int i;\r
1607 // M68k\r
1608 // by default, point everything to fitst 64k of ROM (BIOS)\r
1609 for (i = 0; i < M68K_FETCHBANK1; i++)\r
1610 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
1611 // now real ROM (BIOS)\r
1612 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
1613 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
1614 // .. and RAM\r
1615 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
1616 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
1617 // S68k\r
1618 // PRG RAM is default\r
1619 for (i = 0; i < M68K_FETCHBANK1; i++)\r
1620 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));\r
1621 // real PRG RAM\r
1622 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0x80000; i++)\r
1623 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram;\r
1624 // WORD RAM 2M area\r
1625 for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)\r
1626 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x80000;\r
1627 // PicoMemResetCD() will setup word ram for both\r
1628 }\r
1629#endif\r
1630\r
1631 // m68k_poll_addr = m68k_poll_cnt = 0;\r
1632 s68k_poll_adclk = s68k_poll_cnt = 0;\r
1633}\r
1634\r
1635\r
1636#ifdef EMU_M68K\r
1637unsigned char PicoReadCD8w (unsigned int a) {\r
1638 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k8(a) : PicoReadM68k8(a);\r
1639}\r
1640unsigned short PicoReadCD16w(unsigned int a) {\r
1641 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k16(a) : PicoReadM68k16(a);\r
1642}\r
1643unsigned int PicoReadCD32w(unsigned int a) {\r
1644 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k32(a) : PicoReadM68k32(a);\r
1645}\r
1646void PicoWriteCD8w (unsigned int a, unsigned char d) {\r
1647 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);\r
1648}\r
1649void PicoWriteCD16w(unsigned int a, unsigned short d) {\r
1650 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);\r
1651}\r
1652void PicoWriteCD32w(unsigned int a, unsigned int d) {\r
1653 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);\r
1654}\r
1655\r
1656// these are allowed to access RAM\r
1657unsigned int m68k_read_pcrelative_CD8 (unsigned int a)\r
1658{\r
1659 a&=0xffffff;\r
1660 if(m68ki_cpu_p == &PicoCpuMS68k) {\r
1661 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram\r
1662 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)\r
1663 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));\r
1664 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)\r
1665 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1666 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));\r
1667 }\r
1668 dprintf("s68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);\r
1669 } else {\r
1670 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
1671 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios\r
1672 if((a&0xfc0000)==0x200000) { // word RAM\r
1673 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?\r
1674 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));\r
1675 else if (a < 0x220000) {\r
1676 int bank = Pico_mcd->s68k_regs[3]&1;\r
1677 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));\r
1678 }\r
1679 }\r
1680 dprintf("m68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);\r
1681 }\r
1682 return 0;//(u8) lastread_d;\r
1683}\r
1684unsigned int m68k_read_pcrelative_CD16(unsigned int a)\r
1685{\r
1686 a&=0xffffff;\r
1687 if(m68ki_cpu_p == &PicoCpuMS68k) {\r
1688 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram\r
1689 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)\r
1690 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
1691 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)\r
1692 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1693 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1694 }\r
1695 dprintf("s68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);\r
1696 } else {\r
1697 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
1698 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios\r
1699 if((a&0xfc0000)==0x200000) { // word RAM\r
1700 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?\r
1701 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
1702 else if (a < 0x220000) {\r
1703 int bank = Pico_mcd->s68k_regs[3]&1;\r
1704 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1705 }\r
1706 }\r
1707 dprintf("m68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);\r
1708 }\r
1709 return 0;\r
1710}\r
1711unsigned int m68k_read_pcrelative_CD32(unsigned int a)\r
1712{\r
1713 u16 *pm;\r
1714 a&=0xffffff;\r
1715 if(m68ki_cpu_p == &PicoCpuMS68k) {\r
1716 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram\r
1717 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)\r
1718 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }\r
1719 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)\r
1720 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
1721 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1722 return (pm[0]<<16)|pm[1];\r
1723 }\r
1724 dprintf("s68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);\r
1725 } else {\r
1726 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
1727 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
1728 if((a&0xfc0000)==0x200000) { // word RAM\r
1729 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?\r
1730 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }\r
1731 else if (a < 0x220000) {\r
1732 int bank = Pico_mcd->s68k_regs[3]&1;\r
1733 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1734 return (pm[0]<<16)|pm[1];\r
1735 }\r
1736 }\r
1737 dprintf("m68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);\r
1738 }\r
1739 return 0;\r
1740}\r
1741#endif // EMU_M68K\r
1742\r
fast MegaDrive/MegaCD/32X emulator