| 1 | \r |
| 2 | // Cyclone 68000 Emulator - Header File\r |
| 3 | \r |
| 4 | // Most code (c) Copyright 2004 Dave, All rights reserved.\r |
| 5 | // Some coding/bugfixing was done by notaz\r |
| 6 | // Cyclone 68000 is free for non-commercial use.\r |
| 7 | \r |
| 8 | // For commercial use, separate licencing terms must be obtained.\r |
| 9 | \r |
| 10 | #ifdef __cplusplus\r |
| 11 | extern "C" {\r |
| 12 | #endif\r |
| 13 | \r |
| 14 | extern int CycloneVer; // Version number of library\r |
| 15 | \r |
| 16 | struct Cyclone\r |
| 17 | {\r |
| 18 | unsigned int d[8]; // [r7,#0x00]\r |
| 19 | unsigned int a[8]; // [r7,#0x20]\r |
| 20 | unsigned int pc; // [r7,#0x40] Memory Base+PC\r |
| 21 | unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r |
| 22 | unsigned char xc; // [r7,#0x45] Extend flag (____??X?)\r |
| 23 | unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r |
| 24 | unsigned char irq; // [r7,#0x47] IRQ level\r |
| 25 | unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r |
| 26 | unsigned int vector; // [r7,#0x4c] IRQ vector (temporary)\r |
| 27 | unsigned int pad1[2];\r |
| 28 | int stopped; // [r7,#0x58] 1 == processor is in stopped state\r |
| 29 | int cycles; // [r7,#0x5c]\r |
| 30 | int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r |
| 31 | unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc\r |
| 32 | unsigned char (*read8 )(unsigned int a); // [r7,#0x68]\r |
| 33 | unsigned short (*read16 )(unsigned int a); // [r7,#0x6c]\r |
| 34 | unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r |
| 35 | void (*write8 )(unsigned int a,unsigned char d); // [r7,#0x74]\r |
| 36 | void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]\r |
| 37 | void (*write32)(unsigned int a,unsigned int d); // [r7,#0x7c]\r |
| 38 | unsigned char (*fetch8 )(unsigned int a); // [r7,#0x80]\r |
| 39 | unsigned short (*fetch16)(unsigned int a); // [r7,#0x84]\r |
| 40 | unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r |
| 41 | void (*IrqCallback)(int int_level); // [r7,#0x8c] - optional irq callback function, see config.h\r |
| 42 | void (*ResetCallback)(); // [r7,#0x90] - if enabled in config.h, calls this whenever RESET opcode is encountered.\r |
| 43 | int (*UnrecognizedCallback)(); // [r7,#0x94] - if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r |
| 44 | };\r |
| 45 | \r |
| 46 | // used only if Cyclone was compiled with compressed jumptable, see config.h\r |
| 47 | void CycloneInit();\r |
| 48 | \r |
| 49 | // run cyclone. Cycles should be specified in context (pcy->cycles)\r |
| 50 | void CycloneRun(struct Cyclone *pcy);\r |
| 51 | \r |
| 52 | // utility functions to get and set SR\r |
| 53 | void CycloneSetSr(struct Cyclone *pcy, unsigned int sr); // auto-swaps a7<->osp if detects supervisor change\r |
| 54 | unsigned int CycloneGetSr(struct Cyclone *pcy);\r |
| 55 | \r |
| 56 | // genesis: if 1, switch to normal TAS handlers\r |
| 57 | void CycloneSetRealTAS(int use_real);\r |
| 58 | \r |
| 59 | #ifdef __cplusplus\r |
| 60 | } // End of extern "C"\r |
| 61 | #endif\r |