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Cyclone: direct memhandler calls option + reset function
[picodrive.git] / cpu / Cyclone / OpBranch.cpp
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CommitLineData
1\r
2#include "app.h"\r
3\r
4// in/out address in r0, trashes all temp regs\r
5static void CheckPc(void)\r
6{\r
7#if USE_CHECKPC_CALLBACK\r
8 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
9 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
10 #else\r
11 ot(";@ Check Memory Base+pc\n");\r
12 ot(" mov lr,pc\n");\r
13 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
14 ot("\n");\r
15 #endif\r
16#endif\r
17}\r
18\r
19// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
20void OpPush32()\r
21{\r
22 ot(";@ Push r1 onto stack\n");\r
23 ot(" ldr r0,[r7,#0x3c]\n");\r
24 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
25 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
26 MemHandler(1,2);\r
27 ot("\n");\r
28}\r
29\r
30// Push SR - trashes r0-r3,r12,lr\r
31void OpPushSr(int high)\r
32{\r
33 ot(";@ Push SR:\n");\r
34 OpFlagsToReg(high);\r
35 ot(" ldr r0,[r7,#0x3c]\n");\r
36 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
37 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
38 MemHandler(1,1);\r
39 ot("\n");\r
40}\r
41\r
42// Pop SR - trashes r0-r3\r
43static void PopSr(int high)\r
44{\r
45 ot(";@ Pop SR:\n");\r
46 ot(" ldr r0,[r7,#0x3c]\n");\r
47 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
48 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
49 MemHandler(0,1);\r
50 ot("\n");\r
51 OpRegToFlags(high);\r
52}\r
53\r
54// Pop PC - trashes r0-r3\r
55static void PopPc()\r
56{\r
57 ot(";@ Pop PC:\n");\r
58 ot(" ldr r0,[r7,#0x3c]\n");\r
59 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
60 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
61 MemHandler(0,2);\r
62 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
63 ot(" add r0,r0,r1 ;@ Memory Base+PC\n");\r
64 ot("\n");\r
65 CheckPc();\r
66#if EMULATE_ADDRESS_ERRORS_JUMP\r
67 ot(" mov r4,r0\n");\r
68#else\r
69 ot(" bic r4,r0,#1\n");\r
70#endif\r
71}\r
72\r
73int OpTrap(int op)\r
74{\r
75 int use=0;\r
76\r
77 use=op&~0xf;\r
78 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
79\r
80 OpStart(op,0x10);\r
81 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
82 ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r
83 ot(" bl Exception\n");\r
84 ot("\n");\r
85\r
86 Cycles=38; OpEnd(0x10);\r
87\r
88 return 0;\r
89}\r
90\r
91// --------------------- Opcodes 0x4e50+ ---------------------\r
92int OpLink(int op)\r
93{\r
94 int use=0,reg;\r
95\r
96 use=op&~7;\r
97 reg=op&7;\r
98 if (reg==7) use=op;\r
99 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
100\r
101 OpStart(op,0x10);\r
102\r
103 if(reg!=7) {\r
104 ot(";@ Get An\n");\r
105 EaCalc(11, 7, 8, 2, 1);\r
106 EaRead(11, 1, 8, 2, 7, 1);\r
107 }\r
108\r
109 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
110 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
111 ot(" mov r8,r0 ;@ abuse r8\n");\r
112 if(reg==7) ot(" mov r1,r0\n");\r
113 ot("\n");\r
114 \r
115 ot(";@ Write An to Stack\n");\r
116 MemHandler(1,2);\r
117\r
118 ot(";@ Save to An\n");\r
119 if(reg!=7)\r
120 EaWrite(11,8, 8, 2, 7, 1);\r
121\r
122 ot(";@ Get offset:\n");\r
123 EaCalc(0,0,0x3c,1); // abused r8 is ok because of imm EA\r
124 EaRead(0,0,0x3c,1,0);\r
125\r
126 ot(" add r8,r8,r0 ;@ Add offset to A7\n");\r
127 ot(" str r8,[r7,#0x3c]\n");\r
128 ot("\n");\r
129\r
130 Cycles=16;\r
131 OpEnd(0x10);\r
132 return 0;\r
133}\r
134\r
135// --------------------- Opcodes 0x4e58+ ---------------------\r
136int OpUnlk(int op)\r
137{\r
138 int use=0;\r
139\r
140 use=op&~7;\r
141 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
142\r
143 OpStart(op,0x10);\r
144\r
145 ot(";@ Get An\n");\r
146 EaCalc(11, 0xf, 8, 2, 1);\r
147 EaRead(11, 0, 8, 2, 0xf, 1);\r
148\r
149 ot(" add r8,r0,#4 ;@ A7+=4, abuse r8\n");\r
150 ot("\n");\r
151 ot(";@ Pop An from stack:\n");\r
152 MemHandler(0,2);\r
153 ot("\n");\r
154 ot(" str r8,[r7,#0x3c] ;@ Save A7\n");\r
155 ot("\n");\r
156 ot(";@ An = value from stack:\n");\r
157 EaWrite(11, 0, 8, 2, 7, 1);\r
158\r
159 Cycles=12;\r
160 OpEnd(0x10);\r
161 return 0;\r
162}\r
163\r
164// --------------------- Opcodes 0x4e70+ ---------------------\r
165// 01001110 01110ttt\r
166int Op4E70(int op)\r
167{\r
168 int type=0;\r
169\r
170 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
171\r
172 switch (type)\r
173 {\r
174 case 1: // nop\r
175 OpStart(op);\r
176 Cycles=4;\r
177 OpEnd();\r
178 return 0;\r
179\r
180 case 3: // rte\r
181 OpStart(op,0x10,0,0,1); Cycles=20;\r
182 PopSr(1);\r
183 PopPc();\r
184 ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
185 SuperChange(op,1);\r
186#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
187 ot(" ldr r1,[r7,#0x58]\n");\r
188 ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
189 ot(" str r1,[r7,#0x58]\n");\r
190#endif\r
191#if EMULATE_ADDRESS_ERRORS_JUMP\r
192 ot(" tst r4,#1 ;@ address error?\n");\r
193 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
194#endif\r
195 opend_check_interrupt = 1;\r
196 opend_check_trace = 1;\r
197 OpEnd(0x10,0);\r
198 return 0;\r
199\r
200 case 5: // rts\r
201 OpStart(op,0x10); Cycles=16;\r
202 PopPc();\r
203#if EMULATE_ADDRESS_ERRORS_JUMP\r
204 ot(" tst r4,#1 ;@ address error?\n");\r
205 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
206#endif\r
207 OpEnd(0x10);\r
208 return 0;\r
209\r
210 case 6: // trapv\r
211 OpStart(op,0x10,0,1); Cycles=4;\r
212 ot(" tst r10,#0x10000000\n");\r
213 ot(" subne r5,r5,#%i\n",34);\r
214 ot(" movne r0,#7 ;@ TRAPV exception\n");\r
215 ot(" blne Exception\n");\r
216 opend_op_changes_cycles = 1;\r
217 OpEnd(0x10,0);\r
218 return 0;\r
219\r
220 case 7: // rtr\r
221 OpStart(op,0x10); Cycles=20;\r
222 PopSr(0);\r
223 PopPc();\r
224#if EMULATE_ADDRESS_ERRORS_JUMP\r
225 ot(" tst r4,#1 ;@ address error?\n");\r
226 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
227#endif\r
228 OpEnd(0x10);\r
229 return 0;\r
230\r
231 default:\r
232 return 1;\r
233 }\r
234}\r
235\r
236// --------------------- Opcodes 0x4e80+ ---------------------\r
237// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
238int OpJsr(int op)\r
239{\r
240 int use=0;\r
241 int sea=0;\r
242\r
243 sea=op&0x003f;\r
244\r
245 // See if we can do this opcode:\r
246 if (EaCanRead(sea,-1)==0) return 1;\r
247\r
248 use=OpBase(op,0);\r
249 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
250\r
251 OpStart(op,(op&0x40)?0:0x10);\r
252\r
253 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
254 ot("\n");\r
255 EaCalc(12,0x003f,sea,0);\r
256\r
257 ot(";@ Jump - Get new PC from r12\n");\r
258 ot(" add r0,r12,r11 ;@ Memory Base + New PC\n");\r
259 ot("\n");\r
260 CheckPc();\r
261 if (!(op&0x40))\r
262 {\r
263 ot(" ldr r2,[r7,#0x3c]\n");\r
264 ot(" sub r1,r4,r11 ;@ r1 = Old PC\n");\r
265 }\r
266#if EMULATE_ADDRESS_ERRORS_JUMP\r
267 // jsr prefetches next instruction before pushing old PC,\r
268 // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
269 ot(" mov r4,r0\n");\r
270 ot(" tst r4,#1 ;@ address error?\n");\r
271 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
272#else\r
273 ot(" bic r4,r0,#1\n");\r
274#endif\r
275\r
276 if (!(op&0x40))\r
277 {\r
278 ot(";@ Push old PC onto stack\n");\r
279 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
280 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
281 MemHandler(1,2);\r
282 }\r
283\r
284 Cycles=(op&0x40) ? 4 : 12;\r
285 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
286\r
287 OpEnd((op&0x40)?0:0x10);\r
288\r
289 return 0;\r
290}\r
291\r
292// --------------------- Opcodes 0x50c8+ ---------------------\r
293\r
294// ARM version of 68000 condition codes:\r
295static const char * const Cond[16]=\r
296{\r
297 "", "", "hi","ls","cc","cs","ne","eq",\r
298 "vc","vs","pl","mi","ge","lt","gt","le"\r
299};\r
300\r
301// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
302int OpDbra(int op)\r
303{\r
304 int use=0;\r
305 int cc=0;\r
306\r
307 use=op&~7; // Use same handler\r
308 cc=(op>>8)&15;\r
309 \r
310 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
311 OpStart(op);\r
312\r
313 switch (cc)\r
314 {\r
315 case 0: // T\r
316 case 1: // F\r
317 break;\r
318 case 2: // hi\r
319 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
320 ot(" beq DbraTrue\n\n");\r
321 break;\r
322 case 3: // ls\r
323 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
324 ot(" bne DbraTrue\n\n");\r
325 break;\r
326 default:\r
327 ot(";@ Is the condition true?\n");\r
328 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
329 ot(";@ If so, don't dbra\n");\r
330 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
331 break;\r
332 }\r
333\r
334 if (cc!=0)\r
335 {\r
336 ot(";@ Decrement Dn.w\n");\r
337 ot(" and r1,r8,#0x0007\n");\r
338 ot(" mov r1,r1,lsl #2\n");\r
339 ot(" ldrsh r0,[r7,r1]\n");\r
340 ot(" sub r0,r0,#1\n");\r
341 ot(" strh r0,[r7,r1]\n");\r
342 ot("\n");\r
343\r
344 ot(";@ Check if Dn.w is -1\n");\r
345 ot(" cmn r0,#1\n");\r
346\r
347#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
348 ot(" beq DbraMin1\n");\r
349 ot("\n");\r
350\r
351 ot(";@ Get Branch offset:\n");\r
352 ot(" ldrsh r0,[r4]\n");\r
353 ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r
354 CheckPc();\r
355#if EMULATE_ADDRESS_ERRORS_JUMP\r
356 ot(" mov r4,r0\n");\r
357 ot(" tst r4,#1 ;@ address error?\n");\r
358 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
359#else\r
360 ot(" bic r4,r0,#1\n");\r
361#endif\r
362#else\r
363 ot("\n");\r
364 ot(";@ Get Branch offset:\n");\r
365 ot(" ldrnesh r0,[r4]\n");\r
366 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
367 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
368 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
369 ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
370 ot("\n");\r
371#endif\r
372 Cycles=12-2;\r
373 OpEnd();\r
374 }\r
375 \r
376 //if (cc==0||cc>=2)\r
377 if (op==0x50c8)\r
378 {\r
379 ot(";@ condition true:\n");\r
380 ot("DbraTrue%s\n", ms?"":":");\r
381 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
382 ot("\n");\r
383 Cycles=12;\r
384 OpEnd();\r
385 }\r
386\r
387#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
388 if (op==0x51c8)\r
389 {\r
390 ot(";@ Dn.w is -1:\n");\r
391 ot("DbraMin1%s\n", ms?"":":");\r
392 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
393 ot("\n");\r
394 Cycles=12+2;\r
395 OpEnd();\r
396 }\r
397#endif\r
398\r
399 return 0;\r
400}\r
401\r
402// --------------------- Opcodes 0x6000+ ---------------------\r
403// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
404int OpBranch(int op)\r
405{\r
406 int size=0,use=0,checkpc=0;\r
407 int offset=0;\r
408 int cc=0;\r
409 const char *asr_r11="";\r
410\r
411 offset=(char)(op&0xff);\r
412 cc=(op>>8)&15;\r
413\r
414 // Special offsets:\r
415 if (offset==0) size=1;\r
416 if (offset==-1) size=2;\r
417\r
418 if (size==2) size=0; // 000 model does not support long displacement\r
419 if (size) use=op; // 16-bit or 32-bit\r
420 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
421\r
422 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
423 OpStart(op,size?0x10:0);\r
424 Cycles=10; // Assume branch taken\r
425\r
426 switch (cc)\r
427 {\r
428 case 0: // T\r
429 case 1: // F\r
430 break;\r
431 case 2: // hi\r
432 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
433 ot(" bne BccDontBranch%i\n\n",8<<size);\r
434 break;\r
435 case 3: // ls\r
436 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
437 ot(" beq BccDontBranch%i\n\n",8<<size);\r
438 break;\r
439 default:\r
440 ot(";@ Is the condition true?\n");\r
441 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
442 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
443 break;\r
444 }\r
445\r
446 if (size) \r
447 {\r
448 if (size<2)\r
449 {\r
450 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
451 }\r
452 else\r
453 {\r
454 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
455 ot(" ldrh r11,[r4,#2]\n");\r
456 ot(" orr r11,r11,r2,lsl #16\n");\r
457 }\r
458 }\r
459 else\r
460 {\r
461 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
462 asr_r11=",asr #24";\r
463 }\r
464\r
465 ot(";@ Branch taken - Add on r0 to PC\n");\r
466\r
467 if (cc==1)\r
468 {\r
469 ot(";@ Bsr - remember old PC\n");\r
470 ot(" ldr r12,[r7,#0x60] ;@ Get Memory base\n");\r
471 ot(" ldr r2,[r7,#0x3c]\n");\r
472 ot(" sub r1,r4,r12 ;@ r1 = Old PC\n");\r
473 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
474 ot("\n");\r
475 ot(";@ Push r1 onto stack\n");\r
476 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
477 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
478 MemHandler(1,2);\r
479 ot("\n");\r
480 Cycles=18; // always 18\r
481 }\r
482\r
483 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
484\r
485#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
486 if (offset!=0 && offset!=-1) checkpc=1;\r
487#endif\r
488#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
489 if (offset==0) checkpc=1;\r
490#endif\r
491#if USE_CHECKPC_CALLBACK\r
492 if (offset==-1) checkpc=1;\r
493#endif\r
494 if (checkpc) CheckPc();\r
495#if EMULATE_ADDRESS_ERRORS_JUMP\r
496 ot(" mov r4,r0\n");\r
497 ot(" tst r4,#1 ;@ address error?\n");\r
498 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
499#else\r
500 ot(" bic r4,r0,#1\n");\r
501#endif\r
502 ot("\n");\r
503\r
504 OpEnd(size?0x10:0);\r
505\r
506 // since all "DontBranch" code is same for every size, output only once\r
507 if (cc>=2&&(op&0xff00)==0x6700)\r
508 {\r
509 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
510 if (size) ot(" add r4,r4,#%d\n",1<<size);\r
511 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
512 OpEnd(0);\r
513 }\r
514\r
515 return 0;\r
516}\r
517\r
fast MegaDrive/MegaCD/32X emulator