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more accuracy fixes
[picodrive.git] / cpu / Cyclone / OpBranch.cpp
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1\r
2#include "app.h"\r
3\r
4static void CheckPc(int reg)\r
5{\r
6#if USE_CHECKPC_CALLBACK\r
7 ot(";@ Check Memory Base+pc (r4)\n");\r
8 if (reg != 0)\r
9 ot(" mov r0,r%i\n", reg);\r
10 ot(" mov lr,pc\n");\r
11 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
12 ot(" mov r4,r0\n");\r
13#else\r
14 ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
15#endif\r
16 ot("\n");\r
17}\r
18\r
19// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
20void OpPush32()\r
21{\r
22 ot(";@ Push r1 onto stack\n");\r
23 ot(" ldr r0,[r7,#0x3c]\n");\r
24 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
25 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
26 MemHandler(1,2);\r
27 ot("\n");\r
28}\r
29\r
30// Push SR - trashes r0-r3,r12,lr\r
31void OpPushSr(int high)\r
32{\r
33 ot(";@ Push SR:\n");\r
34 OpFlagsToReg(high);\r
35 ot(" ldr r0,[r7,#0x3c]\n");\r
36 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
37 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
38 MemHandler(1,1);\r
39 ot("\n");\r
40}\r
41\r
42// Pop SR - trashes r0-r3\r
43static void PopSr(int high)\r
44{\r
45 ot(";@ Pop SR:\n");\r
46 ot(" ldr r0,[r7,#0x3c]\n");\r
47 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
48 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
49 MemHandler(0,1);\r
50 ot("\n");\r
51 OpRegToFlags(high);\r
52}\r
53\r
54// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
55static void PopPc()\r
56{\r
57 ot(";@ Pop PC:\n");\r
58 ot(" ldr r0,[r7,#0x3c]\n");\r
59 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
60 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
61 MemHandler(0,2);\r
62 ot(" add r0,r0,r10 ;@ Memory Base+PC\n");\r
63 ot("\n");\r
64 CheckPc(0);\r
65}\r
66\r
67int OpTrap(int op)\r
68{\r
69 int use=0;\r
70\r
71 use=op&~0xf;\r
72 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
73\r
74 OpStart(op,0x10);\r
75 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
76 ot(" orr r0,r0,#0x20\n");\r
77 ot(" mov r0,r0,asl #2\n");\r
78 ot(" bl Exception\n");\r
79 ot("\n");\r
80\r
81 Cycles=38; OpEnd(0x10);\r
82\r
83 return 0;\r
84}\r
85\r
86// --------------------- Opcodes 0x4e50+ ---------------------\r
87int OpLink(int op)\r
88{\r
89 int use=0,reg;\r
90\r
91 use=op&~7;\r
92 reg=op&7;\r
93 if (reg==7) use=op;\r
94 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
95\r
96 OpStart(op,0x10);\r
97\r
98 if(reg!=7) {\r
99 ot(";@ Get An\n");\r
100 EaCalc(10, 7, 8, 2, 1);\r
101 EaRead(10, 1, 8, 2, 7, 1);\r
102 }\r
103\r
104 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
105 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
106 ot(" mov r11,r0\n");\r
107 if(reg==7) ot(" mov r1,r0\n");\r
108 ot("\n");\r
109 \r
110 ot(";@ Write An to Stack\n");\r
111 MemHandler(1,2);\r
112\r
113 ot(";@ Save to An\n");\r
114 if(reg!=7)\r
115 EaWrite(10,11, 8, 2, 7, 1);\r
116\r
117 ot(";@ Get offset:\n");\r
118 EaCalc(0,0,0x3c,1);\r
119 EaRead(0,0,0x3c,1,0);\r
120\r
121 ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r
122 ot(" str r11,[r7,#0x3c]\n");\r
123 ot("\n");\r
124\r
125 Cycles=16;\r
126 OpEnd(0x10);\r
127 return 0;\r
128}\r
129\r
130// --------------------- Opcodes 0x4e58+ ---------------------\r
131int OpUnlk(int op)\r
132{\r
133 int use=0;\r
134\r
135 use=op&~7;\r
136 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
137\r
138 OpStart(op,0x10);\r
139\r
140 ot(";@ Get An\n");\r
141 EaCalc(10, 0xf, 8, 2, 1);\r
142 EaRead(10, 0, 8, 2, 0xf, 1);\r
143\r
144 ot(" add r11,r0,#4 ;@ A7+=4\n");\r
145 ot("\n");\r
146 ot(";@ Pop An from stack:\n");\r
147 MemHandler(0,2);\r
148 ot("\n");\r
149 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r
150 ot("\n");\r
151 ot(";@ An = value from stack:\n");\r
152 EaWrite(10, 0, 8, 2, 7, 1);\r
153\r
154 Cycles=12;\r
155 OpEnd(0x10);\r
156 return 0;\r
157}\r
158\r
159// --------------------- Opcodes 0x4e70+ ---------------------\r
160// 01001110 01110ttt\r
161int Op4E70(int op)\r
162{\r
163 int type=0;\r
164\r
165 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
166\r
167 switch (type)\r
168 {\r
169 case 1: // nop\r
170 OpStart(op);\r
171 Cycles=4;\r
172 OpEnd();\r
173 return 0;\r
174\r
175 case 3: // rte\r
176 OpStart(op,0x10); Cycles=20;\r
177 SuperCheck(op);\r
178 PopSr(1);\r
179 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
180 PopPc();\r
181 SuperChange(op);\r
182 CheckInterrupt(op);\r
183 OpEnd(0x10);\r
184 return 0;\r
185\r
186 case 5: // rts\r
187 OpStart(op,0x10); Cycles=16;\r
188 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
189 PopPc();\r
190 OpEnd(0x10);\r
191 return 0;\r
192\r
193 case 6: // trapv\r
194 OpStart(op,0x10); Cycles=4;\r
195 ot(" tst r9,#0x10000000\n");\r
196 ot(" subne r5,r5,#%i\n",34);\r
197 ot(" movne r0,#0x1c ;@ TRAPV exception\n");\r
198 ot(" blne Exception\n");\r
199 OpEnd(0x10);\r
200 return 0;\r
201\r
202 case 7: // rtr\r
203 OpStart(op,0x10); Cycles=20;\r
204 PopSr(0);\r
205 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
206 PopPc();\r
207 OpEnd(0x10);\r
208 return 0;\r
209\r
210 default:\r
211 return 1;\r
212 }\r
213}\r
214\r
215// --------------------- Opcodes 0x4e80+ ---------------------\r
216// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
217int OpJsr(int op)\r
218{\r
219 int use=0;\r
220 int sea=0;\r
221\r
222 sea=op&0x003f;\r
223\r
224 // See if we can do this opcode:\r
225 if (EaCanRead(sea,-1)==0) return 1;\r
226\r
227 use=OpBase(op,0);\r
228 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
229\r
230 OpStart(op,(op&0x40)?0:0x10);\r
231\r
232 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
233 ot("\n");\r
234 EaCalc(11,0x003f,sea,0);\r
235\r
236 ot(";@ Jump - Get new PC from r0\n");\r
237 if (op&0x40)\r
238 {\r
239 // Jmp - Get new PC from r11\r
240 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
241 ot("\n");\r
242 }\r
243 else\r
244 {\r
245 ot(";@ Jsr - Push old PC first\n");\r
246 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
247 ot(" mov r1,r1,lsl #8\n");\r
248 ot(" ldr r0,[r7,#0x3c]\n");\r
249 ot(" mov r1,r1,asr #8\n");\r
250 ot(";@ Push r1 onto stack\n");\r
251 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
252 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
253 MemHandler(1,2);\r
254 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
255 ot("\n");\r
256 }\r
257\r
258 CheckPc(0);\r
259\r
260 Cycles=(op&0x40) ? 4 : 12;\r
261 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
262\r
263 OpEnd((op&0x40)?0:0x10);\r
264\r
265 return 0;\r
266}\r
267\r
268// --------------------- Opcodes 0x50c8+ ---------------------\r
269\r
270// ARM version of 68000 condition codes:\r
271static char *Cond[16]=\r
272{\r
273 "", "", "hi","ls","cc","cs","ne","eq",\r
274 "vc","vs","pl","mi","ge","lt","gt","le"\r
275};\r
276\r
277// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
278int OpDbra(int op)\r
279{\r
280 int use=0;\r
281 int cc=0;\r
282\r
283 use=op&~7; // Use same handler\r
284 cc=(op>>8)&15;\r
285 \r
286 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
287 OpStart(op);\r
288\r
289 switch (cc)\r
290 {\r
291 case 0: // T\r
292 case 1: // F\r
293 break;\r
294 case 2: // hi\r
295 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
296 ot(" beq DbraTrue\n\n");\r
297 break;\r
298 case 3: // ls\r
299 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
300 ot(" bne DbraTrue\n\n");\r
301 break;\r
302 default:\r
303 ot(";@ Is the condition true?\n");\r
304 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
305 ot(";@ If so, don't dbra\n");\r
306 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
307 break;\r
308 }\r
309\r
310 if (cc!=0)\r
311 {\r
312 ot(";@ Decrement Dn.w\n");\r
313 ot(" and r1,r8,#0x0007\n");\r
314 ot(" mov r1,r1,lsl #2\n");\r
315 ot(" ldrsh r0,[r7,r1]\n");\r
316 ot(" sub r0,r0,#1\n");\r
317 ot(" strh r0,[r7,r1]\n");\r
318 ot("\n");\r
319\r
320 ot(";@ Check if Dn.w is -1\n");\r
321 ot(" cmn r0,#1\n");\r
322\r
323#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
324 ot(" beq DbraMin1\n");\r
325 ot("\n");\r
326\r
327 ot(";@ Get Branch offset:\n");\r
328 ot(" ldrsh r0,[r4]\n");\r
329 ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
330 CheckPc(0);\r
331#else\r
332 ot("\n");\r
333 ot(";@ Get Branch offset:\n");\r
334 ot(" ldrnesh r0,[r4]\n");\r
335 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
336 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
337 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
338 ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
339 ot("\n");\r
340#endif\r
341 Cycles=12-2;\r
342 OpEnd();\r
343 }\r
344 \r
345 //if (cc==0||cc>=2)\r
346 if (op==0x50c8)\r
347 {\r
348 ot(";@ condition true:\n");\r
349 ot("DbraTrue%s\n", ms?"":":");\r
350 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
351 ot("\n");\r
352 Cycles=12;\r
353 OpEnd();\r
354 }\r
355\r
356#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
357 if (op==0x51c8)\r
358 {\r
359 ot(";@ Dn.w is -1:\n");\r
360 ot("DbraMin1%s\n", ms?"":":");\r
361 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
362 ot("\n");\r
363 Cycles=12+2;\r
364 OpEnd();\r
365 }\r
366#endif\r
367\r
368 return 0;\r
369}\r
370\r
371// --------------------- Opcodes 0x6000+ ---------------------\r
372// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
373int OpBranch(int op)\r
374{\r
375 int size=0,use=0,checkpc=0;\r
376 int offset=0;\r
377 int cc=0;\r
378 char *asr_r11="";\r
379\r
380 offset=(char)(op&0xff);\r
381 cc=(op>>8)&15;\r
382\r
383 // Special offsets:\r
384 if (offset==0) size=1;\r
385 if (offset==-1) size=2;\r
386\r
387 if (size==2) size=0; // 000 model does not support long displacement\r
388 if (size) use=op; // 16-bit or 32-bit\r
389 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
390\r
391 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
392 OpStart(op,size?0x10:0);\r
393 Cycles=10; // Assume branch taken\r
394\r
395 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
396\r
397 switch (cc)\r
398 {\r
399 case 0: // T\r
400 case 1: // F\r
401 break;\r
402 case 2: // hi\r
403 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
404 ot(" bne BccDontBranch%i\n\n",8<<size);\r
405 break;\r
406 case 3: // ls\r
407 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
408 ot(" beq BccDontBranch%i\n\n",8<<size);\r
409 break;\r
410 default:\r
411 ot(";@ Is the condition true?\n");\r
412 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
413 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
414 break;\r
415 }\r
416\r
417 if (size) \r
418 {\r
419 if (size<2)\r
420 {\r
421 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
422 }\r
423 else\r
424 {\r
425 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
426 ot(" ldrh r11,[r4,#2]\n");\r
427 ot(" orr r11,r11,r2,lsl #16\n");\r
428 }\r
429 }\r
430 else\r
431 {\r
432 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
433 asr_r11=",asr #24";\r
434 }\r
435\r
436 ot(";@ Branch taken - Add on r0 to PC\n");\r
437\r
438 if (cc==1)\r
439 {\r
440 ot(";@ Bsr - remember old PC\n");\r
441 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
442 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
443 ot(" mov r1,r1, lsl #8\n");\r
444 ot(" ldr r2,[r7,#0x3c]\n");\r
445 ot(" mov r1,r1, asr #8\n");\r
446 ot("\n");\r
447 ot(";@ Push r1 onto stack\n");\r
448 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
449 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
450 MemHandler(1,2);\r
451 ot("\n");\r
452 Cycles=18; // always 18\r
453 }\r
454\r
455 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
456\r
457#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
458 if (offset!=0 && offset!=-1) checkpc=1;\r
459#endif\r
460#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
461 if (offset==0) checkpc=1;\r
462#endif\r
463#if USE_CHECKPC_CALLBACK\r
464 if (offset==-1) checkpc=1;\r
465#endif\r
466 if (checkpc)\r
467 {\r
468 CheckPc(0);\r
469 }\r
470 else\r
471 {\r
472 ot(" bic r4,r0,#1\n"); // we do not emulate address errors\r
473 ot("\n");\r
474 }\r
475\r
476 OpEnd(size?0x10:0);\r
477\r
478 // since all "DontBranch" code is same for every size, output only once\r
479 if (cc>=2&&(op&0xff00)==0x6200)\r
480 {\r
481 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
482 if (size) ot(" add r4,r4,#%d\n",1<<size);\r
483 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
484 OpEnd(0);\r
485 }\r
486\r
487 return 0;\r
488}\r
489\r
fast MegaDrive/MegaCD/32X emulator