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Cyclone: group some often used handlers + minor optimization.
[picodrive.git] / cpu / Cyclone / OpBranch.cpp
... / ...
CommitLineData
1\r
2#include "app.h"\r
3\r
4// in/out address in r0, trashes all temp regs\r
5static void CheckPc(void)\r
6{\r
7#if USE_CHECKPC_CALLBACK\r
8 ot(";@ Check Memory Base+pc\n");\r
9 ot(" mov lr,pc\n");\r
10 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
11 ot("\n");\r
12#endif\r
13}\r
14\r
15// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
16void OpPush32()\r
17{\r
18 ot(";@ Push r1 onto stack\n");\r
19 ot(" ldr r0,[r7,#0x3c]\n");\r
20 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
21 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
22 MemHandler(1,2);\r
23 ot("\n");\r
24}\r
25\r
26// Push SR - trashes r0-r3,r12,lr\r
27void OpPushSr(int high)\r
28{\r
29 ot(";@ Push SR:\n");\r
30 OpFlagsToReg(high);\r
31 ot(" ldr r0,[r7,#0x3c]\n");\r
32 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
33 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
34 MemHandler(1,1);\r
35 ot("\n");\r
36}\r
37\r
38// Pop SR - trashes r0-r3\r
39static void PopSr(int high)\r
40{\r
41 ot(";@ Pop SR:\n");\r
42 ot(" ldr r0,[r7,#0x3c]\n");\r
43 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
44 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
45 MemHandler(0,1);\r
46 ot("\n");\r
47 OpRegToFlags(high);\r
48}\r
49\r
50// Pop PC - trashes r0-r3\r
51static void PopPc()\r
52{\r
53 ot(";@ Pop PC:\n");\r
54 ot(" ldr r0,[r7,#0x3c]\n");\r
55 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
56 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
57 MemHandler(0,2);\r
58 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
59 ot(" add r0,r0,r1 ;@ Memory Base+PC\n");\r
60 ot("\n");\r
61 CheckPc();\r
62#if EMULATE_ADDRESS_ERRORS_JUMP\r
63 ot(" mov r4,r0\n");\r
64#else\r
65 ot(" bic r4,r0,#1\n");\r
66#endif\r
67}\r
68\r
69int OpTrap(int op)\r
70{\r
71 int use=0;\r
72\r
73 use=op&~0xf;\r
74 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
75\r
76 OpStart(op,0x10);\r
77 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
78 ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r
79 ot(" bl Exception\n");\r
80 ot("\n");\r
81\r
82 Cycles=38; OpEnd(0x10);\r
83\r
84 return 0;\r
85}\r
86\r
87// --------------------- Opcodes 0x4e50+ ---------------------\r
88int OpLink(int op)\r
89{\r
90 int use=0,reg;\r
91\r
92 use=op&~7;\r
93 reg=op&7;\r
94 if (reg==7) use=op;\r
95 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
96\r
97 OpStart(op,0x10);\r
98\r
99 if(reg!=7) {\r
100 ot(";@ Get An\n");\r
101 EaCalc(11, 7, 8, 2, 1);\r
102 EaRead(11, 1, 8, 2, 7, 1);\r
103 }\r
104\r
105 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
106 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
107 ot(" mov r8,r0 ;@ abuse r8\n");\r
108 if(reg==7) ot(" mov r1,r0\n");\r
109 ot("\n");\r
110 \r
111 ot(";@ Write An to Stack\n");\r
112 MemHandler(1,2);\r
113\r
114 ot(";@ Save to An\n");\r
115 if(reg!=7)\r
116 EaWrite(11,8, 8, 2, 7, 1);\r
117\r
118 ot(";@ Get offset:\n");\r
119 EaCalc(0,0,0x3c,1); // abused r8 is ok because of imm EA\r
120 EaRead(0,0,0x3c,1,0);\r
121\r
122 ot(" add r8,r8,r0 ;@ Add offset to A7\n");\r
123 ot(" str r8,[r7,#0x3c]\n");\r
124 ot("\n");\r
125\r
126 Cycles=16;\r
127 OpEnd(0x10);\r
128 return 0;\r
129}\r
130\r
131// --------------------- Opcodes 0x4e58+ ---------------------\r
132int OpUnlk(int op)\r
133{\r
134 int use=0;\r
135\r
136 use=op&~7;\r
137 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
138\r
139 OpStart(op,0x10);\r
140\r
141 ot(";@ Get An\n");\r
142 EaCalc(11, 0xf, 8, 2, 1);\r
143 EaRead(11, 0, 8, 2, 0xf, 1);\r
144\r
145 ot(" add r8,r0,#4 ;@ A7+=4, abuse r8\n");\r
146 ot("\n");\r
147 ot(";@ Pop An from stack:\n");\r
148 MemHandler(0,2);\r
149 ot("\n");\r
150 ot(" str r8,[r7,#0x3c] ;@ Save A7\n");\r
151 ot("\n");\r
152 ot(";@ An = value from stack:\n");\r
153 EaWrite(11, 0, 8, 2, 7, 1);\r
154\r
155 Cycles=12;\r
156 OpEnd(0x10);\r
157 return 0;\r
158}\r
159\r
160// --------------------- Opcodes 0x4e70+ ---------------------\r
161// 01001110 01110ttt\r
162int Op4E70(int op)\r
163{\r
164 int type=0;\r
165\r
166 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
167\r
168 switch (type)\r
169 {\r
170 case 1: // nop\r
171 OpStart(op);\r
172 Cycles=4;\r
173 OpEnd();\r
174 return 0;\r
175\r
176 case 3: // rte\r
177 OpStart(op,0x10,0,0,1); Cycles=20;\r
178 PopSr(1);\r
179 PopPc();\r
180 ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
181 SuperChange(op,1);\r
182#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
183 ot(" ldr r1,[r7,#0x58]\n");\r
184 ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
185 ot(" str r1,[r7,#0x58]\n");\r
186#endif\r
187#if EMULATE_ADDRESS_ERRORS_JUMP\r
188 ot(" tst r4,#1 ;@ address error?\n");\r
189 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
190#endif\r
191 opend_check_interrupt = 1;\r
192 opend_check_trace = 1;\r
193 OpEnd(0x10,0);\r
194 return 0;\r
195\r
196 case 5: // rts\r
197 OpStart(op,0x10); Cycles=16;\r
198 PopPc();\r
199#if EMULATE_ADDRESS_ERRORS_JUMP\r
200 ot(" tst r4,#1 ;@ address error?\n");\r
201 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
202#endif\r
203 OpEnd(0x10);\r
204 return 0;\r
205\r
206 case 6: // trapv\r
207 OpStart(op,0x10,0,1); Cycles=4;\r
208 ot(" tst r10,#0x10000000\n");\r
209 ot(" subne r5,r5,#%i\n",34);\r
210 ot(" movne r0,#7 ;@ TRAPV exception\n");\r
211 ot(" blne Exception\n");\r
212 opend_op_changes_cycles = 1;\r
213 OpEnd(0x10,0);\r
214 return 0;\r
215\r
216 case 7: // rtr\r
217 OpStart(op,0x10); Cycles=20;\r
218 PopSr(0);\r
219 PopPc();\r
220#if EMULATE_ADDRESS_ERRORS_JUMP\r
221 ot(" tst r4,#1 ;@ address error?\n");\r
222 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
223#endif\r
224 OpEnd(0x10);\r
225 return 0;\r
226\r
227 default:\r
228 return 1;\r
229 }\r
230}\r
231\r
232// --------------------- Opcodes 0x4e80+ ---------------------\r
233// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
234int OpJsr(int op)\r
235{\r
236 int use=0;\r
237 int sea=0;\r
238\r
239 sea=op&0x003f;\r
240\r
241 // See if we can do this opcode:\r
242 if (EaCanRead(sea,-1)==0) return 1;\r
243\r
244 use=OpBase(op,0);\r
245 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
246\r
247 OpStart(op,(op&0x40)?0:0x10);\r
248\r
249 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
250 ot("\n");\r
251 EaCalc(12,0x003f,sea,0);\r
252\r
253 ot(";@ Jump - Get new PC from r12\n");\r
254 ot(" add r0,r12,r11 ;@ Memory Base + New PC\n");\r
255 ot("\n");\r
256 CheckPc();\r
257 if (!(op&0x40))\r
258 {\r
259 ot(" ldr r2,[r7,#0x3c]\n");\r
260 ot(" sub r1,r4,r11 ;@ r1 = Old PC\n");\r
261 }\r
262#if EMULATE_ADDRESS_ERRORS_JUMP\r
263 // jsr prefetches next instruction before pushing old PC,\r
264 // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
265 ot(" mov r4,r0\n");\r
266 ot(" tst r4,#1 ;@ address error?\n");\r
267 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
268#else\r
269 ot(" bic r4,r0,#1\n");\r
270#endif\r
271\r
272 if (!(op&0x40))\r
273 {\r
274 ot(";@ Push old PC onto stack\n");\r
275 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
276 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
277 MemHandler(1,2);\r
278 }\r
279\r
280 Cycles=(op&0x40) ? 4 : 12;\r
281 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
282\r
283 OpEnd((op&0x40)?0:0x10);\r
284\r
285 return 0;\r
286}\r
287\r
288// --------------------- Opcodes 0x50c8+ ---------------------\r
289\r
290// ARM version of 68000 condition codes:\r
291static const char * const Cond[16]=\r
292{\r
293 "", "", "hi","ls","cc","cs","ne","eq",\r
294 "vc","vs","pl","mi","ge","lt","gt","le"\r
295};\r
296\r
297// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
298int OpDbra(int op)\r
299{\r
300 int use=0;\r
301 int cc=0;\r
302\r
303 use=op&~7; // Use same handler\r
304 cc=(op>>8)&15;\r
305 \r
306 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
307 OpStart(op);\r
308\r
309 switch (cc)\r
310 {\r
311 case 0: // T\r
312 case 1: // F\r
313 break;\r
314 case 2: // hi\r
315 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
316 ot(" beq DbraTrue\n\n");\r
317 break;\r
318 case 3: // ls\r
319 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
320 ot(" bne DbraTrue\n\n");\r
321 break;\r
322 default:\r
323 ot(";@ Is the condition true?\n");\r
324 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
325 ot(";@ If so, don't dbra\n");\r
326 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
327 break;\r
328 }\r
329\r
330 if (cc!=0)\r
331 {\r
332 ot(";@ Decrement Dn.w\n");\r
333 ot(" and r1,r8,#0x0007\n");\r
334 ot(" mov r1,r1,lsl #2\n");\r
335 ot(" ldrsh r0,[r7,r1]\n");\r
336 ot(" sub r0,r0,#1\n");\r
337 ot(" strh r0,[r7,r1]\n");\r
338 ot("\n");\r
339\r
340 ot(";@ Check if Dn.w is -1\n");\r
341 ot(" cmn r0,#1\n");\r
342\r
343#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
344 ot(" beq DbraMin1\n");\r
345 ot("\n");\r
346\r
347 ot(";@ Get Branch offset:\n");\r
348 ot(" ldrsh r0,[r4]\n");\r
349 ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r
350 CheckPc();\r
351#if EMULATE_ADDRESS_ERRORS_JUMP\r
352 ot(" mov r4,r0\n");\r
353 ot(" tst r4,#1 ;@ address error?\n");\r
354 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
355#else\r
356 ot(" bic r4,r0,#1\n");\r
357#endif\r
358#else\r
359 ot("\n");\r
360 ot(";@ Get Branch offset:\n");\r
361 ot(" ldrnesh r0,[r4]\n");\r
362 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
363 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
364 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
365 ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
366 ot("\n");\r
367#endif\r
368 Cycles=12-2;\r
369 OpEnd();\r
370 }\r
371 \r
372 //if (cc==0||cc>=2)\r
373 if (op==0x50c8)\r
374 {\r
375 ot(";@ condition true:\n");\r
376 ot("DbraTrue%s\n", ms?"":":");\r
377 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
378 ot("\n");\r
379 Cycles=12;\r
380 OpEnd();\r
381 }\r
382\r
383#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
384 if (op==0x51c8)\r
385 {\r
386 ot(";@ Dn.w is -1:\n");\r
387 ot("DbraMin1%s\n", ms?"":":");\r
388 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
389 ot("\n");\r
390 Cycles=12+2;\r
391 OpEnd();\r
392 }\r
393#endif\r
394\r
395 return 0;\r
396}\r
397\r
398// --------------------- Opcodes 0x6000+ ---------------------\r
399// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
400int OpBranch(int op)\r
401{\r
402 int size=0,use=0,checkpc=0;\r
403 int offset=0;\r
404 int cc=0;\r
405 const char *asr_r11="";\r
406\r
407 offset=(char)(op&0xff);\r
408 cc=(op>>8)&15;\r
409\r
410 // Special offsets:\r
411 if (offset==0) size=1;\r
412 if (offset==-1) size=2;\r
413\r
414 if (size==2) size=0; // 000 model does not support long displacement\r
415 if (size) use=op; // 16-bit or 32-bit\r
416 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
417\r
418 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
419 OpStart(op,size?0x10:0);\r
420 Cycles=10; // Assume branch taken\r
421\r
422 switch (cc)\r
423 {\r
424 case 0: // T\r
425 case 1: // F\r
426 break;\r
427 case 2: // hi\r
428 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
429 ot(" bne BccDontBranch%i\n\n",8<<size);\r
430 break;\r
431 case 3: // ls\r
432 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
433 ot(" beq BccDontBranch%i\n\n",8<<size);\r
434 break;\r
435 default:\r
436 ot(";@ Is the condition true?\n");\r
437 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
438 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
439 break;\r
440 }\r
441\r
442 if (size) \r
443 {\r
444 if (size<2)\r
445 {\r
446 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
447 }\r
448 else\r
449 {\r
450 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
451 ot(" ldrh r11,[r4,#2]\n");\r
452 ot(" orr r11,r11,r2,lsl #16\n");\r
453 }\r
454 }\r
455 else\r
456 {\r
457 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
458 asr_r11=",asr #24";\r
459 }\r
460\r
461 ot(";@ Branch taken - Add on r0 to PC\n");\r
462\r
463 if (cc==1)\r
464 {\r
465 ot(";@ Bsr - remember old PC\n");\r
466 ot(" ldr r12,[r7,#0x60] ;@ Get Memory base\n");\r
467 ot(" ldr r2,[r7,#0x3c]\n");\r
468 ot(" sub r1,r4,r12 ;@ r1 = Old PC\n");\r
469 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
470 ot("\n");\r
471 ot(";@ Push r1 onto stack\n");\r
472 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
473 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
474 MemHandler(1,2);\r
475 ot("\n");\r
476 Cycles=18; // always 18\r
477 }\r
478\r
479 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
480\r
481#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
482 if (offset!=0 && offset!=-1) checkpc=1;\r
483#endif\r
484#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
485 if (offset==0) checkpc=1;\r
486#endif\r
487#if USE_CHECKPC_CALLBACK\r
488 if (offset==-1) checkpc=1;\r
489#endif\r
490 if (checkpc) CheckPc();\r
491#if EMULATE_ADDRESS_ERRORS_JUMP\r
492 ot(" mov r4,r0\n");\r
493 ot(" tst r4,#1 ;@ address error?\n");\r
494 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
495#else\r
496 ot(" bic r4,r0,#1\n");\r
497#endif\r
498 ot("\n");\r
499\r
500 OpEnd(size?0x10:0);\r
501\r
502 // since all "DontBranch" code is same for every size, output only once\r
503 if (cc>=2&&(op&0xff00)==0x6700)\r
504 {\r
505 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
506 if (size) ot(" add r4,r4,#%d\n",1<<size);\r
507 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
508 OpEnd(0);\r
509 }\r
510\r
511 return 0;\r
512}\r
513\r
fast MegaDrive/MegaCD/32X emulator