32x: drc: more wip, some games work, debug stats
[picodrive.git] / cpu / Cyclone / config.h
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1\r
2\r
3/**\r
4 * Cyclone 68000 configuration file\r
5**/\r
6\r
7\r
8/*\r
9 * If this option is enabled, Microsoft ARMASM compatible output is generated\r
10 * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
11 */\r
12#define USE_MS_SYNTAX 0\r
13\r
14/*\r
15 * Enable this option if you are going to use Cyclone to emulate Genesis /\r
16 * Mega Drive system. As VDP chip in these systems had control of the bus,\r
17 * several instructions were acting differently, for example TAS did'n have\r
18 * the write-back phase. That will be emulated, if this option is enabled.\r
19 */\r
20#define CYCLONE_FOR_GENESIS 0\r
21\r
22/*\r
23 * This option compresses Cyclone's jumptable. Because of this the executable\r
24 * will be smaller and load slightly faster and less relocations will be needed.\r
25 * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
26 * Warning: if you enable this, you MUST call CycloneInit() before calling\r
27 * CycloneRun(), or else it will crash.\r
28 */\r
29#define COMPRESS_JUMPTABLE 1\r
30\r
31/*\r
32 * Address mask for memory hadlers. The bits set will be masked out of address\r
33 * parameter, which is passed to r/w memory handlers.\r
34 * Using 0xff000000 means that only 24 least significant bits should be used.\r
35 * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
36 */\r
37#define MEMHANDLERS_ADDR_MASK 0\r
38\r
39/*\r
40 * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
41 * counter in ARM registers instead of the context for performance reasons. If you for\r
42 * any reason need to access them in your memory handlers, enable the options below,\r
43 * otherwise disable them to improve performance.\r
44 *\r
45 * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
46 * when memhandler was called (opcode address + 2-10 bytes).\r
47 * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
48 * opcode address + 2.\r
49 * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
50 * subtract .membase to get M68k PC value.\r
51 *\r
52 * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
53 * increment the PC before fetching the next instruction and continue executing\r
54 * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
55 *\r
56 * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
57 * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
58 * count and this will screw timing (if not cause a deadlock).\r
59 */\r
60#define MEMHANDLERS_NEED_PC 0\r
61#define MEMHANDLERS_NEED_PREV_PC 0\r
62#define MEMHANDLERS_NEED_FLAGS 0\r
63#define MEMHANDLERS_NEED_CYCLES 0\r
64#define MEMHANDLERS_CHANGE_PC 0\r
65#define MEMHANDLERS_CHANGE_FLAGS 0\r
66#define MEMHANDLERS_CHANGE_CYCLES 0\r
67\r
68/*\r
69 * If the following macro is defined, Cyclone no longer calls read*, write*,\r
70 * fetch* and checkpc from it's context, it calls these functions directly\r
71 * instead, prefixed with prefix selected below. For example, if\r
72 * MEMHANDLERS_DIRECT_PREFIX is set to cyclone_, it will call cyclone_read8\r
73 * on byte reads.\r
74 * This is to avoid indirect jumps, which are slower. It also saves one ARM\r
75 * instruction.\r
76 */\r
77/* MEMHANDLERS_DIRECT_PREFIX "cyclone_" */\r
78\r
79/*\r
80 * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
81 * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
82 * handler if needed.\r
83 * This function must either return vector number to use for interrupt exception,\r
84 * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
85 * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
86 * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
87 * continues execution.\r
88 */\r
89#define USE_INT_ACK_CALLBACK 0\r
90\r
91/*\r
92 * Enable this if you need old PC, flags or cycles;\r
93 * or you change cycles in your IrqCallback function.\r
94 */\r
95#define INT_ACK_NEEDS_STUFF 0\r
96#define INT_ACK_CHANGES_CYCLES 0\r
97\r
98/*\r
99 * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
100 * encountered. All context members are valid and can be changed.\r
101 * If disabled, RESET opcode acts as an NOP.\r
102 */\r
103#define USE_RESET_CALLBACK 0\r
104\r
105/*\r
106 * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
107 * encountered. All context members are valid and can be changed. The handler\r
108 * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
109 * exception after this, or nonzero if not. In the later case you should change\r
110 * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
111 * again.\r
112 * If disabled, "Illegal Instruction" exception is generated and execution is\r
113 * continued.\r
114 */\r
115#define USE_UNRECOGNIZED_CALLBACK 0\r
116\r
117/*\r
118 * This option will also call UnrecognizedCallback for a-line and f-line\r
119 * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
120 * exceptions will be generated.\r
121 */\r
122#define USE_AFLINE_CALLBACK 0\r
123\r
124/*\r
125 * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
126 * by a large value. It takes and should return the PC value in PC+membase form.\r
127 * The flags and cycle counter are not valid in this function.\r
128 */\r
129#define USE_CHECKPC_CALLBACK 1\r
130\r
131/*\r
132 * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
133 * displacement values were used.\r
134 */\r
135#define USE_CHECKPC_OFFSETBITS_16 1\r
136#define USE_CHECKPC_OFFSETBITS_8 0\r
137\r
138/*\r
139 * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
140 * 0.0087 never did that.\r
141 */\r
142#define USE_CHECKPC_DBRA 0\r
143\r
144/*\r
145 * When this option is enabled Cyclone will do two word writes instead of one\r
146 * long write when handling MOVE.L or MOVEM.L with pre-decrementing destination,\r
147 * as described in Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
148 * Enable this if you are emulating a 16 bit system.\r
149 */\r
150#define SPLIT_MOVEL_PD 1\r
151\r
152/*\r
153 * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
154 * should be safe to keep this ON.\r
155 */\r
156#define EMULATE_TRACE 1\r
157\r
158/*\r
159 * If enabled, address error exception will be generated if 68k code jumps to an\r
160 * odd address. Causes very small performance hit (2 ARM instructions for every\r
161 * emulated jump/return/exception in normal case).\r
162 * Note: checkpc() must not clear least significant bit of rebased address\r
163 * for this to work, as checks are performed after calling checkpc().\r
164 */\r
165#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
166\r
167/*\r
168 * If enabled, address error exception will be generated if 68k code tries to\r
169 * access a word or longword at an odd address. The performance cost is also 2 ARM\r
170 * instructions per access (for address error checks).\r
171 */\r
172#define EMULATE_ADDRESS_ERRORS_IO 0\r
173\r
174/*\r
175 * If an address error happens during another address error processing,\r
176 * the processor halts until it is reset (catastrophic system failure, as the manual\r
177 * states). This option enables halt emulation.\r
178 * Note that this might be not desired if it is known that emulated system should\r
179 * never reach this state.\r
180 */\r
181#define EMULATE_HALT 0\r
182\r