notaz.gp2x.de / picodrive.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
new memory handling, but asm and mappers need update.
[picodrive.git] / cpu / DrZ80 / drz80.s
... / ...
CommitLineData
1;@ Reesy's Z80 Emulator Version 0.001\r
2\r
3;@ (c) Copyright 2004 Reesy, All rights reserved\r
4;@ DrZ80 is free for non-commercial use.\r
5\r
6;@ For commercial use, separate licencing terms must be obtained.\r
7\r
8 .data\r
9 .align 4\r
10\r
11 .global DrZ80Run\r
12 .global DrZ80Ver\r
13\r
14 .equiv INTERRUPT_MODE, 0 ;@0 = Use internal int handler, 1 = Use Mames int handler\r
15 .equiv FAST_Z80SP, 1 ;@0 = Use mem functions for stack pointer, 1 = Use direct mem pointer\r
16 .equiv UPDATE_CONTEXT, 0\r
17 .equiv DRZ80_XMAP, 1\r
18 .equiv DRZ80_XMAP_MORE_INLINE, 1\r
19\r
20.if DRZ80_XMAP\r
21 .equ Z80_MEM_SHIFT, 13\r
22 ;@ note: stack is locked in single bank that z80sp_base points to\r
23.endif\r
24\r
25.if INTERRUPT_MODE\r
26 .extern Interrupt\r
27.endif\r
28\r
29DrZ80Ver: .long 0x0001\r
30\r
31;@ --------------------------- Defines ----------------------------\r
32;@ Make sure that regs/pointers for z80pc to z80sp match up!\r
33\r
34 z80_icount .req r3\r
35 opcodes .req r4\r
36 cpucontext .req r5\r
37 z80pc .req r6\r
38 z80a .req r7\r
39 z80f .req r8\r
40 z80bc .req r9\r
41 z80de .req r10\r
42 z80hl .req r11\r
43 z80sp .req r12 \r
44 z80xx .req lr\r
45\r
46 .equ z80pc_pointer, 0 ;@ 0\r
47 .equ z80a_pointer, z80pc_pointer+4 ;@ 4\r
48 .equ z80f_pointer, z80a_pointer+4 ;@ 8\r
49 .equ z80bc_pointer, z80f_pointer+4 ;@ \r
50 .equ z80de_pointer, z80bc_pointer+4\r
51 .equ z80hl_pointer, z80de_pointer+4\r
52 .equ z80sp_pointer, z80hl_pointer+4\r
53 .equ z80pc_base, z80sp_pointer+4\r
54 .equ z80sp_base, z80pc_base+4\r
55 .equ z80ix, z80sp_base+4\r
56 .equ z80iy, z80ix+4\r
57 .equ z80i, z80iy+4\r
58 .equ z80a2, z80i+4\r
59 .equ z80f2, z80a2+4\r
60 .equ z80bc2, z80f2+4\r
61 .equ z80de2, z80bc2+4\r
62 .equ z80hl2, z80de2+4\r
63 .equ cycles_pointer, z80hl2+4 \r
64 .equ previouspc, cycles_pointer+4 \r
65 .equ z80irq, previouspc+4\r
66 .equ z80if, z80irq+1\r
67 .equ z80im, z80if+1\r
68 .equ z80r, z80im+1\r
69 .equ z80irqvector, z80r+1\r
70 .equ z80irqcallback, z80irqvector+4\r
71 .equ z80_write8, z80irqcallback+4\r
72 .equ z80_write16, z80_write8+4\r
73 .equ z80_in, z80_write16+4\r
74 .equ z80_out, z80_in+4\r
75 .equ z80_read8, z80_out+4\r
76 .equ z80_read16, z80_read8+4\r
77 .equ z80_rebaseSP, z80_read16+4\r
78 .equ z80_rebasePC, z80_rebaseSP+4\r
79\r
80 .equ VFlag, 0\r
81 .equ CFlag, 1\r
82 .equ ZFlag, 2\r
83 .equ SFlag, 3\r
84 .equ HFlag, 4\r
85 .equ NFlag, 5\r
86 .equ Flag3, 6\r
87 .equ Flag5, 7\r
88\r
89 .equ Z80_CFlag, 0\r
90 .equ Z80_NFlag, 1\r
91 .equ Z80_VFlag, 2\r
92 .equ Z80_Flag3, 3\r
93 .equ Z80_HFlag, 4\r
94 .equ Z80_Flag5, 5\r
95 .equ Z80_ZFlag, 6\r
96 .equ Z80_SFlag, 7\r
97\r
98 .equ Z80_IF1, 1<<0\r
99 .equ Z80_IF2, 1<<1\r
100 .equ Z80_HALT, 1<<2\r
101\r
102;@---------------------------------------\r
103\r
104.text\r
105\r
106.if DRZ80_XMAP\r
107\r
108z80_xmap_read8: @ addr\r
109 ldr r1,[cpucontext,#z80_read8]\r
110 mov r2,r0,lsr #Z80_MEM_SHIFT\r
111 ldr r1,[r1,r2,lsl #2]\r
112 movs r1,r1,lsl #1\r
113 ldrccb r0,[r1,r0]\r
114 bxcc lr\r
115\r
116z80_xmap_read8_handler: @ addr, func\r
117 str z80_icount,[cpucontext,#cycles_pointer]\r
118 stmfd sp!,{r12,lr}\r
119 mov lr,pc\r
120 bx r1\r
121 ldr z80_icount,[cpucontext,#cycles_pointer]\r
122 ldmfd sp!,{r12,pc}\r
123\r
124z80_xmap_write8: @ data, addr\r
125 ldr r2,[cpucontext,#z80_write8]\r
126 add r2,r2,r1,lsr #Z80_MEM_SHIFT-2\r
127 bic r2,r2,#3\r
128 ldr r2,[r2]\r
129 movs r2,r2,lsl #1\r
130 strccb r0,[r2,r1]\r
131 bxcc lr\r
132\r
133z80_xmap_write8_handler: @ data, addr, func\r
134 str z80_icount,[cpucontext,#cycles_pointer]\r
135 mov r3,r0\r
136 mov r0,r1\r
137 mov r1,r3\r
138 stmfd sp!,{r12,lr}\r
139 mov lr,pc\r
140 bx r2\r
141 ldr z80_icount,[cpucontext,#cycles_pointer]\r
142 ldmfd sp!,{r12,pc}\r
143\r
144z80_xmap_read16: @ addr\r
145 @ check if we cross bank boundary\r
146 add r1,r0,#1\r
147 eor r1,r1,r0\r
148 tst r1,#1<<Z80_MEM_SHIFT\r
149 bne 0f\r
150\r
151 ldr r1,[cpucontext,#z80_read8]\r
152 mov r2,r0,lsr #Z80_MEM_SHIFT\r
153 ldr r1,[r1,r2,lsl #2]\r
154 movs r1,r1,lsl #1\r
155 bcs 0f\r
156 ldrb r0,[r1,r0]!\r
157 ldrb r1,[r1,#1]\r
158 orr r0,r0,r1,lsl #8\r
159 bx lr\r
160\r
1610:\r
162 @ z80_xmap_read8 will save r3 and r12 for us\r
163 stmfd sp!,{r8,r9,lr}\r
164 mov r8,r0\r
165 bl z80_xmap_read8\r
166 mov r9,r0\r
167 add r0,r8,#1\r
168 bl z80_xmap_read8\r
169 orr r0,r9,r0,lsl #8\r
170 ldmfd sp!,{r8,r9,pc}\r
171\r
172z80_xmap_write16: @ data, addr\r
173 add r2,r1,#1\r
174 eor r2,r2,r1\r
175 tst r2,#1<<Z80_MEM_SHIFT\r
176 bne 0f\r
177\r
178 ldr r2,[cpucontext,#z80_write8]\r
179 add r2,r2,r1,lsr #Z80_MEM_SHIFT-2\r
180 bic r2,r2,#3\r
181 ldr r2,[r2]\r
182 movs r2,r2,lsl #1\r
183 bcs 0f\r
184 strb r0,[r2,r1]!\r
185 mov r0,r0,lsr #8\r
186 strb r0,[r2,#1]\r
187 bx lr\r
188\r
1890:\r
190 stmfd sp!,{r8,r9,lr}\r
191 mov r8,r0\r
192 mov r9,r1\r
193 bl z80_xmap_write8\r
194 mov r0,r8,lsr #8\r
195 add r1,r9,#1\r
196 bl z80_xmap_write8\r
197 ldmfd sp!,{r8,r9,pc}\r
198\r
199z80_xmap_rebase_pc:\r
200 ldr r1,[cpucontext,#z80_read8]\r
201 mov r2,r0,lsr #Z80_MEM_SHIFT\r
202 ldr r1,[r1,r2,lsl #2]\r
203 movs r1,r1,lsl #1\r
204 strcc r1,[cpucontext,#z80pc_base]\r
205 addcc z80pc,r1,r0\r
206 bxcc lr\r
207\r
208z80_bad_jump:\r
209 ldr r0,[cpucontext,#z80_read8]\r
210 ldr r0,[r0]\r
211 str r0,[cpucontext,#z80pc_base]\r
212 mov z80pc,r0\r
213 bx lr\r
214.endif\r
215\r
216\r
217.macro fetch cycs\r
218 subs z80_icount,z80_icount,#\cycs\r
219.if UPDATE_CONTEXT\r
220 str z80pc,[cpucontext,#z80pc_pointer]\r
221 str z80_icount,[cpucontext,#cycles_pointer]\r
222 ldr r1,[cpucontext,#z80pc_base]\r
223 sub r2,z80pc,r1\r
224 str r2,[cpucontext,#previouspc]\r
225.endif\r
226 ldrplb r0,[z80pc],#1\r
227 ldrpl pc,[opcodes,r0, lsl #2]\r
228 bmi z80_execute_end\r
229.endm\r
230\r
231.macro eatcycles cycs\r
232 sub z80_icount,z80_icount,#\cycs\r
233.if UPDATE_CONTEXT\r
234 str z80_icount,[cpucontext,#cycles_pointer]\r
235.endif\r
236.endm\r
237\r
238.macro readmem8\r
239.if UPDATE_CONTEXT\r
240 str z80pc,[cpucontext,#z80pc_pointer]\r
241.endif\r
242.if DRZ80_XMAP\r
243.if !DRZ80_XMAP_MORE_INLINE\r
244 ldr r1,[cpucontext,#z80_read8]\r
245 mov r2,r0,lsr #Z80_MEM_SHIFT\r
246 ldr r1,[r1,r2,lsl #2]\r
247 movs r1,r1,lsl #1\r
248 ldrccb r0,[r1,r0]\r
249 blcs z80_xmap_read8_handler\r
250.else\r
251 bl z80_xmap_read8\r
252.endif\r
253.else ;@ if !DRZ80_XMAP\r
254 stmfd sp!,{r3,r12}\r
255 mov lr,pc\r
256 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
257 ldmfd sp!,{r3,r12}\r
258.endif\r
259.endm\r
260\r
261.macro readmem8HL\r
262 mov r0,z80hl, lsr #16\r
263 readmem8\r
264.endm\r
265\r
266.macro readmem16\r
267.if UPDATE_CONTEXT\r
268 str z80pc,[cpucontext,#z80pc_pointer]\r
269.endif\r
270.if DRZ80_XMAP\r
271 bl z80_xmap_read16\r
272.else\r
273 stmfd sp!,{r3,r12}\r
274 mov lr,pc\r
275 ldr pc,[cpucontext,#z80_read16]\r
276 ldmfd sp!,{r3,r12}\r
277.endif\r
278.endm\r
279\r
280.macro writemem8\r
281.if UPDATE_CONTEXT\r
282 str z80pc,[cpucontext,#z80pc_pointer]\r
283.endif\r
284.if DRZ80_XMAP\r
285.if DRZ80_XMAP_MORE_INLINE\r
286 ldr r2,[cpucontext,#z80_write8]\r
287 mov lr,r1,lsr #Z80_MEM_SHIFT\r
288 ldr r2,[r2,lr,lsl #2]\r
289 movs r2,r2,lsl #1\r
290 strccb r0,[r2,r1]\r
291 blcs z80_xmap_write8_handler\r
292.else\r
293 bl z80_xmap_write8\r
294.endif\r
295.else ;@ if !DRZ80_XMAP\r
296 stmfd sp!,{r3,r12}\r
297 mov lr,pc\r
298 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
299 ldmfd sp!,{r3,r12}\r
300.endif\r
301.endm\r
302\r
303.macro writemem8DE\r
304 mov r1,z80de, lsr #16\r
305 writemem8\r
306.endm\r
307\r
308.macro writemem8HL\r
309 mov r1,z80hl, lsr #16\r
310 writemem8\r
311.endm\r
312\r
313.macro writemem16\r
314.if UPDATE_CONTEXT\r
315 str z80pc,[cpucontext,#z80pc_pointer]\r
316.endif\r
317.if DRZ80_XMAP\r
318 bl z80_xmap_write16\r
319.else\r
320 stmfd sp!,{r3,r12}\r
321 mov lr,pc\r
322 ldr pc,[cpucontext,#z80_write16] ;@ r0=data r1=addr\r
323 ldmfd sp!,{r3,r12}\r
324.endif\r
325.endm\r
326\r
327.macro copymem8HL_DE\r
328.if UPDATE_CONTEXT\r
329 str z80pc,[cpucontext,#z80pc_pointer]\r
330.endif\r
331 mov r0,z80hl, lsr #16\r
332.if DRZ80_XMAP\r
333 bl z80_xmap_read8\r
334.else\r
335 stmfd sp!,{r3,r12}\r
336 mov lr,pc\r
337 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
338.endif\r
339 mov r1,z80de, lsr #16\r
340.if DRZ80_XMAP\r
341 bl z80_xmap_write8\r
342.else\r
343 mov lr,pc\r
344 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
345 ldmfd sp!,{r3,r12}\r
346.endif\r
347.endm\r
348;@---------------------------------------\r
349\r
350.macro rebasepc\r
351.if UPDATE_CONTEXT\r
352 str z80pc,[cpucontext,#z80pc_pointer]\r
353.endif\r
354.if DRZ80_XMAP\r
355 bl z80_xmap_rebase_pc\r
356.else\r
357 stmfd sp!,{r3,r12}\r
358 mov lr,pc\r
359 ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0\r
360 ldmfd sp!,{r3,r12}\r
361 mov z80pc,r0\r
362.endif\r
363.endm\r
364\r
365.macro rebasesp\r
366.if UPDATE_CONTEXT\r
367 str z80pc,[cpucontext,#z80pc_pointer]\r
368.endif\r
369.if DRZ80_XMAP\r
370 ;@ XXX: SP is locked to single back z80sp_base points to.\r
371 ldr r1,[cpucontext,#z80sp_base]\r
372 bic r0,r0,#0x7f<<Z80_MEM_SHIFT\r
373 add r0,r1,r0\r
374.else\r
375 stmfd sp!,{r3,r12}\r
376 mov lr,pc\r
377 ldr pc,[cpucontext,#z80_rebaseSP] ;@ external function must rebase sp\r
378 ldmfd sp!,{r3,r12}\r
379.endif\r
380.endm\r
381;@----------------------------------------------------------------------------\r
382\r
383.macro opADC\r
384 movs z80f,z80f,lsr#2 ;@ get C\r
385 subcs r0,r0,#0x100\r
386 eor z80f,r0,z80a,lsr#24 ;@ prepare for check of half carry\r
387 adcs z80a,z80a,r0,ror#8\r
388 mrs r0,cpsr ;@ S,Z,V&C\r
389 eor z80f,z80f,z80a,lsr#24\r
390 and z80f,z80f,#1<<HFlag ;@ H, correct\r
391 orr z80f,z80f,r0,lsr#28\r
392.endm\r
393\r
394.macro opADCA\r
395 movs z80f,z80f,lsr#2 ;@ get C\r
396 orrcs z80a,z80a,#0x00800000\r
397 adds z80a,z80a,z80a\r
398 mrs z80f,cpsr ;@ S,Z,V&C\r
399 mov z80f,z80f,lsr#28\r
400 tst z80a,#0x10000000 ;@ H, correct\r
401 orrne z80f,z80f,#1<<HFlag\r
402 fetch 4\r
403.endm\r
404\r
405.macro opADCH reg\r
406 mov r0,\reg,lsr#24\r
407 opADC\r
408 fetch 4\r
409.endm\r
410\r
411.macro opADCL reg\r
412 movs z80f,z80f,lsr#2 ;@ get C\r
413 adc r0,\reg,\reg,lsr#15\r
414 orrcs z80a,z80a,#0x00800000\r
415 mov r1,z80a,lsl#4 ;@ Prepare for check of half carry\r
416 adds z80a,z80a,r0,lsl#23\r
417 mrs z80f,cpsr ;@ S,Z,V&C\r
418 mov z80f,z80f,lsr#28\r
419 cmn r1,r0,lsl#27\r
420 orrcs z80f,z80f,#1<<HFlag ;@ H, correct\r
421 fetch 4\r
422.endm\r
423\r
424.macro opADCb\r
425 opADC\r
426.endm\r
427;@---------------------------------------\r
428\r
429.macro opADD reg shift\r
430 mov r1,z80a,lsl#4 ;@ Prepare for check of half carry\r
431 adds z80a,z80a,\reg,lsl#\shift\r
432 mrs z80f,cpsr ;@ S,Z,V&C\r
433 mov z80f,z80f,lsr#28\r
434 cmn r1,\reg,lsl#\shift+4\r
435 orrcs z80f,z80f,#1<<HFlag\r
436.endm\r
437\r
438.macro opADDA\r
439 adds z80a,z80a,z80a\r
440 mrs z80f,cpsr ;@ S,Z,V&C\r
441 mov z80f,z80f,lsr#28\r
442 tst z80a,#0x10000000 ;@ H, correct\r
443 orrne z80f,z80f,#1<<HFlag\r
444 fetch 4\r
445.endm\r
446\r
447.macro opADDH reg\r
448 and r0,\reg,#0xFF000000\r
449 opADD r0 0\r
450 fetch 4\r
451.endm\r
452\r
453.macro opADDL reg\r
454 opADD \reg 8\r
455 fetch 4\r
456.endm\r
457\r
458.macro opADDb \r
459 opADD r0 24\r
460.endm\r
461;@---------------------------------------\r
462\r
463.macro opADC16 reg\r
464 movs z80f,z80f,lsr#2 ;@ get C\r
465 adc r0,z80a,\reg,lsr#15\r
466 orrcs z80hl,z80hl,#0x00008000\r
467 mov r1,z80hl,lsl#4\r
468 adds z80hl,z80hl,r0,lsl#15\r
469 mrs z80f,cpsr ;@ S, Z, V & C\r
470 mov z80f,z80f,lsr#28\r
471 cmn r1,r0,lsl#19\r
472 orrcs z80f,z80f,#1<<HFlag\r
473 fetch 15\r
474.endm\r
475\r
476.macro opADC16HL\r
477 movs z80f,z80f,lsr#2 ;@ get C\r
478 orrcs z80hl,z80hl,#0x00008000\r
479 adds z80hl,z80hl,z80hl\r
480 mrs z80f,cpsr ;@ S, Z, V & C\r
481 mov z80f,z80f,lsr#28\r
482 tst z80hl,#0x10000000 ;@ H, correct.\r
483 orrne z80f,z80f,#1<<HFlag\r
484 fetch 15\r
485.endm\r
486\r
487.macro opADD16 reg1 reg2\r
488 mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry\r
489 adds \reg1,\reg1,\reg2\r
490 bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
491 orrcs z80f,z80f,#1<<CFlag\r
492 cmn r1,\reg2,lsl#4\r
493 orrcs z80f,z80f,#1<<HFlag\r
494.endm\r
495\r
496.macro opADD16s reg1 reg2 shift\r
497 mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry\r
498 adds \reg1,\reg1,\reg2,lsl#\shift\r
499 bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
500 orrcs z80f,z80f,#1<<CFlag\r
501 cmn r1,\reg2,lsl#4+\shift\r
502 orrcs z80f,z80f,#1<<HFlag\r
503.endm\r
504\r
505.macro opADD16_2 reg\r
506 adds \reg,\reg,\reg\r
507 bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
508 orrcs z80f,z80f,#1<<CFlag\r
509 tst \reg,#0x10000000 ;@ H, correct.\r
510 orrne z80f,z80f,#1<<HFlag\r
511.endm\r
512;@---------------------------------------\r
513\r
514.macro opAND reg shift\r
515 and z80a,z80a,\reg,lsl#\shift\r
516 sub r0,opcodes,#0x100\r
517 ldrb z80f,[r0,z80a, lsr #24]\r
518 orr z80f,z80f,#1<<HFlag\r
519.endm\r
520\r
521.macro opANDA\r
522 sub r0,opcodes,#0x100\r
523 ldrb z80f,[r0,z80a, lsr #24]\r
524 orr z80f,z80f,#1<<HFlag\r
525 fetch 4\r
526.endm\r
527\r
528.macro opANDH reg\r
529 opAND \reg 0\r
530 fetch 4\r
531.endm\r
532\r
533.macro opANDL reg\r
534 opAND \reg 8\r
535 fetch 4\r
536.endm\r
537\r
538.macro opANDb\r
539 opAND r0 24\r
540.endm\r
541;@---------------------------------------\r
542\r
543.macro opBITH reg bit\r
544 and z80f,z80f,#1<<CFlag\r
545 tst \reg,#1<<(24+\bit)\r
546 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
547 orrne z80f,z80f,#(1<<HFlag)\r
548 fetch 8\r
549.endm\r
550\r
551.macro opBIT7H reg\r
552 and z80f,z80f,#1<<CFlag\r
553 tst \reg,#1<<(24+7)\r
554 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
555 orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
556 fetch 8\r
557.endm\r
558\r
559.macro opBITL reg bit\r
560 and z80f,z80f,#1<<CFlag\r
561 tst \reg,#1<<(16+\bit)\r
562 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
563 orrne z80f,z80f,#(1<<HFlag)\r
564 fetch 8\r
565.endm\r
566\r
567.macro opBIT7L reg\r
568 and z80f,z80f,#1<<CFlag\r
569 tst \reg,#1<<(16+7)\r
570 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
571 orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
572 fetch 8\r
573.endm\r
574\r
575.macro opBITb bit\r
576 and z80f,z80f,#1<<CFlag\r
577 tst r0,#1<<\bit\r
578 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
579 orrne z80f,z80f,#(1<<HFlag)\r
580.endm\r
581\r
582.macro opBIT7b\r
583 and z80f,z80f,#1<<CFlag\r
584 tst r0,#1<<7\r
585 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
586 orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
587.endm\r
588;@---------------------------------------\r
589\r
590.macro opCP reg shift\r
591 mov r1,z80a,lsl#4 ;@ prepare for check of half carry\r
592 cmp z80a,\reg,lsl#\shift\r
593 mrs z80f,cpsr\r
594 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
595 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n\r
596 cmp r1,\reg,lsl#\shift+4\r
597 orrcc z80f,z80f,#1<<HFlag\r
598.endm\r
599\r
600.macro opCPA\r
601 mov z80f,#(1<<ZFlag)|(1<<NFlag) ;@ set Z & n\r
602 fetch 4\r
603.endm\r
604\r
605.macro opCPH reg\r
606 and r0,\reg,#0xFF000000\r
607 opCP r0 0\r
608 fetch 4\r
609.endm\r
610\r
611.macro opCPL reg\r
612 opCP \reg 8\r
613 fetch 4\r
614.endm\r
615\r
616.macro opCPb\r
617 opCP r0 24\r
618.endm\r
619;@---------------------------------------\r
620\r
621.macro opDEC8 reg ;@for A and memory\r
622 and z80f,z80f,#1<<CFlag ;@save carry\r
623 orr z80f,z80f,#1<<NFlag ;@set n\r
624 tst \reg,#0x0f000000\r
625 orreq z80f,z80f,#1<<HFlag\r
626 subs \reg,\reg,#0x01000000\r
627 orrmi z80f,z80f,#1<<SFlag\r
628 orrvs z80f,z80f,#1<<VFlag\r
629 orreq z80f,z80f,#1<<ZFlag\r
630.endm\r
631\r
632.macro opDEC8H reg ;@for B, D & H\r
633 and z80f,z80f,#1<<CFlag ;@save carry\r
634 orr z80f,z80f,#1<<NFlag ;@set n\r
635 tst \reg,#0x0f000000\r
636 orreq z80f,z80f,#1<<HFlag\r
637 subs \reg,\reg,#0x01000000\r
638 orrmi z80f,z80f,#1<<SFlag\r
639 orrvs z80f,z80f,#1<<VFlag\r
640 tst \reg,#0xff000000 ;@Z\r
641 orreq z80f,z80f,#1<<ZFlag\r
642.endm\r
643\r
644.macro opDEC8L reg ;@for C, E & L\r
645 mov \reg,\reg,ror#24\r
646 opDEC8H \reg\r
647 mov \reg,\reg,ror#8\r
648.endm\r
649\r
650.macro opDEC8b ;@for memory\r
651 mov r0,r0,lsl#24\r
652 opDEC8 r0\r
653 mov r0,r0,lsr#24\r
654.endm\r
655;@---------------------------------------\r
656\r
657.macro opIN\r
658 stmfd sp!,{r3,r12}\r
659 mov lr,pc\r
660 ldr pc,[cpucontext,#z80_in] ;@ r0=port - data returned in r0\r
661 ldmfd sp!,{r3,r12}\r
662.endm\r
663\r
664.macro opIN_C\r
665 mov r0,z80bc, lsr #16\r
666 opIN\r
667.endm\r
668;@---------------------------------------\r
669\r
670.macro opINC8 reg ;@for A and memory\r
671 and z80f,z80f,#1<<CFlag ;@save carry, clear n\r
672 adds \reg,\reg,#0x01000000\r
673 orrmi z80f,z80f,#1<<SFlag\r
674 orrvs z80f,z80f,#1<<VFlag\r
675 orrcs z80f,z80f,#1<<ZFlag ;@cs when going from 0xFF to 0x00\r
676 tst \reg,#0x0f000000\r
677 orreq z80f,z80f,#1<<HFlag\r
678.endm\r
679\r
680.macro opINC8H reg ;@for B, D & H\r
681 opINC8 \reg\r
682.endm\r
683\r
684.macro opINC8L reg ;@for C, E & L\r
685 mov \reg,\reg,ror#24\r
686 opINC8 \reg\r
687 mov \reg,\reg,ror#8\r
688.endm\r
689\r
690.macro opINC8b ;@for memory\r
691 mov r0,r0,lsl#24\r
692 opINC8 r0\r
693 mov r0,r0,lsr#24\r
694.endm\r
695;@---------------------------------------\r
696\r
697.macro opOR reg shift\r
698 orr z80a,z80a,\reg,lsl#\shift\r
699 sub r0,opcodes,#0x100\r
700 ldrb z80f,[r0,z80a, lsr #24]\r
701.endm\r
702\r
703.macro opORA\r
704 sub r0,opcodes,#0x100\r
705 ldrb z80f,[r0,z80a, lsr #24]\r
706 fetch 4\r
707.endm\r
708\r
709.macro opORH reg\r
710 and r0,\reg,#0xFF000000\r
711 opOR r0 0\r
712 fetch 4\r
713.endm\r
714\r
715.macro opORL reg\r
716 opOR \reg 8\r
717 fetch 4\r
718.endm\r
719\r
720.macro opORb\r
721 opOR r0 24\r
722.endm\r
723;@---------------------------------------\r
724\r
725.macro opOUT\r
726 stmfd sp!,{r3,r12}\r
727 mov lr,pc\r
728 ldr pc,[cpucontext,#z80_out] ;@ r0=port r1=data\r
729 ldmfd sp!,{r3,r12}\r
730.endm\r
731\r
732.macro opOUT_C\r
733 mov r0,z80bc, lsr #16\r
734 opOUT\r
735.endm\r
736;@---------------------------------------\r
737\r
738.macro opPOP\r
739.if FAST_Z80SP\r
740 ldrb r0,[z80sp],#1\r
741 ldrb r1,[z80sp],#1\r
742 orr r0,r0,r1, lsl #8\r
743.else\r
744 mov r0,z80sp\r
745 readmem16\r
746 add z80sp,z80sp,#2\r
747.endif\r
748.endm\r
749\r
750.macro opPOPreg reg\r
751 opPOP\r
752 mov \reg,r0, lsl #16\r
753 fetch 10\r
754.endm\r
755;@---------------------------------------\r
756\r
757.macro stack_check\r
758 @ try to protect against stack overflows, lock into current bank\r
759 ldr r1,[cpucontext,#z80sp_base]\r
760 sub r1,z80sp,r1\r
761 cmp r1,#2\r
762 addlt z80sp,z80sp,#1<<Z80_MEM_SHIFT\r
763.endm\r
764\r
765.macro opPUSHareg reg @ reg > r1\r
766.if FAST_Z80SP\r
767.if DRZ80_XMAP\r
768 stack_check\r
769.endif\r
770 mov r1,\reg, lsr #8\r
771 strb r1,[z80sp,#-1]!\r
772 strb \reg,[z80sp,#-1]!\r
773.else\r
774 mov r0,\reg\r
775 sub z80sp,z80sp,#2\r
776 mov r1,z80sp\r
777 writemem16\r
778.endif\r
779.endm\r
780\r
781.macro opPUSHreg reg\r
782.if FAST_Z80SP\r
783.if DRZ80_XMAP\r
784 stack_check\r
785.endif\r
786 mov r1,\reg, lsr #24\r
787 strb r1,[z80sp,#-1]!\r
788 mov r1,\reg, lsr #16\r
789 strb r1,[z80sp,#-1]!\r
790.else\r
791 mov r0,\reg,lsr #16\r
792 sub z80sp,z80sp,#2\r
793 mov r1,z80sp\r
794 writemem16\r
795.endif\r
796.endm\r
797;@---------------------------------------\r
798\r
799.macro opRESmemHL bit\r
800 mov r0,z80hl, lsr #16\r
801.if DRZ80_XMAP\r
802 bl z80_xmap_read8\r
803 bic r0,r0,#1<<\bit\r
804 mov r1,z80hl, lsr #16\r
805 bl z80_xmap_write8\r
806.else\r
807 stmfd sp!,{r3,r12}\r
808 mov lr,pc\r
809 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
810 bic r0,r0,#1<<\bit\r
811 mov r1,z80hl, lsr #16\r
812 mov lr,pc\r
813 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
814 ldmfd sp!,{r3,r12}\r
815.endif\r
816 fetch 15\r
817.endm\r
818;@---------------------------------------\r
819\r
820.macro opRESmem bit\r
821.if DRZ80_XMAP\r
822 stmfd sp!,{r0} ;@ save addr as well\r
823 bl z80_xmap_read8\r
824 bic r0,r0,#1<<\bit\r
825 ldmfd sp!,{r1} ;@ restore addr into r1\r
826 bl z80_xmap_write8\r
827.else\r
828 stmfd sp!,{r3,r12}\r
829 stmfd sp!,{r0} ;@ save addr as well\r
830 mov lr,pc\r
831 ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0\r
832 bic r0,r0,#1<<\bit\r
833 ldmfd sp!,{r1} ;@ restore addr into r1\r
834 mov lr,pc\r
835 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
836 ldmfd sp!,{r3,r12}\r
837.endif\r
838 fetch 23\r
839.endm\r
840;@---------------------------------------\r
841\r
842.macro opRL reg1 reg2 shift\r
843 movs \reg1,\reg2,lsl \shift\r
844 tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
845 orrne \reg1,\reg1,#0x01000000\r
846;@ and r2,z80f,#1<<CFlag\r
847;@ orr $x,$x,r2,lsl#23\r
848 sub r1,opcodes,#0x100\r
849 ldrb z80f,[r1,\reg1,lsr#24] ;@get PZS\r
850 orrcs z80f,z80f,#1<<CFlag\r
851.endm\r
852\r
853.macro opRLA\r
854 opRL z80a, z80a, #1\r
855 fetch 8\r
856.endm\r
857\r
858.macro opRLH reg\r
859 and r0,\reg,#0xFF000000 ;@mask high to r0\r
860 adds \reg,\reg,r0\r
861 tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
862 orrne \reg,\reg,#0x01000000\r
863 sub r1,opcodes,#0x100\r
864 ldrb z80f,[r1,\reg,lsr#24] ;@get PZS\r
865 orrcs z80f,z80f,#1<<CFlag\r
866 fetch 8\r
867.endm\r
868\r
869.macro opRLL reg\r
870 opRL r0, \reg, #9\r
871 and \reg,\reg,#0xFF000000 ;@mask out high\r
872 orr \reg,\reg,r0,lsr#8\r
873 fetch 8\r
874.endm\r
875\r
876.macro opRLb\r
877 opRL r0, r0, #25\r
878 mov r0,r0,lsr#24\r
879.endm\r
880;@---------------------------------------\r
881\r
882.macro opRLC reg1 reg2 shift\r
883 movs \reg1,\reg2,lsl#\shift\r
884 orrcs \reg1,\reg1,#0x01000000\r
885 sub r1,opcodes,#0x100\r
886 ldrb z80f,[r1,\reg1,lsr#24]\r
887 orrcs z80f,z80f,#1<<CFlag\r
888.endm\r
889\r
890.macro opRLCA\r
891 opRLC z80a, z80a, 1\r
892 fetch 8\r
893.endm\r
894\r
895.macro opRLCH reg\r
896 and r0,\reg,#0xFF000000 ;@mask high to r0\r
897 adds \reg,\reg,r0\r
898 orrcs \reg,\reg,#0x01000000\r
899 sub r1,opcodes,#0x100\r
900 ldrb z80f,[r1,\reg,lsr#24]\r
901 orrcs z80f,z80f,#1<<CFlag\r
902 fetch 8\r
903.endm\r
904\r
905.macro opRLCL reg\r
906 opRLC r0, \reg, 9\r
907 and \reg,\reg,#0xFF000000 ;@mask out high\r
908 orr \reg,\reg,r0,lsr#8\r
909 fetch 8\r
910.endm\r
911\r
912.macro opRLCb\r
913 opRLC r0, r0, 25\r
914 mov r0,r0,lsr#24\r
915.endm\r
916;@---------------------------------------\r
917\r
918.macro opRR reg1 reg2 shift\r
919 movs \reg1,\reg2,lsr#\shift\r
920 tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
921 orrne \reg1,\reg1,#0x00000080\r
922;@ and r2,z80_f,#PSR_C\r
923;@ orr \reg1,\reg1,r2,lsl#6\r
924 sub r1,opcodes,#0x100\r
925 ldrb z80f,[r1,\reg1]\r
926 orrcs z80f,z80f,#1<<CFlag\r
927.endm\r
928\r
929.macro opRRA\r
930 orr z80a,z80a,z80f,lsr#1 ;@get C\r
931 movs z80a,z80a,ror#25\r
932 mov z80a,z80a,lsl#24\r
933 sub r1,opcodes,#0x100\r
934 ldrb z80f,[r1,z80a,lsr#24]\r
935 orrcs z80f,z80f,#1<<CFlag\r
936 fetch 8\r
937.endm\r
938\r
939.macro opRRH reg\r
940 orr r0,\reg,z80f,lsr#1 ;@get C\r
941 movs r0,r0,ror#25\r
942 and \reg,\reg,#0x00FF0000 ;@mask out low\r
943 orr \reg,\reg,r0,lsl#24\r
944 sub r1,opcodes,#0x100\r
945 ldrb z80f,[r1,\reg,lsr#24]\r
946 orrcs z80f,z80f,#1<<CFlag\r
947 fetch 8\r
948.endm\r
949\r
950.macro opRRL reg\r
951 and r0,\reg,#0x00FF0000 ;@mask out low to r0\r
952 opRR r0 r0 17\r
953 and \reg,\reg,#0xFF000000 ;@mask out high\r
954 orr \reg,\reg,r0,lsl#16\r
955 fetch 8\r
956.endm\r
957\r
958.macro opRRb\r
959 opRR r0 r0 1\r
960.endm\r
961;@---------------------------------------\r
962\r
963.macro opRRC reg1 reg2 shift\r
964 movs \reg1,\reg2,lsr#\shift\r
965 orrcs \reg1,\reg1,#0x00000080\r
966 sub r1,opcodes,#0x100\r
967 ldrb z80f,[r1,\reg1]\r
968 orrcs z80f,z80f,#1<<CFlag\r
969.endm\r
970\r
971.macro opRRCA\r
972 opRRC z80a, z80a, 25\r
973 mov z80a,z80a,lsl#24\r
974 fetch 8\r
975.endm\r
976\r
977.macro opRRCH reg\r
978 opRRC r0, \reg, 25\r
979 and \reg,\reg,#0x00FF0000 ;@mask out low\r
980 orr \reg,\reg,r0,lsl#24\r
981 fetch 8\r
982.endm\r
983\r
984.macro opRRCL reg\r
985 and r0,\reg,#0x00FF0000 ;@mask low to r0\r
986 opRRC r0, r0, 17\r
987 and \reg,\reg,#0xFF000000 ;@mask out high\r
988 orr \reg,\reg,r0,lsl#16\r
989 fetch 8\r
990.endm\r
991\r
992.macro opRRCb\r
993 opRRC r0, r0, 1\r
994.endm\r
995;@---------------------------------------\r
996\r
997.macro opRST addr\r
998 ldr r0,[cpucontext,#z80pc_base]\r
999 sub r2,z80pc,r0\r
1000 opPUSHareg r2\r
1001 mov r0,#\addr\r
1002 rebasepc\r
1003 fetch 11\r
1004.endm\r
1005;@---------------------------------------\r
1006\r
1007.macro opSBC\r
1008 eor z80f,z80f,#1<<CFlag ;@ invert C\r
1009 movs z80f,z80f,lsr#2 ;@ get C\r
1010 subcc r0,r0,#0x100\r
1011 eor z80f,r0,z80a,lsr#24 ;@ prepare for check of H\r
1012 sbcs z80a,z80a,r0,ror#8\r
1013 mrs r0,cpsr\r
1014 eor z80f,z80f,z80a,lsr#24\r
1015 and z80f,z80f,#1<<HFlag ;@ H, correct\r
1016 orr z80f,z80f,r0,lsr#28 ;@ S,Z,V&C\r
1017 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.\r
1018.endm\r
1019\r
1020.macro opSBCA\r
1021 movs z80f,z80f,lsr#2 ;@ get C\r
1022 movcc z80a,#0x00000000\r
1023 movcs z80a,#0xFF000000\r
1024 movcc z80f,#(1<<NFlag)|(1<<ZFlag)\r
1025 movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)\r
1026 fetch 4\r
1027.endm\r
1028\r
1029.macro opSBCH reg\r
1030 mov r0,\reg,lsr#24\r
1031 opSBC\r
1032 fetch 4\r
1033.endm\r
1034\r
1035.macro opSBCL reg\r
1036 mov r0,\reg,lsl#8\r
1037 eor z80f,z80f,#1<<CFlag ;@ invert C\r
1038 movs z80f,z80f,lsr#2 ;@ get C\r
1039 sbccc r0,r0,#0xFF000000\r
1040 mov r1,z80a,lsl#4 ;@ prepare for check of H\r
1041 sbcs z80a,z80a,r0\r
1042 mrs z80f,cpsr\r
1043 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
1044 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.\r
1045 cmp r1,r0,lsl#4\r
1046 orrcc z80f,z80f,#1<<HFlag ;@ H, correct\r
1047 fetch 4\r
1048.endm\r
1049\r
1050.macro opSBCb\r
1051 opSBC\r
1052.endm\r
1053;@---------------------------------------\r
1054\r
1055.macro opSBC16 reg\r
1056 eor z80f,z80f,#1<<CFlag ;@ invert C\r
1057 movs z80f,z80f,lsr#2 ;@ get C\r
1058 sbc r1,r1,r1 ;@ set r1 to -1 or 0.\r
1059 orr r0,\reg,r1,lsr#16\r
1060 mov r1,z80hl,lsl#4 ;@ prepare for check of H\r
1061 sbcs z80hl,z80hl,r0\r
1062 mrs z80f,cpsr\r
1063 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
1064 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.\r
1065 cmp r1,r0,lsl#4\r
1066 orrcc z80f,z80f,#1<<HFlag ;@ H, correct\r
1067 fetch 15\r
1068.endm\r
1069\r
1070.macro opSBC16HL\r
1071 movs z80f,z80f,lsr#2 ;@ get C\r
1072 mov z80hl,#0x00000000\r
1073 subcs z80hl,z80hl,#0x00010000\r
1074 movcc z80f,#(1<<NFlag)|(1<<ZFlag)\r
1075 movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)\r
1076 fetch 15\r
1077.endm\r
1078;@---------------------------------------\r
1079\r
1080.macro opSETmemHL bit\r
1081 mov r0,z80hl, lsr #16\r
1082.if DRZ80_XMAP\r
1083 bl z80_xmap_read8\r
1084 orr r0,r0,#1<<\bit\r
1085 mov r1,z80hl, lsr #16\r
1086 bl z80_xmap_write8\r
1087.else\r
1088 stmfd sp!,{r3,r12}\r
1089 mov lr,pc\r
1090 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
1091 orr r0,r0,#1<<\bit\r
1092 mov r1,z80hl, lsr #16\r
1093 mov lr,pc\r
1094 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
1095 ldmfd sp!,{r3,r12}\r
1096.endif\r
1097 fetch 15\r
1098.endm\r
1099;@---------------------------------------\r
1100\r
1101.macro opSETmem bit\r
1102.if DRZ80_XMAP\r
1103 stmfd sp!,{r0} ;@ save addr as well\r
1104 bl z80_xmap_read8\r
1105 orr r0,r0,#1<<\bit\r
1106 ldmfd sp!,{r1} ;@ restore addr into r1\r
1107 bl z80_xmap_write8\r
1108.else\r
1109 stmfd sp!,{r3,r12}\r
1110 stmfd sp!,{r0} ;@ save addr as well\r
1111 mov lr,pc\r
1112 ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0\r
1113 orr r0,r0,#1<<\bit\r
1114 ldmfd sp!,{r1} ;@ restore addr into r1\r
1115 mov lr,pc\r
1116 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
1117 ldmfd sp!,{r3,r12}\r
1118.endif\r
1119 fetch 23\r
1120.endm\r
1121;@---------------------------------------\r
1122\r
1123.macro opSLA reg1 reg2 shift\r
1124 movs \reg1,\reg2,lsl#\shift\r
1125 sub r1,opcodes,#0x100\r
1126 ldrb z80f,[r1,\reg1,lsr#24]\r
1127 orrcs z80f,z80f,#1<<CFlag\r
1128.endm\r
1129\r
1130.macro opSLAA\r
1131 opSLA z80a, z80a, 1\r
1132 fetch 8\r
1133.endm\r
1134\r
1135.macro opSLAH reg\r
1136 and r0,\reg,#0xFF000000 ;@mask high to r0\r
1137 adds \reg,\reg,r0\r
1138 sub r1,opcodes,#0x100\r
1139 ldrb z80f,[r1,\reg,lsr#24]\r
1140 orrcs z80f,z80f,#1<<CFlag\r
1141 fetch 8\r
1142.endm\r
1143\r
1144.macro opSLAL reg\r
1145 opSLA r0, \reg, 9\r
1146 and \reg,\reg,#0xFF000000 ;@mask out high\r
1147 orr \reg,\reg,r0,lsr#8\r
1148 fetch 8\r
1149.endm\r
1150\r
1151.macro opSLAb\r
1152 opSLA r0, r0, 25\r
1153 mov r0,r0,lsr#24\r
1154.endm\r
1155;@---------------------------------------\r
1156\r
1157.macro opSLL reg1 reg2 shift\r
1158 movs \reg1,\reg2,lsl#\shift\r
1159 orr \reg1,\reg1,#0x01000000\r
1160 sub r1,opcodes,#0x100\r
1161 ldrb z80f,[r1,\reg1,lsr#24]\r
1162 orrcs z80f,z80f,#1<<CFlag\r
1163.endm\r
1164\r
1165.macro opSLLA\r
1166 opSLL z80a, z80a, 1\r
1167 fetch 8\r
1168.endm\r
1169\r
1170.macro opSLLH reg\r
1171 and r0,\reg,#0xFF000000 ;@mask high to r0\r
1172 adds \reg,\reg,r0\r
1173 orr \reg,\reg,#0x01000000\r
1174 sub r1,opcodes,#0x100\r
1175 ldrb z80f,[r1,\reg,lsr#24]\r
1176 orrcs z80f,z80f,#1<<CFlag\r
1177 fetch 8\r
1178.endm\r
1179\r
1180.macro opSLLL reg\r
1181 opSLL r0, \reg, 9\r
1182 and \reg,\reg,#0xFF000000 ;@mask out high\r
1183 orr \reg,\reg,r0,lsr#8\r
1184 fetch 8\r
1185.endm\r
1186\r
1187.macro opSLLb\r
1188 opSLL r0, r0, 25\r
1189 mov r0,r0,lsr#24\r
1190.endm\r
1191;@---------------------------------------\r
1192\r
1193.macro opSRA reg1 reg2\r
1194 movs \reg1,\reg2,asr#25\r
1195 and \reg1,\reg1,#0xFF\r
1196 sub r1,opcodes,#0x100\r
1197 ldrb z80f,[r1,\reg1]\r
1198 orrcs z80f,z80f,#1<<CFlag\r
1199.endm\r
1200\r
1201.macro opSRAA\r
1202 movs r0,z80a,asr#25\r
1203 mov z80a,r0,lsl#24\r
1204 sub r1,opcodes,#0x100\r
1205 ldrb z80f,[r1,z80a,lsr#24]\r
1206 orrcs z80f,z80f,#1<<CFlag\r
1207 fetch 8\r
1208.endm\r
1209\r
1210.macro opSRAH reg\r
1211 movs r0,\reg,asr#25\r
1212 and \reg,\reg,#0x00FF0000 ;@mask out low\r
1213 orr \reg,\reg,r0,lsl#24\r
1214 sub r1,opcodes,#0x100\r
1215 ldrb z80f,[r1,\reg,lsr#24]\r
1216 orrcs z80f,z80f,#1<<CFlag\r
1217 fetch 8\r
1218.endm\r
1219\r
1220.macro opSRAL reg\r
1221 mov r0,\reg,lsl#8\r
1222 opSRA r0, r0\r
1223 and \reg,\reg,#0xFF000000 ;@mask out high\r
1224 orr \reg,\reg,r0,lsl#16\r
1225 fetch 8\r
1226.endm\r
1227\r
1228.macro opSRAb\r
1229 mov r0,r0,lsl#24\r
1230 opSRA r0, r0\r
1231.endm\r
1232;@---------------------------------------\r
1233\r
1234.macro opSRL reg1 reg2 shift\r
1235 movs \reg1,\reg2,lsr#\shift\r
1236 sub r1,opcodes,#0x100\r
1237 ldrb z80f,[r1,\reg1]\r
1238 orrcs z80f,z80f,#1<<CFlag\r
1239.endm\r
1240\r
1241.macro opSRLA\r
1242 opSRL z80a, z80a, 25\r
1243 mov z80a,z80a,lsl#24\r
1244 fetch 8\r
1245.endm\r
1246\r
1247.macro opSRLH reg\r
1248 opSRL r0, \reg, 25\r
1249 and \reg,\reg,#0x00FF0000 ;@mask out low\r
1250 orr \reg,\reg,r0,lsl#24\r
1251 fetch 8\r
1252.endm\r
1253\r
1254.macro opSRLL reg\r
1255 mov r0,\reg,lsl#8\r
1256 opSRL r0, r0, 25\r
1257 and \reg,\reg,#0xFF000000 ;@mask out high\r
1258 orr \reg,\reg,r0,lsl#16\r
1259 fetch 8\r
1260.endm\r
1261\r
1262.macro opSRLb\r
1263 opSRL r0, r0, 1\r
1264.endm\r
1265;@---------------------------------------\r
1266\r
1267.macro opSUB reg shift\r
1268 mov r1,z80a,lsl#4 ;@ Prepare for check of half carry\r
1269 subs z80a,z80a,\reg,lsl#\shift\r
1270 mrs z80f,cpsr\r
1271 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
1272 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n\r
1273 cmp r1,\reg,lsl#\shift+4\r
1274 orrcc z80f,z80f,#1<<HFlag\r
1275.endm\r
1276\r
1277.macro opSUBA\r
1278 mov z80a,#0\r
1279 mov z80f,#(1<<ZFlag)|(1<<NFlag) ;@ set Z & n\r
1280 fetch 4\r
1281.endm\r
1282\r
1283.macro opSUBH reg\r
1284 and r0,\reg,#0xFF000000\r
1285 opSUB r0, 0\r
1286 fetch 4\r
1287.endm\r
1288\r
1289.macro opSUBL reg\r
1290 opSUB \reg, 8\r
1291 fetch 4\r
1292.endm\r
1293\r
1294.macro opSUBb\r
1295 opSUB r0, 24\r
1296.endm\r
1297;@---------------------------------------\r
1298\r
1299.macro opXOR reg shift\r
1300 eor z80a,z80a,\reg,lsl#\shift\r
1301 sub r0,opcodes,#0x100\r
1302 ldrb z80f,[r0,z80a, lsr #24]\r
1303.endm\r
1304\r
1305.macro opXORA\r
1306 mov z80a,#0\r
1307 mov z80f,#(1<<ZFlag)|(1<<VFlag)\r
1308 fetch 4\r
1309.endm\r
1310\r
1311.macro opXORH reg\r
1312 and r0,\reg,#0xFF000000\r
1313 opXOR r0, 0\r
1314 fetch 4\r
1315.endm\r
1316\r
1317.macro opXORL reg\r
1318 opXOR \reg, 8\r
1319 fetch 4\r
1320.endm\r
1321\r
1322.macro opXORb\r
1323 opXOR r0, 24\r
1324.endm\r
1325;@---------------------------------------\r
1326\r
1327\r
1328;@ --------------------------- Framework --------------------------\r
1329 \r
1330.text\r
1331\r
1332DrZ80Run:\r
1333 ;@ r0 = pointer to cpu context\r
1334 ;@ r1 = ISTATES to execute \r
1335 ;@######################################### \r
1336 stmdb sp!,{r4-r12,lr} ;@ save registers on stack\r
1337 mov cpucontext,r0 ;@ setup main memory pointer\r
1338 mov z80_icount,r1 ;@ setup number of Tstates to execute\r
1339\r
1340.if INTERRUPT_MODE == 0\r
1341 ldrh r0,[cpucontext,#z80irq] @ 0x4C, irq and IFF bits\r
1342.endif\r
1343 ldmia cpucontext,{z80pc-z80sp} ;@ load Z80 registers\r
1344\r
1345.if INTERRUPT_MODE == 0\r
1346 ;@ check ints\r
1347 tst r0,#0xff\r
1348 movne r0,r0,lsr #8\r
1349 tstne r0,#1\r
1350 blne DoInterrupt\r
1351.endif\r
1352\r
1353 ldr opcodes,MAIN_opcodes_POINTER2\r
1354\r
1355 cmp z80_icount,#0 ;@ irq might have used all cycles\r
1356 ldrplb r0,[z80pc],#1\r
1357 ldrpl pc,[opcodes,r0, lsl #2]\r
1358\r
1359\r
1360z80_execute_end:\r
1361 ;@ save registers in CPU context\r
1362 stmia cpucontext,{z80pc-z80sp} ;@ save Z80 registers\r
1363 mov r0,z80_icount\r
1364 ldmia sp!,{r4-r12,pc} ;@ restore registers from stack and return to C code\r
1365\r
1366MAIN_opcodes_POINTER2: .word MAIN_opcodes\r
1367.if INTERRUPT_MODE\r
1368Interrupt_local: .word Interrupt\r
1369.endif\r
1370\r
1371DoInterrupt:\r
1372.if INTERRUPT_MODE\r
1373 ;@ Don't do own int handler, call mames instead\r
1374\r
1375 ;@ save everything back into DrZ80 context\r
1376 stmia cpucontext,{z80pc-z80sp} ;@ save Z80 registers\r
1377 stmfd sp!,{r3,r4,r5,lr} ;@ save rest of regs on stack\r
1378 mov lr,pc\r
1379 ldr pc,Interrupt_local\r
1380 ldmfd sp!,{r3,r4,r5,lr} ;@ load regs from stack\r
1381 ;@ reload regs from DrZ80 context\r
1382 ldmia cpucontext,{z80pc-z80sp} ;@ load Z80 registers\r
1383 mov pc,lr ;@ return\r
1384.else\r
1385\r
1386 ;@ r0 == z80if\r
1387 stmfd sp!,{lr}\r
1388\r
1389 tst r0,#4 ;@ check halt\r
1390 addne z80pc,z80pc,#1\r
1391\r
1392 ldrb r1,[cpucontext,#z80im]\r
1393\r
1394 ;@ clear halt and int flags\r
1395 eor r0,r0,r0\r
1396 strb r0,[cpucontext,#z80if]\r
1397\r
1398 ;@ now check int mode\r
1399 cmp r1,#1\r
1400 beq DoInterrupt_mode1\r
1401 bgt DoInterrupt_mode2\r
1402\r
1403DoInterrupt_mode0:\r
1404 ;@ get 3 byte vector\r
1405 ldr r2,[cpucontext, #z80irqvector]\r
1406 and r1,r2,#0xFF0000\r
1407 cmp r1,#0xCD0000 ;@ call\r
1408 bne 1f\r
1409 ;@ ########\r
1410 ;@ # call\r
1411 ;@ ########\r
1412 ;@ save current pc on stack\r
1413 ldr r0,[cpucontext,#z80pc_base]\r
1414 sub r0,z80pc,r0\r
1415.if FAST_Z80SP\r
1416 mov r1,r0, lsr #8\r
1417 strb r1,[z80sp,#-1]!\r
1418 strb r0,[z80sp,#-1]!\r
1419.else\r
1420 sub z80sp,z80sp,#2\r
1421 mov r1,z80sp\r
1422 writemem16\r
1423 ldr r2,[cpucontext, #z80irqvector]\r
1424.endif\r
1425 ;@ jump to vector\r
1426 mov r2,r2,lsl#16\r
1427 mov r0,r2,lsr#16\r
1428 ;@ rebase new pc\r
1429 rebasepc\r
1430\r
1431 eatcycles 13\r
1432 b DoInterrupt_end\r
1433\r
14341:\r
1435 cmp r1,#0xC30000 ;@ jump\r
1436 bne DoInterrupt_mode1 ;@ rst\r
1437 ;@ #######\r
1438 ;@ # jump\r
1439 ;@ #######\r
1440 ;@ jump to vector\r
1441 mov r2,r2,lsl#16\r
1442 mov r0,r2,lsr#16\r
1443 ;@ rebase new pc\r
1444 rebasepc\r
1445\r
1446 eatcycles 13\r
1447 b DoInterrupt_end\r
1448\r
1449DoInterrupt_mode1:\r
1450 ldr r0,[cpucontext,#z80pc_base]\r
1451 sub r2,z80pc,r0\r
1452 opPUSHareg r2\r
1453 mov r0,#0x38\r
1454 rebasepc\r
1455\r
1456 eatcycles 13\r
1457 b DoInterrupt_end\r
1458\r
1459DoInterrupt_mode2:\r
1460 ;@ push pc on stack\r
1461 ldr r0,[cpucontext,#z80pc_base]\r
1462 sub r2,z80pc,r0\r
1463 opPUSHareg r2\r
1464\r
1465 ;@ get 1 byte vector address\r
1466 ldrb r0,[cpucontext, #z80irqvector]\r
1467 ldr r1,[cpucontext, #z80i]\r
1468 orr r0,r0,r1,lsr#16\r
1469\r
1470 ;@ read new pc from vector address\r
1471.if UPDATE_CONTEXT\r
1472 str z80pc,[cpucontext,#z80pc_pointer]\r
1473.endif\r
1474.if DRZ80_XMAP\r
1475 bl z80_xmap_read16\r
1476 rebasepc\r
1477.else\r
1478 stmfd sp!,{r3,r12}\r
1479 mov lr,pc\r
1480 ldr pc,[cpucontext,#z80_read16]\r
1481\r
1482 ;@ rebase new pc\r
1483 mov lr,pc\r
1484 ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0\r
1485 ldmfd sp!,{r3,r12}\r
1486 mov z80pc,r0 \r
1487.endif\r
1488 eatcycles 17\r
1489\r
1490DoInterrupt_end:\r
1491 ;@ interupt accepted so callback irq interface\r
1492 ldr r0,[cpucontext, #z80irqcallback]\r
1493 tst r0,r0\r
1494 streqb r0,[cpucontext,#z80irq] ;@ default handling\r
1495 ldmeqfd sp!,{pc}\r
1496 stmfd sp!,{r3,r12}\r
1497 mov lr,pc\r
1498 mov pc,r0 ;@ call callback function\r
1499 ldmfd sp!,{r3,r12}\r
1500 ldmfd sp!,{pc} ;@ return\r
1501.endif\r
1502\r
1503.data\r
1504.align 4\r
1505\r
1506DAATable: .hword (0x00<<8)|(1<<ZFlag)|(1<<VFlag)\r
1507 .hword (0x01<<8) \r
1508 .hword (0x02<<8) \r
1509 .hword (0x03<<8) |(1<<VFlag)\r
1510 .hword (0x04<<8) \r
1511 .hword (0x05<<8) |(1<<VFlag)\r
1512 .hword (0x06<<8) |(1<<VFlag)\r
1513 .hword (0x07<<8) \r
1514 .hword (0x08<<8) \r
1515 .hword (0x09<<8) |(1<<VFlag)\r
1516 .hword (0x10<<8) |(1<<HFlag) \r
1517 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag)\r
1518 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag)\r
1519 .hword (0x13<<8) |(1<<HFlag) \r
1520 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag)\r
1521 .hword (0x15<<8) |(1<<HFlag) \r
1522 .hword (0x10<<8) \r
1523 .hword (0x11<<8) |(1<<VFlag)\r
1524 .hword (0x12<<8) |(1<<VFlag)\r
1525 .hword (0x13<<8) \r
1526 .hword (0x14<<8) |(1<<VFlag)\r
1527 .hword (0x15<<8) \r
1528 .hword (0x16<<8) \r
1529 .hword (0x17<<8) |(1<<VFlag)\r
1530 .hword (0x18<<8) |(1<<VFlag)\r
1531 .hword (0x19<<8) \r
1532 .hword (0x20<<8) |(1<<HFlag) \r
1533 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag)\r
1534 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag)\r
1535 .hword (0x23<<8) |(1<<HFlag) \r
1536 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag)\r
1537 .hword (0x25<<8) |(1<<HFlag) \r
1538 .hword (0x20<<8) \r
1539 .hword (0x21<<8) |(1<<VFlag)\r
1540 .hword (0x22<<8) |(1<<VFlag)\r
1541 .hword (0x23<<8) \r
1542 .hword (0x24<<8) |(1<<VFlag)\r
1543 .hword (0x25<<8) \r
1544 .hword (0x26<<8) \r
1545 .hword (0x27<<8) |(1<<VFlag)\r
1546 .hword (0x28<<8) |(1<<VFlag)\r
1547 .hword (0x29<<8) \r
1548 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag)\r
1549 .hword (0x31<<8) |(1<<HFlag) \r
1550 .hword (0x32<<8) |(1<<HFlag) \r
1551 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag)\r
1552 .hword (0x34<<8) |(1<<HFlag) \r
1553 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag)\r
1554 .hword (0x30<<8) |(1<<VFlag)\r
1555 .hword (0x31<<8) \r
1556 .hword (0x32<<8) \r
1557 .hword (0x33<<8) |(1<<VFlag)\r
1558 .hword (0x34<<8) \r
1559 .hword (0x35<<8) |(1<<VFlag)\r
1560 .hword (0x36<<8) |(1<<VFlag)\r
1561 .hword (0x37<<8) \r
1562 .hword (0x38<<8) \r
1563 .hword (0x39<<8) |(1<<VFlag)\r
1564 .hword (0x40<<8) |(1<<HFlag) \r
1565 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag)\r
1566 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag)\r
1567 .hword (0x43<<8) |(1<<HFlag) \r
1568 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag)\r
1569 .hword (0x45<<8) |(1<<HFlag) \r
1570 .hword (0x40<<8) \r
1571 .hword (0x41<<8) |(1<<VFlag)\r
1572 .hword (0x42<<8) |(1<<VFlag)\r
1573 .hword (0x43<<8) \r
1574 .hword (0x44<<8) |(1<<VFlag)\r
1575 .hword (0x45<<8) \r
1576 .hword (0x46<<8) \r
1577 .hword (0x47<<8) |(1<<VFlag)\r
1578 .hword (0x48<<8) |(1<<VFlag)\r
1579 .hword (0x49<<8) \r
1580 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag)\r
1581 .hword (0x51<<8) |(1<<HFlag) \r
1582 .hword (0x52<<8) |(1<<HFlag) \r
1583 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag)\r
1584 .hword (0x54<<8) |(1<<HFlag) \r
1585 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag)\r
1586 .hword (0x50<<8) |(1<<VFlag)\r
1587 .hword (0x51<<8) \r
1588 .hword (0x52<<8) \r
1589 .hword (0x53<<8) |(1<<VFlag)\r
1590 .hword (0x54<<8) \r
1591 .hword (0x55<<8) |(1<<VFlag)\r
1592 .hword (0x56<<8) |(1<<VFlag)\r
1593 .hword (0x57<<8) \r
1594 .hword (0x58<<8) \r
1595 .hword (0x59<<8) |(1<<VFlag)\r
1596 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag)\r
1597 .hword (0x61<<8) |(1<<HFlag) \r
1598 .hword (0x62<<8) |(1<<HFlag) \r
1599 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag)\r
1600 .hword (0x64<<8) |(1<<HFlag) \r
1601 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag)\r
1602 .hword (0x60<<8) |(1<<VFlag)\r
1603 .hword (0x61<<8) \r
1604 .hword (0x62<<8) \r
1605 .hword (0x63<<8) |(1<<VFlag)\r
1606 .hword (0x64<<8) \r
1607 .hword (0x65<<8) |(1<<VFlag)\r
1608 .hword (0x66<<8) |(1<<VFlag)\r
1609 .hword (0x67<<8) \r
1610 .hword (0x68<<8) \r
1611 .hword (0x69<<8) |(1<<VFlag)\r
1612 .hword (0x70<<8) |(1<<HFlag) \r
1613 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag)\r
1614 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag)\r
1615 .hword (0x73<<8) |(1<<HFlag) \r
1616 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag)\r
1617 .hword (0x75<<8) |(1<<HFlag) \r
1618 .hword (0x70<<8) \r
1619 .hword (0x71<<8) |(1<<VFlag)\r
1620 .hword (0x72<<8) |(1<<VFlag)\r
1621 .hword (0x73<<8) \r
1622 .hword (0x74<<8) |(1<<VFlag)\r
1623 .hword (0x75<<8) \r
1624 .hword (0x76<<8) \r
1625 .hword (0x77<<8) |(1<<VFlag)\r
1626 .hword (0x78<<8) |(1<<VFlag)\r
1627 .hword (0x79<<8) \r
1628 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) \r
1629 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1630 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1631 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) \r
1632 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1633 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) \r
1634 .hword (0x80<<8)|(1<<SFlag) \r
1635 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)\r
1636 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)\r
1637 .hword (0x83<<8)|(1<<SFlag) \r
1638 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)\r
1639 .hword (0x85<<8)|(1<<SFlag) \r
1640 .hword (0x86<<8)|(1<<SFlag) \r
1641 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)\r
1642 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)\r
1643 .hword (0x89<<8)|(1<<SFlag) \r
1644 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1645 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) \r
1646 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) \r
1647 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1648 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) \r
1649 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1650 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)\r
1651 .hword (0x91<<8)|(1<<SFlag) \r
1652 .hword (0x92<<8)|(1<<SFlag) \r
1653 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)\r
1654 .hword (0x94<<8)|(1<<SFlag) \r
1655 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)\r
1656 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)\r
1657 .hword (0x97<<8)|(1<<SFlag) \r
1658 .hword (0x98<<8)|(1<<SFlag) \r
1659 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)\r
1660 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1661 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
1662 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
1663 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1664 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
1665 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1666 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag) |(1<<CFlag)\r
1667 .hword (0x01<<8) |(1<<CFlag)\r
1668 .hword (0x02<<8) |(1<<CFlag)\r
1669 .hword (0x03<<8) |(1<<VFlag) |(1<<CFlag)\r
1670 .hword (0x04<<8) |(1<<CFlag)\r
1671 .hword (0x05<<8) |(1<<VFlag) |(1<<CFlag)\r
1672 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
1673 .hword (0x07<<8) |(1<<CFlag)\r
1674 .hword (0x08<<8) |(1<<CFlag)\r
1675 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
1676 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
1677 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1678 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1679 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
1680 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1681 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
1682 .hword (0x10<<8) |(1<<CFlag)\r
1683 .hword (0x11<<8) |(1<<VFlag) |(1<<CFlag)\r
1684 .hword (0x12<<8) |(1<<VFlag) |(1<<CFlag)\r
1685 .hword (0x13<<8) |(1<<CFlag)\r
1686 .hword (0x14<<8) |(1<<VFlag) |(1<<CFlag)\r
1687 .hword (0x15<<8) |(1<<CFlag)\r
1688 .hword (0x16<<8) |(1<<CFlag)\r
1689 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
1690 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
1691 .hword (0x19<<8) |(1<<CFlag)\r
1692 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
1693 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1694 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1695 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
1696 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1697 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
1698 .hword (0x20<<8) |(1<<CFlag)\r
1699 .hword (0x21<<8) |(1<<VFlag) |(1<<CFlag)\r
1700 .hword (0x22<<8) |(1<<VFlag) |(1<<CFlag)\r
1701 .hword (0x23<<8) |(1<<CFlag)\r
1702 .hword (0x24<<8) |(1<<VFlag) |(1<<CFlag)\r
1703 .hword (0x25<<8) |(1<<CFlag)\r
1704 .hword (0x26<<8) |(1<<CFlag)\r
1705 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
1706 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
1707 .hword (0x29<<8) |(1<<CFlag)\r
1708 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1709 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
1710 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
1711 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1712 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
1713 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1714 .hword (0x30<<8) |(1<<VFlag) |(1<<CFlag)\r
1715 .hword (0x31<<8) |(1<<CFlag)\r
1716 .hword (0x32<<8) |(1<<CFlag)\r
1717 .hword (0x33<<8) |(1<<VFlag) |(1<<CFlag)\r
1718 .hword (0x34<<8) |(1<<CFlag)\r
1719 .hword (0x35<<8) |(1<<VFlag) |(1<<CFlag)\r
1720 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
1721 .hword (0x37<<8) |(1<<CFlag)\r
1722 .hword (0x38<<8) |(1<<CFlag)\r
1723 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
1724 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
1725 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1726 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1727 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
1728 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1729 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
1730 .hword (0x40<<8) |(1<<CFlag)\r
1731 .hword (0x41<<8) |(1<<VFlag) |(1<<CFlag)\r
1732 .hword (0x42<<8) |(1<<VFlag) |(1<<CFlag)\r
1733 .hword (0x43<<8) |(1<<CFlag)\r
1734 .hword (0x44<<8) |(1<<VFlag) |(1<<CFlag)\r
1735 .hword (0x45<<8) |(1<<CFlag)\r
1736 .hword (0x46<<8) |(1<<CFlag)\r
1737 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
1738 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
1739 .hword (0x49<<8) |(1<<CFlag)\r
1740 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1741 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
1742 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
1743 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1744 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
1745 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1746 .hword (0x50<<8) |(1<<VFlag) |(1<<CFlag)\r
1747 .hword (0x51<<8) |(1<<CFlag)\r
1748 .hword (0x52<<8) |(1<<CFlag)\r
1749 .hword (0x53<<8) |(1<<VFlag) |(1<<CFlag)\r
1750 .hword (0x54<<8) |(1<<CFlag)\r
1751 .hword (0x55<<8) |(1<<VFlag) |(1<<CFlag)\r
1752 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
1753 .hword (0x57<<8) |(1<<CFlag)\r
1754 .hword (0x58<<8) |(1<<CFlag)\r
1755 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
1756 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1757 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
1758 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
1759 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1760 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
1761 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1762 .hword (0x60<<8) |(1<<VFlag) |(1<<CFlag)\r
1763 .hword (0x61<<8) |(1<<CFlag)\r
1764 .hword (0x62<<8) |(1<<CFlag)\r
1765 .hword (0x63<<8) |(1<<VFlag) |(1<<CFlag)\r
1766 .hword (0x64<<8) |(1<<CFlag)\r
1767 .hword (0x65<<8) |(1<<VFlag) |(1<<CFlag)\r
1768 .hword (0x66<<8) |(1<<VFlag) |(1<<CFlag)\r
1769 .hword (0x67<<8) |(1<<CFlag)\r
1770 .hword (0x68<<8) |(1<<CFlag)\r
1771 .hword (0x69<<8) |(1<<VFlag) |(1<<CFlag)\r
1772 .hword (0x70<<8) |(1<<HFlag) |(1<<CFlag)\r
1773 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1774 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1775 .hword (0x73<<8) |(1<<HFlag) |(1<<CFlag)\r
1776 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1777 .hword (0x75<<8) |(1<<HFlag) |(1<<CFlag)\r
1778 .hword (0x70<<8) |(1<<CFlag)\r
1779 .hword (0x71<<8) |(1<<VFlag) |(1<<CFlag)\r
1780 .hword (0x72<<8) |(1<<VFlag) |(1<<CFlag)\r
1781 .hword (0x73<<8) |(1<<CFlag)\r
1782 .hword (0x74<<8) |(1<<VFlag) |(1<<CFlag)\r
1783 .hword (0x75<<8) |(1<<CFlag)\r
1784 .hword (0x76<<8) |(1<<CFlag)\r
1785 .hword (0x77<<8) |(1<<VFlag) |(1<<CFlag)\r
1786 .hword (0x78<<8) |(1<<VFlag) |(1<<CFlag)\r
1787 .hword (0x79<<8) |(1<<CFlag)\r
1788 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1789 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1790 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1791 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1792 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1793 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1794 .hword (0x80<<8)|(1<<SFlag) |(1<<CFlag)\r
1795 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1796 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1797 .hword (0x83<<8)|(1<<SFlag) |(1<<CFlag)\r
1798 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1799 .hword (0x85<<8)|(1<<SFlag) |(1<<CFlag)\r
1800 .hword (0x86<<8)|(1<<SFlag) |(1<<CFlag)\r
1801 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1802 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1803 .hword (0x89<<8)|(1<<SFlag) |(1<<CFlag)\r
1804 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1805 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1806 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1807 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1808 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1809 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1810 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1811 .hword (0x91<<8)|(1<<SFlag) |(1<<CFlag)\r
1812 .hword (0x92<<8)|(1<<SFlag) |(1<<CFlag)\r
1813 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1814 .hword (0x94<<8)|(1<<SFlag) |(1<<CFlag)\r
1815 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1816 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1817 .hword (0x97<<8)|(1<<SFlag) |(1<<CFlag)\r
1818 .hword (0x98<<8)|(1<<SFlag) |(1<<CFlag)\r
1819 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1820 .hword (0xA0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1821 .hword (0xA1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1822 .hword (0xA2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1823 .hword (0xA3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1824 .hword (0xA4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1825 .hword (0xA5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1826 .hword (0xA0<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1827 .hword (0xA1<<8)|(1<<SFlag) |(1<<CFlag)\r
1828 .hword (0xA2<<8)|(1<<SFlag) |(1<<CFlag)\r
1829 .hword (0xA3<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1830 .hword (0xA4<<8)|(1<<SFlag) |(1<<CFlag)\r
1831 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1832 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1833 .hword (0xA7<<8)|(1<<SFlag) |(1<<CFlag)\r
1834 .hword (0xA8<<8)|(1<<SFlag) |(1<<CFlag)\r
1835 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1836 .hword (0xB0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1837 .hword (0xB1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1838 .hword (0xB2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1839 .hword (0xB3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1840 .hword (0xB4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1841 .hword (0xB5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1842 .hword (0xB0<<8)|(1<<SFlag) |(1<<CFlag)\r
1843 .hword (0xB1<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1844 .hword (0xB2<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1845 .hword (0xB3<<8)|(1<<SFlag) |(1<<CFlag)\r
1846 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1847 .hword (0xB5<<8)|(1<<SFlag) |(1<<CFlag)\r
1848 .hword (0xB6<<8)|(1<<SFlag) |(1<<CFlag)\r
1849 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1850 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1851 .hword (0xB9<<8)|(1<<SFlag) |(1<<CFlag)\r
1852 .hword (0xC0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1853 .hword (0xC1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1854 .hword (0xC2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1855 .hword (0xC3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1856 .hword (0xC4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1857 .hword (0xC5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1858 .hword (0xC0<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1859 .hword (0xC1<<8)|(1<<SFlag) |(1<<CFlag)\r
1860 .hword (0xC2<<8)|(1<<SFlag) |(1<<CFlag)\r
1861 .hword (0xC3<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1862 .hword (0xC4<<8)|(1<<SFlag) |(1<<CFlag)\r
1863 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1864 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1865 .hword (0xC7<<8)|(1<<SFlag) |(1<<CFlag)\r
1866 .hword (0xC8<<8)|(1<<SFlag) |(1<<CFlag)\r
1867 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1868 .hword (0xD0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1869 .hword (0xD1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1870 .hword (0xD2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1871 .hword (0xD3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1872 .hword (0xD4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1873 .hword (0xD5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1874 .hword (0xD0<<8)|(1<<SFlag) |(1<<CFlag)\r
1875 .hword (0xD1<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1876 .hword (0xD2<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1877 .hword (0xD3<<8)|(1<<SFlag) |(1<<CFlag)\r
1878 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1879 .hword (0xD5<<8)|(1<<SFlag) |(1<<CFlag)\r
1880 .hword (0xD6<<8)|(1<<SFlag) |(1<<CFlag)\r
1881 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1882 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1883 .hword (0xD9<<8)|(1<<SFlag) |(1<<CFlag)\r
1884 .hword (0xE0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1885 .hword (0xE1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1886 .hword (0xE2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1887 .hword (0xE3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1888 .hword (0xE4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1889 .hword (0xE5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1890 .hword (0xE0<<8)|(1<<SFlag) |(1<<CFlag)\r
1891 .hword (0xE1<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1892 .hword (0xE2<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1893 .hword (0xE3<<8)|(1<<SFlag) |(1<<CFlag)\r
1894 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1895 .hword (0xE5<<8)|(1<<SFlag) |(1<<CFlag)\r
1896 .hword (0xE6<<8)|(1<<SFlag) |(1<<CFlag)\r
1897 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1898 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1899 .hword (0xE9<<8)|(1<<SFlag) |(1<<CFlag)\r
1900 .hword (0xF0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1901 .hword (0xF1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1902 .hword (0xF2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1903 .hword (0xF3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1904 .hword (0xF4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1905 .hword (0xF5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1906 .hword (0xF0<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1907 .hword (0xF1<<8)|(1<<SFlag) |(1<<CFlag)\r
1908 .hword (0xF2<<8)|(1<<SFlag) |(1<<CFlag)\r
1909 .hword (0xF3<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1910 .hword (0xF4<<8)|(1<<SFlag) |(1<<CFlag)\r
1911 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1912 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1913 .hword (0xF7<<8)|(1<<SFlag) |(1<<CFlag)\r
1914 .hword (0xF8<<8)|(1<<SFlag) |(1<<CFlag)\r
1915 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1916 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1917 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
1918 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
1919 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1920 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
1921 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1922 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag) |(1<<CFlag)\r
1923 .hword (0x01<<8) |(1<<CFlag)\r
1924 .hword (0x02<<8) |(1<<CFlag)\r
1925 .hword (0x03<<8) |(1<<VFlag) |(1<<CFlag)\r
1926 .hword (0x04<<8) |(1<<CFlag)\r
1927 .hword (0x05<<8) |(1<<VFlag) |(1<<CFlag)\r
1928 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
1929 .hword (0x07<<8) |(1<<CFlag)\r
1930 .hword (0x08<<8) |(1<<CFlag)\r
1931 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
1932 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
1933 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1934 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1935 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
1936 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1937 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
1938 .hword (0x10<<8) |(1<<CFlag)\r
1939 .hword (0x11<<8) |(1<<VFlag) |(1<<CFlag)\r
1940 .hword (0x12<<8) |(1<<VFlag) |(1<<CFlag)\r
1941 .hword (0x13<<8) |(1<<CFlag)\r
1942 .hword (0x14<<8) |(1<<VFlag) |(1<<CFlag)\r
1943 .hword (0x15<<8) |(1<<CFlag)\r
1944 .hword (0x16<<8) |(1<<CFlag)\r
1945 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
1946 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
1947 .hword (0x19<<8) |(1<<CFlag)\r
1948 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
1949 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1950 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1951 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
1952 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1953 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
1954 .hword (0x20<<8) |(1<<CFlag)\r
1955 .hword (0x21<<8) |(1<<VFlag) |(1<<CFlag)\r
1956 .hword (0x22<<8) |(1<<VFlag) |(1<<CFlag)\r
1957 .hword (0x23<<8) |(1<<CFlag)\r
1958 .hword (0x24<<8) |(1<<VFlag) |(1<<CFlag)\r
1959 .hword (0x25<<8) |(1<<CFlag)\r
1960 .hword (0x26<<8) |(1<<CFlag)\r
1961 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
1962 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
1963 .hword (0x29<<8) |(1<<CFlag)\r
1964 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1965 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
1966 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
1967 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1968 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
1969 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1970 .hword (0x30<<8) |(1<<VFlag) |(1<<CFlag)\r
1971 .hword (0x31<<8) |(1<<CFlag)\r
1972 .hword (0x32<<8) |(1<<CFlag)\r
1973 .hword (0x33<<8) |(1<<VFlag) |(1<<CFlag)\r
1974 .hword (0x34<<8) |(1<<CFlag)\r
1975 .hword (0x35<<8) |(1<<VFlag) |(1<<CFlag)\r
1976 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
1977 .hword (0x37<<8) |(1<<CFlag)\r
1978 .hword (0x38<<8) |(1<<CFlag)\r
1979 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
1980 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
1981 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1982 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1983 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
1984 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1985 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
1986 .hword (0x40<<8) |(1<<CFlag)\r
1987 .hword (0x41<<8) |(1<<VFlag) |(1<<CFlag)\r
1988 .hword (0x42<<8) |(1<<VFlag) |(1<<CFlag)\r
1989 .hword (0x43<<8) |(1<<CFlag)\r
1990 .hword (0x44<<8) |(1<<VFlag) |(1<<CFlag)\r
1991 .hword (0x45<<8) |(1<<CFlag)\r
1992 .hword (0x46<<8) |(1<<CFlag)\r
1993 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
1994 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
1995 .hword (0x49<<8) |(1<<CFlag)\r
1996 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1997 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
1998 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
1999 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2000 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
2001 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2002 .hword (0x50<<8) |(1<<VFlag) |(1<<CFlag)\r
2003 .hword (0x51<<8) |(1<<CFlag)\r
2004 .hword (0x52<<8) |(1<<CFlag)\r
2005 .hword (0x53<<8) |(1<<VFlag) |(1<<CFlag)\r
2006 .hword (0x54<<8) |(1<<CFlag)\r
2007 .hword (0x55<<8) |(1<<VFlag) |(1<<CFlag)\r
2008 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
2009 .hword (0x57<<8) |(1<<CFlag)\r
2010 .hword (0x58<<8) |(1<<CFlag)\r
2011 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
2012 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2013 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
2014 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
2015 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2016 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
2017 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2018 .hword (0x06<<8) |(1<<VFlag)\r
2019 .hword (0x07<<8) \r
2020 .hword (0x08<<8) \r
2021 .hword (0x09<<8) |(1<<VFlag)\r
2022 .hword (0x0A<<8) |(1<<VFlag)\r
2023 .hword (0x0B<<8) \r
2024 .hword (0x0C<<8) |(1<<VFlag)\r
2025 .hword (0x0D<<8) \r
2026 .hword (0x0E<<8) \r
2027 .hword (0x0F<<8) |(1<<VFlag)\r
2028 .hword (0x10<<8) |(1<<HFlag) \r
2029 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag)\r
2030 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag)\r
2031 .hword (0x13<<8) |(1<<HFlag) \r
2032 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag)\r
2033 .hword (0x15<<8) |(1<<HFlag) \r
2034 .hword (0x16<<8) \r
2035 .hword (0x17<<8) |(1<<VFlag)\r
2036 .hword (0x18<<8) |(1<<VFlag)\r
2037 .hword (0x19<<8) \r
2038 .hword (0x1A<<8) \r
2039 .hword (0x1B<<8) |(1<<VFlag)\r
2040 .hword (0x1C<<8) \r
2041 .hword (0x1D<<8) |(1<<VFlag)\r
2042 .hword (0x1E<<8) |(1<<VFlag)\r
2043 .hword (0x1F<<8) \r
2044 .hword (0x20<<8) |(1<<HFlag) \r
2045 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag)\r
2046 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag)\r
2047 .hword (0x23<<8) |(1<<HFlag) \r
2048 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag)\r
2049 .hword (0x25<<8) |(1<<HFlag) \r
2050 .hword (0x26<<8) \r
2051 .hword (0x27<<8) |(1<<VFlag)\r
2052 .hword (0x28<<8) |(1<<VFlag)\r
2053 .hword (0x29<<8) \r
2054 .hword (0x2A<<8) \r
2055 .hword (0x2B<<8) |(1<<VFlag)\r
2056 .hword (0x2C<<8) \r
2057 .hword (0x2D<<8) |(1<<VFlag)\r
2058 .hword (0x2E<<8) |(1<<VFlag)\r
2059 .hword (0x2F<<8) \r
2060 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag)\r
2061 .hword (0x31<<8) |(1<<HFlag) \r
2062 .hword (0x32<<8) |(1<<HFlag) \r
2063 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag)\r
2064 .hword (0x34<<8) |(1<<HFlag) \r
2065 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag)\r
2066 .hword (0x36<<8) |(1<<VFlag)\r
2067 .hword (0x37<<8) \r
2068 .hword (0x38<<8) \r
2069 .hword (0x39<<8) |(1<<VFlag)\r
2070 .hword (0x3A<<8) |(1<<VFlag)\r
2071 .hword (0x3B<<8) \r
2072 .hword (0x3C<<8) |(1<<VFlag)\r
2073 .hword (0x3D<<8) \r
2074 .hword (0x3E<<8) \r
2075 .hword (0x3F<<8) |(1<<VFlag)\r
2076 .hword (0x40<<8) |(1<<HFlag) \r
2077 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag)\r
2078 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag)\r
2079 .hword (0x43<<8) |(1<<HFlag) \r
2080 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag)\r
2081 .hword (0x45<<8) |(1<<HFlag) \r
2082 .hword (0x46<<8) \r
2083 .hword (0x47<<8) |(1<<VFlag)\r
2084 .hword (0x48<<8) |(1<<VFlag)\r
2085 .hword (0x49<<8) \r
2086 .hword (0x4A<<8) \r
2087 .hword (0x4B<<8) |(1<<VFlag)\r
2088 .hword (0x4C<<8) \r
2089 .hword (0x4D<<8) |(1<<VFlag)\r
2090 .hword (0x4E<<8) |(1<<VFlag)\r
2091 .hword (0x4F<<8) \r
2092 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag)\r
2093 .hword (0x51<<8) |(1<<HFlag) \r
2094 .hword (0x52<<8) |(1<<HFlag) \r
2095 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag)\r
2096 .hword (0x54<<8) |(1<<HFlag) \r
2097 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag)\r
2098 .hword (0x56<<8) |(1<<VFlag)\r
2099 .hword (0x57<<8) \r
2100 .hword (0x58<<8) \r
2101 .hword (0x59<<8) |(1<<VFlag)\r
2102 .hword (0x5A<<8) |(1<<VFlag)\r
2103 .hword (0x5B<<8) \r
2104 .hword (0x5C<<8) |(1<<VFlag)\r
2105 .hword (0x5D<<8) \r
2106 .hword (0x5E<<8) \r
2107 .hword (0x5F<<8) |(1<<VFlag)\r
2108 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag)\r
2109 .hword (0x61<<8) |(1<<HFlag) \r
2110 .hword (0x62<<8) |(1<<HFlag) \r
2111 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag)\r
2112 .hword (0x64<<8) |(1<<HFlag) \r
2113 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag)\r
2114 .hword (0x66<<8) |(1<<VFlag)\r
2115 .hword (0x67<<8) \r
2116 .hword (0x68<<8) \r
2117 .hword (0x69<<8) |(1<<VFlag)\r
2118 .hword (0x6A<<8) |(1<<VFlag)\r
2119 .hword (0x6B<<8) \r
2120 .hword (0x6C<<8) |(1<<VFlag)\r
2121 .hword (0x6D<<8) \r
2122 .hword (0x6E<<8) \r
2123 .hword (0x6F<<8) |(1<<VFlag)\r
2124 .hword (0x70<<8) |(1<<HFlag) \r
2125 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag)\r
2126 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag)\r
2127 .hword (0x73<<8) |(1<<HFlag) \r
2128 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag)\r
2129 .hword (0x75<<8) |(1<<HFlag) \r
2130 .hword (0x76<<8) \r
2131 .hword (0x77<<8) |(1<<VFlag)\r
2132 .hword (0x78<<8) |(1<<VFlag)\r
2133 .hword (0x79<<8) \r
2134 .hword (0x7A<<8) \r
2135 .hword (0x7B<<8) |(1<<VFlag)\r
2136 .hword (0x7C<<8) \r
2137 .hword (0x7D<<8) |(1<<VFlag)\r
2138 .hword (0x7E<<8) |(1<<VFlag)\r
2139 .hword (0x7F<<8) \r
2140 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) \r
2141 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2142 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2143 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) \r
2144 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2145 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) \r
2146 .hword (0x86<<8)|(1<<SFlag) \r
2147 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)\r
2148 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)\r
2149 .hword (0x89<<8)|(1<<SFlag) \r
2150 .hword (0x8A<<8)|(1<<SFlag) \r
2151 .hword (0x8B<<8)|(1<<SFlag) |(1<<VFlag)\r
2152 .hword (0x8C<<8)|(1<<SFlag) \r
2153 .hword (0x8D<<8)|(1<<SFlag) |(1<<VFlag)\r
2154 .hword (0x8E<<8)|(1<<SFlag) |(1<<VFlag)\r
2155 .hword (0x8F<<8)|(1<<SFlag) \r
2156 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2157 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) \r
2158 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) \r
2159 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2160 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) \r
2161 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2162 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)\r
2163 .hword (0x97<<8)|(1<<SFlag) \r
2164 .hword (0x98<<8)|(1<<SFlag) \r
2165 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)\r
2166 .hword (0x9A<<8)|(1<<SFlag) |(1<<VFlag)\r
2167 .hword (0x9B<<8)|(1<<SFlag) \r
2168 .hword (0x9C<<8)|(1<<SFlag) |(1<<VFlag)\r
2169 .hword (0x9D<<8)|(1<<SFlag) \r
2170 .hword (0x9E<<8)|(1<<SFlag) \r
2171 .hword (0x9F<<8)|(1<<SFlag) |(1<<VFlag)\r
2172 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2173 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
2174 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
2175 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2176 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
2177 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2178 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
2179 .hword (0x07<<8) |(1<<CFlag)\r
2180 .hword (0x08<<8) |(1<<CFlag)\r
2181 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
2182 .hword (0x0A<<8) |(1<<VFlag) |(1<<CFlag)\r
2183 .hword (0x0B<<8) |(1<<CFlag)\r
2184 .hword (0x0C<<8) |(1<<VFlag) |(1<<CFlag)\r
2185 .hword (0x0D<<8) |(1<<CFlag)\r
2186 .hword (0x0E<<8) |(1<<CFlag)\r
2187 .hword (0x0F<<8) |(1<<VFlag) |(1<<CFlag)\r
2188 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
2189 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2190 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2191 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
2192 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2193 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
2194 .hword (0x16<<8) |(1<<CFlag)\r
2195 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
2196 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
2197 .hword (0x19<<8) |(1<<CFlag)\r
2198 .hword (0x1A<<8) |(1<<CFlag)\r
2199 .hword (0x1B<<8) |(1<<VFlag) |(1<<CFlag)\r
2200 .hword (0x1C<<8) |(1<<CFlag)\r
2201 .hword (0x1D<<8) |(1<<VFlag) |(1<<CFlag)\r
2202 .hword (0x1E<<8) |(1<<VFlag) |(1<<CFlag)\r
2203 .hword (0x1F<<8) |(1<<CFlag)\r
2204 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
2205 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2206 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2207 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
2208 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2209 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
2210 .hword (0x26<<8) |(1<<CFlag)\r
2211 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
2212 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
2213 .hword (0x29<<8) |(1<<CFlag)\r
2214 .hword (0x2A<<8) |(1<<CFlag)\r
2215 .hword (0x2B<<8) |(1<<VFlag) |(1<<CFlag)\r
2216 .hword (0x2C<<8) |(1<<CFlag)\r
2217 .hword (0x2D<<8) |(1<<VFlag) |(1<<CFlag)\r
2218 .hword (0x2E<<8) |(1<<VFlag) |(1<<CFlag)\r
2219 .hword (0x2F<<8) |(1<<CFlag)\r
2220 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2221 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
2222 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
2223 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2224 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
2225 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2226 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
2227 .hword (0x37<<8) |(1<<CFlag)\r
2228 .hword (0x38<<8) |(1<<CFlag)\r
2229 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
2230 .hword (0x3A<<8) |(1<<VFlag) |(1<<CFlag)\r
2231 .hword (0x3B<<8) |(1<<CFlag)\r
2232 .hword (0x3C<<8) |(1<<VFlag) |(1<<CFlag)\r
2233 .hword (0x3D<<8) |(1<<CFlag)\r
2234 .hword (0x3E<<8) |(1<<CFlag)\r
2235 .hword (0x3F<<8) |(1<<VFlag) |(1<<CFlag)\r
2236 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
2237 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2238 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2239 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
2240 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2241 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
2242 .hword (0x46<<8) |(1<<CFlag)\r
2243 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
2244 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
2245 .hword (0x49<<8) |(1<<CFlag)\r
2246 .hword (0x4A<<8) |(1<<CFlag)\r
2247 .hword (0x4B<<8) |(1<<VFlag) |(1<<CFlag)\r
2248 .hword (0x4C<<8) |(1<<CFlag)\r
2249 .hword (0x4D<<8) |(1<<VFlag) |(1<<CFlag)\r
2250 .hword (0x4E<<8) |(1<<VFlag) |(1<<CFlag)\r
2251 .hword (0x4F<<8) |(1<<CFlag)\r
2252 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2253 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
2254 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
2255 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2256 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
2257 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2258 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
2259 .hword (0x57<<8) |(1<<CFlag)\r
2260 .hword (0x58<<8) |(1<<CFlag)\r
2261 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
2262 .hword (0x5A<<8) |(1<<VFlag) |(1<<CFlag)\r
2263 .hword (0x5B<<8) |(1<<CFlag)\r
2264 .hword (0x5C<<8) |(1<<VFlag) |(1<<CFlag)\r
2265 .hword (0x5D<<8) |(1<<CFlag)\r
2266 .hword (0x5E<<8) |(1<<CFlag)\r
2267 .hword (0x5F<<8) |(1<<VFlag) |(1<<CFlag)\r
2268 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2269 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
2270 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
2271 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2272 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
2273 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2274 .hword (0x66<<8) |(1<<VFlag) |(1<<CFlag)\r
2275 .hword (0x67<<8) |(1<<CFlag)\r
2276 .hword (0x68<<8) |(1<<CFlag)\r
2277 .hword (0x69<<8) |(1<<VFlag) |(1<<CFlag)\r
2278 .hword (0x6A<<8) |(1<<VFlag) |(1<<CFlag)\r
2279 .hword (0x6B<<8) |(1<<CFlag)\r
2280 .hword (0x6C<<8) |(1<<VFlag) |(1<<CFlag)\r
2281 .hword (0x6D<<8) |(1<<CFlag)\r
2282 .hword (0x6E<<8) |(1<<CFlag)\r
2283 .hword (0x6F<<8) |(1<<VFlag) |(1<<CFlag)\r
2284 .hword (0x70<<8) |(1<<HFlag) |(1<<CFlag)\r
2285 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2286 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2287 .hword (0x73<<8) |(1<<HFlag) |(1<<CFlag)\r
2288 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2289 .hword (0x75<<8) |(1<<HFlag) |(1<<CFlag)\r
2290 .hword (0x76<<8) |(1<<CFlag)\r
2291 .hword (0x77<<8) |(1<<VFlag) |(1<<CFlag)\r
2292 .hword (0x78<<8) |(1<<VFlag) |(1<<CFlag)\r
2293 .hword (0x79<<8) |(1<<CFlag)\r
2294 .hword (0x7A<<8) |(1<<CFlag)\r
2295 .hword (0x7B<<8) |(1<<VFlag) |(1<<CFlag)\r
2296 .hword (0x7C<<8) |(1<<CFlag)\r
2297 .hword (0x7D<<8) |(1<<VFlag) |(1<<CFlag)\r
2298 .hword (0x7E<<8) |(1<<VFlag) |(1<<CFlag)\r
2299 .hword (0x7F<<8) |(1<<CFlag)\r
2300 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2301 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2302 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2303 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2304 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2305 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2306 .hword (0x86<<8)|(1<<SFlag) |(1<<CFlag)\r
2307 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2308 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2309 .hword (0x89<<8)|(1<<SFlag) |(1<<CFlag)\r
2310 .hword (0x8A<<8)|(1<<SFlag) |(1<<CFlag)\r
2311 .hword (0x8B<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2312 .hword (0x8C<<8)|(1<<SFlag) |(1<<CFlag)\r
2313 .hword (0x8D<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2314 .hword (0x8E<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2315 .hword (0x8F<<8)|(1<<SFlag) |(1<<CFlag)\r
2316 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2317 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2318 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2319 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2320 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2321 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2322 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2323 .hword (0x97<<8)|(1<<SFlag) |(1<<CFlag)\r
2324 .hword (0x98<<8)|(1<<SFlag) |(1<<CFlag)\r
2325 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2326 .hword (0x9A<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2327 .hword (0x9B<<8)|(1<<SFlag) |(1<<CFlag)\r
2328 .hword (0x9C<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2329 .hword (0x9D<<8)|(1<<SFlag) |(1<<CFlag)\r
2330 .hword (0x9E<<8)|(1<<SFlag) |(1<<CFlag)\r
2331 .hword (0x9F<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2332 .hword (0xA0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2333 .hword (0xA1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2334 .hword (0xA2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2335 .hword (0xA3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2336 .hword (0xA4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2337 .hword (0xA5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2338 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2339 .hword (0xA7<<8)|(1<<SFlag) |(1<<CFlag)\r
2340 .hword (0xA8<<8)|(1<<SFlag) |(1<<CFlag)\r
2341 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2342 .hword (0xAA<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2343 .hword (0xAB<<8)|(1<<SFlag) |(1<<CFlag)\r
2344 .hword (0xAC<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2345 .hword (0xAD<<8)|(1<<SFlag) |(1<<CFlag)\r
2346 .hword (0xAE<<8)|(1<<SFlag) |(1<<CFlag)\r
2347 .hword (0xAF<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2348 .hword (0xB0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2349 .hword (0xB1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2350 .hword (0xB2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2351 .hword (0xB3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2352 .hword (0xB4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2353 .hword (0xB5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2354 .hword (0xB6<<8)|(1<<SFlag) |(1<<CFlag)\r
2355 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2356 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2357 .hword (0xB9<<8)|(1<<SFlag) |(1<<CFlag)\r
2358 .hword (0xBA<<8)|(1<<SFlag) |(1<<CFlag)\r
2359 .hword (0xBB<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2360 .hword (0xBC<<8)|(1<<SFlag) |(1<<CFlag)\r
2361 .hword (0xBD<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2362 .hword (0xBE<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2363 .hword (0xBF<<8)|(1<<SFlag) |(1<<CFlag)\r
2364 .hword (0xC0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2365 .hword (0xC1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2366 .hword (0xC2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2367 .hword (0xC3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2368 .hword (0xC4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2369 .hword (0xC5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2370 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2371 .hword (0xC7<<8)|(1<<SFlag) |(1<<CFlag)\r
2372 .hword (0xC8<<8)|(1<<SFlag) |(1<<CFlag)\r
2373 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2374 .hword (0xCA<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2375 .hword (0xCB<<8)|(1<<SFlag) |(1<<CFlag)\r
2376 .hword (0xCC<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2377 .hword (0xCD<<8)|(1<<SFlag) |(1<<CFlag)\r
2378 .hword (0xCE<<8)|(1<<SFlag) |(1<<CFlag)\r
2379 .hword (0xCF<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2380 .hword (0xD0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2381 .hword (0xD1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2382 .hword (0xD2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2383 .hword (0xD3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2384 .hword (0xD4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2385 .hword (0xD5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2386 .hword (0xD6<<8)|(1<<SFlag) |(1<<CFlag)\r
2387 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2388 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2389 .hword (0xD9<<8)|(1<<SFlag) |(1<<CFlag)\r
2390 .hword (0xDA<<8)|(1<<SFlag) |(1<<CFlag)\r
2391 .hword (0xDB<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2392 .hword (0xDC<<8)|(1<<SFlag) |(1<<CFlag)\r
2393 .hword (0xDD<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2394 .hword (0xDE<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2395 .hword (0xDF<<8)|(1<<SFlag) |(1<<CFlag)\r
2396 .hword (0xE0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2397 .hword (0xE1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2398 .hword (0xE2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2399 .hword (0xE3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2400 .hword (0xE4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2401 .hword (0xE5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2402 .hword (0xE6<<8)|(1<<SFlag) |(1<<CFlag)\r
2403 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2404 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2405 .hword (0xE9<<8)|(1<<SFlag) |(1<<CFlag)\r
2406 .hword (0xEA<<8)|(1<<SFlag) |(1<<CFlag)\r
2407 .hword (0xEB<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2408 .hword (0xEC<<8)|(1<<SFlag) |(1<<CFlag)\r
2409 .hword (0xED<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2410 .hword (0xEE<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2411 .hword (0xEF<<8)|(1<<SFlag) |(1<<CFlag)\r
2412 .hword (0xF0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2413 .hword (0xF1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2414 .hword (0xF2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2415 .hword (0xF3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2416 .hword (0xF4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2417 .hword (0xF5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2418 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2419 .hword (0xF7<<8)|(1<<SFlag) |(1<<CFlag)\r
2420 .hword (0xF8<<8)|(1<<SFlag) |(1<<CFlag)\r
2421 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2422 .hword (0xFA<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2423 .hword (0xFB<<8)|(1<<SFlag) |(1<<CFlag)\r
2424 .hword (0xFC<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2425 .hword (0xFD<<8)|(1<<SFlag) |(1<<CFlag)\r
2426 .hword (0xFE<<8)|(1<<SFlag) |(1<<CFlag)\r
2427 .hword (0xFF<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2428 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2429 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
2430 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
2431 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2432 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
2433 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2434 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
2435 .hword (0x07<<8) |(1<<CFlag)\r
2436 .hword (0x08<<8) |(1<<CFlag)\r
2437 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
2438 .hword (0x0A<<8) |(1<<VFlag) |(1<<CFlag)\r
2439 .hword (0x0B<<8) |(1<<CFlag)\r
2440 .hword (0x0C<<8) |(1<<VFlag) |(1<<CFlag)\r
2441 .hword (0x0D<<8) |(1<<CFlag)\r
2442 .hword (0x0E<<8) |(1<<CFlag)\r
2443 .hword (0x0F<<8) |(1<<VFlag) |(1<<CFlag)\r
2444 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
2445 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2446 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2447 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
2448 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2449 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
2450 .hword (0x16<<8) |(1<<CFlag)\r
2451 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
2452 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
2453 .hword (0x19<<8) |(1<<CFlag)\r
2454 .hword (0x1A<<8) |(1<<CFlag)\r
2455 .hword (0x1B<<8) |(1<<VFlag) |(1<<CFlag)\r
2456 .hword (0x1C<<8) |(1<<CFlag)\r
2457 .hword (0x1D<<8) |(1<<VFlag) |(1<<CFlag)\r
2458 .hword (0x1E<<8) |(1<<VFlag) |(1<<CFlag)\r
2459 .hword (0x1F<<8) |(1<<CFlag)\r
2460 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
2461 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2462 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2463 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
2464 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2465 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
2466 .hword (0x26<<8) |(1<<CFlag)\r
2467 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
2468 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
2469 .hword (0x29<<8) |(1<<CFlag)\r
2470 .hword (0x2A<<8) |(1<<CFlag)\r
2471 .hword (0x2B<<8) |(1<<VFlag) |(1<<CFlag)\r
2472 .hword (0x2C<<8) |(1<<CFlag)\r
2473 .hword (0x2D<<8) |(1<<VFlag) |(1<<CFlag)\r
2474 .hword (0x2E<<8) |(1<<VFlag) |(1<<CFlag)\r
2475 .hword (0x2F<<8) |(1<<CFlag)\r
2476 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2477 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
2478 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
2479 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2480 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
2481 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2482 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
2483 .hword (0x37<<8) |(1<<CFlag)\r
2484 .hword (0x38<<8) |(1<<CFlag)\r
2485 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
2486 .hword (0x3A<<8) |(1<<VFlag) |(1<<CFlag)\r
2487 .hword (0x3B<<8) |(1<<CFlag)\r
2488 .hword (0x3C<<8) |(1<<VFlag) |(1<<CFlag)\r
2489 .hword (0x3D<<8) |(1<<CFlag)\r
2490 .hword (0x3E<<8) |(1<<CFlag)\r
2491 .hword (0x3F<<8) |(1<<VFlag) |(1<<CFlag)\r
2492 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
2493 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2494 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2495 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
2496 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2497 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
2498 .hword (0x46<<8) |(1<<CFlag)\r
2499 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
2500 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
2501 .hword (0x49<<8) |(1<<CFlag)\r
2502 .hword (0x4A<<8) |(1<<CFlag)\r
2503 .hword (0x4B<<8) |(1<<VFlag) |(1<<CFlag)\r
2504 .hword (0x4C<<8) |(1<<CFlag)\r
2505 .hword (0x4D<<8) |(1<<VFlag) |(1<<CFlag)\r
2506 .hword (0x4E<<8) |(1<<VFlag) |(1<<CFlag)\r
2507 .hword (0x4F<<8) |(1<<CFlag)\r
2508 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2509 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
2510 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
2511 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2512 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
2513 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2514 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
2515 .hword (0x57<<8) |(1<<CFlag)\r
2516 .hword (0x58<<8) |(1<<CFlag)\r
2517 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
2518 .hword (0x5A<<8) |(1<<VFlag) |(1<<CFlag)\r
2519 .hword (0x5B<<8) |(1<<CFlag)\r
2520 .hword (0x5C<<8) |(1<<VFlag) |(1<<CFlag)\r
2521 .hword (0x5D<<8) |(1<<CFlag)\r
2522 .hword (0x5E<<8) |(1<<CFlag)\r
2523 .hword (0x5F<<8) |(1<<VFlag) |(1<<CFlag)\r
2524 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2525 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
2526 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
2527 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2528 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
2529 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2530 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag) \r
2531 .hword (0x01<<8) |(1<<NFlag) \r
2532 .hword (0x02<<8) |(1<<NFlag) \r
2533 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag) \r
2534 .hword (0x04<<8) |(1<<NFlag) \r
2535 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag) \r
2536 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag) \r
2537 .hword (0x07<<8) |(1<<NFlag) \r
2538 .hword (0x08<<8) |(1<<NFlag) \r
2539 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag) \r
2540 .hword (0x04<<8) |(1<<NFlag) \r
2541 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag) \r
2542 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag) \r
2543 .hword (0x07<<8) |(1<<NFlag) \r
2544 .hword (0x08<<8) |(1<<NFlag) \r
2545 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag) \r
2546 .hword (0x10<<8) |(1<<NFlag) \r
2547 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag) \r
2548 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag) \r
2549 .hword (0x13<<8) |(1<<NFlag) \r
2550 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag) \r
2551 .hword (0x15<<8) |(1<<NFlag) \r
2552 .hword (0x16<<8) |(1<<NFlag) \r
2553 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag) \r
2554 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag) \r
2555 .hword (0x19<<8) |(1<<NFlag) \r
2556 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag) \r
2557 .hword (0x15<<8) |(1<<NFlag) \r
2558 .hword (0x16<<8) |(1<<NFlag) \r
2559 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag) \r
2560 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag) \r
2561 .hword (0x19<<8) |(1<<NFlag) \r
2562 .hword (0x20<<8) |(1<<NFlag) \r
2563 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag) \r
2564 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag) \r
2565 .hword (0x23<<8) |(1<<NFlag) \r
2566 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag) \r
2567 .hword (0x25<<8) |(1<<NFlag) \r
2568 .hword (0x26<<8) |(1<<NFlag) \r
2569 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag) \r
2570 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag) \r
2571 .hword (0x29<<8) |(1<<NFlag) \r
2572 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag) \r
2573 .hword (0x25<<8) |(1<<NFlag) \r
2574 .hword (0x26<<8) |(1<<NFlag) \r
2575 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag) \r
2576 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag) \r
2577 .hword (0x29<<8) |(1<<NFlag) \r
2578 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag) \r
2579 .hword (0x31<<8) |(1<<NFlag) \r
2580 .hword (0x32<<8) |(1<<NFlag) \r
2581 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag) \r
2582 .hword (0x34<<8) |(1<<NFlag) \r
2583 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag) \r
2584 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag) \r
2585 .hword (0x37<<8) |(1<<NFlag) \r
2586 .hword (0x38<<8) |(1<<NFlag) \r
2587 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag) \r
2588 .hword (0x34<<8) |(1<<NFlag) \r
2589 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag) \r
2590 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag) \r
2591 .hword (0x37<<8) |(1<<NFlag) \r
2592 .hword (0x38<<8) |(1<<NFlag) \r
2593 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag) \r
2594 .hword (0x40<<8) |(1<<NFlag) \r
2595 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag) \r
2596 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag) \r
2597 .hword (0x43<<8) |(1<<NFlag) \r
2598 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag) \r
2599 .hword (0x45<<8) |(1<<NFlag) \r
2600 .hword (0x46<<8) |(1<<NFlag) \r
2601 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag) \r
2602 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag) \r
2603 .hword (0x49<<8) |(1<<NFlag) \r
2604 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag) \r
2605 .hword (0x45<<8) |(1<<NFlag) \r
2606 .hword (0x46<<8) |(1<<NFlag) \r
2607 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag) \r
2608 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag) \r
2609 .hword (0x49<<8) |(1<<NFlag) \r
2610 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag) \r
2611 .hword (0x51<<8) |(1<<NFlag) \r
2612 .hword (0x52<<8) |(1<<NFlag) \r
2613 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag) \r
2614 .hword (0x54<<8) |(1<<NFlag) \r
2615 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag) \r
2616 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag) \r
2617 .hword (0x57<<8) |(1<<NFlag) \r
2618 .hword (0x58<<8) |(1<<NFlag) \r
2619 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag) \r
2620 .hword (0x54<<8) |(1<<NFlag) \r
2621 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag) \r
2622 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag) \r
2623 .hword (0x57<<8) |(1<<NFlag) \r
2624 .hword (0x58<<8) |(1<<NFlag) \r
2625 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag) \r
2626 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag) \r
2627 .hword (0x61<<8) |(1<<NFlag) \r
2628 .hword (0x62<<8) |(1<<NFlag) \r
2629 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag) \r
2630 .hword (0x64<<8) |(1<<NFlag) \r
2631 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag) \r
2632 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag) \r
2633 .hword (0x67<<8) |(1<<NFlag) \r
2634 .hword (0x68<<8) |(1<<NFlag) \r
2635 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag) \r
2636 .hword (0x64<<8) |(1<<NFlag) \r
2637 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag) \r
2638 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag) \r
2639 .hword (0x67<<8) |(1<<NFlag) \r
2640 .hword (0x68<<8) |(1<<NFlag) \r
2641 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag) \r
2642 .hword (0x70<<8) |(1<<NFlag) \r
2643 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag) \r
2644 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag) \r
2645 .hword (0x73<<8) |(1<<NFlag) \r
2646 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag) \r
2647 .hword (0x75<<8) |(1<<NFlag) \r
2648 .hword (0x76<<8) |(1<<NFlag) \r
2649 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag) \r
2650 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag) \r
2651 .hword (0x79<<8) |(1<<NFlag) \r
2652 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag) \r
2653 .hword (0x75<<8) |(1<<NFlag) \r
2654 .hword (0x76<<8) |(1<<NFlag) \r
2655 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag) \r
2656 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag) \r
2657 .hword (0x79<<8) |(1<<NFlag) \r
2658 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag) \r
2659 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2660 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2661 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag) \r
2662 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2663 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag) \r
2664 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag) \r
2665 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2666 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2667 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag) \r
2668 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2669 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag) \r
2670 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag) \r
2671 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2672 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2673 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag) \r
2674 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2675 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag) \r
2676 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag) \r
2677 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2678 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag) \r
2679 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2680 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2681 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag) \r
2682 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag) \r
2683 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2684 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
2685 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2686 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2687 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
2688 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
2689 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2690 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
2691 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2692 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2693 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
2694 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2695 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
2696 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
2697 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2698 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2699 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
2700 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2701 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
2702 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
2703 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2704 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2705 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
2706 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2707 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
2708 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
2709 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2710 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
2711 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2712 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2713 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
2714 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
2715 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2716 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
2717 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2718 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2719 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
2720 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
2721 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2722 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2723 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
2724 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
2725 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2726 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
2727 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2728 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2729 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
2730 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
2731 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2732 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
2733 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2734 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2735 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
2736 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
2737 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2738 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
2739 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2740 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2741 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
2742 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2743 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
2744 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
2745 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2746 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2747 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
2748 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2749 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
2750 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
2751 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2752 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2753 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
2754 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2755 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2756 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2757 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2758 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2759 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2760 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2761 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2762 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2763 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2764 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2765 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2766 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2767 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2768 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2769 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2770 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2771 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2772 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2773 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2774 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2775 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2776 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2777 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2778 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2779 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2780 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2781 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2782 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2783 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2784 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2785 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2786 .hword (0xA0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2787 .hword (0xA1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2788 .hword (0xA2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2789 .hword (0xA3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2790 .hword (0xA4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2791 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2792 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2793 .hword (0xA7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2794 .hword (0xA8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2795 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2796 .hword (0xA4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2797 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2798 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2799 .hword (0xA7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2800 .hword (0xA8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2801 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2802 .hword (0xB0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2803 .hword (0xB1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2804 .hword (0xB2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2805 .hword (0xB3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2806 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2807 .hword (0xB5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2808 .hword (0xB6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2809 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2810 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2811 .hword (0xB9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2812 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2813 .hword (0xB5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2814 .hword (0xB6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2815 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2816 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2817 .hword (0xB9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2818 .hword (0xC0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2819 .hword (0xC1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2820 .hword (0xC2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2821 .hword (0xC3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2822 .hword (0xC4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2823 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2824 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2825 .hword (0xC7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2826 .hword (0xC8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2827 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2828 .hword (0xC4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2829 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2830 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2831 .hword (0xC7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2832 .hword (0xC8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2833 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2834 .hword (0xD0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2835 .hword (0xD1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2836 .hword (0xD2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2837 .hword (0xD3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2838 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2839 .hword (0xD5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2840 .hword (0xD6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2841 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2842 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2843 .hword (0xD9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2844 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2845 .hword (0xD5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2846 .hword (0xD6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2847 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2848 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2849 .hword (0xD9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2850 .hword (0xE0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2851 .hword (0xE1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2852 .hword (0xE2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2853 .hword (0xE3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2854 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2855 .hword (0xE5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2856 .hword (0xE6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2857 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2858 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2859 .hword (0xE9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2860 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2861 .hword (0xE5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2862 .hword (0xE6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2863 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2864 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2865 .hword (0xE9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2866 .hword (0xF0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2867 .hword (0xF1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2868 .hword (0xF2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2869 .hword (0xF3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2870 .hword (0xF4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2871 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2872 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2873 .hword (0xF7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2874 .hword (0xF8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2875 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2876 .hword (0xF4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2877 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2878 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2879 .hword (0xF7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2880 .hword (0xF8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2881 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2882 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2883 .hword (0x01<<8) |(1<<NFlag)|(1<<CFlag)\r
2884 .hword (0x02<<8) |(1<<NFlag)|(1<<CFlag)\r
2885 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2886 .hword (0x04<<8) |(1<<NFlag)|(1<<CFlag)\r
2887 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2888 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2889 .hword (0x07<<8) |(1<<NFlag)|(1<<CFlag)\r
2890 .hword (0x08<<8) |(1<<NFlag)|(1<<CFlag)\r
2891 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2892 .hword (0x04<<8) |(1<<NFlag)|(1<<CFlag)\r
2893 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2894 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2895 .hword (0x07<<8) |(1<<NFlag)|(1<<CFlag)\r
2896 .hword (0x08<<8) |(1<<NFlag)|(1<<CFlag)\r
2897 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2898 .hword (0x10<<8) |(1<<NFlag)|(1<<CFlag)\r
2899 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2900 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2901 .hword (0x13<<8) |(1<<NFlag)|(1<<CFlag)\r
2902 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2903 .hword (0x15<<8) |(1<<NFlag)|(1<<CFlag)\r
2904 .hword (0x16<<8) |(1<<NFlag)|(1<<CFlag)\r
2905 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2906 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2907 .hword (0x19<<8) |(1<<NFlag)|(1<<CFlag)\r
2908 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2909 .hword (0x15<<8) |(1<<NFlag)|(1<<CFlag)\r
2910 .hword (0x16<<8) |(1<<NFlag)|(1<<CFlag)\r
2911 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2912 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2913 .hword (0x19<<8) |(1<<NFlag)|(1<<CFlag)\r
2914 .hword (0x20<<8) |(1<<NFlag)|(1<<CFlag)\r
2915 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2916 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2917 .hword (0x23<<8) |(1<<NFlag)|(1<<CFlag)\r
2918 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2919 .hword (0x25<<8) |(1<<NFlag)|(1<<CFlag)\r
2920 .hword (0x26<<8) |(1<<NFlag)|(1<<CFlag)\r
2921 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2922 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2923 .hword (0x29<<8) |(1<<NFlag)|(1<<CFlag)\r
2924 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2925 .hword (0x25<<8) |(1<<NFlag)|(1<<CFlag)\r
2926 .hword (0x26<<8) |(1<<NFlag)|(1<<CFlag)\r
2927 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2928 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2929 .hword (0x29<<8) |(1<<NFlag)|(1<<CFlag)\r
2930 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2931 .hword (0x31<<8) |(1<<NFlag)|(1<<CFlag)\r
2932 .hword (0x32<<8) |(1<<NFlag)|(1<<CFlag)\r
2933 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2934 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
2935 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2936 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2937 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
2938 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
2939 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2940 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
2941 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2942 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2943 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
2944 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
2945 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2946 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
2947 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2948 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2949 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
2950 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2951 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
2952 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
2953 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2954 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2955 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
2956 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2957 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
2958 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
2959 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2960 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2961 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
2962 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2963 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
2964 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
2965 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2966 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
2967 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2968 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2969 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
2970 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
2971 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2972 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
2973 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2974 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2975 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
2976 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
2977 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2978 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2979 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
2980 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
2981 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2982 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
2983 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2984 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2985 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
2986 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
2987 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2988 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
2989 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2990 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2991 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
2992 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
2993 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2994 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
2995 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2996 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2997 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
2998 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2999 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3000 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3001 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3002 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3003 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3004 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3005 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3006 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3007 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3008 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3009 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3010 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3011 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3012 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3013 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3014 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3015 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3016 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3017 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3018 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3019 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3020 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3021 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3022 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3023 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3024 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3025 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3026 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3027 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3028 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3029 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3030 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3031 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3032 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3033 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3034 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3035 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3036 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3037 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3038 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3039 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3040 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3041 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3042 .hword (0xFA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3043 .hword (0xFB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3044 .hword (0xFC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3045 .hword (0xFD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3046 .hword (0xFE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3047 .hword (0xFF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3048 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag) \r
3049 .hword (0x01<<8) |(1<<NFlag) \r
3050 .hword (0x02<<8) |(1<<NFlag) \r
3051 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag) \r
3052 .hword (0x04<<8) |(1<<NFlag) \r
3053 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag) \r
3054 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag) \r
3055 .hword (0x07<<8) |(1<<NFlag) \r
3056 .hword (0x08<<8) |(1<<NFlag) \r
3057 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag) \r
3058 .hword (0x0A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3059 .hword (0x0B<<8) |(1<<HFlag) |(1<<NFlag) \r
3060 .hword (0x0C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3061 .hword (0x0D<<8) |(1<<HFlag) |(1<<NFlag) \r
3062 .hword (0x0E<<8) |(1<<HFlag) |(1<<NFlag) \r
3063 .hword (0x0F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3064 .hword (0x10<<8) |(1<<NFlag) \r
3065 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag) \r
3066 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag) \r
3067 .hword (0x13<<8) |(1<<NFlag) \r
3068 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag) \r
3069 .hword (0x15<<8) |(1<<NFlag) \r
3070 .hword (0x16<<8) |(1<<NFlag) \r
3071 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag) \r
3072 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag) \r
3073 .hword (0x19<<8) |(1<<NFlag) \r
3074 .hword (0x1A<<8) |(1<<HFlag) |(1<<NFlag) \r
3075 .hword (0x1B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3076 .hword (0x1C<<8) |(1<<HFlag) |(1<<NFlag) \r
3077 .hword (0x1D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3078 .hword (0x1E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3079 .hword (0x1F<<8) |(1<<HFlag) |(1<<NFlag) \r
3080 .hword (0x20<<8) |(1<<NFlag) \r
3081 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag) \r
3082 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag) \r
3083 .hword (0x23<<8) |(1<<NFlag) \r
3084 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag) \r
3085 .hword (0x25<<8) |(1<<NFlag) \r
3086 .hword (0x26<<8) |(1<<NFlag) \r
3087 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag) \r
3088 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag) \r
3089 .hword (0x29<<8) |(1<<NFlag) \r
3090 .hword (0x2A<<8) |(1<<HFlag) |(1<<NFlag) \r
3091 .hword (0x2B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3092 .hword (0x2C<<8) |(1<<HFlag) |(1<<NFlag) \r
3093 .hword (0x2D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3094 .hword (0x2E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3095 .hword (0x2F<<8) |(1<<HFlag) |(1<<NFlag) \r
3096 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag) \r
3097 .hword (0x31<<8) |(1<<NFlag) \r
3098 .hword (0x32<<8) |(1<<NFlag) \r
3099 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag) \r
3100 .hword (0x34<<8) |(1<<NFlag) \r
3101 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag) \r
3102 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag) \r
3103 .hword (0x37<<8) |(1<<NFlag) \r
3104 .hword (0x38<<8) |(1<<NFlag) \r
3105 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag) \r
3106 .hword (0x3A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3107 .hword (0x3B<<8) |(1<<HFlag) |(1<<NFlag) \r
3108 .hword (0x3C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3109 .hword (0x3D<<8) |(1<<HFlag) |(1<<NFlag) \r
3110 .hword (0x3E<<8) |(1<<HFlag) |(1<<NFlag) \r
3111 .hword (0x3F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3112 .hword (0x40<<8) |(1<<NFlag) \r
3113 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag) \r
3114 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag) \r
3115 .hword (0x43<<8) |(1<<NFlag) \r
3116 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag) \r
3117 .hword (0x45<<8) |(1<<NFlag) \r
3118 .hword (0x46<<8) |(1<<NFlag) \r
3119 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag) \r
3120 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag) \r
3121 .hword (0x49<<8) |(1<<NFlag) \r
3122 .hword (0x4A<<8) |(1<<HFlag) |(1<<NFlag) \r
3123 .hword (0x4B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3124 .hword (0x4C<<8) |(1<<HFlag) |(1<<NFlag) \r
3125 .hword (0x4D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3126 .hword (0x4E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3127 .hword (0x4F<<8) |(1<<HFlag) |(1<<NFlag) \r
3128 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag) \r
3129 .hword (0x51<<8) |(1<<NFlag) \r
3130 .hword (0x52<<8) |(1<<NFlag) \r
3131 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag) \r
3132 .hword (0x54<<8) |(1<<NFlag) \r
3133 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag) \r
3134 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag) \r
3135 .hword (0x57<<8) |(1<<NFlag) \r
3136 .hword (0x58<<8) |(1<<NFlag) \r
3137 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag) \r
3138 .hword (0x5A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3139 .hword (0x5B<<8) |(1<<HFlag) |(1<<NFlag) \r
3140 .hword (0x5C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3141 .hword (0x5D<<8) |(1<<HFlag) |(1<<NFlag) \r
3142 .hword (0x5E<<8) |(1<<HFlag) |(1<<NFlag) \r
3143 .hword (0x5F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3144 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag) \r
3145 .hword (0x61<<8) |(1<<NFlag) \r
3146 .hword (0x62<<8) |(1<<NFlag) \r
3147 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag) \r
3148 .hword (0x64<<8) |(1<<NFlag) \r
3149 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag) \r
3150 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag) \r
3151 .hword (0x67<<8) |(1<<NFlag) \r
3152 .hword (0x68<<8) |(1<<NFlag) \r
3153 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag) \r
3154 .hword (0x6A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3155 .hword (0x6B<<8) |(1<<HFlag) |(1<<NFlag) \r
3156 .hword (0x6C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3157 .hword (0x6D<<8) |(1<<HFlag) |(1<<NFlag) \r
3158 .hword (0x6E<<8) |(1<<HFlag) |(1<<NFlag) \r
3159 .hword (0x6F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3160 .hword (0x70<<8) |(1<<NFlag) \r
3161 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag) \r
3162 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag) \r
3163 .hword (0x73<<8) |(1<<NFlag) \r
3164 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag) \r
3165 .hword (0x75<<8) |(1<<NFlag) \r
3166 .hword (0x76<<8) |(1<<NFlag) \r
3167 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag) \r
3168 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag) \r
3169 .hword (0x79<<8) |(1<<NFlag) \r
3170 .hword (0x7A<<8) |(1<<HFlag) |(1<<NFlag) \r
3171 .hword (0x7B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3172 .hword (0x7C<<8) |(1<<HFlag) |(1<<NFlag) \r
3173 .hword (0x7D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3174 .hword (0x7E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3175 .hword (0x7F<<8) |(1<<HFlag) |(1<<NFlag) \r
3176 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag) \r
3177 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3178 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3179 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag) \r
3180 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3181 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag) \r
3182 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag) \r
3183 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3184 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3185 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag) \r
3186 .hword (0x8A<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3187 .hword (0x8B<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3188 .hword (0x8C<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3189 .hword (0x8D<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3190 .hword (0x8E<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3191 .hword (0x8F<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3192 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3193 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag) \r
3194 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag) \r
3195 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3196 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
3197 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3198 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3199 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
3200 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
3201 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3202 .hword (0x3A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3203 .hword (0x3B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3204 .hword (0x3C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3205 .hword (0x3D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3206 .hword (0x3E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3207 .hword (0x3F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3208 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
3209 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3210 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3211 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
3212 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3213 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
3214 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
3215 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3216 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3217 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
3218 .hword (0x4A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3219 .hword (0x4B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3220 .hword (0x4C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3221 .hword (0x4D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3222 .hword (0x4E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3223 .hword (0x4F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3224 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3225 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
3226 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
3227 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3228 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
3229 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3230 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3231 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
3232 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
3233 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3234 .hword (0x5A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3235 .hword (0x5B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3236 .hword (0x5C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3237 .hword (0x5D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3238 .hword (0x5E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3239 .hword (0x5F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3240 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3241 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
3242 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
3243 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3244 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
3245 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3246 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3247 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
3248 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
3249 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3250 .hword (0x6A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3251 .hword (0x6B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3252 .hword (0x6C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3253 .hword (0x6D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3254 .hword (0x6E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3255 .hword (0x6F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3256 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
3257 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3258 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3259 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
3260 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3261 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3262 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3263 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3264 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3265 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3266 .hword (0x7A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3267 .hword (0x7B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3268 .hword (0x7C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3269 .hword (0x7D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3270 .hword (0x7E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3271 .hword (0x7F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3272 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3273 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3274 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3275 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3276 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3277 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3278 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3279 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3280 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3281 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3282 .hword (0x8A<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3283 .hword (0x8B<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3284 .hword (0x8C<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3285 .hword (0x8D<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3286 .hword (0x8E<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3287 .hword (0x8F<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3288 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3289 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3290 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3291 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3292 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3293 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3294 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3295 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3296 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3297 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3298 .hword (0x9A<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3299 .hword (0x9B<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3300 .hword (0x9C<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3301 .hword (0x9D<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3302 .hword (0x9E<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3303 .hword (0x9F<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3304 .hword (0xA0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3305 .hword (0xA1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3306 .hword (0xA2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3307 .hword (0xA3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3308 .hword (0xA4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3309 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3310 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3311 .hword (0xA7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3312 .hword (0xA8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3313 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3314 .hword (0xAA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3315 .hword (0xAB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3316 .hword (0xAC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3317 .hword (0xAD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3318 .hword (0xAE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3319 .hword (0xAF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3320 .hword (0xB0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3321 .hword (0xB1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3322 .hword (0xB2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3323 .hword (0xB3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3324 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3325 .hword (0xB5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3326 .hword (0xB6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3327 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3328 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3329 .hword (0xB9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3330 .hword (0xBA<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3331 .hword (0xBB<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3332 .hword (0xBC<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3333 .hword (0xBD<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3334 .hword (0xBE<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3335 .hword (0xBF<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3336 .hword (0xC0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3337 .hword (0xC1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3338 .hword (0xC2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3339 .hword (0xC3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3340 .hword (0xC4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3341 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3342 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3343 .hword (0xC7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3344 .hword (0xC8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3345 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3346 .hword (0xCA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3347 .hword (0xCB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3348 .hword (0xCC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3349 .hword (0xCD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3350 .hword (0xCE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3351 .hword (0xCF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3352 .hword (0xD0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3353 .hword (0xD1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3354 .hword (0xD2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3355 .hword (0xD3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3356 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3357 .hword (0xD5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3358 .hword (0xD6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3359 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3360 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3361 .hword (0xD9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3362 .hword (0xDA<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3363 .hword (0xDB<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3364 .hword (0xDC<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3365 .hword (0xDD<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3366 .hword (0xDE<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3367 .hword (0xDF<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3368 .hword (0xE0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3369 .hword (0xE1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3370 .hword (0xE2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3371 .hword (0xE3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3372 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3373 .hword (0xE5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3374 .hword (0xE6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3375 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3376 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3377 .hword (0xE9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3378 .hword (0xEA<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3379 .hword (0xEB<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3380 .hword (0xEC<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3381 .hword (0xED<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3382 .hword (0xEE<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3383 .hword (0xEF<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3384 .hword (0xF0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3385 .hword (0xF1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3386 .hword (0xF2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3387 .hword (0xF3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3388 .hword (0xF4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3389 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3390 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3391 .hword (0xF7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3392 .hword (0xF8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3393 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3394 .hword (0xFA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3395 .hword (0xFB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3396 .hword (0xFC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3397 .hword (0xFD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3398 .hword (0xFE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3399 .hword (0xFF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3400 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3401 .hword (0x01<<8) |(1<<NFlag)|(1<<CFlag)\r
3402 .hword (0x02<<8) |(1<<NFlag)|(1<<CFlag)\r
3403 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3404 .hword (0x04<<8) |(1<<NFlag)|(1<<CFlag)\r
3405 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3406 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3407 .hword (0x07<<8) |(1<<NFlag)|(1<<CFlag)\r
3408 .hword (0x08<<8) |(1<<NFlag)|(1<<CFlag)\r
3409 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3410 .hword (0x0A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3411 .hword (0x0B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3412 .hword (0x0C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3413 .hword (0x0D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3414 .hword (0x0E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3415 .hword (0x0F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3416 .hword (0x10<<8) |(1<<NFlag)|(1<<CFlag)\r
3417 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3418 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3419 .hword (0x13<<8) |(1<<NFlag)|(1<<CFlag)\r
3420 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3421 .hword (0x15<<8) |(1<<NFlag)|(1<<CFlag)\r
3422 .hword (0x16<<8) |(1<<NFlag)|(1<<CFlag)\r
3423 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3424 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3425 .hword (0x19<<8) |(1<<NFlag)|(1<<CFlag)\r
3426 .hword (0x1A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3427 .hword (0x1B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3428 .hword (0x1C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3429 .hword (0x1D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3430 .hword (0x1E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3431 .hword (0x1F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3432 .hword (0x20<<8) |(1<<NFlag)|(1<<CFlag)\r
3433 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3434 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3435 .hword (0x23<<8) |(1<<NFlag)|(1<<CFlag)\r
3436 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3437 .hword (0x25<<8) |(1<<NFlag)|(1<<CFlag)\r
3438 .hword (0x26<<8) |(1<<NFlag)|(1<<CFlag)\r
3439 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3440 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3441 .hword (0x29<<8) |(1<<NFlag)|(1<<CFlag)\r
3442 .hword (0x2A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3443 .hword (0x2B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3444 .hword (0x2C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3445 .hword (0x2D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3446 .hword (0x2E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3447 .hword (0x2F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3448 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3449 .hword (0x31<<8) |(1<<NFlag)|(1<<CFlag)\r
3450 .hword (0x32<<8) |(1<<NFlag)|(1<<CFlag)\r
3451 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3452 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
3453 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3454 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3455 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
3456 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
3457 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3458 .hword (0x3A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3459 .hword (0x3B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3460 .hword (0x3C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3461 .hword (0x3D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3462 .hword (0x3E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3463 .hword (0x3F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3464 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
3465 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3466 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3467 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
3468 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3469 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
3470 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
3471 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3472 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3473 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
3474 .hword (0x4A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3475 .hword (0x4B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3476 .hword (0x4C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3477 .hword (0x4D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3478 .hword (0x4E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3479 .hword (0x4F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3480 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3481 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
3482 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
3483 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3484 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
3485 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3486 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3487 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
3488 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
3489 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3490 .hword (0x5A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3491 .hword (0x5B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3492 .hword (0x5C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3493 .hword (0x5D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3494 .hword (0x5E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3495 .hword (0x5F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3496 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3497 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
3498 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
3499 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3500 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
3501 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3502 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3503 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
3504 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
3505 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3506 .hword (0x6A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3507 .hword (0x6B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3508 .hword (0x6C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3509 .hword (0x6D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3510 .hword (0x6E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3511 .hword (0x6F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3512 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
3513 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3514 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3515 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
3516 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3517 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3518 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3519 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3520 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3521 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3522 .hword (0x7A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3523 .hword (0x7B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3524 .hword (0x7C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3525 .hword (0x7D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3526 .hword (0x7E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3527 .hword (0x7F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3528 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3529 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3530 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3531 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3532 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3533 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3534 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3535 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3536 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3537 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3538 .hword (0x8A<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3539 .hword (0x8B<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3540 .hword (0x8C<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3541 .hword (0x8D<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3542 .hword (0x8E<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3543 .hword (0x8F<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3544 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3545 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3546 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3547 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3548 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3549 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3550 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3551 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3552 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3553 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3554 \r
3555.align 4\r
3556\r
3557AF_Z80: .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 0\r
3558 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 1\r
3559 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 2\r
3560 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 3\r
3561 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 4\r
3562 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 5\r
3563 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 6\r
3564 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 7\r
3565 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 8\r
3566 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 9\r
3567 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 10\r
3568 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 11\r
3569 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 12\r
3570 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 13\r
3571 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 14\r
3572 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 15\r
3573 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 16\r
3574 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 17\r
3575 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 18\r
3576 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 19\r
3577 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 20\r
3578 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 21\r
3579 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 22\r
3580 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 23\r
3581 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 24\r
3582 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 25\r
3583 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 26\r
3584 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 27\r
3585 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 28\r
3586 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 29\r
3587 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 30\r
3588 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 31\r
3589 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 32\r
3590 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 33\r
3591 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 34\r
3592 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 35\r
3593 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 36\r
3594 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 37\r
3595 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 38\r
3596 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 39\r
3597 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 40\r
3598 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 41\r
3599 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 42\r
3600 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 43\r
3601 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 44\r
3602 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 45\r
3603 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 46\r
3604 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 47\r
3605 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 48\r
3606 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 49\r
3607 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 50\r
3608 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 51\r
3609 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 52\r
3610 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 53\r
3611 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 54\r
3612 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 55\r
3613 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 56\r
3614 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 57\r
3615 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 58\r
3616 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 59\r
3617 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 60\r
3618 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 61\r
3619 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 62\r
3620 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 63\r
3621 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 64\r
3622 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 65\r
3623 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 66\r
3624 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 67\r
3625 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 68\r
3626 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 69\r
3627 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 70\r
3628 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 71\r
3629 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 72\r
3630 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 73\r
3631 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 74\r
3632 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 75\r
3633 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 76\r
3634 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 77\r
3635 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 78\r
3636 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 79\r
3637 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 80\r
3638 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 81\r
3639 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 82\r
3640 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 83\r
3641 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 84\r
3642 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 85\r
3643 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 86\r
3644 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 87\r
3645 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 88\r
3646 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 89\r
3647 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 90\r
3648 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 91\r
3649 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 92\r
3650 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 93\r
3651 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 94\r
3652 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 95\r
3653 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 96\r
3654 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 97\r
3655 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 98\r
3656 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 99\r
3657 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 100\r
3658 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 101\r
3659 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 102\r
3660 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 103\r
3661 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 104\r
3662 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 105\r
3663 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 106\r
3664 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 107\r
3665 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 108\r
3666 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 109\r
3667 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 110\r
3668 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 111\r
3669 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 112\r
3670 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 113\r
3671 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 114\r
3672 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 115\r
3673 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 116\r
3674 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 117\r
3675 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 118\r
3676 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 119\r
3677 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 120\r
3678 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 121\r
3679 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 122\r
3680 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 123\r
3681 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 124\r
3682 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 125\r
3683 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 126\r
3684 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 127\r
3685 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 128\r
3686 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 129\r
3687 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 130\r
3688 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 131\r
3689 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 132\r
3690 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 133\r
3691 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 134\r
3692 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 135\r
3693 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 136\r
3694 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 137\r
3695 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 138\r
3696 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 139\r
3697 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 140\r
3698 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 141\r
3699 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 142\r
3700 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 143\r
3701 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 144\r
3702 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 145\r
3703 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 146\r
3704 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 147\r
3705 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 148\r
3706 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 149\r
3707 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 150\r
3708 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 151\r
3709 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 152\r
3710 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 153\r
3711 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 154\r
3712 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 155\r
3713 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 156\r
3714 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 157\r
3715 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 158\r
3716 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 159\r
3717 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 160\r
3718 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 161\r
3719 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 162\r
3720 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 163\r
3721 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 164\r
3722 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 165\r
3723 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 166\r
3724 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 167\r
3725 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 168\r
3726 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 169\r
3727 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 170\r
3728 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 171\r
3729 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 172\r
3730 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 173\r
3731 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 174\r
3732 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 175\r
3733 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 176\r
3734 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 177\r
3735 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 178\r
3736 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 179\r
3737 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 180\r
3738 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 181\r
3739 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 182\r
3740 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 183\r
3741 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 184\r
3742 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 185\r
3743 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 186\r
3744 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 187\r
3745 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 188\r
3746 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 189\r
3747 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 190\r
3748 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 191\r
3749 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 192\r
3750 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 193\r
3751 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 194\r
3752 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 195\r
3753 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 196\r
3754 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 197\r
3755 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 198\r
3756 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 199\r
3757 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 200\r
3758 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 201\r
3759 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 202\r
3760 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 203\r
3761 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 204\r
3762 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 205\r
3763 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 206\r
3764 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 207\r
3765 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 208\r
3766 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 209\r
3767 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 210\r
3768 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 211\r
3769 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 212\r
3770 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 213\r
3771 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 214\r
3772 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 215\r
3773 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 216\r
3774 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 217\r
3775 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 218\r
3776 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 219\r
3777 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 220\r
3778 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 221\r
3779 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 222\r
3780 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 223\r
3781 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 224\r
3782 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 225\r
3783 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 226\r
3784 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 227\r
3785 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 228\r
3786 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 229\r
3787 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 230\r
3788 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 231\r
3789 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 232\r
3790 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 233\r
3791 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 234\r
3792 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 235\r
3793 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 236\r
3794 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 237\r
3795 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 238\r
3796 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 239\r
3797 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 240\r
3798 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 241\r
3799 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 242\r
3800 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 243\r
3801 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 244\r
3802 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 245\r
3803 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 246\r
3804 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 247\r
3805 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 248\r
3806 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 249\r
3807 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 250\r
3808 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 251\r
3809 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 252\r
3810 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 253\r
3811 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 254\r
3812 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 255\r
3813\r
3814.align 4\r
3815\r
3816AF_ARM: .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 0\r
3817 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 1\r
3818 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 2\r
3819 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 3\r
3820 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 4\r
3821 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 5\r
3822 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 6\r
3823 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 7\r
3824 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 8\r
3825 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 9\r
3826 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 10\r
3827 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 11\r
3828 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 12\r
3829 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 13\r
3830 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 14\r
3831 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 15\r
3832 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 16\r
3833 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 17\r
3834 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 18\r
3835 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 19\r
3836 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 20\r
3837 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 21\r
3838 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 22\r
3839 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 23\r
3840 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 24\r
3841 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 25\r
3842 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 26\r
3843 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 27\r
3844 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 28\r
3845 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 29\r
3846 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 30\r
3847 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 31\r
3848 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 32\r
3849 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 33\r
3850 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 34\r
3851 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 35\r
3852 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 36\r
3853 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 37\r
3854 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 38\r
3855 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 39\r
3856 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 40\r
3857 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 41\r
3858 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 42\r
3859 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 43\r
3860 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 44\r
3861 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 45\r
3862 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 46\r
3863 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 47\r
3864 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 48\r
3865 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 49\r
3866 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 50\r
3867 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 51\r
3868 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 52\r
3869 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 53\r
3870 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 54\r
3871 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 55\r
3872 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 56\r
3873 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 57\r
3874 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 58\r
3875 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 59\r
3876 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 60\r
3877 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 61\r
3878 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 62\r
3879 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 63\r
3880 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 64\r
3881 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 65\r
3882 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 66\r
3883 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 67\r
3884 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 68\r
3885 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 69\r
3886 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 70\r
3887 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 71\r
3888 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 72\r
3889 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 73\r
3890 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 74\r
3891 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 75\r
3892 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 76\r
3893 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 77\r
3894 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 78\r
3895 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 79\r
3896 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 80\r
3897 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 81\r
3898 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 82\r
3899 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 83\r
3900 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 84\r
3901 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 85\r
3902 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 86\r
3903 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 87\r
3904 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 88\r
3905 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 89\r
3906 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 90\r
3907 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 91\r
3908 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 92\r
3909 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 93\r
3910 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 94\r
3911 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 95\r
3912 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 96\r
3913 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 97\r
3914 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 98\r
3915 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 99\r
3916 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 100\r
3917 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 101\r
3918 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 102\r
3919 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 103\r
3920 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 104\r
3921 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 105\r
3922 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 106\r
3923 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 107\r
3924 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 108\r
3925 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 109\r
3926 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 110\r
3927 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 111\r
3928 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 112\r
3929 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 113\r
3930 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 114\r
3931 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 115\r
3932 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 116\r
3933 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 117\r
3934 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 118\r
3935 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 119\r
3936 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 120\r
3937 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 121\r
3938 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 122\r
3939 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 123\r
3940 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 124\r
3941 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 125\r
3942 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 126\r
3943 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 127\r
3944 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 128\r
3945 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 129\r
3946 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 130\r
3947 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 131\r
3948 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 132\r
3949 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 133\r
3950 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 134\r
3951 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 135\r
3952 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 136\r
3953 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 137\r
3954 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 138\r
3955 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 139\r
3956 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 140\r
3957 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 141\r
3958 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 142\r
3959 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 143\r
3960 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 144\r
3961 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 145\r
3962 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 146\r
3963 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 147\r
3964 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 148\r
3965 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 149\r
3966 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 150\r
3967 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 151\r
3968 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 152\r
3969 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 153\r
3970 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 154\r
3971 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 155\r
3972 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 156\r
3973 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 157\r
3974 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 158\r
3975 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 159\r
3976 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 160\r
3977 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 161\r
3978 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 162\r
3979 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 163\r
3980 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 164\r
3981 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 165\r
3982 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 166\r
3983 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 167\r
3984 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 168\r
3985 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 169\r
3986 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 170\r
3987 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 171\r
3988 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 172\r
3989 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 173\r
3990 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 174\r
3991 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 175\r
3992 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 176\r
3993 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 177\r
3994 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 178\r
3995 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 179\r
3996 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 180\r
3997 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 181\r
3998 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 182\r
3999 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 183\r
4000 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 184\r
4001 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 185\r
4002 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 186\r
4003 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 187\r
4004 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 188\r
4005 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 189\r
4006 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 190\r
4007 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 191\r
4008 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 192\r
4009 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 193\r
4010 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 194\r
4011 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 195\r
4012 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 196\r
4013 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 197\r
4014 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 198\r
4015 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 199\r
4016 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 200\r
4017 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 201\r
4018 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 202\r
4019 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 203\r
4020 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 204\r
4021 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 205\r
4022 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 206\r
4023 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 207\r
4024 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 208\r
4025 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 209\r
4026 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 210\r
4027 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 211\r
4028 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 212\r
4029 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 213\r
4030 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 214\r
4031 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 215\r
4032 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 216\r
4033 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 217\r
4034 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 218\r
4035 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 219\r
4036 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 220\r
4037 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 221\r
4038 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 222\r
4039 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 223\r
4040 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 224\r
4041 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 225\r
4042 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 226\r
4043 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 227\r
4044 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 228\r
4045 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 229\r
4046 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 230\r
4047 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 231\r
4048 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 232\r
4049 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 233\r
4050 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 234\r
4051 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 235\r
4052 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 236\r
4053 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 237\r
4054 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 238\r
4055 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 239\r
4056 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 240\r
4057 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 241\r
4058 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 242\r
4059 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 243\r
4060 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 244\r
4061 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 245\r
4062 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 246\r
4063 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 247\r
4064 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 248\r
4065 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 249\r
4066 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 250\r
4067 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 251\r
4068 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 252\r
4069 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 253\r
4070 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 254\r
4071 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 255\r
4072\r
4073.align 4\r
4074\r
4075PZSTable_data: .byte (1<<ZFlag)|(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4076 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4077 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4078 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4079 .byte (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4080 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4081 .byte (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4082 .byte (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4083 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4084 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4085 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4086 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4087 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4088 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4089 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4090 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4091 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4092 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4093 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4094 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4095 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4096 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4097 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4098 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4099 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4100 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4101 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4102 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4103 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4104 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4105 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4106 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4107 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4108 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4109 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4110 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4111 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4112 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4113 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4114 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4115 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag) \r
4116\r
4117.align 4\r
4118\r
4119MAIN_opcodes: \r
4120 .word opcode_0_0,opcode_0_1,opcode_0_2,opcode_0_3,opcode_0_4,opcode_0_5,opcode_0_6,opcode_0_7\r
4121 .word opcode_0_8,opcode_0_9,opcode_0_A,opcode_0_B,opcode_0_C,opcode_0_D,opcode_0_E,opcode_0_F\r
4122 .word opcode_1_0,opcode_1_1,opcode_1_2,opcode_1_3,opcode_1_4,opcode_1_5,opcode_1_6,opcode_1_7\r
4123 .word opcode_1_8,opcode_1_9,opcode_1_A,opcode_1_B,opcode_1_C,opcode_1_D,opcode_1_E,opcode_1_F\r
4124 .word opcode_2_0,opcode_2_1,opcode_2_2,opcode_2_3,opcode_2_4,opcode_2_5,opcode_2_6,opcode_2_7\r
4125 .word opcode_2_8,opcode_2_9,opcode_2_A,opcode_2_B,opcode_2_C,opcode_2_D,opcode_2_E,opcode_2_F\r
4126 .word opcode_3_0,opcode_3_1,opcode_3_2,opcode_3_3,opcode_3_4,opcode_3_5,opcode_3_6,opcode_3_7\r
4127 .word opcode_3_8,opcode_3_9,opcode_3_A,opcode_3_B,opcode_3_C,opcode_3_D,opcode_3_E,opcode_3_F\r
4128 .word opcode_4_0,opcode_4_1,opcode_4_2,opcode_4_3,opcode_4_4,opcode_4_5,opcode_4_6,opcode_4_7\r
4129 .word opcode_4_8,opcode_4_9,opcode_4_A,opcode_4_B,opcode_4_C,opcode_4_D,opcode_4_E,opcode_4_F\r
4130 .word opcode_5_0,opcode_5_1,opcode_5_2,opcode_5_3,opcode_5_4,opcode_5_5,opcode_5_6,opcode_5_7\r
4131 .word opcode_5_8,opcode_5_9,opcode_5_A,opcode_5_B,opcode_5_C,opcode_5_D,opcode_5_E,opcode_5_F\r
4132 .word opcode_6_0,opcode_6_1,opcode_6_2,opcode_6_3,opcode_6_4,opcode_6_5,opcode_6_6,opcode_6_7\r
4133 .word opcode_6_8,opcode_6_9,opcode_6_A,opcode_6_B,opcode_6_C,opcode_6_D,opcode_6_E,opcode_6_F\r
4134 .word opcode_7_0,opcode_7_1,opcode_7_2,opcode_7_3,opcode_7_4,opcode_7_5,opcode_7_6,opcode_7_7\r
4135 .word opcode_7_8,opcode_7_9,opcode_7_A,opcode_7_B,opcode_7_C,opcode_7_D,opcode_7_E,opcode_7_F\r
4136 .word opcode_8_0,opcode_8_1,opcode_8_2,opcode_8_3,opcode_8_4,opcode_8_5,opcode_8_6,opcode_8_7\r
4137 .word opcode_8_8,opcode_8_9,opcode_8_A,opcode_8_B,opcode_8_C,opcode_8_D,opcode_8_E,opcode_8_F\r
4138 .word opcode_9_0,opcode_9_1,opcode_9_2,opcode_9_3,opcode_9_4,opcode_9_5,opcode_9_6,opcode_9_7\r
4139 .word opcode_9_8,opcode_9_9,opcode_9_A,opcode_9_B,opcode_9_C,opcode_9_D,opcode_9_E,opcode_9_F\r
4140 .word opcode_A_0,opcode_A_1,opcode_A_2,opcode_A_3,opcode_A_4,opcode_A_5,opcode_A_6,opcode_A_7\r
4141 .word opcode_A_8,opcode_A_9,opcode_A_A,opcode_A_B,opcode_A_C,opcode_A_D,opcode_A_E,opcode_A_F\r
4142 .word opcode_B_0,opcode_B_1,opcode_B_2,opcode_B_3,opcode_B_4,opcode_B_5,opcode_B_6,opcode_B_7\r
4143 .word opcode_B_8,opcode_B_9,opcode_B_A,opcode_B_B,opcode_B_C,opcode_B_D,opcode_B_E,opcode_B_F\r
4144 .word opcode_C_0,opcode_C_1,opcode_C_2,opcode_C_3,opcode_C_4,opcode_C_5,opcode_C_6,opcode_C_7\r
4145 .word opcode_C_8,opcode_C_9,opcode_C_A,opcode_C_B,opcode_C_C,opcode_C_D,opcode_C_E,opcode_C_F\r
4146 .word opcode_D_0,opcode_D_1,opcode_D_2,opcode_D_3,opcode_D_4,opcode_D_5,opcode_D_6,opcode_D_7\r
4147 .word opcode_D_8,opcode_D_9,opcode_D_A,opcode_D_B,opcode_D_C,opcode_D_D,opcode_D_E,opcode_D_F\r
4148 .word opcode_E_0,opcode_E_1,opcode_E_2,opcode_E_3,opcode_E_4,opcode_E_5,opcode_E_6,opcode_E_7\r
4149 .word opcode_E_8,opcode_E_9,opcode_E_A,opcode_E_B,opcode_E_C,opcode_E_D,opcode_E_E,opcode_E_F\r
4150 .word opcode_F_0,opcode_F_1,opcode_F_2,opcode_F_3,opcode_F_4,opcode_F_5,opcode_F_6,opcode_F_7\r
4151 .word opcode_F_8,opcode_F_9,opcode_F_A,opcode_F_B,opcode_F_C,opcode_F_D,opcode_F_E,opcode_F_F\r
4152\r
4153.align 4\r
4154\r
4155EI_DUMMY_opcodes:\r
4156 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@0\r
4157 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@0\r
4158 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@1\r
4159 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@1\r
4160 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@2\r
4161 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@2\r
4162 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@3\r
4163 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@3\r
4164 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@4\r
4165 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@4\r
4166 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@5\r
4167 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@5\r
4168 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@6\r
4169 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@6\r
4170 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@7\r
4171 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@7\r
4172 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@8\r
4173 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@8\r
4174 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@9\r
4175 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@9\r
4176 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@A\r
4177 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@A\r
4178 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@B\r
4179 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@B\r
4180 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@C\r
4181 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@C\r
4182 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@D\r
4183 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@D\r
4184 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@E\r
4185 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@E\r
4186 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@F\r
4187 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@F\r
4188\r
4189.text\r
4190.align 4\r
4191\r
4192;@NOP\r
4193opcode_0_0:\r
4194;@LD B,B\r
4195opcode_4_0:\r
4196;@LD C,C\r
4197opcode_4_9:\r
4198;@LD D,D\r
4199opcode_5_2:\r
4200;@LD E,E\r
4201opcode_5_B:\r
4202;@LD H,H\r
4203opcode_6_4:\r
4204;@LD L,L\r
4205opcode_6_D:\r
4206;@LD A,A\r
4207opcode_7_F:\r
4208 fetch 4\r
4209;@LD BC,NN\r
4210opcode_0_1:\r
4211 ldrb r0,[z80pc],#1\r
4212 ldrb r1,[z80pc],#1\r
4213 orr r0,r0,r1, lsl #8\r
4214 mov z80bc,r0, lsl #16\r
4215 fetch 10\r
4216;@LD (BC),A\r
4217opcode_0_2:\r
4218 mov r0,z80a, lsr #24\r
4219 mov r1,z80bc, lsr #16\r
4220 writemem8\r
4221 fetch 7\r
4222;@INC BC\r
4223opcode_0_3:\r
4224 add z80bc,z80bc,#1<<16\r
4225 fetch 6\r
4226;@INC B\r
4227opcode_0_4:\r
4228 opINC8H z80bc\r
4229 fetch 4\r
4230;@DEC B\r
4231opcode_0_5:\r
4232 opDEC8H z80bc\r
4233 fetch 4\r
4234;@LD B,N\r
4235opcode_0_6:\r
4236 ldrb r1,[z80pc],#1\r
4237 and z80bc,z80bc,#0xFF<<16\r
4238 orr z80bc,z80bc,r1, lsl #24\r
4239 fetch 7\r
4240;@RLCA\r
4241opcode_0_7:\r
4242 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4243 movs z80a,z80a, lsl #1\r
4244 orrcs z80a,z80a,#1<<24\r
4245 orrcs z80f,z80f,#1<<CFlag\r
4246 fetch 4\r
4247;@EX AF,AF'\r
4248opcode_0_8:\r
4249 add r1,cpucontext,#z80a2\r
4250 swp z80a,z80a,[r1]\r
4251 add r1,cpucontext,#z80f2\r
4252 swp z80f,z80f,[r1]\r
4253 fetch 4\r
4254;@ADD HL,BC\r
4255opcode_0_9:\r
4256 opADD16 z80hl z80bc\r
4257 fetch 11\r
4258;@LD A,(BC)\r
4259opcode_0_A:\r
4260 mov r0,z80bc, lsr #16\r
4261 readmem8\r
4262 mov z80a,r0, lsl #24\r
4263 fetch 7\r
4264;@DEC BC\r
4265opcode_0_B:\r
4266 sub z80bc,z80bc,#1<<16\r
4267 fetch 6\r
4268;@INC C\r
4269opcode_0_C:\r
4270 opINC8L z80bc\r
4271 fetch 4\r
4272;@DEC C\r
4273opcode_0_D:\r
4274 opDEC8L z80bc\r
4275 fetch 4\r
4276;@LD C,N\r
4277opcode_0_E:\r
4278 ldrb r1,[z80pc],#1\r
4279 and z80bc,z80bc,#0xFF<<24\r
4280 orr z80bc,z80bc,r1, lsl #16\r
4281 fetch 7\r
4282;@RRCA\r
4283opcode_0_F:\r
4284 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4285 movs z80a,z80a, lsr #25\r
4286 orrcs z80a,z80a,#1<<7\r
4287 orrcs z80f,z80f,#1<<CFlag\r
4288 mov z80a,z80a, lsl #24\r
4289 fetch 4\r
4290;@DJNZ $+2\r
4291opcode_1_0:\r
4292 sub z80bc,z80bc,#1<<24\r
4293 tst z80bc,#0xFF<<24\r
4294 ldrsb r1,[z80pc],#1\r
4295 addne z80pc,z80pc,r1\r
4296 subne z80_icount,z80_icount,#5\r
4297 fetch 8\r
4298\r
4299;@LD DE,NN\r
4300opcode_1_1:\r
4301 ldrb r0,[z80pc],#1\r
4302 ldrb r1,[z80pc],#1\r
4303 orr r0,r0,r1, lsl #8\r
4304 mov z80de,r0, lsl #16\r
4305 fetch 10\r
4306;@LD (DE),A\r
4307opcode_1_2:\r
4308 mov r0,z80a, lsr #24\r
4309 writemem8DE\r
4310 fetch 7\r
4311;@INC DE\r
4312opcode_1_3:\r
4313 add z80de,z80de,#1<<16\r
4314 fetch 6\r
4315;@INC D\r
4316opcode_1_4:\r
4317 opINC8H z80de\r
4318 fetch 4\r
4319;@DEC D\r
4320opcode_1_5:\r
4321 opDEC8H z80de\r
4322 fetch 4\r
4323;@LD D,N\r
4324opcode_1_6:\r
4325 ldrb r1,[z80pc],#1\r
4326 and z80de,z80de,#0xFF<<16\r
4327 orr z80de,z80de,r1, lsl #24\r
4328 fetch 7\r
4329;@RLA\r
4330opcode_1_7:\r
4331 tst z80f,#1<<CFlag\r
4332 orrne z80a,z80a,#1<<23\r
4333 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4334 movs z80a,z80a, lsl #1\r
4335 orrcs z80f,z80f,#1<<CFlag\r
4336 fetch 4\r
4337;@JR $+2\r
4338opcode_1_8:\r
4339 ldrsb r1,[z80pc],#1\r
4340 add z80pc,z80pc,r1\r
4341 fetch 12\r
4342;@ADD HL,DE\r
4343opcode_1_9:\r
4344 opADD16 z80hl z80de\r
4345 fetch 11\r
4346;@LD A,(DE)\r
4347opcode_1_A:\r
4348 mov r0,z80de, lsr #16\r
4349 readmem8\r
4350 mov z80a,r0, lsl #24\r
4351 fetch 7\r
4352;@DEC DE\r
4353opcode_1_B:\r
4354 sub z80de,z80de,#1<<16\r
4355 fetch 6\r
4356;@INC E\r
4357opcode_1_C:\r
4358 opINC8L z80de\r
4359 fetch 4\r
4360;@DEC E\r
4361opcode_1_D:\r
4362 opDEC8L z80de\r
4363 fetch 4\r
4364;@LD E,N\r
4365opcode_1_E:\r
4366 ldrb r0,[z80pc],#1\r
4367 and z80de,z80de,#0xFF<<24\r
4368 orr z80de,z80de,r0, lsl #16\r
4369 fetch 7\r
4370;@RRA\r
4371opcode_1_F:\r
4372 orr z80a,z80a,z80f,lsr#1 ;@get C\r
4373 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4374 movs z80a,z80a,ror#25\r
4375 orrcs z80f,z80f,#1<<CFlag\r
4376 mov z80a,z80a,lsl#24\r
4377 fetch 4\r
4378;@JR NZ,$+2\r
4379opcode_2_0:\r
4380 tst z80f,#1<<ZFlag\r
4381 beq opcode_1_8\r
4382 add z80pc,z80pc,#1\r
4383 fetch 7\r
4384;@LD HL,NN\r
4385opcode_2_1:\r
4386 ldrb r0,[z80pc],#1\r
4387 ldrb r1,[z80pc],#1\r
4388 orr r0,r0,r1, lsl #8\r
4389 mov z80hl,r0, lsl #16\r
4390 fetch 10\r
4391;@LD (NN),HL\r
4392opcode_ED_63:\r
4393 eatcycles 4\r
4394;@LD (NN),HL\r
4395opcode_2_2:\r
4396 ldrb r0,[z80pc],#1\r
4397 ldrb r1,[z80pc],#1\r
4398 orr r1,r0,r1, lsl #8\r
4399 mov r0,z80hl, lsr #16\r
4400 writemem16\r
4401 fetch 16\r
4402;@INC HL\r
4403opcode_2_3:\r
4404 add z80hl,z80hl,#1<<16\r
4405 fetch 6\r
4406;@INC H\r
4407opcode_2_4:\r
4408 opINC8H z80hl\r
4409 fetch 4\r
4410;@DEC H\r
4411opcode_2_5:\r
4412 opDEC8H z80hl\r
4413 fetch 4\r
4414;@LD H,N\r
4415opcode_2_6:\r
4416 ldrb r1,[z80pc],#1\r
4417 and z80hl,z80hl,#0xFF<<16\r
4418 orr z80hl,z80hl,r1, lsl #24\r
4419 fetch 7\r
4420DAATABLE_LOCAL: .word DAATable\r
4421;@DAA\r
4422opcode_2_7:\r
4423 mov r1,z80a, lsr #24\r
4424 tst z80f,#1<<CFlag\r
4425 orrne r1,r1,#256\r
4426 tst z80f,#1<<HFlag\r
4427 orrne r1,r1,#512\r
4428 tst z80f,#1<<NFlag\r
4429 orrne r1,r1,#1024\r
4430 ldr r2,DAATABLE_LOCAL\r
4431 add r2,r2,r1, lsl #1\r
4432 ldrh r1,[r2]\r
4433 and z80f,r1,#0xFF\r
4434 and r2,r1,#0xFF<<8\r
4435 mov z80a,r2, lsl #16\r
4436 fetch 4\r
4437;@JR Z,$+2\r
4438opcode_2_8:\r
4439 tst z80f,#1<<ZFlag\r
4440 bne opcode_1_8\r
4441 add z80pc,z80pc,#1\r
4442 fetch 7\r
4443;@ADD HL,HL\r
4444opcode_2_9:\r
4445 opADD16_2 z80hl\r
4446 fetch 11\r
4447;@LD HL,(NN)\r
4448opcode_ED_6B:\r
4449 eatcycles 4\r
4450;@LD HL,(NN)\r
4451opcode_2_A:\r
4452 ldrb r0,[z80pc],#1\r
4453 ldrb r1,[z80pc],#1\r
4454 orr r0,r0,r1, lsl #8\r
4455 readmem16\r
4456 mov z80hl,r0, lsl #16\r
4457 fetch 16\r
4458;@DEC HL\r
4459opcode_2_B:\r
4460 sub z80hl,z80hl,#1<<16\r
4461 fetch 6\r
4462;@INC L\r
4463opcode_2_C:\r
4464 opINC8L z80hl\r
4465 fetch 4\r
4466;@DEC L\r
4467opcode_2_D:\r
4468 opDEC8L z80hl\r
4469 fetch 4\r
4470;@LD L,N\r
4471opcode_2_E:\r
4472 ldrb r0,[z80pc],#1\r
4473 and z80hl,z80hl,#0xFF<<24\r
4474 orr z80hl,z80hl,r0, lsl #16\r
4475 fetch 7\r
4476;@CPL\r
4477opcode_2_F:\r
4478 eor z80a,z80a,#0xFF<<24\r
4479 orr z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
4480 fetch 4\r
4481;@JR NC,$+2\r
4482opcode_3_0:\r
4483 tst z80f,#1<<CFlag\r
4484 beq opcode_1_8\r
4485 add z80pc,z80pc,#1\r
4486 fetch 7\r
4487;@LD SP,NN\r
4488opcode_3_1:\r
4489 ldrb r0,[z80pc],#1\r
4490 ldrb r1,[z80pc],#1\r
4491\r
4492.if FAST_Z80SP\r
4493 orr r0,r0,r1, lsl #8\r
4494 rebasesp\r
4495 mov z80sp,r0\r
4496.else\r
4497 orr z80sp,r0,r1, lsl #8\r
4498.endif\r
4499 fetch 10\r
4500;@LD (NN),A\r
4501opcode_3_2:\r
4502 ldrb r0,[z80pc],#1\r
4503 ldrb r1,[z80pc],#1\r
4504 orr r1,r0,r1, lsl #8\r
4505 mov r0,z80a, lsr #24\r
4506 writemem8\r
4507 fetch 13\r
4508;@INC SP\r
4509opcode_3_3:\r
4510 add z80sp,z80sp,#1\r
4511 fetch 6\r
4512;@INC (HL)\r
4513opcode_3_4:\r
4514 readmem8HL\r
4515 opINC8b\r
4516 writemem8HL\r
4517 fetch 11\r
4518;@DEC (HL)\r
4519opcode_3_5:\r
4520 readmem8HL\r
4521 opDEC8b\r
4522 writemem8HL\r
4523 fetch 11\r
4524;@LD (HL),N\r
4525opcode_3_6:\r
4526 ldrb r0,[z80pc],#1\r
4527 writemem8HL\r
4528 fetch 10\r
4529;@SCF\r
4530opcode_3_7:\r
4531 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
4532 orr z80f,z80f,#1<<CFlag\r
4533 fetch 4\r
4534;@JR C,$+2\r
4535opcode_3_8:\r
4536 tst z80f,#1<<CFlag\r
4537 bne opcode_1_8\r
4538 add z80pc,z80pc,#1\r
4539 fetch 7\r
4540;@ADD HL,SP\r
4541opcode_3_9:\r
4542.if FAST_Z80SP\r
4543 ldr r0,[cpucontext,#z80sp_base]\r
4544 sub r0,z80sp,r0\r
4545 opADD16s z80hl r0 16\r
4546.else\r
4547 opADD16s z80hl z80sp 16\r
4548.endif\r
4549 fetch 11\r
4550;@LD A,(NN)\r
4551opcode_3_A:\r
4552 ldrb r0,[z80pc],#1\r
4553 ldrb r1,[z80pc],#1\r
4554 orr r0,r0,r1, lsl #8\r
4555 readmem8\r
4556 mov z80a,r0, lsl #24\r
4557 fetch 13\r
4558;@DEC SP\r
4559opcode_3_B:\r
4560 sub z80sp,z80sp,#1\r
4561 fetch 6\r
4562;@INC A\r
4563opcode_3_C:\r
4564 opINC8 z80a\r
4565 fetch 4\r
4566;@DEC A\r
4567opcode_3_D:\r
4568 opDEC8 z80a\r
4569 fetch 4\r
4570;@LD A,N\r
4571opcode_3_E:\r
4572 ldrb r0,[z80pc],#1\r
4573 mov z80a,r0, lsl #24\r
4574 fetch 7\r
4575;@CCF\r
4576opcode_3_F:\r
4577 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
4578 tst z80f,#1<<CFlag\r
4579 orrne z80f,z80f,#1<<HFlag\r
4580 eor z80f,z80f,#1<<CFlag\r
4581 fetch 4\r
4582\r
4583;@LD B,C\r
4584opcode_4_1:\r
4585 and z80bc,z80bc,#0xFF<<16\r
4586 orr z80bc,z80bc,z80bc, lsl #8\r
4587 fetch 4\r
4588;@LD B,D\r
4589opcode_4_2:\r
4590 and z80bc,z80bc,#0xFF<<16\r
4591 and r1,z80de,#0xFF<<24\r
4592 orr z80bc,z80bc,r1\r
4593 fetch 4\r
4594;@LD B,E\r
4595opcode_4_3:\r
4596 and z80bc,z80bc,#0xFF<<16\r
4597 and r1,z80de,#0xFF<<16\r
4598 orr z80bc,z80bc,r1, lsl #8\r
4599 fetch 4\r
4600;@LD B,H\r
4601opcode_4_4:\r
4602 and z80bc,z80bc,#0xFF<<16\r
4603 and r1,z80hl,#0xFF<<24\r
4604 orr z80bc,z80bc,r1\r
4605 fetch 4\r
4606;@LD B,L\r
4607opcode_4_5:\r
4608 and z80bc,z80bc,#0xFF<<16\r
4609 and r1,z80hl,#0xFF<<16\r
4610 orr z80bc,z80bc,r1, lsl #8\r
4611 fetch 4\r
4612;@LD B,(HL)\r
4613opcode_4_6:\r
4614 readmem8HL\r
4615 and z80bc,z80bc,#0xFF<<16\r
4616 orr z80bc,z80bc,r0, lsl #24\r
4617 fetch 7\r
4618;@LD B,A\r
4619opcode_4_7:\r
4620 and z80bc,z80bc,#0xFF<<16\r
4621 orr z80bc,z80bc,z80a\r
4622 fetch 4\r
4623;@LD C,B\r
4624opcode_4_8:\r
4625 and z80bc,z80bc,#0xFF<<24\r
4626 orr z80bc,z80bc,z80bc, lsr #8\r
4627 fetch 4\r
4628;@LD C,D\r
4629opcode_4_A:\r
4630 and z80bc,z80bc,#0xFF<<24\r
4631 and r1,z80de,#0xFF<<24\r
4632 orr z80bc,z80bc,r1, lsr #8\r
4633 fetch 4\r
4634;@LD C,E\r
4635opcode_4_B:\r
4636 and z80bc,z80bc,#0xFF<<24\r
4637 and r1,z80de,#0xFF<<16\r
4638 orr z80bc,z80bc,r1 \r
4639 fetch 4\r
4640;@LD C,H\r
4641opcode_4_C:\r
4642 and z80bc,z80bc,#0xFF<<24\r
4643 and r1,z80hl,#0xFF<<24\r
4644 orr z80bc,z80bc,r1, lsr #8\r
4645 fetch 4\r
4646;@LD C,L\r
4647opcode_4_D:\r
4648 and z80bc,z80bc,#0xFF<<24\r
4649 and r1,z80hl,#0xFF<<16\r
4650 orr z80bc,z80bc,r1 \r
4651 fetch 4\r
4652;@LD C,(HL)\r
4653opcode_4_E:\r
4654 readmem8HL\r
4655 and z80bc,z80bc,#0xFF<<24\r
4656 orr z80bc,z80bc,r0, lsl #16\r
4657 fetch 7\r
4658;@LD C,A\r
4659opcode_4_F:\r
4660 and z80bc,z80bc,#0xFF<<24\r
4661 orr z80bc,z80bc,z80a, lsr #8\r
4662 fetch 4\r
4663;@LD D,B\r
4664opcode_5_0:\r
4665 and z80de,z80de,#0xFF<<16\r
4666 and r1,z80bc,#0xFF<<24\r
4667 orr z80de,z80de,r1\r
4668 fetch 4\r
4669;@LD D,C\r
4670opcode_5_1:\r
4671 and z80de,z80de,#0xFF<<16\r
4672 orr z80de,z80de,z80bc, lsl #8\r
4673 fetch 4\r
4674;@LD D,E\r
4675opcode_5_3:\r
4676 and z80de,z80de,#0xFF<<16\r
4677 orr z80de,z80de,z80de, lsl #8\r
4678 fetch 4\r
4679;@LD D,H\r
4680opcode_5_4:\r
4681 and z80de,z80de,#0xFF<<16\r
4682 and r1,z80hl,#0xFF<<24\r
4683 orr z80de,z80de,r1\r
4684 fetch 4\r
4685;@LD D,L\r
4686opcode_5_5:\r
4687 and z80de,z80de,#0xFF<<16\r
4688 orr z80de,z80de,z80hl, lsl #8\r
4689 fetch 4\r
4690;@LD D,(HL)\r
4691opcode_5_6:\r
4692 readmem8HL\r
4693 and z80de,z80de,#0xFF<<16\r
4694 orr z80de,z80de,r0, lsl #24\r
4695 fetch 7\r
4696;@LD D,A\r
4697opcode_5_7:\r
4698 and z80de,z80de,#0xFF<<16\r
4699 orr z80de,z80de,z80a\r
4700 fetch 4\r
4701;@LD E,B\r
4702opcode_5_8:\r
4703 and z80de,z80de,#0xFF<<24\r
4704 and r1,z80bc,#0xFF<<24\r
4705 orr z80de,z80de,r1, lsr #8\r
4706 fetch 4\r
4707;@LD E,C\r
4708opcode_5_9:\r
4709 and z80de,z80de,#0xFF<<24\r
4710 and r1,z80bc,#0xFF<<16\r
4711 orr z80de,z80de,r1 \r
4712 fetch 4\r
4713;@LD E,D\r
4714opcode_5_A:\r
4715 and z80de,z80de,#0xFF<<24\r
4716 orr z80de,z80de,z80de, lsr #8\r
4717 fetch 4\r
4718;@LD E,H\r
4719opcode_5_C:\r
4720 and z80de,z80de,#0xFF<<24\r
4721 and r1,z80hl,#0xFF<<24\r
4722 orr z80de,z80de,r1, lsr #8\r
4723 fetch 4\r
4724;@LD E,L\r
4725opcode_5_D:\r
4726 and z80de,z80de,#0xFF<<24\r
4727 and r1,z80hl,#0xFF<<16\r
4728 orr z80de,z80de,r1 \r
4729 fetch 4\r
4730;@LD E,(HL)\r
4731opcode_5_E:\r
4732 readmem8HL\r
4733 and z80de,z80de,#0xFF<<24\r
4734 orr z80de,z80de,r0, lsl #16\r
4735 fetch 7\r
4736;@LD E,A\r
4737opcode_5_F:\r
4738 and z80de,z80de,#0xFF<<24\r
4739 orr z80de,z80de,z80a, lsr #8\r
4740 fetch 4\r
4741\r
4742;@LD H,B\r
4743opcode_6_0:\r
4744 and z80hl,z80hl,#0xFF<<16\r
4745 and r1,z80bc,#0xFF<<24\r
4746 orr z80hl,z80hl,r1\r
4747 fetch 4\r
4748;@LD H,C\r
4749opcode_6_1:\r
4750 and z80hl,z80hl,#0xFF<<16\r
4751 orr z80hl,z80hl,z80bc, lsl #8\r
4752 fetch 4\r
4753;@LD H,D\r
4754opcode_6_2:\r
4755 and z80hl,z80hl,#0xFF<<16\r
4756 and r1,z80de,#0xFF<<24\r
4757 orr z80hl,z80hl,r1\r
4758 fetch 4\r
4759;@LD H,E\r
4760opcode_6_3:\r
4761 and z80hl,z80hl,#0xFF<<16\r
4762 orr z80hl,z80hl,z80de, lsl #8\r
4763 fetch 4\r
4764;@LD H,L\r
4765opcode_6_5:\r
4766 and z80hl,z80hl,#0xFF<<16\r
4767 orr z80hl,z80hl,z80hl, lsl #8\r
4768 fetch 4\r
4769;@LD H,(HL)\r
4770opcode_6_6:\r
4771 readmem8HL\r
4772 and z80hl,z80hl,#0xFF<<16\r
4773 orr z80hl,z80hl,r0, lsl #24\r
4774 fetch 7\r
4775;@LD H,A\r
4776opcode_6_7:\r
4777 and z80hl,z80hl,#0xFF<<16\r
4778 orr z80hl,z80hl,z80a\r
4779 fetch 4\r
4780\r
4781;@LD L,B\r
4782opcode_6_8:\r
4783 and z80hl,z80hl,#0xFF<<24\r
4784 and r1,z80bc,#0xFF<<24\r
4785 orr z80hl,z80hl,r1, lsr #8\r
4786 fetch 4\r
4787;@LD L,C\r
4788opcode_6_9:\r
4789 and z80hl,z80hl,#0xFF<<24\r
4790 and r1,z80bc,#0xFF<<16\r
4791 orr z80hl,z80hl,r1\r
4792 fetch 4\r
4793;@LD L,D\r
4794opcode_6_A:\r
4795 and z80hl,z80hl,#0xFF<<24\r
4796 and r1,z80de,#0xFF<<24\r
4797 orr z80hl,z80hl,r1, lsr #8\r
4798 fetch 4\r
4799;@LD L,E\r
4800opcode_6_B:\r
4801 and z80hl,z80hl,#0xFF<<24\r
4802 and r1,z80de,#0xFF<<16\r
4803 orr z80hl,z80hl,r1\r
4804 fetch 4\r
4805;@LD L,H\r
4806opcode_6_C:\r
4807 and z80hl,z80hl,#0xFF<<24\r
4808 orr z80hl,z80hl,z80hl, lsr #8\r
4809 fetch 4\r
4810;@LD L,(HL)\r
4811opcode_6_E:\r
4812 readmem8HL\r
4813 and z80hl,z80hl,#0xFF<<24\r
4814 orr z80hl,z80hl,r0, lsl #16\r
4815 fetch 7\r
4816;@LD L,A\r
4817opcode_6_F:\r
4818 and z80hl,z80hl,#0xFF<<24\r
4819 orr z80hl,z80hl,z80a, lsr #8\r
4820 fetch 4\r
4821\r
4822;@LD (HL),B\r
4823opcode_7_0:\r
4824 mov r0,z80bc, lsr #24\r
4825 writemem8HL\r
4826 fetch 7\r
4827;@LD (HL),C\r
4828opcode_7_1:\r
4829 mov r0,z80bc, lsr #16\r
4830 and r0,r0,#0xFF\r
4831 writemem8HL\r
4832 fetch 7\r
4833;@LD (HL),D\r
4834opcode_7_2:\r
4835 mov r0,z80de, lsr #24\r
4836 writemem8HL\r
4837 fetch 7\r
4838;@LD (HL),E\r
4839opcode_7_3:\r
4840 mov r0,z80de, lsr #16\r
4841 and r0,r0,#0xFF\r
4842 writemem8HL\r
4843 fetch 7\r
4844;@LD (HL),H\r
4845opcode_7_4:\r
4846 mov r0,z80hl, lsr #24\r
4847 writemem8HL\r
4848 fetch 7\r
4849;@LD (HL),L\r
4850opcode_7_5:\r
4851 mov r1,z80hl, lsr #16\r
4852 and r0,r1,#0xFF\r
4853 writemem8\r
4854 fetch 7\r
4855;@HALT\r
4856opcode_7_6:\r
4857 sub z80pc,z80pc,#1\r
4858 ldrb r0,[cpucontext,#z80if]\r
4859 orr r0,r0,#Z80_HALT\r
4860 strb r0,[cpucontext,#z80if]\r
4861 mov z80_icount,#0\r
4862 b z80_execute_end\r
4863;@LD (HL),A\r
4864opcode_7_7:\r
4865 mov r0,z80a, lsr #24\r
4866 writemem8HL\r
4867 fetch 7\r
4868\r
4869;@LD A,B\r
4870opcode_7_8:\r
4871 and z80a,z80bc,#0xFF<<24\r
4872 fetch 4\r
4873;@LD A,C\r
4874opcode_7_9:\r
4875 mov z80a,z80bc, lsl #8\r
4876 fetch 4\r
4877;@LD A,D\r
4878opcode_7_A:\r
4879 and z80a,z80de,#0xFF<<24\r
4880 fetch 4\r
4881;@LD A,E\r
4882opcode_7_B:\r
4883 mov z80a,z80de, lsl #8\r
4884 fetch 4\r
4885;@LD A,H\r
4886opcode_7_C:\r
4887 and z80a,z80hl,#0xFF<<24\r
4888 fetch 4\r
4889;@LD A,L\r
4890opcode_7_D:\r
4891 mov z80a,z80hl, lsl #8\r
4892 fetch 4\r
4893;@LD A,(HL)\r
4894opcode_7_E:\r
4895 readmem8HL\r
4896 mov z80a,r0, lsl #24\r
4897 fetch 7\r
4898\r
4899;@ADD A,B\r
4900opcode_8_0:\r
4901 opADDH z80bc\r
4902;@ADD A,C\r
4903opcode_8_1:\r
4904 opADDL z80bc\r
4905;@ADD A,D\r
4906opcode_8_2:\r
4907 opADDH z80de\r
4908;@ADD A,E\r
4909opcode_8_3:\r
4910 opADDL z80de\r
4911;@ADD A,H\r
4912opcode_8_4:\r
4913 opADDH z80hl\r
4914;@ADD A,L\r
4915opcode_8_5:\r
4916 opADDL z80hl\r
4917;@ADD A,(HL)\r
4918opcode_8_6:\r
4919 readmem8HL\r
4920 opADDb\r
4921 fetch 7\r
4922;@ADD A,A\r
4923opcode_8_7:\r
4924 opADDA\r
4925\r
4926;@ADC A,B\r
4927opcode_8_8:\r
4928 opADCH z80bc\r
4929;@ADC A,C\r
4930opcode_8_9:\r
4931 opADCL z80bc\r
4932;@ADC A,D\r
4933opcode_8_A:\r
4934 opADCH z80de\r
4935;@ADC A,E\r
4936opcode_8_B:\r
4937 opADCL z80de\r
4938;@ADC A,H\r
4939opcode_8_C:\r
4940 opADCH z80hl\r
4941;@ADC A,L\r
4942opcode_8_D:\r
4943 opADCL z80hl\r
4944;@ADC A,(HL)\r
4945opcode_8_E:\r
4946 readmem8HL\r
4947 opADCb\r
4948 fetch 7\r
4949;@ADC A,A\r
4950opcode_8_F:\r
4951 opADCA\r
4952\r
4953;@SUB B\r
4954opcode_9_0:\r
4955 opSUBH z80bc\r
4956;@SUB C\r
4957opcode_9_1:\r
4958 opSUBL z80bc\r
4959;@SUB D\r
4960opcode_9_2:\r
4961 opSUBH z80de\r
4962;@SUB E\r
4963opcode_9_3:\r
4964 opSUBL z80de\r
4965;@SUB H\r
4966opcode_9_4:\r
4967 opSUBH z80hl\r
4968;@SUB L\r
4969opcode_9_5:\r
4970 opSUBL z80hl\r
4971;@SUB (HL)\r
4972opcode_9_6:\r
4973 readmem8HL\r
4974 opSUBb\r
4975 fetch 7\r
4976;@SUB A\r
4977opcode_9_7:\r
4978 opSUBA\r
4979\r
4980;@SBC B \r
4981opcode_9_8:\r
4982 opSBCH z80bc\r
4983;@SBC C\r
4984opcode_9_9:\r
4985 opSBCL z80bc\r
4986;@SBC D\r
4987opcode_9_A:\r
4988 opSBCH z80de\r
4989;@SBC E\r
4990opcode_9_B:\r
4991 opSBCL z80de\r
4992;@SBC H\r
4993opcode_9_C:\r
4994 opSBCH z80hl\r
4995;@SBC L\r
4996opcode_9_D:\r
4997 opSBCL z80hl\r
4998;@SBC (HL)\r
4999opcode_9_E:\r
5000 readmem8HL\r
5001 opSBCb\r
5002 fetch 7\r
5003;@SBC A\r
5004opcode_9_F:\r
5005 opSBCA\r
5006\r
5007;@AND B\r
5008opcode_A_0:\r
5009 opANDH z80bc\r
5010;@AND C\r
5011opcode_A_1:\r
5012 opANDL z80bc\r
5013;@AND D\r
5014opcode_A_2:\r
5015 opANDH z80de\r
5016;@AND E\r
5017opcode_A_3:\r
5018 opANDL z80de\r
5019;@AND H\r
5020opcode_A_4:\r
5021 opANDH z80hl\r
5022;@AND L\r
5023opcode_A_5:\r
5024 opANDL z80hl\r
5025;@AND (HL)\r
5026opcode_A_6:\r
5027 readmem8HL\r
5028 opANDb\r
5029 fetch 7\r
5030;@AND A\r
5031opcode_A_7:\r
5032 opANDA\r
5033\r
5034;@XOR B\r
5035opcode_A_8:\r
5036 opXORH z80bc\r
5037;@XOR C\r
5038opcode_A_9:\r
5039 opXORL z80bc\r
5040;@XOR D\r
5041opcode_A_A:\r
5042 opXORH z80de\r
5043;@XOR E\r
5044opcode_A_B:\r
5045 opXORL z80de\r
5046;@XOR H\r
5047opcode_A_C:\r
5048 opXORH z80hl\r
5049;@XOR L\r
5050opcode_A_D:\r
5051 opXORL z80hl\r
5052;@XOR (HL)\r
5053opcode_A_E:\r
5054 readmem8HL\r
5055 opXORb\r
5056 fetch 7\r
5057;@XOR A\r
5058opcode_A_F:\r
5059 opXORA\r
5060\r
5061;@OR B\r
5062opcode_B_0:\r
5063 opORH z80bc\r
5064;@OR C\r
5065opcode_B_1:\r
5066 opORL z80bc\r
5067;@OR D\r
5068opcode_B_2:\r
5069 opORH z80de\r
5070;@OR E\r
5071opcode_B_3:\r
5072 opORL z80de\r
5073;@OR H\r
5074opcode_B_4:\r
5075 opORH z80hl\r
5076;@OR L\r
5077opcode_B_5:\r
5078 opORL z80hl\r
5079;@OR (HL)\r
5080opcode_B_6:\r
5081 readmem8HL\r
5082 opORb\r
5083 fetch 7\r
5084;@OR A\r
5085opcode_B_7:\r
5086 opORA\r
5087\r
5088;@CP B\r
5089opcode_B_8:\r
5090 opCPH z80bc\r
5091;@CP C\r
5092opcode_B_9:\r
5093 opCPL z80bc\r
5094;@CP D\r
5095opcode_B_A:\r
5096 opCPH z80de\r
5097;@CP E\r
5098opcode_B_B:\r
5099 opCPL z80de\r
5100;@CP H\r
5101opcode_B_C:\r
5102 opCPH z80hl\r
5103;@CP L\r
5104opcode_B_D:\r
5105 opCPL z80hl\r
5106;@CP (HL)\r
5107opcode_B_E:\r
5108 readmem8HL\r
5109 opCPb\r
5110 fetch 7\r
5111;@CP A\r
5112opcode_B_F:\r
5113 opCPA\r
5114\r
5115;@RET NZ\r
5116opcode_C_0:\r
5117 tst z80f,#1<<ZFlag\r
5118 beq opcode_C_9_cond ;@unconditional RET\r
5119 fetch 5\r
5120\r
5121;@POP BC\r
5122opcode_C_1:\r
5123 opPOPreg z80bc\r
5124\r
5125;@JP NZ,$+3\r
5126opcode_C_2:\r
5127 tst z80f,#1<<ZFlag\r
5128 beq opcode_C_3 ;@unconditional JP\r
5129 add z80pc,z80pc,#2\r
5130 fetch 10\r
5131;@JP $+3\r
5132opcode_C_3:\r
5133 ldrb r0,[z80pc],#1\r
5134 ldrb r1,[z80pc],#1\r
5135 orr r0,r0,r1, lsl #8\r
5136 rebasepc\r
5137 fetch 10\r
5138;@CALL NZ,NN\r
5139opcode_C_4:\r
5140 tst z80f,#1<<ZFlag\r
5141 beq opcode_C_D ;@unconditional CALL\r
5142 add z80pc,z80pc,#2\r
5143 fetch 10\r
5144\r
5145;@PUSH BC\r
5146opcode_C_5:\r
5147 opPUSHreg z80bc\r
5148 fetch 11\r
5149;@ADD A,N\r
5150opcode_C_6:\r
5151 ldrb r0,[z80pc],#1\r
5152 opADDb\r
5153 fetch 7\r
5154;@RST 0\r
5155opcode_C_7:\r
5156 opRST 0x00\r
5157\r
5158;@RET Z\r
5159opcode_C_8:\r
5160 tst z80f,#1<<ZFlag\r
5161 bne opcode_C_9_cond ;@unconditional RET\r
5162 fetch 5\r
5163\r
5164opcode_C_9_cond:\r
5165 eatcycles 1\r
5166;@RET\r
5167opcode_C_9:\r
5168 opPOP\r
5169 rebasepc\r
5170 fetch 10\r
5171;@JP Z,$+3\r
5172opcode_C_A:\r
5173 tst z80f,#1<<ZFlag\r
5174 bne opcode_C_3 ;@unconditional JP\r
5175 add z80pc,z80pc,#2\r
5176 fetch 10\r
5177\r
5178;@This reads this opcodes_CB lookup table to find the location of\r
5179;@the CB sub for the intruction and then branches to that location\r
5180opcode_C_B:\r
5181 ldrb r0,[z80pc],#1\r
5182 ldr pc,[pc,r0, lsl #2]\r
5183opcodes_CB: .word 0x00000000\r
5184 .word opcode_CB_00,opcode_CB_01,opcode_CB_02,opcode_CB_03,opcode_CB_04,opcode_CB_05,opcode_CB_06,opcode_CB_07\r
5185 .word opcode_CB_08,opcode_CB_09,opcode_CB_0A,opcode_CB_0B,opcode_CB_0C,opcode_CB_0D,opcode_CB_0E,opcode_CB_0F\r
5186 .word opcode_CB_10,opcode_CB_11,opcode_CB_12,opcode_CB_13,opcode_CB_14,opcode_CB_15,opcode_CB_16,opcode_CB_17\r
5187 .word opcode_CB_18,opcode_CB_19,opcode_CB_1A,opcode_CB_1B,opcode_CB_1C,opcode_CB_1D,opcode_CB_1E,opcode_CB_1F\r
5188 .word opcode_CB_20,opcode_CB_21,opcode_CB_22,opcode_CB_23,opcode_CB_24,opcode_CB_25,opcode_CB_26,opcode_CB_27\r
5189 .word opcode_CB_28,opcode_CB_29,opcode_CB_2A,opcode_CB_2B,opcode_CB_2C,opcode_CB_2D,opcode_CB_2E,opcode_CB_2F\r
5190 .word opcode_CB_30,opcode_CB_31,opcode_CB_32,opcode_CB_33,opcode_CB_34,opcode_CB_35,opcode_CB_36,opcode_CB_37\r
5191 .word opcode_CB_38,opcode_CB_39,opcode_CB_3A,opcode_CB_3B,opcode_CB_3C,opcode_CB_3D,opcode_CB_3E,opcode_CB_3F\r
5192 .word opcode_CB_40,opcode_CB_41,opcode_CB_42,opcode_CB_43,opcode_CB_44,opcode_CB_45,opcode_CB_46,opcode_CB_47\r
5193 .word opcode_CB_48,opcode_CB_49,opcode_CB_4A,opcode_CB_4B,opcode_CB_4C,opcode_CB_4D,opcode_CB_4E,opcode_CB_4F\r
5194 .word opcode_CB_50,opcode_CB_51,opcode_CB_52,opcode_CB_53,opcode_CB_54,opcode_CB_55,opcode_CB_56,opcode_CB_57\r
5195 .word opcode_CB_58,opcode_CB_59,opcode_CB_5A,opcode_CB_5B,opcode_CB_5C,opcode_CB_5D,opcode_CB_5E,opcode_CB_5F\r
5196 .word opcode_CB_60,opcode_CB_61,opcode_CB_62,opcode_CB_63,opcode_CB_64,opcode_CB_65,opcode_CB_66,opcode_CB_67\r
5197 .word opcode_CB_68,opcode_CB_69,opcode_CB_6A,opcode_CB_6B,opcode_CB_6C,opcode_CB_6D,opcode_CB_6E,opcode_CB_6F\r
5198 .word opcode_CB_70,opcode_CB_71,opcode_CB_72,opcode_CB_73,opcode_CB_74,opcode_CB_75,opcode_CB_76,opcode_CB_77\r
5199 .word opcode_CB_78,opcode_CB_79,opcode_CB_7A,opcode_CB_7B,opcode_CB_7C,opcode_CB_7D,opcode_CB_7E,opcode_CB_7F\r
5200 .word opcode_CB_80,opcode_CB_81,opcode_CB_82,opcode_CB_83,opcode_CB_84,opcode_CB_85,opcode_CB_86,opcode_CB_87\r
5201 .word opcode_CB_88,opcode_CB_89,opcode_CB_8A,opcode_CB_8B,opcode_CB_8C,opcode_CB_8D,opcode_CB_8E,opcode_CB_8F\r
5202 .word opcode_CB_90,opcode_CB_91,opcode_CB_92,opcode_CB_93,opcode_CB_94,opcode_CB_95,opcode_CB_96,opcode_CB_97\r
5203 .word opcode_CB_98,opcode_CB_99,opcode_CB_9A,opcode_CB_9B,opcode_CB_9C,opcode_CB_9D,opcode_CB_9E,opcode_CB_9F\r
5204 .word opcode_CB_A0,opcode_CB_A1,opcode_CB_A2,opcode_CB_A3,opcode_CB_A4,opcode_CB_A5,opcode_CB_A6,opcode_CB_A7\r
5205 .word opcode_CB_A8,opcode_CB_A9,opcode_CB_AA,opcode_CB_AB,opcode_CB_AC,opcode_CB_AD,opcode_CB_AE,opcode_CB_AF\r
5206 .word opcode_CB_B0,opcode_CB_B1,opcode_CB_B2,opcode_CB_B3,opcode_CB_B4,opcode_CB_B5,opcode_CB_B6,opcode_CB_B7\r
5207 .word opcode_CB_B8,opcode_CB_B9,opcode_CB_BA,opcode_CB_BB,opcode_CB_BC,opcode_CB_BD,opcode_CB_BE,opcode_CB_BF\r
5208 .word opcode_CB_C0,opcode_CB_C1,opcode_CB_C2,opcode_CB_C3,opcode_CB_C4,opcode_CB_C5,opcode_CB_C6,opcode_CB_C7\r
5209 .word opcode_CB_C8,opcode_CB_C9,opcode_CB_CA,opcode_CB_CB,opcode_CB_CC,opcode_CB_CD,opcode_CB_CE,opcode_CB_CF\r
5210 .word opcode_CB_D0,opcode_CB_D1,opcode_CB_D2,opcode_CB_D3,opcode_CB_D4,opcode_CB_D5,opcode_CB_D6,opcode_CB_D7\r
5211 .word opcode_CB_D8,opcode_CB_D9,opcode_CB_DA,opcode_CB_DB,opcode_CB_DC,opcode_CB_DD,opcode_CB_DE,opcode_CB_DF\r
5212 .word opcode_CB_E0,opcode_CB_E1,opcode_CB_E2,opcode_CB_E3,opcode_CB_E4,opcode_CB_E5,opcode_CB_E6,opcode_CB_E7\r
5213 .word opcode_CB_E8,opcode_CB_E9,opcode_CB_EA,opcode_CB_EB,opcode_CB_EC,opcode_CB_ED,opcode_CB_EE,opcode_CB_EF\r
5214 .word opcode_CB_F0,opcode_CB_F1,opcode_CB_F2,opcode_CB_F3,opcode_CB_F4,opcode_CB_F5,opcode_CB_F6,opcode_CB_F7\r
5215 .word opcode_CB_F8,opcode_CB_F9,opcode_CB_FA,opcode_CB_FB,opcode_CB_FC,opcode_CB_FD,opcode_CB_FE,opcode_CB_FF\r
5216\r
5217;@CALL Z,NN\r
5218opcode_C_C:\r
5219 tst z80f,#1<<ZFlag\r
5220 bne opcode_C_D ;@unconditional CALL\r
5221 add z80pc,z80pc,#2\r
5222 fetch 10\r
5223;@CALL NN\r
5224opcode_C_D:\r
5225 ldrb r0,[z80pc],#1\r
5226 ldrb r1,[z80pc],#1\r
5227 ldr r2,[cpucontext,#z80pc_base]\r
5228 sub r2,z80pc,r2\r
5229 orr z80pc,r0,r1, lsl #8\r
5230 opPUSHareg r2\r
5231 mov r0,z80pc\r
5232 rebasepc\r
5233 fetch 17\r
5234;@ADC A,N\r
5235opcode_C_E:\r
5236 ldrb r0,[z80pc],#1\r
5237 opADCb\r
5238 fetch 7\r
5239;@RST 8H\r
5240opcode_C_F:\r
5241 opRST 0x08\r
5242\r
5243;@RET NC\r
5244opcode_D_0:\r
5245 tst z80f,#1<<CFlag\r
5246 beq opcode_C_9_cond ;@unconditional RET\r
5247 fetch 5\r
5248;@POP DE\r
5249opcode_D_1:\r
5250 opPOPreg z80de\r
5251\r
5252;@JP NC, $+3\r
5253opcode_D_2 :\r
5254 tst z80f,#1<<CFlag\r
5255 beq opcode_C_3 ;@unconditional JP\r
5256 add z80pc,z80pc,#2\r
5257 fetch 10\r
5258;@OUT (N),A\r
5259opcode_D_3:\r
5260 ldrb r0,[z80pc],#1\r
5261 orr r0,r0,z80a,lsr#16\r
5262 mov r1,z80a, lsr #24\r
5263 opOUT\r
5264 fetch 11\r
5265;@CALL NC,NN\r
5266opcode_D_4:\r
5267 tst z80f,#1<<CFlag\r
5268 beq opcode_C_D ;@unconditional CALL\r
5269 add z80pc,z80pc,#2\r
5270 fetch 10\r
5271;@PUSH DE\r
5272opcode_D_5:\r
5273 opPUSHreg z80de\r
5274 fetch 11\r
5275;@SUB N\r
5276opcode_D_6:\r
5277 ldrb r0,[z80pc],#1\r
5278 opSUBb\r
5279 fetch 7\r
5280\r
5281;@RST 10H\r
5282opcode_D_7:\r
5283 opRST 0x10\r
5284\r
5285;@RET C\r
5286opcode_D_8:\r
5287 tst z80f,#1<<CFlag\r
5288 bne opcode_C_9_cond ;@unconditional RET\r
5289 fetch 5\r
5290;@EXX\r
5291opcode_D_9:\r
5292 add r1,cpucontext,#z80bc2\r
5293 swp z80bc,z80bc,[r1]\r
5294 add r1,cpucontext,#z80de2\r
5295 swp z80de,z80de,[r1]\r
5296 add r1,cpucontext,#z80hl2\r
5297 swp z80hl,z80hl,[r1]\r
5298 fetch 4\r
5299;@JP C,$+3\r
5300opcode_D_A:\r
5301 tst z80f,#1<<CFlag\r
5302 bne opcode_C_3 ;@unconditional JP\r
5303 add z80pc,z80pc,#2\r
5304 fetch 10\r
5305;@IN A,(N)\r
5306opcode_D_B:\r
5307 ldrb r0,[z80pc],#1\r
5308 orr r0,r0,z80a,lsr#16\r
5309 opIN\r
5310 mov z80a,r0, lsl #24 ;@ r0 = data read\r
5311 fetch 11\r
5312;@CALL C,NN\r
5313opcode_D_C:\r
5314 tst z80f,#1<<CFlag\r
5315 bne opcode_C_D ;@unconditional CALL\r
5316 add z80pc,z80pc,#2\r
5317 fetch 10\r
5318\r
5319;@opcodes_DD\r
5320opcode_D_D:\r
5321 add z80xx,cpucontext,#z80ix\r
5322 b opcode_D_D_F_D\r
5323opcode_F_D:\r
5324 add z80xx,cpucontext,#z80iy\r
5325opcode_D_D_F_D:\r
5326 ldrb r0,[z80pc],#1\r
5327 ldr pc,[pc,r0, lsl #2]\r
5328opcodes_DD: .word 0x00000000\r
5329 .word opcode_0_0, opcode_0_1, opcode_0_2, opcode_0_3, opcode_0_4, opcode_0_5, opcode_0_6, opcode_0_7\r
5330 .word opcode_0_8, opcode_DD_09,opcode_0_A, opcode_0_B, opcode_0_C, opcode_0_D, opcode_0_E, opcode_0_F\r
5331 .word opcode_1_0, opcode_1_1, opcode_1_2, opcode_1_3, opcode_1_4, opcode_1_5, opcode_1_6, opcode_1_7\r
5332 .word opcode_1_8, opcode_DD_19,opcode_1_A, opcode_1_B, opcode_1_C, opcode_1_D, opcode_1_E, opcode_1_F\r
5333 .word opcode_2_0, opcode_DD_21,opcode_DD_22,opcode_DD_23,opcode_DD_24,opcode_DD_25,opcode_DD_26,opcode_2_7\r
5334 .word opcode_2_8, opcode_DD_29,opcode_DD_2A,opcode_DD_2B,opcode_DD_2C,opcode_DD_2D,opcode_DD_2E,opcode_2_F\r
5335 .word opcode_3_0, opcode_3_1, opcode_3_2, opcode_3_3, opcode_DD_34,opcode_DD_35,opcode_DD_36,opcode_3_7\r
5336 .word opcode_3_8, opcode_DD_39,opcode_3_A, opcode_3_B, opcode_3_C, opcode_3_D, opcode_3_E, opcode_3_F\r
5337 .word opcode_4_0, opcode_4_1, opcode_4_2, opcode_4_3, opcode_DD_44,opcode_DD_45,opcode_DD_46,opcode_4_7\r
5338 .word opcode_4_8, opcode_4_9, opcode_4_A, opcode_4_B, opcode_DD_4C,opcode_DD_4D,opcode_DD_4E,opcode_4_F\r
5339 .word opcode_5_0, opcode_5_1, opcode_5_2, opcode_5_3, opcode_DD_54,opcode_DD_55,opcode_DD_56,opcode_5_7\r
5340 .word opcode_5_8, opcode_5_9, opcode_5_A, opcode_5_B, opcode_DD_5C,opcode_DD_5D,opcode_DD_5E,opcode_5_F\r
5341 .word opcode_DD_60,opcode_DD_61,opcode_DD_62,opcode_DD_63,opcode_DD_64,opcode_DD_65,opcode_DD_66,opcode_DD_67\r
5342 .word opcode_DD_68,opcode_DD_69,opcode_DD_6A,opcode_DD_6B,opcode_DD_6C,opcode_DD_6D,opcode_DD_6E,opcode_DD_6F\r
5343 .word opcode_DD_70,opcode_DD_71,opcode_DD_72,opcode_DD_73,opcode_DD_74,opcode_DD_75,opcode_7_6, opcode_DD_77\r
5344 .word opcode_7_8, opcode_7_9, opcode_7_A, opcode_7_B, opcode_DD_7C,opcode_DD_7D,opcode_DD_7E,opcode_7_F\r
5345 .word opcode_8_0, opcode_8_1, opcode_8_2, opcode_8_3, opcode_DD_84,opcode_DD_85,opcode_DD_86,opcode_8_7\r
5346 .word opcode_8_8, opcode_8_9, opcode_8_A, opcode_8_B, opcode_DD_8C,opcode_DD_8D,opcode_DD_8E,opcode_8_F\r
5347 .word opcode_9_0, opcode_9_1, opcode_9_2, opcode_9_3, opcode_DD_94,opcode_DD_95,opcode_DD_96,opcode_9_7\r
5348 .word opcode_9_8, opcode_9_9, opcode_9_A, opcode_9_B, opcode_DD_9C,opcode_DD_9D,opcode_DD_9E,opcode_9_F\r
5349 .word opcode_A_0, opcode_A_1, opcode_A_2, opcode_A_3, opcode_DD_A4,opcode_DD_A5,opcode_DD_A6,opcode_A_7\r
5350 .word opcode_A_8, opcode_A_9, opcode_A_A, opcode_A_B, opcode_DD_AC,opcode_DD_AD,opcode_DD_AE,opcode_A_F\r
5351 .word opcode_B_0, opcode_B_1, opcode_B_2, opcode_B_3, opcode_DD_B4,opcode_DD_B5,opcode_DD_B6,opcode_B_7\r
5352 .word opcode_B_8, opcode_B_9, opcode_B_A, opcode_B_B, opcode_DD_BC,opcode_DD_BD,opcode_DD_BE,opcode_B_F\r
5353 .word opcode_C_0, opcode_C_1, opcode_C_2, opcode_C_3, opcode_C_4, opcode_C_5, opcode_C_6, opcode_C_7\r
5354 .word opcode_C_8, opcode_C_9, opcode_C_A, opcode_DD_CB,opcode_C_C, opcode_C_D, opcode_C_E, opcode_C_F\r
5355 .word opcode_D_0, opcode_D_1, opcode_D_2, opcode_D_3, opcode_D_4, opcode_D_5, opcode_D_6, opcode_D_7\r
5356 .word opcode_D_8, opcode_D_9, opcode_D_A, opcode_D_B, opcode_D_C, opcode_D_D, opcode_D_E, opcode_D_F\r
5357 .word opcode_E_0, opcode_DD_E1,opcode_E_2, opcode_DD_E3,opcode_E_4, opcode_DD_E5,opcode_E_6, opcode_E_7\r
5358 .word opcode_E_8, opcode_DD_E9,opcode_E_A, opcode_E_B, opcode_E_C, opcode_E_D, opcode_E_E, opcode_E_F\r
5359 .word opcode_F_0, opcode_F_1, opcode_F_2, opcode_F_3, opcode_F_4, opcode_F_5, opcode_F_6, opcode_F_7\r
5360 .word opcode_F_8, opcode_DD_F9,opcode_F_A, opcode_F_B, opcode_F_C, opcode_F_D, opcode_F_E, opcode_F_F\r
5361\r
5362;@SBC A,N\r
5363opcode_D_E:\r
5364 ldrb r0,[z80pc],#1\r
5365 opSBCb\r
5366 fetch 7\r
5367;@RST 18H\r
5368opcode_D_F:\r
5369 opRST 0x18\r
5370\r
5371;@RET PO\r
5372opcode_E_0:\r
5373 tst z80f,#1<<VFlag\r
5374 beq opcode_C_9_cond ;@unconditional RET\r
5375 fetch 5\r
5376;@POP HL\r
5377opcode_E_1:\r
5378 opPOPreg z80hl\r
5379\r
5380;@JP PO,$+3\r
5381opcode_E_2:\r
5382 tst z80f,#1<<VFlag\r
5383 beq opcode_C_3 ;@unconditional JP\r
5384 add z80pc,z80pc,#2\r
5385 fetch 10\r
5386;@EX (SP),HL\r
5387opcode_E_3:\r
5388.if FAST_Z80SP\r
5389 ldrb r0,[z80sp]\r
5390 ldrb r1,[z80sp,#1]\r
5391 orr r0,r0,r1, lsl #8\r
5392 mov r1,z80hl, lsr #24\r
5393 strb r1,[z80sp,#1]\r
5394 mov r1,z80hl, lsr #16\r
5395 strb r1,[z80sp]\r
5396 mov z80hl,r0, lsl #16\r
5397.else\r
5398 mov r0,z80sp\r
5399 readmem16\r
5400 mov r1,r0\r
5401 mov r0,z80hl,lsr#16\r
5402 mov z80hl,r1,lsl#16\r
5403 mov r1,z80sp\r
5404 writemem16\r
5405.endif\r
5406 fetch 19\r
5407;@CALL PO,NN\r
5408opcode_E_4:\r
5409 tst z80f,#1<<VFlag\r
5410 beq opcode_C_D ;@unconditional CALL\r
5411 add z80pc,z80pc,#2\r
5412 fetch 10\r
5413;@PUSH HL\r
5414opcode_E_5:\r
5415 opPUSHreg z80hl\r
5416 fetch 11\r
5417;@AND N\r
5418opcode_E_6:\r
5419 ldrb r0,[z80pc],#1\r
5420 opANDb\r
5421 fetch 7\r
5422;@RST 20H\r
5423opcode_E_7:\r
5424 opRST 0x20\r
5425\r
5426;@RET PE\r
5427opcode_E_8:\r
5428 tst z80f,#1<<VFlag\r
5429 bne opcode_C_9_cond ;@unconditional RET\r
5430 fetch 5\r
5431;@JP (HL)\r
5432opcode_E_9:\r
5433 mov r0,z80hl, lsr #16\r
5434 rebasepc\r
5435 fetch 4\r
5436;@JP PE,$+3\r
5437opcode_E_A:\r
5438 tst z80f,#1<<VFlag\r
5439 bne opcode_C_3 ;@unconditional JP\r
5440 add z80pc,z80pc,#2\r
5441 fetch 10\r
5442;@EX DE,HL\r
5443opcode_E_B:\r
5444 mov r1,z80de\r
5445 mov z80de,z80hl\r
5446 mov z80hl,r1\r
5447 fetch 4\r
5448;@CALL PE,NN\r
5449opcode_E_C:\r
5450 tst z80f,#1<<VFlag\r
5451 bne opcode_C_D ;@unconditional CALL\r
5452 add z80pc,z80pc,#2\r
5453 fetch 10\r
5454\r
5455;@This should be caught at start\r
5456opcode_E_D:\r
5457 ldrb r1,[z80pc],#1\r
5458 ldr pc,[pc,r1, lsl #2]\r
5459opcodes_ED: .word 0x00000000\r
5460 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5461 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5462 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5463 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5464 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5465 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5466 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5467 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5468 .word opcode_ED_40,opcode_ED_41,opcode_ED_42,opcode_ED_43,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_47\r
5469 .word opcode_ED_48,opcode_ED_49,opcode_ED_4A,opcode_ED_4B,opcode_ED_44,opcode_ED_4D,opcode_ED_46,opcode_ED_4F\r
5470 .word opcode_ED_50,opcode_ED_51,opcode_ED_52,opcode_ED_53,opcode_ED_44,opcode_ED_45,opcode_ED_56,opcode_ED_57\r
5471 .word opcode_ED_58,opcode_ED_59,opcode_ED_5A,opcode_ED_5B,opcode_ED_44,opcode_ED_45,opcode_ED_5E,opcode_ED_5F\r
5472 .word opcode_ED_60,opcode_ED_61,opcode_ED_62,opcode_ED_63,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_67\r
5473 .word opcode_ED_68,opcode_ED_69,opcode_ED_6A,opcode_ED_6B,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_6F\r
5474 .word opcode_ED_70,opcode_ED_71,opcode_ED_72,opcode_ED_73,opcode_ED_44,opcode_ED_45,opcode_ED_56,opcode_ED_NF\r
5475 .word opcode_ED_78,opcode_ED_79,opcode_ED_7A,opcode_ED_7B,opcode_ED_44,opcode_ED_45,opcode_ED_5E,opcode_ED_NF\r
5476 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5477 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5478 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5479 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5480 .word opcode_ED_A0,opcode_ED_A1,opcode_ED_A2,opcode_ED_A3,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5481 .word opcode_ED_A8,opcode_ED_A9,opcode_ED_AA,opcode_ED_AB,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5482 .word opcode_ED_B0,opcode_ED_B1,opcode_ED_B2,opcode_ED_B3,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5483 .word opcode_ED_B8,opcode_ED_B9,opcode_ED_BA,opcode_ED_BB,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5484 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5485 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5486 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5487 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5488 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5489 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5490 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5491 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5492\r
5493;@XOR N\r
5494opcode_E_E:\r
5495 ldrb r0,[z80pc],#1\r
5496 opXORb\r
5497 fetch 7\r
5498;@RST 28H\r
5499opcode_E_F:\r
5500 opRST 0x28\r
5501\r
5502;@RET P\r
5503opcode_F_0:\r
5504 tst z80f,#1<<SFlag\r
5505 beq opcode_C_9_cond ;@unconditional RET\r
5506 fetch 5\r
5507;@POP AF\r
5508opcode_F_1:\r
5509.if FAST_Z80SP\r
5510 ldrb z80f,[z80sp],#1\r
5511 sub r0,opcodes,#0x200\r
5512 ldrb z80f,[r0,z80f]\r
5513 ldrb z80a,[z80sp],#1\r
5514 mov z80a,z80a, lsl #24\r
5515.else\r
5516 mov r0,z80sp\r
5517 readmem16\r
5518 add z80sp,z80sp,#2\r
5519 and z80a,r0,#0xFF00\r
5520 mov z80a,z80a,lsl#16\r
5521 and z80f,r0,#0xFF\r
5522 sub r0,opcodes,#0x200\r
5523 ldrb z80f,[r0,z80f]\r
5524.endif\r
5525 fetch 10\r
5526;@JP P,$+3\r
5527opcode_F_2:\r
5528 tst z80f,#1<<SFlag\r
5529 beq opcode_C_3 ;@unconditional JP\r
5530 add z80pc,z80pc,#2\r
5531 fetch 10\r
5532;@DI\r
5533opcode_F_3:\r
5534 ldrb r1,[cpucontext,#z80if]\r
5535 bic r1,r1,#(Z80_IF1)|(Z80_IF2)\r
5536 strb r1,[cpucontext,#z80if]\r
5537 fetch 4\r
5538;@CALL P,NN\r
5539opcode_F_4:\r
5540 tst z80f,#1<<SFlag\r
5541 beq opcode_C_D ;@unconditional CALL\r
5542 add z80pc,z80pc,#2\r
5543 fetch 10\r
5544;@PUSH AF\r
5545opcode_F_5:\r
5546 sub r0,opcodes,#0x300\r
5547 ldrb r0,[r0,z80f]\r
5548 orr r2,r0,z80a,lsr#16\r
5549 opPUSHareg r2\r
5550 fetch 11\r
5551;@OR N\r
5552opcode_F_6:\r
5553 ldrb r0,[z80pc],#1\r
5554 opORb\r
5555 fetch 7\r
5556;@RST 30H\r
5557opcode_F_7:\r
5558 opRST 0x30\r
5559\r
5560;@RET M\r
5561opcode_F_8:\r
5562 tst z80f,#1<<SFlag\r
5563 bne opcode_C_9_cond ;@unconditional RET\r
5564 fetch 5\r
5565;@LD SP,HL\r
5566opcode_F_9:\r
5567.if FAST_Z80SP\r
5568 mov r0,z80hl, lsr #16\r
5569 rebasesp\r
5570 mov z80sp,r0\r
5571.else\r
5572 mov z80sp,z80hl, lsr #16\r
5573.endif\r
5574 fetch 6\r
5575;@JP M,$+3\r
5576opcode_F_A:\r
5577 tst z80f,#1<<SFlag\r
5578 bne opcode_C_3 ;@unconditional JP\r
5579 add z80pc,z80pc,#2\r
5580 fetch 10\r
5581MAIN_opcodes_POINTER: .word MAIN_opcodes\r
5582EI_DUMMY_opcodes_POINTER: .word EI_DUMMY_opcodes\r
5583;@EI\r
5584opcode_F_B:\r
5585 ldrb r1,[cpucontext,#z80if]\r
5586 mov r2,opcodes\r
5587 orr r1,r1,#(Z80_IF1)|(Z80_IF2)\r
5588 strb r1,[cpucontext,#z80if]\r
5589\r
5590 ldrb r0,[z80pc],#1\r
5591 eatcycles 4\r
5592 ldr opcodes,EI_DUMMY_opcodes_POINTER\r
5593 ldr pc,[r2,r0, lsl #2]\r
5594\r
5595ei_return:\r
5596 ;@point that program returns from EI to check interupts\r
5597 ;@an interupt can not be taken directly after a EI opcode\r
5598 ;@ reset z80pc and opcode pointer\r
5599 ldrh r0,[cpucontext,#z80irq] @ 0x4C, irq and IFF bits\r
5600 sub z80pc,z80pc,#1\r
5601 ldr opcodes,MAIN_opcodes_POINTER\r
5602 ;@ check ints\r
5603 tst r0,#0xff\r
5604 movne r0,r0,lsr #8\r
5605 tstne r0,#1\r
5606 blne DoInterrupt\r
5607\r
5608 ;@ continue\r
5609 fetch 0\r
5610\r
5611;@CALL M,NN\r
5612opcode_F_C:\r
5613 tst z80f,#1<<SFlag\r
5614 bne opcode_C_D ;@unconditional CALL\r
5615 add z80pc,z80pc,#2\r
5616 fetch 10\r
5617\r
5618;@SHOULD BE CAUGHT AT START - FD SECTION\r
5619\r
5620;@CP N\r
5621opcode_F_E:\r
5622 ldrb r0,[z80pc],#1\r
5623 opCPb\r
5624 fetch 7\r
5625;@RST 38H\r
5626opcode_F_F:\r
5627 opRST 0x38\r
5628\r
5629\r
5630;@##################################\r
5631;@##################################\r
5632;@### opcodes CB #########################\r
5633;@##################################\r
5634;@##################################\r
5635\r
5636\r
5637;@RLC B\r
5638opcode_CB_00:\r
5639 opRLCH z80bc\r
5640;@RLC C\r
5641opcode_CB_01:\r
5642 opRLCL z80bc\r
5643;@RLC D\r
5644opcode_CB_02:\r
5645 opRLCH z80de\r
5646;@RLC E\r
5647opcode_CB_03:\r
5648 opRLCL z80de\r
5649;@RLC H\r
5650opcode_CB_04:\r
5651 opRLCH z80hl\r
5652;@RLC L\r
5653opcode_CB_05:\r
5654 opRLCL z80hl\r
5655;@RLC (HL)\r
5656opcode_CB_06:\r
5657 readmem8HL\r
5658 opRLCb\r
5659 writemem8HL\r
5660 fetch 15\r
5661;@RLC A\r
5662opcode_CB_07:\r
5663 opRLCA\r
5664\r
5665;@RRC B\r
5666opcode_CB_08:\r
5667 opRRCH z80bc\r
5668;@RRC C\r
5669opcode_CB_09:\r
5670 opRRCL z80bc\r
5671;@RRC D\r
5672opcode_CB_0A:\r
5673 opRRCH z80de\r
5674;@RRC E\r
5675opcode_CB_0B:\r
5676 opRRCL z80de\r
5677;@RRC H\r
5678opcode_CB_0C:\r
5679 opRRCH z80hl\r
5680;@RRC L\r
5681opcode_CB_0D:\r
5682 opRRCL z80hl\r
5683;@RRC (HL)\r
5684opcode_CB_0E :\r
5685 readmem8HL\r
5686 opRRCb\r
5687 writemem8HL\r
5688 fetch 15\r
5689;@RRC A\r
5690opcode_CB_0F:\r
5691 opRRCA\r
5692\r
5693;@RL B\r
5694opcode_CB_10:\r
5695 opRLH z80bc\r
5696;@RL C\r
5697opcode_CB_11:\r
5698 opRLL z80bc\r
5699;@RL D\r
5700opcode_CB_12:\r
5701 opRLH z80de\r
5702;@RL E\r
5703opcode_CB_13:\r
5704 opRLL z80de\r
5705;@RL H\r
5706opcode_CB_14:\r
5707 opRLH z80hl\r
5708;@RL L\r
5709opcode_CB_15:\r
5710 opRLL z80hl\r
5711;@RL (HL)\r
5712opcode_CB_16:\r
5713 readmem8HL\r
5714 opRLb\r
5715 writemem8HL\r
5716 fetch 15\r
5717;@RL A\r
5718opcode_CB_17:\r
5719 opRLA\r
5720\r
5721;@RR B \r
5722opcode_CB_18:\r
5723 opRRH z80bc\r
5724;@RR C\r
5725opcode_CB_19:\r
5726 opRRL z80bc\r
5727;@RR D\r
5728opcode_CB_1A:\r
5729 opRRH z80de\r
5730;@RR E\r
5731opcode_CB_1B:\r
5732 opRRL z80de\r
5733;@RR H\r
5734opcode_CB_1C:\r
5735 opRRH z80hl\r
5736;@RR L\r
5737opcode_CB_1D:\r
5738 opRRL z80hl\r
5739;@RR (HL)\r
5740opcode_CB_1E:\r
5741 readmem8HL\r
5742 opRRb\r
5743 writemem8HL\r
5744 fetch 15\r
5745;@RR A\r
5746opcode_CB_1F:\r
5747 opRRA\r
5748\r
5749;@SLA B\r
5750opcode_CB_20:\r
5751 opSLAH z80bc\r
5752;@SLA C\r
5753opcode_CB_21:\r
5754 opSLAL z80bc\r
5755;@SLA D\r
5756opcode_CB_22:\r
5757 opSLAH z80de\r
5758;@SLA E\r
5759opcode_CB_23:\r
5760 opSLAL z80de\r
5761;@SLA H\r
5762opcode_CB_24:\r
5763 opSLAH z80hl\r
5764;@SLA L\r
5765opcode_CB_25:\r
5766 opSLAL z80hl\r
5767;@SLA (HL)\r
5768opcode_CB_26:\r
5769 readmem8HL\r
5770 opSLAb\r
5771 writemem8HL\r
5772 fetch 15\r
5773;@SLA A\r
5774opcode_CB_27:\r
5775 opSLAA\r
5776\r
5777;@SRA B\r
5778opcode_CB_28:\r
5779 opSRAH z80bc\r
5780;@SRA C\r
5781opcode_CB_29:\r
5782 opSRAL z80bc\r
5783;@SRA D\r
5784opcode_CB_2A:\r
5785 opSRAH z80de\r
5786;@SRA E\r
5787opcode_CB_2B:\r
5788 opSRAL z80de\r
5789;@SRA H\r
5790opcode_CB_2C:\r
5791 opSRAH z80hl\r
5792;@SRA L\r
5793opcode_CB_2D:\r
5794 opSRAL z80hl\r
5795;@SRA (HL)\r
5796opcode_CB_2E:\r
5797 readmem8HL\r
5798 opSRAb\r
5799 writemem8HL\r
5800 fetch 15\r
5801;@SRA A\r
5802opcode_CB_2F:\r
5803 opSRAA\r
5804\r
5805;@SLL B\r
5806opcode_CB_30:\r
5807 opSLLH z80bc\r
5808;@SLL C\r
5809opcode_CB_31:\r
5810 opSLLL z80bc\r
5811;@SLL D\r
5812opcode_CB_32:\r
5813 opSLLH z80de\r
5814;@SLL E\r
5815opcode_CB_33:\r
5816 opSLLL z80de\r
5817;@SLL H\r
5818opcode_CB_34:\r
5819 opSLLH z80hl\r
5820;@SLL L\r
5821opcode_CB_35:\r
5822 opSLLL z80hl\r
5823;@SLL (HL)\r
5824opcode_CB_36:\r
5825 readmem8HL\r
5826 opSLLb\r
5827 writemem8HL\r
5828 fetch 15\r
5829;@SLL A\r
5830opcode_CB_37:\r
5831 opSLLA\r
5832\r
5833;@SRL B\r
5834opcode_CB_38:\r
5835 opSRLH z80bc\r
5836;@SRL C\r
5837opcode_CB_39:\r
5838 opSRLL z80bc\r
5839;@SRL D\r
5840opcode_CB_3A:\r
5841 opSRLH z80de\r
5842;@SRL E\r
5843opcode_CB_3B:\r
5844 opSRLL z80de\r
5845;@SRL H\r
5846opcode_CB_3C:\r
5847 opSRLH z80hl\r
5848;@SRL L\r
5849opcode_CB_3D:\r
5850 opSRLL z80hl\r
5851;@SRL (HL)\r
5852opcode_CB_3E:\r
5853 readmem8HL\r
5854 opSRLb\r
5855 writemem8HL\r
5856 fetch 15\r
5857;@SRL A\r
5858opcode_CB_3F:\r
5859 opSRLA\r
5860\r
5861\r
5862;@BIT 0,B\r
5863opcode_CB_40:\r
5864 opBITH z80bc 0\r
5865;@BIT 0,C\r
5866opcode_CB_41:\r
5867 opBITL z80bc 0\r
5868;@BIT 0,D\r
5869opcode_CB_42:\r
5870 opBITH z80de 0\r
5871;@BIT 0,E\r
5872opcode_CB_43:\r
5873 opBITL z80de 0\r
5874;@BIT 0,H\r
5875opcode_CB_44:\r
5876 opBITH z80hl 0\r
5877;@BIT 0,L\r
5878opcode_CB_45:\r
5879 opBITL z80hl 0\r
5880;@BIT 0,(HL)\r
5881opcode_CB_46:\r
5882 readmem8HL\r
5883 opBITb 0\r
5884 fetch 12\r
5885;@BIT 0,A\r
5886opcode_CB_47:\r
5887 opBITH z80a 0\r
5888\r
5889;@BIT 1,B\r
5890opcode_CB_48:\r
5891 opBITH z80bc 1\r
5892;@BIT 1,C\r
5893opcode_CB_49:\r
5894 opBITL z80bc 1\r
5895;@BIT 1,D\r
5896opcode_CB_4A:\r
5897 opBITH z80de 1\r
5898;@BIT 1,E\r
5899opcode_CB_4B:\r
5900 opBITL z80de 1\r
5901;@BIT 1,H\r
5902opcode_CB_4C:\r
5903 opBITH z80hl 1\r
5904;@BIT 1,L\r
5905opcode_CB_4D:\r
5906 opBITL z80hl 1\r
5907;@BIT 1,(HL)\r
5908opcode_CB_4E:\r
5909 readmem8HL\r
5910 opBITb 1\r
5911 fetch 12\r
5912;@BIT 1,A\r
5913opcode_CB_4F:\r
5914 opBITH z80a 1\r
5915\r
5916;@BIT 2,B\r
5917opcode_CB_50:\r
5918 opBITH z80bc 2\r
5919;@BIT 2,C\r
5920opcode_CB_51:\r
5921 opBITL z80bc 2\r
5922;@BIT 2,D\r
5923opcode_CB_52:\r
5924 opBITH z80de 2\r
5925;@BIT 2,E\r
5926opcode_CB_53:\r
5927 opBITL z80de 2\r
5928;@BIT 2,H\r
5929opcode_CB_54:\r
5930 opBITH z80hl 2\r
5931;@BIT 2,L\r
5932opcode_CB_55:\r
5933 opBITL z80hl 2\r
5934;@BIT 2,(HL)\r
5935opcode_CB_56:\r
5936 readmem8HL\r
5937 opBITb 2\r
5938 fetch 12\r
5939;@BIT 2,A\r
5940opcode_CB_57:\r
5941 opBITH z80a 2\r
5942\r
5943;@BIT 3,B\r
5944opcode_CB_58:\r
5945 opBITH z80bc 3\r
5946;@BIT 3,C\r
5947opcode_CB_59:\r
5948 opBITL z80bc 3\r
5949;@BIT 3,D\r
5950opcode_CB_5A:\r
5951 opBITH z80de 3\r
5952;@BIT 3,E\r
5953opcode_CB_5B:\r
5954 opBITL z80de 3\r
5955;@BIT 3,H\r
5956opcode_CB_5C:\r
5957 opBITH z80hl 3\r
5958;@BIT 3,L\r
5959opcode_CB_5D:\r
5960 opBITL z80hl 3\r
5961;@BIT 3,(HL)\r
5962opcode_CB_5E:\r
5963 readmem8HL\r
5964 opBITb 3\r
5965 fetch 12\r
5966;@BIT 3,A\r
5967opcode_CB_5F:\r
5968 opBITH z80a 3\r
5969\r
5970;@BIT 4,B\r
5971opcode_CB_60:\r
5972 opBITH z80bc 4\r
5973;@BIT 4,C\r
5974opcode_CB_61:\r
5975 opBITL z80bc 4\r
5976;@BIT 4,D\r
5977opcode_CB_62:\r
5978 opBITH z80de 4\r
5979;@BIT 4,E\r
5980opcode_CB_63:\r
5981 opBITL z80de 4\r
5982;@BIT 4,H\r
5983opcode_CB_64:\r
5984 opBITH z80hl 4\r
5985;@BIT 4,L\r
5986opcode_CB_65:\r
5987 opBITL z80hl 4\r
5988;@BIT 4,(HL)\r
5989opcode_CB_66:\r
5990 readmem8HL\r
5991 opBITb 4\r
5992 fetch 12\r
5993;@BIT 4,A\r
5994opcode_CB_67:\r
5995 opBITH z80a 4\r
5996\r
5997;@BIT 5,B\r
5998opcode_CB_68:\r
5999 opBITH z80bc 5\r
6000;@BIT 5,C\r
6001opcode_CB_69:\r
6002 opBITL z80bc 5\r
6003;@BIT 5,D\r
6004opcode_CB_6A:\r
6005 opBITH z80de 5\r
6006;@BIT 5,E\r
6007opcode_CB_6B:\r
6008 opBITL z80de 5\r
6009;@BIT 5,H\r
6010opcode_CB_6C:\r
6011 opBITH z80hl 5\r
6012;@BIT 5,L\r
6013opcode_CB_6D:\r
6014 opBITL z80hl 5\r
6015;@BIT 5,(HL)\r
6016opcode_CB_6E:\r
6017 readmem8HL\r
6018 opBITb 5\r
6019 fetch 12\r
6020;@BIT 5,A\r
6021opcode_CB_6F:\r
6022 opBITH z80a 5\r
6023\r
6024;@BIT 6,B\r
6025opcode_CB_70:\r
6026 opBITH z80bc 6\r
6027;@BIT 6,C\r
6028opcode_CB_71:\r
6029 opBITL z80bc 6\r
6030;@BIT 6,D\r
6031opcode_CB_72:\r
6032 opBITH z80de 6\r
6033;@BIT 6,E\r
6034opcode_CB_73:\r
6035 opBITL z80de 6\r
6036;@BIT 6,H\r
6037opcode_CB_74:\r
6038 opBITH z80hl 6\r
6039;@BIT 6,L\r
6040opcode_CB_75:\r
6041 opBITL z80hl 6\r
6042;@BIT 6,(HL)\r
6043opcode_CB_76:\r
6044 readmem8HL\r
6045 opBITb 6\r
6046 fetch 12\r
6047;@BIT 6,A\r
6048opcode_CB_77:\r
6049 opBITH z80a 6\r
6050\r
6051;@BIT 7,B\r
6052opcode_CB_78:\r
6053 opBIT7H z80bc\r
6054;@BIT 7,C\r
6055opcode_CB_79:\r
6056 opBIT7L z80bc\r
6057;@BIT 7,D\r
6058opcode_CB_7A:\r
6059 opBIT7H z80de\r
6060;@BIT 7,E\r
6061opcode_CB_7B:\r
6062 opBIT7L z80de\r
6063;@BIT 7,H\r
6064opcode_CB_7C:\r
6065 opBIT7H z80hl\r
6066;@BIT 7,L\r
6067opcode_CB_7D:\r
6068 opBIT7L z80hl\r
6069;@BIT 7,(HL)\r
6070opcode_CB_7E:\r
6071 readmem8HL\r
6072 opBIT7b\r
6073 fetch 12\r
6074;@BIT 7,A\r
6075opcode_CB_7F:\r
6076 opBIT7H z80a\r
6077\r
6078;@RES 0,B\r
6079opcode_CB_80:\r
6080 bic z80bc,z80bc,#1<<24\r
6081 fetch 8\r
6082;@RES 0,C\r
6083opcode_CB_81:\r
6084 bic z80bc,z80bc,#1<<16\r
6085 fetch 8\r
6086;@RES 0,D\r
6087opcode_CB_82:\r
6088 bic z80de,z80de,#1<<24\r
6089 fetch 8\r
6090;@RES 0,E\r
6091opcode_CB_83:\r
6092 bic z80de,z80de,#1<<16\r
6093 fetch 8\r
6094;@RES 0,H\r
6095opcode_CB_84:\r
6096 bic z80hl,z80hl,#1<<24\r
6097 fetch 8\r
6098;@RES 0,L\r
6099opcode_CB_85:\r
6100 bic z80hl,z80hl,#1<<16\r
6101 fetch 8\r
6102;@RES 0,(HL)\r
6103opcode_CB_86:\r
6104 opRESmemHL 0\r
6105;@RES 0,A\r
6106opcode_CB_87:\r
6107 bic z80a,z80a,#1<<24\r
6108 fetch 8\r
6109\r
6110;@RES 1,B\r
6111opcode_CB_88:\r
6112 bic z80bc,z80bc,#1<<25\r
6113 fetch 8\r
6114;@RES 1,C\r
6115opcode_CB_89:\r
6116 bic z80bc,z80bc,#1<<17\r
6117 fetch 8\r
6118;@RES 1,D\r
6119opcode_CB_8A:\r
6120 bic z80de,z80de,#1<<25\r
6121 fetch 8\r
6122;@RES 1,E\r
6123opcode_CB_8B:\r
6124 bic z80de,z80de,#1<<17\r
6125 fetch 8\r
6126;@RES 1,H\r
6127opcode_CB_8C:\r
6128 bic z80hl,z80hl,#1<<25\r
6129 fetch 8\r
6130;@RES 1,L\r
6131opcode_CB_8D:\r
6132 bic z80hl,z80hl,#1<<17\r
6133 fetch 8\r
6134;@RES 1,(HL)\r
6135opcode_CB_8E:\r
6136 opRESmemHL 1\r
6137;@RES 1,A\r
6138opcode_CB_8F:\r
6139 bic z80a,z80a,#1<<25\r
6140 fetch 8\r
6141\r
6142;@RES 2,B\r
6143opcode_CB_90:\r
6144 bic z80bc,z80bc,#1<<26\r
6145 fetch 8\r
6146;@RES 2,C\r
6147opcode_CB_91:\r
6148 bic z80bc,z80bc,#1<<18\r
6149 fetch 8\r
6150;@RES 2,D\r
6151opcode_CB_92:\r
6152 bic z80de,z80de,#1<<26\r
6153 fetch 8\r
6154;@RES 2,E\r
6155opcode_CB_93:\r
6156 bic z80de,z80de,#1<<18\r
6157 fetch 8\r
6158;@RES 2,H\r
6159opcode_CB_94:\r
6160 bic z80hl,z80hl,#1<<26\r
6161 fetch 8\r
6162;@RES 2,L\r
6163opcode_CB_95:\r
6164 bic z80hl,z80hl,#1<<18\r
6165 fetch 8\r
6166;@RES 2,(HL)\r
6167opcode_CB_96:\r
6168 opRESmemHL 2\r
6169;@RES 2,A\r
6170opcode_CB_97:\r
6171 bic z80a,z80a,#1<<26\r
6172 fetch 8\r
6173\r
6174;@RES 3,B\r
6175opcode_CB_98:\r
6176 bic z80bc,z80bc,#1<<27\r
6177 fetch 8\r
6178;@RES 3,C\r
6179opcode_CB_99:\r
6180 bic z80bc,z80bc,#1<<19\r
6181 fetch 8\r
6182;@RES 3,D\r
6183opcode_CB_9A:\r
6184 bic z80de,z80de,#1<<27\r
6185 fetch 8\r
6186;@RES 3,E\r
6187opcode_CB_9B:\r
6188 bic z80de,z80de,#1<<19\r
6189 fetch 8\r
6190;@RES 3,H\r
6191opcode_CB_9C:\r
6192 bic z80hl,z80hl,#1<<27\r
6193 fetch 8\r
6194;@RES 3,L\r
6195opcode_CB_9D:\r
6196 bic z80hl,z80hl,#1<<19\r
6197 fetch 8\r
6198;@RES 3,(HL)\r
6199opcode_CB_9E:\r
6200 opRESmemHL 3\r
6201;@RES 3,A\r
6202opcode_CB_9F:\r
6203 bic z80a,z80a,#1<<27\r
6204 fetch 8\r
6205\r
6206;@RES 4,B\r
6207opcode_CB_A0:\r
6208 bic z80bc,z80bc,#1<<28\r
6209 fetch 8\r
6210;@RES 4,C\r
6211opcode_CB_A1:\r
6212 bic z80bc,z80bc,#1<<20\r
6213 fetch 8\r
6214;@RES 4,D\r
6215opcode_CB_A2:\r
6216 bic z80de,z80de,#1<<28\r
6217 fetch 8\r
6218;@RES 4,E\r
6219opcode_CB_A3:\r
6220 bic z80de,z80de,#1<<20\r
6221 fetch 8\r
6222;@RES 4,H\r
6223opcode_CB_A4:\r
6224 bic z80hl,z80hl,#1<<28\r
6225 fetch 8\r
6226;@RES 4,L\r
6227opcode_CB_A5:\r
6228 bic z80hl,z80hl,#1<<20\r
6229 fetch 8\r
6230;@RES 4,(HL)\r
6231opcode_CB_A6:\r
6232 opRESmemHL 4\r
6233;@RES 4,A\r
6234opcode_CB_A7:\r
6235 bic z80a,z80a,#1<<28\r
6236 fetch 8\r
6237\r
6238;@RES 5,B\r
6239opcode_CB_A8:\r
6240 bic z80bc,z80bc,#1<<29\r
6241 fetch 8\r
6242;@RES 5,C\r
6243opcode_CB_A9:\r
6244 bic z80bc,z80bc,#1<<21\r
6245 fetch 8\r
6246;@RES 5,D\r
6247opcode_CB_AA:\r
6248 bic z80de,z80de,#1<<29\r
6249 fetch 8\r
6250;@RES 5,E\r
6251opcode_CB_AB:\r
6252 bic z80de,z80de,#1<<21\r
6253 fetch 8\r
6254;@RES 5,H\r
6255opcode_CB_AC:\r
6256 bic z80hl,z80hl,#1<<29\r
6257 fetch 8\r
6258;@RES 5,L\r
6259opcode_CB_AD:\r
6260 bic z80hl,z80hl,#1<<21\r
6261 fetch 8\r
6262;@RES 5,(HL)\r
6263opcode_CB_AE:\r
6264 opRESmemHL 5\r
6265;@RES 5,A\r
6266opcode_CB_AF:\r
6267 bic z80a,z80a,#1<<29\r
6268 fetch 8\r
6269\r
6270;@RES 6,B\r
6271opcode_CB_B0:\r
6272 bic z80bc,z80bc,#1<<30\r
6273 fetch 8\r
6274;@RES 6,C\r
6275opcode_CB_B1:\r
6276 bic z80bc,z80bc,#1<<22\r
6277 fetch 8\r
6278;@RES 6,D\r
6279opcode_CB_B2:\r
6280 bic z80de,z80de,#1<<30\r
6281 fetch 8\r
6282;@RES 6,E\r
6283opcode_CB_B3:\r
6284 bic z80de,z80de,#1<<22\r
6285 fetch 8\r
6286;@RES 6,H\r
6287opcode_CB_B4:\r
6288 bic z80hl,z80hl,#1<<30\r
6289 fetch 8\r
6290;@RES 6,L\r
6291opcode_CB_B5:\r
6292 bic z80hl,z80hl,#1<<22\r
6293 fetch 8\r
6294;@RES 6,(HL)\r
6295opcode_CB_B6:\r
6296 opRESmemHL 6\r
6297;@RES 6,A\r
6298opcode_CB_B7:\r
6299 bic z80a,z80a,#1<<30\r
6300 fetch 8\r
6301\r
6302;@RES 7,B\r
6303opcode_CB_B8:\r
6304 bic z80bc,z80bc,#1<<31\r
6305 fetch 8\r
6306;@RES 7,C\r
6307opcode_CB_B9:\r
6308 bic z80bc,z80bc,#1<<23\r
6309 fetch 8\r
6310;@RES 7,D\r
6311opcode_CB_BA:\r
6312 bic z80de,z80de,#1<<31\r
6313 fetch 8\r
6314;@RES 7,E\r
6315opcode_CB_BB:\r
6316 bic z80de,z80de,#1<<23\r
6317 fetch 8\r
6318;@RES 7,H\r
6319opcode_CB_BC:\r
6320 bic z80hl,z80hl,#1<<31\r
6321 fetch 8\r
6322;@RES 7,L\r
6323opcode_CB_BD:\r
6324 bic z80hl,z80hl,#1<<23\r
6325 fetch 8\r
6326;@RES 7,(HL)\r
6327opcode_CB_BE:\r
6328 opRESmemHL 7\r
6329;@RES 7,A\r
6330opcode_CB_BF:\r
6331 bic z80a,z80a,#1<<31\r
6332 fetch 8\r
6333\r
6334;@SET 0,B\r
6335opcode_CB_C0:\r
6336 orr z80bc,z80bc,#1<<24\r
6337 fetch 8\r
6338;@SET 0,C\r
6339opcode_CB_C1:\r
6340 orr z80bc,z80bc,#1<<16\r
6341 fetch 8\r
6342;@SET 0,D\r
6343opcode_CB_C2:\r
6344 orr z80de,z80de,#1<<24\r
6345 fetch 8\r
6346;@SET 0,E\r
6347opcode_CB_C3:\r
6348 orr z80de,z80de,#1<<16\r
6349 fetch 8\r
6350;@SET 0,H\r
6351opcode_CB_C4:\r
6352 orr z80hl,z80hl,#1<<24\r
6353 fetch 8\r
6354;@SET 0,L\r
6355opcode_CB_C5:\r
6356 orr z80hl,z80hl,#1<<16\r
6357 fetch 8\r
6358;@SET 0,(HL)\r
6359opcode_CB_C6:\r
6360 opSETmemHL 0\r
6361;@SET 0,A\r
6362opcode_CB_C7:\r
6363 orr z80a,z80a,#1<<24\r
6364 fetch 8\r
6365\r
6366;@SET 1,B\r
6367opcode_CB_C8:\r
6368 orr z80bc,z80bc,#1<<25\r
6369 fetch 8\r
6370;@SET 1,C\r
6371opcode_CB_C9:\r
6372 orr z80bc,z80bc,#1<<17\r
6373 fetch 8\r
6374;@SET 1,D\r
6375opcode_CB_CA:\r
6376 orr z80de,z80de,#1<<25\r
6377 fetch 8\r
6378;@SET 1,E\r
6379opcode_CB_CB:\r
6380 orr z80de,z80de,#1<<17\r
6381 fetch 8\r
6382;@SET 1,H\r
6383opcode_CB_CC:\r
6384 orr z80hl,z80hl,#1<<25\r
6385 fetch 8\r
6386;@SET 1,L\r
6387opcode_CB_CD:\r
6388 orr z80hl,z80hl,#1<<17\r
6389 fetch 8\r
6390;@SET 1,(HL)\r
6391opcode_CB_CE:\r
6392 opSETmemHL 1\r
6393;@SET 1,A\r
6394opcode_CB_CF:\r
6395 orr z80a,z80a,#1<<25\r
6396 fetch 8\r
6397\r
6398;@SET 2,B\r
6399opcode_CB_D0:\r
6400 orr z80bc,z80bc,#1<<26\r
6401 fetch 8\r
6402;@SET 2,C\r
6403opcode_CB_D1:\r
6404 orr z80bc,z80bc,#1<<18\r
6405 fetch 8\r
6406;@SET 2,D\r
6407opcode_CB_D2:\r
6408 orr z80de,z80de,#1<<26\r
6409 fetch 8\r
6410;@SET 2,E\r
6411opcode_CB_D3:\r
6412 orr z80de,z80de,#1<<18\r
6413 fetch 8\r
6414;@SET 2,H\r
6415opcode_CB_D4:\r
6416 orr z80hl,z80hl,#1<<26\r
6417 fetch 8\r
6418;@SET 2,L\r
6419opcode_CB_D5:\r
6420 orr z80hl,z80hl,#1<<18\r
6421 fetch 8\r
6422;@SET 2,(HL)\r
6423opcode_CB_D6:\r
6424 opSETmemHL 2\r
6425;@SET 2,A\r
6426opcode_CB_D7:\r
6427 orr z80a,z80a,#1<<26\r
6428 fetch 8\r
6429\r
6430;@SET 3,B\r
6431opcode_CB_D8:\r
6432 orr z80bc,z80bc,#1<<27\r
6433 fetch 8\r
6434;@SET 3,C\r
6435opcode_CB_D9:\r
6436 orr z80bc,z80bc,#1<<19\r
6437 fetch 8\r
6438;@SET 3,D\r
6439opcode_CB_DA:\r
6440 orr z80de,z80de,#1<<27\r
6441 fetch 8\r
6442;@SET 3,E\r
6443opcode_CB_DB:\r
6444 orr z80de,z80de,#1<<19\r
6445 fetch 8\r
6446;@SET 3,H\r
6447opcode_CB_DC:\r
6448 orr z80hl,z80hl,#1<<27\r
6449 fetch 8\r
6450;@SET 3,L\r
6451opcode_CB_DD:\r
6452 orr z80hl,z80hl,#1<<19\r
6453 fetch 8\r
6454;@SET 3,(HL)\r
6455opcode_CB_DE:\r
6456 opSETmemHL 3\r
6457;@SET 3,A\r
6458opcode_CB_DF:\r
6459 orr z80a,z80a,#1<<27\r
6460 fetch 8\r
6461\r
6462;@SET 4,B\r
6463opcode_CB_E0:\r
6464 orr z80bc,z80bc,#1<<28\r
6465 fetch 8\r
6466;@SET 4,C\r
6467opcode_CB_E1:\r
6468 orr z80bc,z80bc,#1<<20\r
6469 fetch 8\r
6470;@SET 4,D\r
6471opcode_CB_E2:\r
6472 orr z80de,z80de,#1<<28\r
6473 fetch 8\r
6474;@SET 4,E\r
6475opcode_CB_E3:\r
6476 orr z80de,z80de,#1<<20\r
6477 fetch 8\r
6478;@SET 4,H\r
6479opcode_CB_E4:\r
6480 orr z80hl,z80hl,#1<<28\r
6481 fetch 8\r
6482;@SET 4,L\r
6483opcode_CB_E5:\r
6484 orr z80hl,z80hl,#1<<20\r
6485 fetch 8\r
6486;@SET 4,(HL)\r
6487opcode_CB_E6:\r
6488 opSETmemHL 4\r
6489;@SET 4,A\r
6490opcode_CB_E7:\r
6491 orr z80a,z80a,#1<<28\r
6492 fetch 8\r
6493\r
6494;@SET 5,B\r
6495opcode_CB_E8:\r
6496 orr z80bc,z80bc,#1<<29\r
6497 fetch 8\r
6498;@SET 5,C\r
6499opcode_CB_E9:\r
6500 orr z80bc,z80bc,#1<<21\r
6501 fetch 8\r
6502;@SET 5,D\r
6503opcode_CB_EA:\r
6504 orr z80de,z80de,#1<<29\r
6505 fetch 8\r
6506;@SET 5,E\r
6507opcode_CB_EB:\r
6508 orr z80de,z80de,#1<<21\r
6509 fetch 8\r
6510;@SET 5,H\r
6511opcode_CB_EC:\r
6512 orr z80hl,z80hl,#1<<29\r
6513 fetch 8\r
6514;@SET 5,L\r
6515opcode_CB_ED:\r
6516 orr z80hl,z80hl,#1<<21\r
6517 fetch 8\r
6518;@SET 5,(HL)\r
6519opcode_CB_EE:\r
6520 opSETmemHL 5\r
6521;@SET 5,A\r
6522opcode_CB_EF:\r
6523 orr z80a,z80a,#1<<29\r
6524 fetch 8\r
6525\r
6526;@SET 6,B\r
6527opcode_CB_F0:\r
6528 orr z80bc,z80bc,#1<<30\r
6529 fetch 8\r
6530;@SET 6,C\r
6531opcode_CB_F1:\r
6532 orr z80bc,z80bc,#1<<22\r
6533 fetch 8\r
6534;@SET 6,D\r
6535opcode_CB_F2:\r
6536 orr z80de,z80de,#1<<30\r
6537 fetch 8\r
6538;@SET 6,E\r
6539opcode_CB_F3:\r
6540 orr z80de,z80de,#1<<22\r
6541 fetch 8\r
6542;@SET 6,H\r
6543opcode_CB_F4:\r
6544 orr z80hl,z80hl,#1<<30\r
6545 fetch 8\r
6546;@SET 6,L\r
6547opcode_CB_F5:\r
6548 orr z80hl,z80hl,#1<<22\r
6549 fetch 8\r
6550;@SET 6,(HL)\r
6551opcode_CB_F6:\r
6552 opSETmemHL 6\r
6553;@SET 6,A\r
6554opcode_CB_F7:\r
6555 orr z80a,z80a,#1<<30\r
6556 fetch 8\r
6557\r
6558;@SET 7,B\r
6559opcode_CB_F8:\r
6560 orr z80bc,z80bc,#1<<31\r
6561 fetch 8\r
6562;@SET 7,C\r
6563opcode_CB_F9:\r
6564 orr z80bc,z80bc,#1<<23\r
6565 fetch 8\r
6566;@SET 7,D\r
6567opcode_CB_FA:\r
6568 orr z80de,z80de,#1<<31\r
6569 fetch 8\r
6570;@SET 7,E\r
6571opcode_CB_FB:\r
6572 orr z80de,z80de,#1<<23\r
6573 fetch 8\r
6574;@SET 7,H\r
6575opcode_CB_FC:\r
6576 orr z80hl,z80hl,#1<<31\r
6577 fetch 8\r
6578;@SET 7,L\r
6579opcode_CB_FD:\r
6580 orr z80hl,z80hl,#1<<23\r
6581 fetch 8\r
6582;@SET 7,(HL)\r
6583opcode_CB_FE:\r
6584 opSETmemHL 7\r
6585;@SET 7,A\r
6586opcode_CB_FF:\r
6587 orr z80a,z80a,#1<<31\r
6588 fetch 8\r
6589\r
6590\r
6591\r
6592;@##################################\r
6593;@##################################\r
6594;@### opcodes DD #########################\r
6595;@##################################\r
6596;@##################################\r
6597;@Because the DD opcodes are not a complete range from 00-FF I have\r
6598;@created this sub routine that will catch any undocumented ops\r
6599;@halt the emulator and mov the current instruction to r0\r
6600;@at a later stage I may change to display a text message on the screen\r
6601opcode_DD_NF:\r
6602 eatcycles 4\r
6603 ldr pc,[opcodes,r0, lsl #2]\r
6604;@ mov r2,#0x10*4\r
6605;@ cmp r2,z80xx\r
6606;@ bne opcode_FD_NF\r
6607;@ mov r0,#0xDD00\r
6608;@ orr r0,r0,r1\r
6609;@ b end_loop\r
6610;@opcode_FD_NF:\r
6611;@ mov r0,#0xFD00\r
6612;@ orr r0,r0,r1\r
6613;@ b end_loop\r
6614\r
6615opcode_DD_NF2:\r
6616 fetch 23\r
6617;@ notaz: we don't want to deadlock here\r
6618;@ mov r0,#0xDD0000\r
6619;@ orr r0,r0,#0xCB00\r
6620;@ orr r0,r0,r1\r
6621;@ b end_loop\r
6622\r
6623;@ADD IX,BC\r
6624opcode_DD_09:\r
6625 ldr r0,[z80xx]\r
6626 opADD16 r0 z80bc\r
6627 str r0,[z80xx]\r
6628 fetch 15\r
6629;@ADD IX,DE\r
6630opcode_DD_19:\r
6631 ldr r0,[z80xx]\r
6632 opADD16 r0 z80de\r
6633 str r0,[z80xx]\r
6634 fetch 15\r
6635;@LD IX,NN\r
6636opcode_DD_21:\r
6637 ldrb r0,[z80pc],#1\r
6638 ldrb r1,[z80pc],#1\r
6639 orr r0,r0,r1, lsl #8\r
6640 strh r0,[z80xx,#2]\r
6641 fetch 14\r
6642;@LD (NN),IX\r
6643opcode_DD_22:\r
6644 ldrb r0,[z80pc],#1\r
6645 ldrb r1,[z80pc],#1\r
6646 orr r1,r0,r1, lsl #8\r
6647 ldrh r0,[z80xx,#2]\r
6648 writemem16\r
6649 fetch 20\r
6650;@INC IX\r
6651opcode_DD_23:\r
6652 ldr r0,[z80xx]\r
6653 add r0,r0,#1<<16\r
6654 str r0,[z80xx]\r
6655 fetch 10\r
6656;@INC I (IX)\r
6657opcode_DD_24:\r
6658 ldr r0,[z80xx]\r
6659 opINC8H r0\r
6660 str r0,[z80xx]\r
6661 fetch 8\r
6662;@DEC I (IX)\r
6663opcode_DD_25:\r
6664 ldr r0,[z80xx]\r
6665 opDEC8H r0\r
6666 str r0,[z80xx]\r
6667 fetch 8\r
6668;@LD I,N (IX)\r
6669opcode_DD_26:\r
6670 ldrb r0,[z80pc],#1\r
6671 strb r0,[z80xx,#3]\r
6672 fetch 11\r
6673;@ADD IX,IX\r
6674opcode_DD_29:\r
6675 ldr r0,[z80xx]\r
6676 opADD16_2 r0\r
6677 str r0,[z80xx]\r
6678 fetch 15\r
6679;@LD IX,(NN)\r
6680opcode_DD_2A:\r
6681 ldrb r0,[z80pc],#1\r
6682 ldrb r1,[z80pc],#1\r
6683 orr r0,r0,r1, lsl #8\r
6684 stmfd sp!,{z80xx}\r
6685 readmem16\r
6686 ldmfd sp!,{z80xx}\r
6687 strh r0,[z80xx,#2]\r
6688 fetch 20\r
6689;@DEC IX\r
6690opcode_DD_2B:\r
6691 ldr r0,[z80xx]\r
6692 sub r0,r0,#1<<16\r
6693 str r0,[z80xx]\r
6694 fetch 10\r
6695;@INC X (IX)\r
6696opcode_DD_2C:\r
6697 ldr r0,[z80xx]\r
6698 opINC8L r0\r
6699 str r0,[z80xx]\r
6700 fetch 8\r
6701;@DEC X (IX)\r
6702opcode_DD_2D:\r
6703 ldr r0,[z80xx]\r
6704 opDEC8L r0\r
6705 str r0,[z80xx]\r
6706 fetch 8\r
6707;@LD X,N (IX)\r
6708opcode_DD_2E:\r
6709 ldrb r0,[z80pc],#1\r
6710 strb r0,[z80xx,#2]\r
6711 fetch 11\r
6712;@INC (IX+N)\r
6713opcode_DD_34:\r
6714 ldrsb r0,[z80pc],#1\r
6715 ldr r1,[z80xx]\r
6716 add r0,r0,r1, lsr #16\r
6717 stmfd sp!,{r0} ;@ save addr\r
6718 readmem8\r
6719 opINC8b\r
6720 ldmfd sp!,{r1} ;@ restore addr into r1\r
6721 writemem8\r
6722 fetch 23\r
6723;@DEC (IX+N)\r
6724opcode_DD_35:\r
6725 ldrsb r0,[z80pc],#1\r
6726 ldr r1,[z80xx]\r
6727 add r0,r0,r1, lsr #16\r
6728 stmfd sp!,{r0} ;@ save addr\r
6729 readmem8\r
6730 opDEC8b\r
6731 ldmfd sp!,{r1} ;@ restore addr into r1\r
6732 writemem8\r
6733 fetch 23\r
6734;@LD (IX+N),N\r
6735opcode_DD_36:\r
6736 ldrsb r2,[z80pc],#1\r
6737 ldrb r0,[z80pc],#1\r
6738 ldr r1,[z80xx]\r
6739 add r1,r2,r1, lsr #16\r
6740 writemem8\r
6741 fetch 19\r
6742;@ADD IX,SP\r
6743opcode_DD_39:\r
6744 ldr r0,[z80xx]\r
6745.if FAST_Z80SP\r
6746 ldr r2,[cpucontext,#z80sp_base]\r
6747 sub r2,z80sp,r2\r
6748 opADD16s r0 r2 16\r
6749.else\r
6750 opADD16s r0 z80sp 16\r
6751.endif\r
6752 str r0,[z80xx]\r
6753 fetch 15\r
6754;@LD B,I ( IX )\r
6755opcode_DD_44:\r
6756 ldrb r0,[z80xx,#3]\r
6757 and z80bc,z80bc,#0xFF<<16\r
6758 orr z80bc,z80bc,r0, lsl #24\r
6759 fetch 8\r
6760;@LD B,X ( IX )\r
6761opcode_DD_45:\r
6762 ldrb r0,[z80xx,#2]\r
6763 and z80bc,z80bc,#0xFF<<16\r
6764 orr z80bc,z80bc,r0, lsl #24\r
6765 fetch 8\r
6766;@LD B,(IX,N)\r
6767opcode_DD_46:\r
6768 ldrsb r0,[z80pc],#1\r
6769 ldr r1,[z80xx]\r
6770 add r0,r0,r1, lsr #16\r
6771 readmem8\r
6772 and z80bc,z80bc,#0xFF<<16\r
6773 orr z80bc,z80bc,r0, lsl #24\r
6774 fetch 19\r
6775;@LD C,I (IX)\r
6776opcode_DD_4C:\r
6777 ldrb r0,[z80xx,#3]\r
6778 and z80bc,z80bc,#0xFF<<24\r
6779 orr z80bc,z80bc,r0, lsl #16\r
6780 fetch 8\r
6781;@LD C,X (IX)\r
6782opcode_DD_4D:\r
6783 ldrb r0,[z80xx,#2]\r
6784 and z80bc,z80bc,#0xFF<<24\r
6785 orr z80bc,z80bc,r0, lsl #16\r
6786 fetch 8\r
6787;@LD C,(IX,N)\r
6788opcode_DD_4E:\r
6789 ldrsb r0,[z80pc],#1\r
6790 ldr r1,[z80xx]\r
6791 add r0,r0,r1, lsr #16\r
6792 readmem8\r
6793 and z80bc,z80bc,#0xFF<<24\r
6794 orr z80bc,z80bc,r0, lsl #16\r
6795 fetch 19\r
6796\r
6797;@LD D,I (IX)\r
6798opcode_DD_54:\r
6799 ldrb r0,[z80xx,#3]\r
6800 and z80de,z80de,#0xFF<<16\r
6801 orr z80de,z80de,r0, lsl #24\r
6802 fetch 8\r
6803;@LD D,X (IX)\r
6804opcode_DD_55:\r
6805 ldrb r0,[z80xx,#2]\r
6806 and z80de,z80de,#0xFF<<16\r
6807 orr z80de,z80de,r0, lsl #24\r
6808 fetch 8\r
6809;@LD D,(IX,N)\r
6810opcode_DD_56:\r
6811 ldrsb r0,[z80pc],#1\r
6812 ldr r1,[z80xx]\r
6813 add r0,r0,r1, lsr #16\r
6814 readmem8\r
6815 and z80de,z80de,#0xFF<<16\r
6816 orr z80de,z80de,r0, lsl #24\r
6817 fetch 19\r
6818;@LD E,I (IX)\r
6819opcode_DD_5C:\r
6820 ldrb r0,[z80xx,#3]\r
6821 and z80de,z80de,#0xFF<<24\r
6822 orr z80de,z80de,r0, lsl #16\r
6823 fetch 8\r
6824;@LD E,X (IX)\r
6825opcode_DD_5D:\r
6826 ldrb r0,[z80xx,#2]\r
6827 and z80de,z80de,#0xFF<<24\r
6828 orr z80de,z80de,r0, lsl #16\r
6829 fetch 8\r
6830;@LD E,(IX,N)\r
6831opcode_DD_5E:\r
6832 ldrsb r0,[z80pc],#1\r
6833 ldr r1,[z80xx]\r
6834 add r0,r0,r1, lsr #16\r
6835 readmem8\r
6836 and z80de,z80de,#0xFF<<24\r
6837 orr z80de,z80de,r0, lsl #16\r
6838 fetch 19\r
6839;@LD I,B (IX)\r
6840opcode_DD_60:\r
6841 mov r0,z80bc,lsr#24\r
6842 strb r0,[z80xx,#3]\r
6843 fetch 8\r
6844;@LD I,C (IX)\r
6845opcode_DD_61:\r
6846 mov r0,z80bc,lsr#16\r
6847 strb r0,[z80xx,#3]\r
6848 fetch 8\r
6849;@LD I,D (IX)\r
6850opcode_DD_62:\r
6851 mov r0,z80de,lsr#24\r
6852 strb r0,[z80xx,#3]\r
6853 fetch 8\r
6854;@LD I,E (IX)\r
6855opcode_DD_63:\r
6856 mov r0,z80de,lsr#16\r
6857 strb r0,[z80xx,#3]\r
6858 fetch 8\r
6859;@LD I,I (IX)\r
6860opcode_DD_64:\r
6861 fetch 8\r
6862;@LD I,X (IX)\r
6863opcode_DD_65:\r
6864 ldrb r0,[z80xx,#2]\r
6865 strb r0,[z80xx,#3]\r
6866 fetch 8\r
6867;@LD H,(IX,N)\r
6868opcode_DD_66:\r
6869 ldrsb r0,[z80pc],#1\r
6870 ldr r1,[z80xx]\r
6871 add r0,r0,r1, lsr #16\r
6872 readmem8\r
6873 and z80hl,z80hl,#0xFF<<16\r
6874 orr z80hl,z80hl,r0, lsl #24\r
6875 fetch 19\r
6876;@LD I,A (IX)\r
6877opcode_DD_67:\r
6878 mov r0,z80a,lsr#24\r
6879 strb r0,[z80xx,#3]\r
6880 fetch 8\r
6881;@LD X,B (IX)\r
6882opcode_DD_68:\r
6883 mov r0,z80bc,lsr#24\r
6884 strb r0,[z80xx,#2]\r
6885 fetch 8\r
6886;@LD X,C (IX)\r
6887opcode_DD_69:\r
6888 mov r0,z80bc,lsr#16\r
6889 strb r0,[z80xx,#2]\r
6890 fetch 8\r
6891;@LD X,D (IX)\r
6892opcode_DD_6A:\r
6893 mov r0,z80de,lsr#24\r
6894 strb r0,[z80xx,#2]\r
6895 fetch 8\r
6896;@LD X,E (IX)\r
6897opcode_DD_6B:\r
6898 mov r0,z80de,lsr#16\r
6899 strb r0,[z80xx,#2]\r
6900 fetch 8\r
6901;@LD X,I (IX)\r
6902opcode_DD_6C:\r
6903 ldrb r0,[z80xx,#3]\r
6904 strb r0,[z80xx,#2]\r
6905 fetch 8\r
6906;@LD X,X (IX)\r
6907opcode_DD_6D:\r
6908 fetch 8\r
6909;@LD L,(IX,N)\r
6910opcode_DD_6E:\r
6911 ldrsb r0,[z80pc],#1\r
6912 ldr r1,[z80xx]\r
6913 add r0,r0,r1, lsr #16\r
6914 readmem8\r
6915 and z80hl,z80hl,#0xFF<<24\r
6916 orr z80hl,z80hl,r0, lsl #16\r
6917 fetch 19\r
6918;@LD X,A (IX)\r
6919opcode_DD_6F:\r
6920 mov r0,z80a,lsr#24\r
6921 strb r0,[z80xx,#2]\r
6922 fetch 8\r
6923\r
6924;@LD (IX,N),B\r
6925opcode_DD_70:\r
6926 ldrsb r0,[z80pc],#1\r
6927 ldr r1,[z80xx]\r
6928 add r1,r0,r1, lsr #16\r
6929 mov r0,z80bc, lsr #24\r
6930 writemem8\r
6931 fetch 19\r
6932;@LD (IX,N),C\r
6933opcode_DD_71:\r
6934 ldrsb r0,[z80pc],#1\r
6935 ldr r1,[z80xx]\r
6936 add r1,r0,r1, lsr #16\r
6937 mov r0,z80bc, lsr #16\r
6938 and r0,r0,#0xFF\r
6939 writemem8\r
6940 fetch 19\r
6941;@LD (IX,N),D\r
6942opcode_DD_72:\r
6943 ldrsb r0,[z80pc],#1\r
6944 ldr r1,[z80xx]\r
6945 add r1,r0,r1, lsr #16\r
6946 mov r0,z80de, lsr #24\r
6947 writemem8\r
6948 fetch 19\r
6949;@LD (IX,N),E\r
6950opcode_DD_73:\r
6951 ldrsb r0,[z80pc],#1\r
6952 ldr r1,[z80xx]\r
6953 add r1,r0,r1, lsr #16\r
6954 mov r0,z80de, lsr #16\r
6955 and r0,r0,#0xFF\r
6956 writemem8\r
6957 fetch 19\r
6958;@LD (IX,N),H\r
6959opcode_DD_74:\r
6960 ldrsb r0,[z80pc],#1\r
6961 ldr r1,[z80xx]\r
6962 add r1,r0,r1, lsr #16\r
6963 mov r0,z80hl, lsr #24\r
6964 writemem8\r
6965 fetch 19\r
6966;@LD (IX,N),L\r
6967opcode_DD_75:\r
6968 ldrsb r0,[z80pc],#1\r
6969 ldr r1,[z80xx]\r
6970 add r1,r0,r1, lsr #16\r
6971 mov r0,z80hl, lsr #16\r
6972 and r0,r0,#0xFF\r
6973 writemem8\r
6974 fetch 19\r
6975;@LD (IX,N),A\r
6976opcode_DD_77:\r
6977 ldrsb r0,[z80pc],#1\r
6978 ldr r1,[z80xx]\r
6979 add r1,r0,r1, lsr #16\r
6980 mov r0,z80a, lsr #24\r
6981 writemem8\r
6982 fetch 19\r
6983\r
6984;@LD A,I from (IX)\r
6985opcode_DD_7C:\r
6986 ldrb r0,[z80xx,#3]\r
6987 mov z80a,r0, lsl #24\r
6988 fetch 8\r
6989;@LD A,X from (IX)\r
6990opcode_DD_7D:\r
6991 ldrb r0,[z80xx,#2]\r
6992 mov z80a,r0, lsl #24\r
6993 fetch 8\r
6994;@LD A,(IX,N)\r
6995opcode_DD_7E:\r
6996 ldrsb r0,[z80pc],#1\r
6997 ldr r1,[z80xx]\r
6998 add r0,r0,r1, lsr #16\r
6999 readmem8\r
7000 mov z80a,r0, lsl #24\r
7001 fetch 19\r
7002\r
7003;@ADD A,I ( IX)\r
7004opcode_DD_84:\r
7005 ldrb r0,[z80xx,#3]\r
7006 opADDb\r
7007 fetch 8\r
7008;@ADD A,X ( IX)\r
7009opcode_DD_85:\r
7010 ldrb r0,[z80xx,#2]\r
7011 opADDb\r
7012 fetch 8\r
7013;@ADD A,(IX+N)\r
7014opcode_DD_86:\r
7015 ldrsb r0,[z80pc],#1\r
7016 ldr r1,[z80xx]\r
7017 add r0,r0,r1, lsr #16\r
7018 readmem8\r
7019 opADDb\r
7020 fetch 19\r
7021\r
7022;@ADC A,I (IX)\r
7023opcode_DD_8C:\r
7024 ldrb r0,[z80xx,#3]\r
7025 opADCb\r
7026 fetch 8\r
7027;@ADC A,X (IX)\r
7028opcode_DD_8D:\r
7029 ldrb r0,[z80xx,#2]\r
7030 opADCb\r
7031 fetch 8\r
7032;@ADC A,(IX+N)\r
7033opcode_DD_8E:\r
7034 ldrsb r0,[z80pc],#1\r
7035 ldr r1,[z80xx]\r
7036 add r0,r0,r1, lsr #16\r
7037 readmem8\r
7038 opADCb\r
7039 fetch 19\r
7040\r
7041;@SUB A,I (IX)\r
7042opcode_DD_94:\r
7043 ldrb r0,[z80xx,#3]\r
7044 opSUBb\r
7045 fetch 8\r
7046;@SUB A,X (IX)\r
7047opcode_DD_95:\r
7048 ldrb r0,[z80xx,#2]\r
7049 opSUBb\r
7050 fetch 8\r
7051;@SUB A,(IX+N)\r
7052opcode_DD_96:\r
7053 ldrsb r0,[z80pc],#1\r
7054 ldr r1,[z80xx]\r
7055 add r0,r0,r1, lsr #16\r
7056 readmem8\r
7057 opSUBb\r
7058 fetch 19\r
7059\r
7060;@SBC A,I (IX)\r
7061opcode_DD_9C:\r
7062 ldrb r0,[z80xx,#3]\r
7063 opSBCb\r
7064 fetch 8\r
7065;@SBC A,X (IX)\r
7066opcode_DD_9D:\r
7067 ldrb r0,[z80xx,#2]\r
7068 opSBCb\r
7069 fetch 8\r
7070;@SBC A,(IX+N)\r
7071opcode_DD_9E:\r
7072 ldrsb r0,[z80pc],#1\r
7073 ldr r1,[z80xx]\r
7074 add r0,r0,r1, lsr #16\r
7075 readmem8\r
7076 opSBCb\r
7077 fetch 19\r
7078\r
7079;@AND I (IX)\r
7080opcode_DD_A4:\r
7081 ldrb r0,[z80xx,#3]\r
7082 opANDb\r
7083 fetch 8\r
7084;@AND X (IX)\r
7085opcode_DD_A5:\r
7086 ldrb r0,[z80xx,#2]\r
7087 opANDb\r
7088 fetch 8\r
7089;@AND (IX+N)\r
7090opcode_DD_A6:\r
7091 ldrsb r0,[z80pc],#1\r
7092 ldr r1,[z80xx]\r
7093 add r0,r0,r1, lsr #16\r
7094 readmem8\r
7095 opANDb\r
7096 fetch 19\r
7097\r
7098;@XOR I (IX)\r
7099opcode_DD_AC:\r
7100 ldrb r0,[z80xx,#3]\r
7101 opXORb\r
7102 fetch 8\r
7103;@XOR X (IX)\r
7104opcode_DD_AD:\r
7105 ldrb r0,[z80xx,#2]\r
7106 opXORb\r
7107 fetch 8\r
7108;@XOR (IX+N)\r
7109opcode_DD_AE:\r
7110 ldrsb r0,[z80pc],#1\r
7111 ldr r1,[z80xx]\r
7112 add r0,r0,r1, lsr #16\r
7113 readmem8\r
7114 opXORb\r
7115 fetch 19\r
7116\r
7117;@OR I (IX)\r
7118opcode_DD_B4:\r
7119 ldrb r0,[z80xx,#3]\r
7120 opORb\r
7121 fetch 8\r
7122;@OR X (IX)\r
7123opcode_DD_B5:\r
7124 ldrb r0,[z80xx,#2]\r
7125 opORb\r
7126 fetch 8\r
7127;@OR (IX+N)\r
7128opcode_DD_B6:\r
7129 ldrsb r0,[z80pc],#1\r
7130 ldr r1,[z80xx]\r
7131 add r0,r0,r1, lsr #16\r
7132 readmem8\r
7133 opORb\r
7134 fetch 19\r
7135\r
7136;@CP I (IX)\r
7137opcode_DD_BC:\r
7138 ldrb r0,[z80xx,#3]\r
7139 opCPb\r
7140 fetch 8\r
7141;@CP X (IX)\r
7142opcode_DD_BD:\r
7143 ldrb r0,[z80xx,#2]\r
7144 opCPb\r
7145 fetch 8\r
7146;@CP (IX+N)\r
7147opcode_DD_BE:\r
7148 ldrsb r0,[z80pc],#1\r
7149 ldr r1,[z80xx]\r
7150 add r0,r0,r1, lsr #16\r
7151 readmem8\r
7152 opCPb\r
7153 fetch 19\r
7154\r
7155\r
7156opcodes_DD_CB_LOCAL: .word opcodes_DD_CB\r
7157opcode_DD_CB:\r
7158;@Looks up the opcode on the opcodes_DD_CB table and then \r
7159;@moves the PC to the location of the subroutine\r
7160 ldrsb r0,[z80pc],#1\r
7161 ldr r1,[z80xx]\r
7162 add r0,r0,r1, lsr #16\r
7163\r
7164 ldrb r1,[z80pc],#1\r
7165 ldr pc,[pc,r1, lsl #2]\r
7166 .word 0x00\r
7167opcodes_DD_CB:\r
7168 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_06,opcode_DD_NF2\r
7169 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_0E,opcode_DD_NF2\r
7170 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_16,opcode_DD_NF2\r
7171 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_1E,opcode_DD_NF2\r
7172 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_26,opcode_DD_NF2\r
7173 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_2E,opcode_DD_NF2\r
7174 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_36,opcode_DD_NF2\r
7175 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_3E,opcode_DD_NF2\r
7176 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_46,opcode_DD_NF2\r
7177 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_4E,opcode_DD_NF2\r
7178 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_56,opcode_DD_NF2\r
7179 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_5E,opcode_DD_NF2\r
7180 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_66,opcode_DD_NF2\r
7181 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_6E,opcode_DD_NF2\r
7182 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_76,opcode_DD_NF2\r
7183 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_7E,opcode_DD_NF2\r
7184 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_86,opcode_DD_NF2\r
7185 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_8E,opcode_DD_NF2\r
7186 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_96,opcode_DD_NF2\r
7187 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_9E,opcode_DD_NF2\r
7188 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_A6,opcode_DD_NF2\r
7189 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_AE,opcode_DD_NF2\r
7190 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_B6,opcode_DD_NF2\r
7191 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_BE,opcode_DD_NF2\r
7192 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_C6,opcode_DD_NF2\r
7193 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_CE,opcode_DD_NF2\r
7194 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_D6,opcode_DD_NF2\r
7195 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_DE,opcode_DD_NF2\r
7196 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_E6,opcode_DD_NF2\r
7197 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_EE,opcode_DD_NF2\r
7198 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_F6,opcode_DD_NF2\r
7199 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_FE,opcode_DD_NF2\r
7200\r
7201;@RLC (IX+N) \r
7202opcode_DD_CB_06:\r
7203 stmfd sp!,{r0} ;@ save addr\r
7204 readmem8\r
7205 opRLCb\r
7206 ldmfd sp!,{r1} ;@ restore addr into r1\r
7207 writemem8\r
7208 fetch 23\r
7209;@RRC (IX+N) \r
7210opcode_DD_CB_0E:\r
7211 stmfd sp!,{r0} ;@ save addr\r
7212 readmem8\r
7213 opRRCb\r
7214 ldmfd sp!,{r1} ;@ restore addr into r1\r
7215 writemem8\r
7216 fetch 23\r
7217;@RL (IX+N) \r
7218opcode_DD_CB_16:\r
7219 stmfd sp!,{r0} ;@ save addr\r
7220 readmem8\r
7221 opRLb\r
7222 ldmfd sp!,{r1} ;@ restore addr into r1\r
7223 writemem8\r
7224 fetch 23\r
7225;@RR (IX+N) \r
7226opcode_DD_CB_1E:\r
7227 stmfd sp!,{r0} ;@ save addr \r
7228 readmem8\r
7229 opRRb\r
7230 ldmfd sp!,{r1} ;@ restore addr into r1\r
7231 writemem8\r
7232 fetch 23\r
7233\r
7234;@SLA (IX+N) \r
7235opcode_DD_CB_26:\r
7236 stmfd sp!,{r0} ;@ save addr \r
7237 readmem8\r
7238 opSLAb\r
7239 ldmfd sp!,{r1} ;@ restore addr into r1\r
7240 writemem8\r
7241 fetch 23\r
7242;@SRA (IX+N) \r
7243opcode_DD_CB_2E:\r
7244 stmfd sp!,{r0} ;@ save addr \r
7245 readmem8\r
7246 opSRAb\r
7247 ldmfd sp!,{r1} ;@ restore addr into r1\r
7248 writemem8\r
7249 fetch 23\r
7250;@SLL (IX+N) \r
7251opcode_DD_CB_36:\r
7252 stmfd sp!,{r0} ;@ save addr \r
7253 readmem8\r
7254 opSLLb\r
7255 ldmfd sp!,{r1} ;@ restore addr into r1\r
7256 writemem8\r
7257 fetch 23\r
7258;@SRL (IX+N)\r
7259opcode_DD_CB_3E:\r
7260 stmfd sp!,{r0} ;@ save addr \r
7261 readmem8\r
7262 opSRLb\r
7263 ldmfd sp!,{r1} ;@ restore addr into r1\r
7264 writemem8\r
7265 fetch 23\r
7266\r
7267;@BIT 0,(IX+N) \r
7268opcode_DD_CB_46:\r
7269 readmem8\r
7270 opBITb 0\r
7271 fetch 20\r
7272;@BIT 1,(IX+N) \r
7273opcode_DD_CB_4E:\r
7274 readmem8\r
7275 opBITb 1\r
7276 fetch 20\r
7277;@BIT 2,(IX+N) \r
7278opcode_DD_CB_56:\r
7279 readmem8\r
7280 opBITb 2\r
7281 fetch 20\r
7282;@BIT 3,(IX+N) \r
7283opcode_DD_CB_5E:\r
7284 readmem8\r
7285 opBITb 3\r
7286 fetch 20\r
7287;@BIT 4,(IX+N) \r
7288opcode_DD_CB_66:\r
7289 readmem8\r
7290 opBITb 4\r
7291 fetch 20\r
7292;@BIT 5,(IX+N) \r
7293opcode_DD_CB_6E:\r
7294 readmem8\r
7295 opBITb 5\r
7296 fetch 20\r
7297;@BIT 6,(IX+N) \r
7298opcode_DD_CB_76:\r
7299 readmem8\r
7300 opBITb 6\r
7301 fetch 20\r
7302;@BIT 7,(IX+N) \r
7303opcode_DD_CB_7E:\r
7304 readmem8\r
7305 opBIT7b\r
7306 fetch 20\r
7307;@RES 0,(IX+N) \r
7308opcode_DD_CB_86:\r
7309 opRESmem 0\r
7310;@RES 1,(IX+N) \r
7311opcode_DD_CB_8E:\r
7312 opRESmem 1\r
7313;@RES 2,(IX+N) \r
7314opcode_DD_CB_96:\r
7315 opRESmem 2\r
7316;@RES 3,(IX+N) \r
7317opcode_DD_CB_9E:\r
7318 opRESmem 3\r
7319;@RES 4,(IX+N) \r
7320opcode_DD_CB_A6:\r
7321 opRESmem 4\r
7322;@RES 5,(IX+N) \r
7323opcode_DD_CB_AE:\r
7324 opRESmem 5\r
7325;@RES 6,(IX+N) \r
7326opcode_DD_CB_B6:\r
7327 opRESmem 6\r
7328;@RES 7,(IX+N) \r
7329opcode_DD_CB_BE:\r
7330 opRESmem 7\r
7331\r
7332;@SET 0,(IX+N) \r
7333opcode_DD_CB_C6:\r
7334 opSETmem 0\r
7335;@SET 1,(IX+N) \r
7336opcode_DD_CB_CE:\r
7337 opSETmem 1\r
7338;@SET 2,(IX+N) \r
7339opcode_DD_CB_D6:\r
7340 opSETmem 2\r
7341;@SET 3,(IX+N) \r
7342opcode_DD_CB_DE:\r
7343 opSETmem 3\r
7344;@SET 4,(IX+N) \r
7345opcode_DD_CB_E6:\r
7346 opSETmem 4\r
7347;@SET 5,(IX+N) \r
7348opcode_DD_CB_EE:\r
7349 opSETmem 5\r
7350;@SET 6,(IX+N) \r
7351opcode_DD_CB_F6:\r
7352 opSETmem 6\r
7353;@SET 7,(IX+N) \r
7354opcode_DD_CB_FE:\r
7355 opSETmem 7\r
7356\r
7357\r
7358\r
7359;@POP IX\r
7360opcode_DD_E1:\r
7361.if FAST_Z80SP\r
7362 opPOP\r
7363.else\r
7364 mov r0,z80sp\r
7365 stmfd sp!,{z80xx}\r
7366 readmem16\r
7367 ldmfd sp!,{z80xx}\r
7368 add z80sp,z80sp,#2\r
7369.endif\r
7370 strh r0,[z80xx,#2]\r
7371 fetch 14\r
7372;@EX (SP),IX\r
7373opcode_DD_E3:\r
7374.if FAST_Z80SP\r
7375 ldrb r0,[z80sp]\r
7376 ldrb r1,[z80sp,#1]\r
7377 orr r2,r0,r1, lsl #8\r
7378 ldrh r1,[z80xx,#2]\r
7379 mov r0,r1, lsr #8\r
7380 strb r0,[z80sp,#1]\r
7381 strb r1,[z80sp]\r
7382 strh r2,[z80xx,#2]\r
7383.else\r
7384 mov r0,z80sp\r
7385 stmfd sp!,{z80xx}\r
7386 readmem16\r
7387 ldmfd sp!,{z80xx}\r
7388 mov r2,r0\r
7389 ldrh r0,[z80xx,#2]\r
7390 strh r2,[z80xx,#2]\r
7391 mov r1,z80sp\r
7392 writemem16\r
7393.endif\r
7394 fetch 23\r
7395;@PUSH IX\r
7396opcode_DD_E5:\r
7397 ldr r2,[z80xx]\r
7398 opPUSHreg r2\r
7399 fetch 15\r
7400;@JP (IX)\r
7401opcode_DD_E9:\r
7402 ldrh r0,[z80xx,#2]\r
7403 rebasepc\r
7404 fetch 8\r
7405;@LD SP,IX\r
7406opcode_DD_F9:\r
7407.if FAST_Z80SP\r
7408 ldrh r0,[z80xx,#2]\r
7409 rebasesp\r
7410 mov z80sp,r0\r
7411.else\r
7412 ldrh z80sp,[z80xx,#2]\r
7413.endif\r
7414 fetch 10\r
7415\r
7416;@##################################\r
7417;@##################################\r
7418;@### opcodes ED #########################\r
7419;@##################################\r
7420;@##################################\r
7421\r
7422opcode_ED_NF:\r
7423 fetch 8\r
7424;@ ldrb r0,[z80pc],#1\r
7425;@ ldr pc,[opcodes,r0, lsl #2]\r
7426;@ mov r0,#0xED00\r
7427;@ orr r0,r0,r1\r
7428;@ b end_loop\r
7429\r
7430;@IN B,(C)\r
7431opcode_ED_40:\r
7432 opIN_C\r
7433 and z80bc,z80bc,#0xFF<<16\r
7434 orr z80bc,z80bc,r0, lsl #24\r
7435 sub r1,opcodes,#0x100\r
7436 ldrb r0,[r1,r0]\r
7437 and z80f,z80f,#1<<CFlag\r
7438 orr z80f,z80f,r0\r
7439 fetch 12\r
7440;@OUT (C),B\r
7441opcode_ED_41:\r
7442 mov r1,z80bc, lsr #24\r
7443 opOUT_C\r
7444 fetch 12\r
7445\r
7446;@SBC HL,BC\r
7447opcode_ED_42:\r
7448 opSBC16 z80bc\r
7449\r
7450;@LD (NN),BC\r
7451opcode_ED_43:\r
7452 ldrb r0,[z80pc],#1\r
7453 ldrb r1,[z80pc],#1\r
7454 orr r1,r0,r1, lsl #8\r
7455 mov r0,z80bc, lsr #16\r
7456 writemem16\r
7457 fetch 20\r
7458;@NEG\r
7459opcode_ED_44:\r
7460 rsbs z80a,z80a,#0\r
7461 mrs z80f,cpsr\r
7462 mov z80f,z80f,lsr#28 ;@S,Z,V&C\r
7463 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@invert C and set n.\r
7464 tst z80a,#0x0F000000 ;@H, correct\r
7465 orrne z80f,z80f,#1<<HFlag\r
7466 fetch 8\r
7467 \r
7468;@RETN, moved to ED_4D\r
7469;@opcode_ED_45:\r
7470\r
7471;@IM 0\r
7472opcode_ED_46:\r
7473 strb z80a,[cpucontext,#z80im]\r
7474 fetch 8\r
7475;@LD I,A\r
7476opcode_ED_47:\r
7477 str z80a,[cpucontext,#z80i]\r
7478 fetch 9\r
7479;@IN C,(C)\r
7480opcode_ED_48:\r
7481 opIN_C\r
7482 and z80bc,z80bc,#0xFF<<24\r
7483 orr z80bc,z80bc,r0, lsl #16\r
7484 sub r1,opcodes,#0x100\r
7485 ldrb r0,[r1,r0]\r
7486 and z80f,z80f,#1<<CFlag\r
7487 orr z80f,z80f,r0\r
7488 fetch 12\r
7489;@OUT (C),C\r
7490opcode_ED_49:\r
7491 mov r0,z80bc, lsr #16\r
7492 and r1,r0,#0xFF\r
7493 opOUT\r
7494 fetch 12\r
7495;@ADC HL,BC\r
7496opcode_ED_4A:\r
7497 opADC16 z80bc\r
7498;@LD BC,(NN)\r
7499opcode_ED_4B:\r
7500 ldrb r0,[z80pc],#1\r
7501 ldrb r1,[z80pc],#1\r
7502 orr r0,r0,r1, lsl #8\r
7503 readmem16\r
7504 mov z80bc,r0, lsl #16\r
7505 fetch 20\r
7506\r
7507;@RETN\r
7508opcode_ED_45:\r
7509;@RETI\r
7510opcode_ED_4D:\r
7511 ldrb r0,[cpucontext,#z80if]\r
7512 tst r0,#Z80_IF2\r
7513 orrne r0,r0,#Z80_IF1\r
7514 biceq r0,r0,#Z80_IF1\r
7515 strb r0,[cpucontext,#z80if]\r
7516 opPOP\r
7517 rebasepc\r
7518 fetch 14\r
7519\r
7520;@LD R,A\r
7521opcode_ED_4F:\r
7522 mov r0,z80a,lsr#24\r
7523 strb r0,[cpucontext,#z80r]\r
7524 fetch 9\r
7525\r
7526;@IN D,(C)\r
7527opcode_ED_50:\r
7528 opIN_C\r
7529 and z80de,z80de,#0xFF<<16\r
7530 orr z80de,z80de,r0, lsl #24\r
7531 sub r1,opcodes,#0x100\r
7532 ldrb r0,[r1,r0]\r
7533 and z80f,z80f,#1<<CFlag\r
7534 orr z80f,z80f,r0\r
7535 fetch 12\r
7536;@OUT (C),D\r
7537opcode_ED_51:\r
7538 mov r1,z80de, lsr #24\r
7539 opOUT_C\r
7540 fetch 12\r
7541;@SBC HL,DE\r
7542opcode_ED_52:\r
7543 opSBC16 z80de\r
7544;@LD (NN),DE\r
7545opcode_ED_53:\r
7546 ldrb r0,[z80pc],#1\r
7547 ldrb r1,[z80pc],#1\r
7548 orr r1,r0,r1, lsl #8\r
7549 mov r0,z80de, lsr #16\r
7550 writemem16\r
7551 fetch 20\r
7552;@IM 1\r
7553opcode_ED_56:\r
7554 mov r0,#1\r
7555 strb r0,[cpucontext,#z80im]\r
7556 fetch 8\r
7557;@LD A,I\r
7558opcode_ED_57:\r
7559 ldr z80a,[cpucontext,#z80i]\r
7560 tst z80a,#0xFF000000\r
7561 and z80f,z80f,#(1<<CFlag)\r
7562 orreq z80f,z80f,#(1<<ZFlag)\r
7563 orrmi z80f,z80f,#(1<<SFlag)\r
7564 ldrb r0,[cpucontext,#z80if]\r
7565 tst r0,#Z80_IF2\r
7566 orrne z80f,z80f,#(1<<VFlag)\r
7567 fetch 9\r
7568;@IN E,(C)\r
7569opcode_ED_58:\r
7570 opIN_C\r
7571 and z80de,z80de,#0xFF<<24\r
7572 orr z80de,z80de,r0, lsl #16\r
7573 sub r1,opcodes,#0x100\r
7574 ldrb r0,[r1,r0]\r
7575 and z80f,z80f,#1<<CFlag\r
7576 orr z80f,z80f,r0\r
7577 fetch 12\r
7578;@OUT (C),E\r
7579opcode_ED_59:\r
7580 mov r1,z80de, lsr #16\r
7581 and r1,r1,#0xFF\r
7582 opOUT_C\r
7583 fetch 12\r
7584;@ADC HL,DE\r
7585opcode_ED_5A:\r
7586 opADC16 z80de\r
7587;@LD DE,(NN)\r
7588opcode_ED_5B:\r
7589 ldrb r0,[z80pc],#1\r
7590 ldrb r1,[z80pc],#1\r
7591 orr r0,r0,r1, lsl #8\r
7592 readmem16\r
7593 mov z80de,r0, lsl #16\r
7594 fetch 20\r
7595;@IM 2\r
7596opcode_ED_5E:\r
7597 mov r0,#2\r
7598 strb r0,[cpucontext,#z80im]\r
7599 fetch 8\r
7600;@LD A,R\r
7601opcode_ED_5F:\r
7602 ldrb r0,[cpucontext,#z80r]\r
7603 and r0,r0,#0x80\r
7604 rsb r1,z80_icount,#0\r
7605 and r1,r1,#0x7F\r
7606 orr r0,r0,r1\r
7607 movs z80a,r0, lsl #24\r
7608 and z80f,z80f,#1<<CFlag\r
7609 orrmi z80f,z80f,#(1<<SFlag)\r
7610 orreq z80f,z80f,#(1<<ZFlag)\r
7611 ldrb r0,[cpucontext,#z80if]\r
7612 tst r0,#Z80_IF2\r
7613 orrne z80f,z80f,#(1<<VFlag)\r
7614 fetch 9\r
7615;@IN H,(C)\r
7616opcode_ED_60:\r
7617 opIN_C\r
7618 and z80hl,z80hl,#0xFF<<16\r
7619 orr z80hl,z80hl,r0, lsl #24\r
7620 sub r1,opcodes,#0x100\r
7621 ldrb r0,[r1,r0]\r
7622 and z80f,z80f,#1<<CFlag\r
7623 orr z80f,z80f,r0\r
7624 fetch 12\r
7625;@OUT (C),H\r
7626opcode_ED_61:\r
7627 mov r1,z80hl, lsr #24\r
7628 opOUT_C\r
7629 fetch 12\r
7630;@SBC HL,HL\r
7631opcode_ED_62:\r
7632 opSBC16HL\r
7633;@RRD\r
7634opcode_ED_67:\r
7635 readmem8HL\r
7636 mov r1,r0,ror#4\r
7637 orr r0,r1,z80a,lsr#20\r
7638 bic z80a,z80a,#0x0F000000\r
7639 orr z80a,z80a,r1,lsr#4\r
7640 writemem8HL\r
7641 sub r1,opcodes,#0x100\r
7642 ldrb r0,[r1,z80a, lsr #24]\r
7643 and z80f,z80f,#1<<CFlag\r
7644 orr z80f,z80f,r0\r
7645 fetch 18\r
7646;@IN L,(C)\r
7647opcode_ED_68:\r
7648 opIN_C\r
7649 and z80hl,z80hl,#0xFF<<24\r
7650 orr z80hl,z80hl,r0, lsl #16\r
7651 and z80f,z80f,#1<<CFlag\r
7652 sub r1,opcodes,#0x100\r
7653 ldrb r0,[r1,r0]\r
7654 orr z80f,z80f,r0\r
7655 fetch 12\r
7656;@OUT (C),L\r
7657opcode_ED_69:\r
7658 mov r1,z80hl, lsr #16\r
7659 and r1,r1,#0xFF\r
7660 opOUT_C\r
7661 fetch 12\r
7662;@ADC HL,HL\r
7663opcode_ED_6A:\r
7664 opADC16HL\r
7665;@RLD\r
7666opcode_ED_6F:\r
7667 readmem8HL\r
7668 orr r0,r0,z80a,lsl#4\r
7669 mov r0,r0,ror#28\r
7670 and z80a,z80a,#0xF0000000\r
7671 orr z80a,z80a,r0,lsl#16\r
7672 and z80a,z80a,#0xFF000000\r
7673 writemem8HL\r
7674 sub r1,opcodes,#0x100\r
7675 ldrb r0,[r1,z80a, lsr #24]\r
7676 and z80f,z80f,#1<<CFlag\r
7677 orr z80f,z80f,r0\r
7678 fetch 18\r
7679;@IN F,(C)\r
7680opcode_ED_70:\r
7681 opIN_C\r
7682 and z80f,z80f,#1<<CFlag\r
7683 sub r1,opcodes,#0x100\r
7684 ldrb r0,[r1,r0]\r
7685 orr z80f,z80f,r0\r
7686 fetch 12\r
7687;@OUT (C),0\r
7688opcode_ED_71:\r
7689 mov r1,#0\r
7690 opOUT_C\r
7691 fetch 12\r
7692\r
7693;@SBC HL,SP\r
7694opcode_ED_72:\r
7695.if FAST_Z80SP\r
7696 ldr r0,[cpucontext,#z80sp_base]\r
7697 sub r0,z80sp,r0\r
7698 mov r0, r0, lsl #16\r
7699.else\r
7700 mov r0,z80sp,lsl#16\r
7701.endif\r
7702 opSBC16 r0\r
7703;@LD (NN),SP\r
7704opcode_ED_73:\r
7705 ldrb r0,[z80pc],#1\r
7706 ldrb r1,[z80pc],#1\r
7707 orr r1,r0,r1, lsl #8\r
7708.if FAST_Z80SP\r
7709 ldr r0,[cpucontext,#z80sp_base]\r
7710 sub r0,z80sp,r0\r
7711.else\r
7712 mov r0,z80sp\r
7713.endif\r
7714 writemem16\r
7715 fetch 16\r
7716;@IN A,(C)\r
7717opcode_ED_78:\r
7718 opIN_C\r
7719 mov z80a,r0, lsl #24\r
7720 and z80f,z80f,#1<<CFlag\r
7721 sub r1,opcodes,#0x100\r
7722 ldrb r0,[r1,r0]\r
7723 orr z80f,z80f,r0\r
7724 fetch 12\r
7725;@OUT (C),A\r
7726opcode_ED_79:\r
7727 mov r1,z80a, lsr #24\r
7728 opOUT_C\r
7729 fetch 12\r
7730;@ADC HL,SP\r
7731opcode_ED_7A:\r
7732.if FAST_Z80SP\r
7733 ldr r0,[cpucontext,#z80sp_base]\r
7734 sub r0,z80sp,r0\r
7735 mov r0, r0, lsl #16\r
7736.else\r
7737 mov r0,z80sp,lsl#16\r
7738.endif\r
7739 opADC16 r0\r
7740;@LD SP,(NN)\r
7741opcode_ED_7B:\r
7742 ldrb r0,[z80pc],#1\r
7743 ldrb r1,[z80pc],#1\r
7744 orr r0,r0,r1, lsl #8\r
7745 readmem16\r
7746.if FAST_Z80SP\r
7747 rebasesp\r
7748.endif\r
7749 mov z80sp,r0\r
7750 fetch 20\r
7751;@LDI\r
7752opcode_ED_A0:\r
7753 copymem8HL_DE\r
7754 add z80hl,z80hl,#1<<16\r
7755 add z80de,z80de,#1<<16\r
7756 subs z80bc,z80bc,#1<<16\r
7757 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7758 orrne z80f,z80f,#1<<VFlag\r
7759 fetch 16\r
7760;@CPI\r
7761opcode_ED_A1:\r
7762 readmem8HL\r
7763 add z80hl,z80hl,#0x00010000\r
7764 mov r1,z80a,lsl#4\r
7765 cmp z80a,r0,lsl#24\r
7766 and z80f,z80f,#1<<CFlag\r
7767 orr z80f,z80f,#1<<NFlag\r
7768 orrmi z80f,z80f,#1<<SFlag\r
7769 orreq z80f,z80f,#1<<ZFlag\r
7770 cmp r1,r0,lsl#28\r
7771 orrcc z80f,z80f,#1<<HFlag\r
7772 subs z80bc,z80bc,#0x00010000\r
7773 orrne z80f,z80f,#1<<VFlag\r
7774 fetch 16\r
7775;@INI\r
7776opcode_ED_A2:\r
7777 opIN_C\r
7778 and z80f,r0,#0x80\r
7779 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7780;@ mov r1,z80bc,lsl#8\r
7781;@ add r1,r1,#0x01000000\r
7782;@ adds r1,r1,r0,lsl#24\r
7783;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C+1) & 0xFF) > 0xFF\r
7784 writemem8HL\r
7785 add z80hl,z80hl,#1<<16\r
7786 sub z80bc,z80bc,#1<<24\r
7787 tst z80bc,#0xFF<<24\r
7788 orrmi z80f,z80f,#1<<SFlag\r
7789 orreq z80f,z80f,#1<<ZFlag\r
7790 fetch 16\r
7791\r
7792;@OUTI\r
7793opcode_ED_A3:\r
7794 readmem8HL\r
7795 add z80hl,z80hl,#1<<16\r
7796 and z80f,r0,#0x80\r
7797 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7798 mov r1,z80hl,lsl#8\r
7799 adds r1,r1,r0,lsl#24\r
7800 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL)+L > 0xFF\r
7801 sub z80bc,z80bc,#1<<24\r
7802 tst z80bc,#0xFF<<24\r
7803 orrmi z80f,z80f,#1<<SFlag\r
7804 orreq z80f,z80f,#1<<ZFlag\r
7805 mov r1,r0\r
7806 opOUT_C\r
7807 fetch 16\r
7808\r
7809;@LDD\r
7810opcode_ED_A8:\r
7811 copymem8HL_DE\r
7812 sub z80hl,z80hl,#1<<16\r
7813 sub z80de,z80de,#1<<16\r
7814 subs z80bc,z80bc,#1<<16\r
7815 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7816 orrne z80f,z80f,#1<<VFlag\r
7817 fetch 16\r
7818\r
7819;@CPD\r
7820opcode_ED_A9:\r
7821 readmem8HL\r
7822 sub z80hl,z80hl,#1<<16\r
7823 mov r1,z80a,lsl#4\r
7824 cmp z80a,r0,lsl#24\r
7825 and z80f,z80f,#1<<CFlag\r
7826 orr z80f,z80f,#1<<NFlag\r
7827 orrmi z80f,z80f,#1<<SFlag\r
7828 orreq z80f,z80f,#1<<ZFlag\r
7829 cmp r1,r0,lsl#28\r
7830 orrcc z80f,z80f,#1<<HFlag\r
7831 subs z80bc,z80bc,#0x00010000\r
7832 orrne z80f,z80f,#1<<VFlag\r
7833 fetch 16\r
7834\r
7835;@IND\r
7836opcode_ED_AA:\r
7837 opIN_C\r
7838 and z80f,r0,#0x80\r
7839 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7840;@ mov r1,z80bc,lsl#8\r
7841;@ sub r1,r1,#0x01000000\r
7842;@ adds r1,r1,r0,lsl#24\r
7843;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C-1) & 0xFF) > 0xFF\r
7844 writemem8HL\r
7845 sub z80hl,z80hl,#1<<16\r
7846 sub z80bc,z80bc,#1<<24\r
7847 tst z80bc,#0xFF<<24\r
7848 orrmi z80f,z80f,#1<<SFlag\r
7849 orreq z80f,z80f,#1<<ZFlag\r
7850 fetch 16\r
7851\r
7852;@OUTD\r
7853opcode_ED_AB:\r
7854 readmem8HL\r
7855 sub z80hl,z80hl,#1<<16\r
7856 and z80f,r0,#0x80\r
7857 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7858 mov r1,z80hl,lsl#8\r
7859 adds r1,r1,r0,lsl#24\r
7860 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if r0+HL > 0xFF\r
7861 sub z80bc,z80bc,#1<<24\r
7862 tst z80bc,#0xFF<<24\r
7863 orrmi z80f,z80f,#1<<SFlag\r
7864 orreq z80f,z80f,#1<<ZFlag\r
7865 mov r1,r0\r
7866 opOUT_C\r
7867 fetch 16\r
7868;@LDIR\r
7869opcode_ED_B0:\r
7870 copymem8HL_DE\r
7871 add z80hl,z80hl,#1<<16\r
7872 add z80de,z80de,#1<<16\r
7873 subs z80bc,z80bc,#1<<16\r
7874 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7875 orrne z80f,z80f,#1<<VFlag\r
7876 subne z80pc,z80pc,#2\r
7877 subne z80_icount,z80_icount,#5\r
7878 fetch 16\r
7879\r
7880;@CPIR\r
7881opcode_ED_B1:\r
7882 readmem8HL\r
7883 add z80hl,z80hl,#1<<16 \r
7884 mov r1,z80a,lsl#4\r
7885 cmp z80a,r0,lsl#24\r
7886 and z80f,z80f,#1<<CFlag\r
7887 orr z80f,z80f,#1<<NFlag\r
7888 orrmi z80f,z80f,#1<<SFlag\r
7889 orreq z80f,z80f,#1<<ZFlag\r
7890 cmp r1,r0,lsl#28\r
7891 orrcc z80f,z80f,#1<<HFlag\r
7892 subs z80bc,z80bc,#1<<16\r
7893 bne opcode_ED_B1_decpc\r
7894 fetch 16\r
7895opcode_ED_B1_decpc:\r
7896 orr z80f,z80f,#1<<VFlag\r
7897 tst z80f,#1<<ZFlag\r
7898 subeq z80pc,z80pc,#2\r
7899 subeq z80_icount,z80_icount,#5\r
7900 fetch 16\r
7901;@INIR\r
7902opcode_ED_B2:\r
7903 opIN_C\r
7904 and z80f,r0,#0x80\r
7905 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7906;@ mov r1,z80bc,lsl#8\r
7907;@ add r1,r1,#0x01000000\r
7908;@ adds r1,r1,r0,lsl#24\r
7909;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C+1) & 0xFF) > 0xFF\r
7910 writemem8HL\r
7911 add z80hl,z80hl,#1<<16\r
7912 sub z80bc,z80bc,#1<<24\r
7913 tst z80bc,#0xFF<<24\r
7914 orrmi z80f,z80f,#1<<SFlag\r
7915 orreq z80f,z80f,#1<<ZFlag\r
7916 subne z80pc,z80pc,#2\r
7917 subne z80_icount,z80_icount,#5\r
7918 fetch 16\r
7919;@OTIR\r
7920opcode_ED_B3:\r
7921 readmem8HL\r
7922 add z80hl,z80hl,#1<<16\r
7923 and z80f,r0,#0x80\r
7924 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7925 mov r1,z80hl,lsl#8\r
7926 adds r1,r1,r0,lsl#24\r
7927 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if r0+HL > 0xFF\r
7928 sub z80bc,z80bc,#1<<24\r
7929 tst z80bc,#0xFF<<24\r
7930 orrmi z80f,z80f,#1<<SFlag\r
7931 orreq z80f,z80f,#1<<ZFlag\r
7932 subne z80pc,z80pc,#2\r
7933 subne z80_icount,z80_icount,#5\r
7934 mov r1,r0\r
7935 opOUT_C\r
7936 fetch 16\r
7937;@LDDR\r
7938opcode_ED_B8:\r
7939 copymem8HL_DE\r
7940 sub z80hl,z80hl,#1<<16\r
7941 sub z80de,z80de,#1<<16\r
7942 subs z80bc,z80bc,#1<<16\r
7943 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7944 orrne z80f,z80f,#1<<VFlag\r
7945 subne z80pc,z80pc,#2\r
7946 subne z80_icount,z80_icount,#5\r
7947 fetch 16\r
7948\r
7949;@CPDR\r
7950opcode_ED_B9:\r
7951 readmem8HL\r
7952 sub z80hl,z80hl,#1<<16\r
7953 mov r1,z80a,lsl#4\r
7954 cmp z80a,r0,lsl#24\r
7955 and z80f,z80f,#1<<CFlag\r
7956 orr z80f,z80f,#1<<NFlag\r
7957 orrmi z80f,z80f,#1<<SFlag\r
7958 orreq z80f,z80f,#1<<ZFlag\r
7959 cmp r1,r0,lsl#28\r
7960 orrcc z80f,z80f,#1<<HFlag\r
7961 subs z80bc,z80bc,#1<<16\r
7962 bne opcode_ED_B9_decpc\r
7963 fetch 16\r
7964opcode_ED_B9_decpc:\r
7965 orr z80f,z80f,#1<<VFlag\r
7966 tst z80f,#1<<ZFlag\r
7967 subeq z80pc,z80pc,#2\r
7968 subeq z80_icount,z80_icount,#5\r
7969 fetch 16\r
7970;@INDR\r
7971opcode_ED_BA:\r
7972 opIN_C\r
7973 and z80f,r0,#0x80\r
7974 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7975;@ mov r1,z80bc,lsl#8\r
7976;@ sub r1,r1,#0x01000000\r
7977;@ adds r1,r1,r0,lsl#24\r
7978;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C-1) & 0xFF) > 0xFF\r
7979 writemem8HL\r
7980 sub z80hl,z80hl,#1<<16\r
7981 sub z80bc,z80bc,#1<<24\r
7982 tst z80bc,#0xFF<<24\r
7983 orrmi z80f,z80f,#1<<SFlag\r
7984 orreq z80f,z80f,#1<<ZFlag\r
7985 subne z80pc,z80pc,#2\r
7986 subne z80_icount,z80_icount,#5\r
7987 fetch 16\r
7988;@OTDR\r
7989opcode_ED_BB:\r
7990 readmem8HL\r
7991 sub z80hl,z80hl,#1<<16\r
7992 and z80f,r0,#0x80\r
7993 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7994 mov r1,z80hl,lsl#8\r
7995 adds r1,r1,r0,lsl#24\r
7996 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if r0+HL > 0xFF\r
7997 sub z80bc,z80bc,#1<<24\r
7998 tst z80bc,#0xFF<<24\r
7999 orrmi z80f,z80f,#1<<SFlag\r
8000 orreq z80f,z80f,#1<<ZFlag\r
8001 subne z80pc,z80pc,#2\r
8002 subne z80_icount,z80_icount,#5\r
8003 mov r1,r0\r
8004 opOUT_C\r
8005 fetch 16\r
8006;@##################################\r
8007;@##################################\r
8008;@### opcodes FD #########################\r
8009;@##################################\r
8010;@##################################\r
8011;@Since DD and FD opcodes are all the same apart from the address\r
8012;@register they use. When a FD intruction the program runs the code\r
8013;@from the DD location but the address of the IY reg is passed instead\r
8014;@of IX\r
8015\r
8016;@end_loop:\r
8017;@ b end_loop\r
8018\r
8019;@ vim:filetype=armasm\r
8020\r
fast MegaDrive/MegaCD/32X emulator