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32x, take over sh2 cycles setting in-game
[picodrive.git] / cpu / musashi / m68k_in.c
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1/*\r
2must fix:\r
3 callm\r
4 chk\r
5*/\r
6/* ======================================================================== */\r
7/* ========================= LICENSING & COPYRIGHT ======================== */\r
8/* ======================================================================== */\r
9/*\r
10 * MUSASHI\r
11 * Version 3.31\r
12 *\r
13 * A portable Motorola M680x0 processor emulation engine.\r
14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.\r
15 *\r
16 * This code may be freely used for non-commercial purposes as long as this\r
17 * copyright notice remains unaltered in the source code and any binary files\r
18 * containing this code in compiled form.\r
19 *\r
20 * All other lisencing terms must be negotiated with the author\r
21 * (Karl Stenerud).\r
22 *\r
23 * The latest version of this code can be obtained at:\r
24 * http://kstenerud.cjb.net\r
25 */\r
26\r
27/* Special thanks to Bart Trzynadlowski for his insight into the\r
28 * undocumented features of this chip:\r
29 *\r
30 * http://dynarec.com/~bart/files/68knotes.txt\r
31 */\r
32\r
33\r
34/* Input file for m68kmake\r
35 * -----------------------\r
36 *\r
37 * All sections begin with 80 X's in a row followed by an end-of-line\r
38 * sequence.\r
39 * After this, m68kmake will expect to find one of the following section\r
40 * identifiers:\r
41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes\r
42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes\r
43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable\r
44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable\r
45 * M68KMAKE_TABLE_BODY - the table itself\r
46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation\r
47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation\r
48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation\r
49 *\r
50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and\r
51 * M68KMAKE_TABLE_BODY must be second last in the file.\r
52 *\r
53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler\r
54 * primitives themselves. Each opcode handler begins with:\r
55 * M68KMAKE_OP(A, B, C, D)\r
56 *\r
57 * where A is the opcode handler name, B is the size of the operation,\r
58 * C denotes any special processing mode, and D denotes a specific\r
59 * addressing mode.\r
60 * For C and D where nothing is specified, use "."\r
61 *\r
62 * Example:\r
63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA\r
64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7\r
65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing\r
66 *\r
67 * All opcode handler primitives end with a closing curly brace "}" at column 1\r
68 *\r
69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,\r
70 * and do not put a closing curly brace at column 1 unless it is\r
71 * marking the end of the handler!\r
72 *\r
73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,\r
74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple\r
75 * opcode handlers to handle variations in the opcode handler.\r
76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.\r
77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only\r
78 * be interpreted on instructions where the corresponding table entry\r
79 * specifies multiple effective addressing modes.\r
80 * Example:\r
81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4\r
82 *\r
83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).\r
84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for\r
85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.\r
86 */\r
87\r
88XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
89M68KMAKE_PROTOTYPE_HEADER\r
90\r
91#ifndef M68KOPS__HEADER\r
92#define M68KOPS__HEADER\r
93\r
94/* ======================================================================== */\r
95/* ============================ OPCODE HANDLERS =========================== */\r
96/* ======================================================================== */\r
97\r
98\r
99\r
100XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
101M68KMAKE_PROTOTYPE_FOOTER\r
102\r
103\r
104/* Build the opcode handler table */\r
105void m68ki_build_opcode_table(void);\r
106\r
107extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
108extern unsigned char m68ki_cycles[][0x10000];\r
109\r
110\r
111/* ======================================================================== */\r
112/* ============================== END OF FILE ============================= */\r
113/* ======================================================================== */\r
114\r
115#endif /* M68KOPS__HEADER */\r
116\r
117\r
118\r
119XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
120M68KMAKE_TABLE_HEADER\r
121\r
122/* ======================================================================== */\r
123/* ========================= OPCODE TABLE BUILDER ========================= */\r
124/* ======================================================================== */\r
125\r
126#include "m68kops.h"\r
127\r
128#define NUM_CPU_TYPES 4\r
129\r
130void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
131unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */\r
132\r
133/* This is used to generate the opcode handler jump table */\r
134typedef struct\r
135{\r
136 void (*opcode_handler)(void); /* handler function */\r
137 unsigned int mask; /* mask on opcode */\r
138 unsigned int match; /* what to match after masking */\r
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */\r
140} opcode_handler_struct;\r
141\r
142\r
143/* Opcode handler table */\r
144static opcode_handler_struct m68k_opcode_handler_table[] =\r
145{\r
146/* function mask match 000 010 020 040 */\r
147\r
148\r
149\r
150XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
151M68KMAKE_TABLE_FOOTER\r
152\r
153 {0, 0, 0, {0, 0, 0, 0}}\r
154};\r
155\r
156\r
157/* Build the opcode handler jump table */\r
158void m68ki_build_opcode_table(void)\r
159{\r
160 opcode_handler_struct *ostruct;\r
161 int instr;\r
162 int i;\r
163 int j;\r
164 int k;\r
165\r
166 for(i = 0; i < 0x10000; i++)\r
167 {\r
168 /* default to illegal */\r
169 m68ki_instruction_jump_table[i] = m68k_op_illegal;\r
170 for(k=0;k<NUM_CPU_TYPES;k++)\r
171 m68ki_cycles[k][i] = 0;\r
172 }\r
173\r
174 ostruct = m68k_opcode_handler_table;\r
175 while(ostruct->mask != 0xff00)\r
176 {\r
177 for(i = 0;i < 0x10000;i++)\r
178 {\r
179 if((i & ostruct->mask) == ostruct->match)\r
180 {\r
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;\r
182 for(k=0;k<NUM_CPU_TYPES;k++)\r
183 m68ki_cycles[k][i] = ostruct->cycles[k];\r
184 }\r
185 }\r
186 ostruct++;\r
187 }\r
188 while(ostruct->mask == 0xff00)\r
189 {\r
190 for(i = 0;i <= 0xff;i++)\r
191 {\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
193 for(k=0;k<NUM_CPU_TYPES;k++)\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
195 }\r
196 ostruct++;\r
197 }\r
198 while(ostruct->mask == 0xf1f8)\r
199 {\r
200 for(i = 0;i < 8;i++)\r
201 {\r
202 for(j = 0;j < 8;j++)\r
203 {\r
204 instr = ostruct->match | (i << 9) | j;\r
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;\r
206 for(k=0;k<NUM_CPU_TYPES;k++)\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];\r
208 }\r
209 }\r
210 ostruct++;\r
211 }\r
212 while(ostruct->mask == 0xfff0)\r
213 {\r
214 for(i = 0;i <= 0x0f;i++)\r
215 {\r
216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
217 for(k=0;k<NUM_CPU_TYPES;k++)\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
219 }\r
220 ostruct++;\r
221 }\r
222 while(ostruct->mask == 0xf1ff)\r
223 {\r
224 for(i = 0;i <= 0x07;i++)\r
225 {\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;\r
227 for(k=0;k<NUM_CPU_TYPES;k++)\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];\r
229 }\r
230 ostruct++;\r
231 }\r
232 while(ostruct->mask == 0xfff8)\r
233 {\r
234 for(i = 0;i <= 0x07;i++)\r
235 {\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
237 for(k=0;k<NUM_CPU_TYPES;k++)\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
239 }\r
240 ostruct++;\r
241 }\r
242 while(ostruct->mask == 0xffff)\r
243 {\r
244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;\r
245 for(k=0;k<NUM_CPU_TYPES;k++)\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];\r
247 ostruct++;\r
248 }\r
249}\r
250\r
251\r
252/* ======================================================================== */\r
253/* ============================== END OF FILE ============================= */\r
254/* ======================================================================== */\r
255\r
256\r
257\r
258XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
259M68KMAKE_OPCODE_HANDLER_HEADER\r
260#include <stdlib.h>\r
261\r
262#include "m68kcpu.h"\r
263extern void m68040_fpu_op0(void);\r
264extern void m68040_fpu_op1(void);\r
265\r
266/* Count non-0 bits */\r
267INLINE int m68ki_bit_count(uint32 arg)\r
268{\r
269 arg = arg - ((arg>>1)&0x55555555);\r
270 arg = (arg&0x33333333) + ((arg>>2)&0x33333333);\r
271 return (((arg + (arg>>4))&0x0f0f0f0f) * 0x01010101) >> 24;\r
272}\r
273\r
274INLINE int m68ki_mulu_cycles(uint32 arg)\r
275{\r
276 if (CPU_TYPE_IS_000(CPU_TYPE))\r
277 return m68ki_bit_count(arg) * 2;\r
278 else if (CPU_TYPE_IS_010(CPU_TYPE))\r
279 return m68ki_bit_count(arg); /* guesswork */\r
280 else\r
281 return m68ki_bit_count(arg) / 2; /* guesswork */\r
282}\r
283\r
284INLINE int m68ki_muls_cycles(sint32 arg)\r
285{\r
286 if (CPU_TYPE_IS_000(CPU_TYPE))\r
287 return m68ki_bit_count(arg ^ (arg<<1)) * 2;\r
288 else if (CPU_TYPE_IS_010(CPU_TYPE))\r
289 return m68ki_bit_count(arg ^ (arg<<1)); /* guesswork */\r
290 else\r
291 return m68ki_bit_count(arg ^ (arg<<1)) / 2; /* guesswork */\r
292}\r
293\r
294INLINE int m68ki_divu_cycles(uint32 arg)\r
295{\r
296 /* approximation only. Doesn't factor in shorter cycles by carry */\r
297 if (CPU_TYPE_IS_000(CPU_TYPE))\r
298 return 128 - m68ki_bit_count(arg) * 2;\r
299 else if (CPU_TYPE_IS_010(CPU_TYPE))\r
300 return 96; /* guesswork */\r
301 else\r
302 return 32; /* guesswork */\r
303}\r
304\r
305INLINE int m68ki_divs_cycles(uint32 scyc, sint32 arg)\r
306{\r
307 /* approximation only. Doesn't factor in shorter cycles by carry */\r
308 if (CPU_TYPE_IS_000(CPU_TYPE))\r
309 return 128 - m68ki_bit_count(abs(arg)) * 2 + scyc*2 + 8;\r
310 else if (CPU_TYPE_IS_010(CPU_TYPE))\r
311 return 96 + scyc*2 + 8; /* guesswork */\r
312 else\r
313 return 32 + scyc + 4; /* guesswork */\r
314}\r
315\r
316/* ======================================================================== */\r
317/* ========================= INSTRUCTION HANDLERS ========================= */\r
318/* ======================================================================== */\r
319\r
320\r
321\r
322XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
323M68KMAKE_OPCODE_HANDLER_FOOTER\r
324\r
325/* ======================================================================== */\r
326/* ============================== END OF FILE ============================= */\r
327/* ======================================================================== */\r
328\r
329\r
330\r
331XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
332M68KMAKE_TABLE_BODY\r
333\r
334The following table is arranged as follows:\r
335\r
336name: Opcode mnemonic\r
337\r
338size: Operation size\r
339\r
340spec proc: Special processing mode:\r
341 .: normal\r
342 s: static operand\r
343 r: register operand\r
344 rr: register to register\r
345 mm: memory to memory\r
346 er: effective address to register\r
347 re: register to effective address\r
348 dd: data register to data register\r
349 da: data register to address register\r
350 aa: address register to address register\r
351 cr: control register to register\r
352 rc: register to control register\r
353 toc: to condition code register\r
354 tos: to status register\r
355 tou: to user stack pointer\r
356 frc: from condition code register\r
357 frs: from status register\r
358 fru: from user stack pointer\r
359 * for move.x, the special processing mode is a specific\r
360 destination effective addressing mode.\r
361\r
362spec ea: Specific effective addressing mode:\r
363 .: normal\r
364 i: immediate\r
365 d: data register\r
366 a: address register\r
367 ai: address register indirect\r
368 pi: address register indirect with postincrement\r
369 pd: address register indirect with predecrement\r
370 di: address register indirect with displacement\r
371 ix: address register indirect with index\r
372 aw: absolute word address\r
373 al: absolute long address\r
374 pcdi: program counter relative with displacement\r
375 pcix: program counter relative with index\r
376 a7: register specified in instruction is A7\r
377 ax7: register field X of instruction is A7\r
378 ay7: register field Y of instruction is A7\r
379 axy7: register fields X and Y of instruction are A7\r
380\r
381bit pattern: Pattern to recognize this opcode. "." means don't care.\r
382\r
383allowed ea: List of allowed addressing modes:\r
384 .: not present\r
385 A: address register indirect\r
386 +: ARI (address register indirect) with postincrement\r
387 -: ARI with predecrement\r
388 D: ARI with displacement\r
389 X: ARI with index\r
390 W: absolute word address\r
391 L: absolute long address\r
392 d: program counter indirect with displacement\r
393 x: program counter indirect with index\r
394 I: immediate\r
395mode: CPU operating mode for each cpu type. U = user or supervisor,\r
396 S = supervisor only, "." = opcode not present.\r
397\r
398cpu cycles: Base number of cycles required to execute this opcode on the\r
399 specified CPU type.\r
400 Use "." if CPU does not have this opcode.\r
401\r
402\r
403\r
404 spec spec allowed ea mode cpu cycles\r
405name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments\r
406====== ==== ==== ==== ================ ========== = = = = === === === === =============\r
407M68KMAKE_TABLE_START\r
4081010 0 . . 1010............ .......... U U U U 4 4 4 4\r
4091111 0 . . 1111............ .......... U U U U 4 4 4 4\r
410040fpu0 32 . . 11110010........ .......... . . . U . . . 0\r
411040fpu1 32 . . 11110011........ .......... . . . U . . . 0\r
412abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4\r
413abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16\r
414abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16\r
415abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16\r
416abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16\r
417add 8 er d 1101...000000... .......... U U U U 4 4 2 2\r
418add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2\r
419add 16 er d 1101...001000... .......... U U U U 4 4 2 2\r
420add 16 er a 1101...001001... .......... U U U U 4 4 2 2\r
421add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2\r
422add 32 er d 1101...010000... .......... U U U U 6 6 2 2\r
423add 32 er a 1101...010001... .......... U U U U 6 6 2 2\r
424add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2\r
425add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4\r
426add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4\r
427add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4\r
428adda 16 . d 1101...011000... .......... U U U U 8 8 2 2\r
429adda 16 . a 1101...011001... .......... U U U U 8 8 2 2\r
430adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2\r
431adda 32 . d 1101...111000... .......... U U U U 6 6 2 2\r
432adda 32 . a 1101...111001... .......... U U U U 6 6 2 2\r
433adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2\r
434addi 8 . d 0000011000000... .......... U U U U 8 8 2 2\r
435addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4\r
436addi 16 . d 0000011001000... .......... U U U U 8 8 2 2\r
437addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4\r
438addi 32 . d 0000011010000... .......... U U U U 16 14 2 2\r
439addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4\r
440addq 8 . d 0101...000000... .......... U U U U 4 4 2 2\r
441addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4\r
442addq 16 . d 0101...001000... .......... U U U U 4 4 2 2\r
443addq 16 . a 0101...001001... .......... U U U U 8 8 2 2\r
444addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4\r
445addq 32 . d 0101...010000... .......... U U U U 8 8 2 2\r
446addq 32 . a 0101...010001... .......... U U U U 8 8 2 2\r
447addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4\r
448addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2\r
449addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2\r
450addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2\r
451addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12\r
452addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12\r
453addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12\r
454addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12\r
455addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12\r
456addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12\r
457and 8 er d 1100...000000... .......... U U U U 4 4 2 2\r
458and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2\r
459and 16 er d 1100...001000... .......... U U U U 4 4 2 2\r
460and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2\r
461and 32 er d 1100...010000... .......... U U U U 6 6 2 2\r
462and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2\r
463and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4\r
464and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4\r
465and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4\r
466andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12\r
467andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12\r
468andi 8 . d 0000001000000... .......... U U U U 8 8 2 2\r
469andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4\r
470andi 16 . d 0000001001000... .......... U U U U 8 8 2 2\r
471andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4\r
472andi 32 . d 0000001010000... .......... U U U U 16 14 2 2\r
473andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4\r
474asr 8 s . 1110...000000... .......... U U U U 6 6 6 6\r
475asr 16 s . 1110...001000... .......... U U U U 6 6 6 6\r
476asr 32 s . 1110...010000... .......... U U U U 8 8 6 6\r
477asr 8 r . 1110...000100... .......... U U U U 6 6 6 6\r
478asr 16 r . 1110...001100... .......... U U U U 6 6 6 6\r
479asr 32 r . 1110...010100... .......... U U U U 8 8 6 6\r
480asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5\r
481asl 8 s . 1110...100000... .......... U U U U 6 6 8 8\r
482asl 16 s . 1110...101000... .......... U U U U 6 6 8 8\r
483asl 32 s . 1110...110000... .......... U U U U 8 8 8 8\r
484asl 8 r . 1110...100100... .......... U U U U 6 6 8 8\r
485asl 16 r . 1110...101100... .......... U U U U 6 6 8 8\r
486asl 32 r . 1110...110100... .......... U U U U 8 8 8 8\r
487asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6\r
488bcc 8 . . 0110............ .......... U U U U 10 10 6 6\r
489bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6\r
490bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6\r
491bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4\r
492bchg 32 r d 0000...101000... .......... U U U U 6 6 4 4\r
493bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4\r
494bchg 32 s d 0000100001000... .......... U U U U 10 10 4 4\r
495bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 8 4 4\r
496bclr 32 r d 0000...110000... .......... U U U U 8 8 4 4\r
497bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4\r
498bclr 32 s d 0000100010000... .......... U U U U 12 12 4 4\r
499bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct\r
500bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20\r
501bfclr 32 . d 1110110011000... .......... . . U U . . 12 12\r
502bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20\r
503bfexts 32 . d 1110101111000... .......... . . U U . . 8 8\r
504bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15\r
505bfextu 32 . d 1110100111000... .......... . . U U . . 8 8\r
506bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15\r
507bfffo 32 . d 1110110111000... .......... . . U U . . 18 18\r
508bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28\r
509bfins 32 . d 1110111111000... .......... . . U U . . 10 10\r
510bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17\r
511bfset 32 . d 1110111011000... .......... . . U U . . 12 12\r
512bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20\r
513bftst 32 . d 1110100011000... .......... . . U U . . 6 6\r
514bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13\r
515bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10\r
516bra 8 . . 01100000........ .......... U U U U 10 10 10 10\r
517bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10\r
518bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10\r
519bset 32 r d 0000...111000... .......... U U U U 6 6 4 4\r
520bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4\r
521bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4\r
522bset 32 s d 0000100011000... .......... U U U U 10 10 4 4\r
523bsr 8 . . 01100001........ .......... U U U U 18 18 7 7\r
524bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7\r
525bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7\r
526btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4\r
527btst 32 r d 0000...100000... .......... U U U U 6 6 4 4\r
528btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4\r
529btst 32 s d 0000100000000... .......... U U U U 10 10 4 4\r
530callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated\r
531cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12\r
532cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12\r
533cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12\r
534cas2 16 . . 0000110011111100 .......... . . U U . . 12 12\r
535cas2 32 . . 0000111011111100 .......... . . U U . . 12 12\r
536chk 16 . d 0100...110000... .......... U U U U 4 2 2 2\r
537chk 16 . . 0100...110...... A+-DXWLdxI U U U U 4 2 2 2\r
538chk 32 . d 0100...100000... .......... . . U U . . 8 8\r
539chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8\r
540chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23\r
541chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23\r
542chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18\r
543chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23\r
544chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23\r
545chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18\r
546chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23\r
547chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23\r
548chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18\r
549clr 8 . d 0100001000000... .......... U U U U 4 4 2 2\r
550clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4\r
551clr 16 . d 0100001001000... .......... U U U U 4 4 2 2\r
552clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4\r
553clr 32 . d 0100001010000... .......... U U U U 6 6 2 2\r
554clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4\r
555cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2\r
556cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
557cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2\r
558cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2\r
559cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
560cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2\r
561cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2\r
562cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2\r
563cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4\r
564cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4\r
565cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4\r
566cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4\r
567cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4\r
568cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4\r
569cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2\r
570cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2\r
571cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7\r
572cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9\r
573cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2\r
574cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2\r
575cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7\r
576cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9\r
577cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2\r
578cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2\r
579cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7\r
580cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9\r
581cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9\r
582cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9\r
583cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9\r
584cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9\r
585cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9\r
586cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9\r
587cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated\r
588cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated\r
589cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated\r
590cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated\r
591cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated\r
592dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6\r
593dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6\r
594dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6\r
595divs 16 . d 1000...111000... .......... U U U U 16 16 16 16 cycles depending on operands\r
596divs 16 . . 1000...111...... A+-DXWLdxI U U U U 16 16 16 16 cycles depending on operands\r
597divu 16 . d 1000...011000... .......... U U U U 10 10 10 10 cycles depending on operands\r
598divu 16 . . 1000...011...... A+-DXWLdxI U U U U 10 10 10 10 cycles depending on operands\r
599divl 32 . d 0100110001000... .......... . . U U . . 84 84\r
600divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84\r
601eor 8 . d 1011...100000... .......... U U U U 4 4 2 2\r
602eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4\r
603eor 16 . d 1011...101000... .......... U U U U 4 4 2 2\r
604eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4\r
605eor 32 . d 1011...110000... .......... U U U U 8 6 2 2\r
606eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4\r
607eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12\r
608eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12\r
609eori 8 . d 0000101000000... .......... U U U U 8 8 2 2\r
610eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4\r
611eori 16 . d 0000101001000... .......... U U U U 8 8 2 2\r
612eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4\r
613eori 32 . d 0000101010000... .......... U U U U 16 14 2 2\r
614eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4\r
615exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2\r
616exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2\r
617exg 32 da . 1100...110001... .......... U U U U 6 6 2 2\r
618ext 16 . . 0100100010000... .......... U U U U 4 4 4 4\r
619ext 32 . . 0100100011000... .......... U U U U 4 4 4 4\r
620extb 32 . . 0100100111000... .......... . . U U . . 4 4\r
621illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4\r
622jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0\r
623jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0\r
624lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2\r
625link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5\r
626link 16 . . 0100111001010... .......... U U U U 16 16 5 5\r
627link 32 . a7 0100100000001111 .......... . . U U . . 6 6\r
628link 32 . . 0100100000001... .......... . . U U . . 6 6\r
629lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4\r
630lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4\r
631lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4\r
632lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6\r
633lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6\r
634lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6\r
635lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5\r
636lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4\r
637lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4\r
638lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4\r
639lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6\r
640lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6\r
641lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6\r
642lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5\r
643move 8 d d 0001...000000... .......... U U U U 4 4 2 2\r
644move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
645move 8 ai d 0001...010000... .......... U U U U 8 8 4 4\r
646move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4\r
647move 8 pi d 0001...011000... .......... U U U U 8 8 4 4\r
648move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4\r
649move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4\r
650move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4\r
651move 8 pd d 0001...100000... .......... U U U U 8 8 5 5\r
652move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5\r
653move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5\r
654move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5\r
655move 8 di d 0001...101000... .......... U U U U 12 12 5 5\r
656move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5\r
657move 8 ix d 0001...110000... .......... U U U U 14 14 7 7\r
658move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7\r
659move 8 aw d 0001000111000... .......... U U U U 12 12 4 4\r
660move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4\r
661move 8 al d 0001001111000... .......... U U U U 16 16 6 6\r
662move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6\r
663move 16 d d 0011...000000... .......... U U U U 4 4 2 2\r
664move 16 d a 0011...000001... .......... U U U U 4 4 2 2\r
665move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
666move 16 ai d 0011...010000... .......... U U U U 8 8 4 4\r
667move 16 ai a 0011...010001... .......... U U U U 8 8 4 4\r
668move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4\r
669move 16 pi d 0011...011000... .......... U U U U 8 8 4 4\r
670move 16 pi a 0011...011001... .......... U U U U 8 8 4 4\r
671move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4\r
672move 16 pd d 0011...100000... .......... U U U U 8 8 5 5\r
673move 16 pd a 0011...100001... .......... U U U U 8 8 5 5\r
674move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5\r
675move 16 di d 0011...101000... .......... U U U U 12 12 5 5\r
676move 16 di a 0011...101001... .......... U U U U 12 12 5 5\r
677move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5\r
678move 16 ix d 0011...110000... .......... U U U U 14 14 7 7\r
679move 16 ix a 0011...110001... .......... U U U U 14 14 7 7\r
680move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7\r
681move 16 aw d 0011000111000... .......... U U U U 12 12 4 4\r
682move 16 aw a 0011000111001... .......... U U U U 12 12 4 4\r
683move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4\r
684move 16 al d 0011001111000... .......... U U U U 16 16 6 6\r
685move 16 al a 0011001111001... .......... U U U U 16 16 6 6\r
686move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6\r
687move 32 d d 0010...000000... .......... U U U U 4 4 2 2\r
688move 32 d a 0010...000001... .......... U U U U 4 4 2 2\r
689move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2\r
690move 32 ai d 0010...010000... .......... U U U U 12 12 4 4\r
691move 32 ai a 0010...010001... .......... U U U U 12 12 4 4\r
692move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4\r
693move 32 pi d 0010...011000... .......... U U U U 12 12 4 4\r
694move 32 pi a 0010...011001... .......... U U U U 12 12 4 4\r
695move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4\r
696move 32 pd d 0010...100000... .......... U U U U 12 14 5 5\r
697move 32 pd a 0010...100001... .......... U U U U 12 14 5 5\r
698move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5\r
699move 32 di d 0010...101000... .......... U U U U 16 16 5 5\r
700move 32 di a 0010...101001... .......... U U U U 16 16 5 5\r
701move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5\r
702move 32 ix d 0010...110000... .......... U U U U 18 18 7 7\r
703move 32 ix a 0010...110001... .......... U U U U 18 18 7 7\r
704move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7\r
705move 32 aw d 0010000111000... .......... U U U U 16 16 4 4\r
706move 32 aw a 0010000111001... .......... U U U U 16 16 4 4\r
707move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4\r
708move 32 al d 0010001111000... .......... U U U U 20 20 6 6\r
709move 32 al a 0010001111001... .......... U U U U 20 20 6 6\r
710move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6\r
711movea 16 . d 0011...001000... .......... U U U U 4 4 2 2\r
712movea 16 . a 0011...001001... .......... U U U U 4 4 2 2\r
713movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
714movea 32 . d 0010...001000... .......... U U U U 4 4 2 2\r
715movea 32 . a 0010...001001... .......... U U U U 4 4 2 2\r
716movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2\r
717move 16 frc d 0100001011000... .......... . U U U . 4 4 4\r
718move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4\r
719move 16 toc d 0100010011000... .......... U U U U 12 12 4 4\r
720move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4\r
721move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000\r
722move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000\r
723move 16 tos d 0100011011000... .......... S S S S 12 12 8 8\r
724move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8\r
725move 32 fru . 0100111001101... .......... S S S S 4 6 2 2\r
726move 32 tou . 0100111001100... .......... S S S S 4 6 2 2\r
727movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6\r
728movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12\r
729movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4\r
730movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4\r
731movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4\r
732movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4\r
733movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8\r
734movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9\r
735movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11\r
736movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8\r
737movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8\r
738movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9\r
739movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11\r
740movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8\r
741movep 16 er . 0000...100001... .......... U U U U 16 16 12 12\r
742movep 32 er . 0000...101001... .......... U U U U 24 24 18 18\r
743movep 16 re . 0000...110001... .......... U U U U 16 16 11 11\r
744movep 32 re . 0000...111001... .......... U U U U 24 24 17 17\r
745moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2\r
746moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5\r
747moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5\r
748moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5\r
749move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing\r
750muls 16 . d 1100...111000... .......... U U U U 38 28 20 20 cycles depending on operands\r
751muls 16 . . 1100...111...... A+-DXWLdxI U U U U 38 28 20 20 cycles depending on operands\r
752mulu 16 . d 1100...011000... .......... U U U U 38 26 20 20 cycles depending on operands\r
753mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 38 26 20 20 cycles depending on operands\r
754mull 32 . d 0100110000000... .......... . . U U . . 43 43\r
755mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43\r
756nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6\r
757nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6\r
758neg 8 . d 0100010000000... .......... U U U U 4 4 2 2\r
759neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4\r
760neg 16 . d 0100010001000... .......... U U U U 4 4 2 2\r
761neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4\r
762neg 32 . d 0100010010000... .......... U U U U 6 6 2 2\r
763neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4\r
764negx 8 . d 0100000000000... .......... U U U U 4 4 2 2\r
765negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4\r
766negx 16 . d 0100000001000... .......... U U U U 4 4 2 2\r
767negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4\r
768negx 32 . d 0100000010000... .......... U U U U 6 6 2 2\r
769negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4\r
770nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2\r
771not 8 . d 0100011000000... .......... U U U U 4 4 2 2\r
772not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4\r
773not 16 . d 0100011001000... .......... U U U U 4 4 2 2\r
774not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4\r
775not 32 . d 0100011010000... .......... U U U U 6 6 2 2\r
776not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4\r
777or 8 er d 1000...000000... .......... U U U U 4 4 2 2\r
778or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2\r
779or 16 er d 1000...001000... .......... U U U U 4 4 2 2\r
780or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2\r
781or 32 er d 1000...010000... .......... U U U U 6 6 2 2\r
782or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2\r
783or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4\r
784or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4\r
785or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4\r
786ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12\r
787ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12\r
788ori 8 . d 0000000000000... .......... U U U U 8 8 2 2\r
789ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4\r
790ori 16 . d 0000000001000... .......... U U U U 8 8 2 2\r
791ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4\r
792ori 32 . d 0000000010000... .......... U U U U 16 14 2 2\r
793ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4\r
794pack 16 rr . 1000...101000... .......... . . U U . . 6 6\r
795pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13\r
796pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13\r
797pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13\r
798pack 16 mm . 1000...101001... .......... . . U U . . 13 13\r
799pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5\r
800pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing\r
801reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0\r
802ror 8 s . 1110...000011... .......... U U U U 6 6 8 8\r
803ror 16 s . 1110...001011... .......... U U U U 6 6 8 8\r
804ror 32 s . 1110...010011... .......... U U U U 8 8 8 8\r
805ror 8 r . 1110...000111... .......... U U U U 6 6 8 8\r
806ror 16 r . 1110...001111... .......... U U U U 6 6 8 8\r
807ror 32 r . 1110...010111... .......... U U U U 8 8 8 8\r
808ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7\r
809rol 8 s . 1110...100011... .......... U U U U 6 6 8 8\r
810rol 16 s . 1110...101011... .......... U U U U 6 6 8 8\r
811rol 32 s . 1110...110011... .......... U U U U 8 8 8 8\r
812rol 8 r . 1110...100111... .......... U U U U 6 6 8 8\r
813rol 16 r . 1110...101111... .......... U U U U 6 6 8 8\r
814rol 32 r . 1110...110111... .......... U U U U 8 8 8 8\r
815rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7\r
816roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12\r
817roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12\r
818roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12\r
819roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12\r
820roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12\r
821roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12\r
822roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5\r
823roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12\r
824roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12\r
825roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12\r
826roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12\r
827roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12\r
828roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12\r
829roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5\r
830rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10\r
831rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated\r
832rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated\r
833rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14\r
834rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10\r
835sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4\r
836sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16\r
837sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16\r
838sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16\r
839sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16\r
840st 8 . d 0101000011000... .......... U U U U 6 4 4 4\r
841st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6\r
842sf 8 . d 0101000111000... .......... U U U U 4 4 4 4\r
843sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6\r
844scc 8 . d 0101....11000... .......... U U U U 4 4 4 4\r
845scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6\r
846stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8\r
847sub 8 er d 1001...000000... .......... U U U U 4 4 2 2\r
848sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
849sub 16 er d 1001...001000... .......... U U U U 4 4 2 2\r
850sub 16 er a 1001...001001... .......... U U U U 4 4 2 2\r
851sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2\r
852sub 32 er d 1001...010000... .......... U U U U 6 6 2 2\r
853sub 32 er a 1001...010001... .......... U U U U 6 6 2 2\r
854sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2\r
855sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4\r
856sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4\r
857sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4\r
858suba 16 . d 1001...011000... .......... U U U U 8 8 2 2\r
859suba 16 . a 1001...011001... .......... U U U U 8 8 2 2\r
860suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2\r
861suba 32 . d 1001...111000... .......... U U U U 6 6 2 2\r
862suba 32 . a 1001...111001... .......... U U U U 6 6 2 2\r
863suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2\r
864subi 8 . d 0000010000000... .......... U U U U 8 8 2 2\r
865subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4\r
866subi 16 . d 0000010001000... .......... U U U U 8 8 2 2\r
867subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4\r
868subi 32 . d 0000010010000... .......... U U U U 16 14 2 2\r
869subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4\r
870subq 8 . d 0101...100000... .......... U U U U 4 4 2 2\r
871subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4\r
872subq 16 . d 0101...101000... .......... U U U U 4 4 2 2\r
873subq 16 . a 0101...101001... .......... U U U U 8 4 2 2\r
874subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4\r
875subq 32 . d 0101...110000... .......... U U U U 8 8 2 2\r
876subq 32 . a 0101...110001... .......... U U U U 8 8 2 2\r
877subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4\r
878subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2\r
879subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2\r
880subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2\r
881subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12\r
882subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12\r
883subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12\r
884subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12\r
885subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12\r
886subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12\r
887swap 32 . . 0100100001000... .......... U U U U 4 4 4 4\r
888tas 8 . d 0100101011000... .......... U U U U 4 4 4 4\r
889tas 8 . . 0100101011...... A+-DXWL... U U U U 10 10 8 8\r
890trap 0 . . 010011100100.... .......... U U U U 4 4 4 4\r
891trapt 0 . . 0101000011111100 .......... . . U U . . 4 4\r
892trapt 16 . . 0101000011111010 .......... . . U U . . 6 6\r
893trapt 32 . . 0101000011111011 .......... . . U U . . 8 8\r
894trapf 0 . . 0101000111111100 .......... . . U U . . 4 4\r
895trapf 16 . . 0101000111111010 .......... . . U U . . 6 6\r
896trapf 32 . . 0101000111111011 .......... . . U U . . 8 8\r
897trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4\r
898trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6\r
899trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8\r
900trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4\r
901tst 8 . d 0100101000000... .......... U U U U 4 4 2 2\r
902tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2\r
903tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7\r
904tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9\r
905tst 8 . i 0100101000111100 .......... . . U U . . 6 6\r
906tst 16 . d 0100101001000... .......... U U U U 4 4 2 2\r
907tst 16 . a 0100101001001... .......... . . U U . . 2 2\r
908tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2\r
909tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7\r
910tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9\r
911tst 16 . i 0100101001111100 .......... . . U U . . 6 6\r
912tst 32 . d 0100101010000... .......... U U U U 4 4 2 2\r
913tst 32 . a 0100101010001... .......... . . U U . . 2 2\r
914tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2\r
915tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7\r
916tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9\r
917tst 32 . i 0100101010111100 .......... . . U U . . 6 6\r
918unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6\r
919unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6\r
920unpk 16 rr . 1000...110000... .......... . . U U . . 8 8\r
921unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13\r
922unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13\r
923unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13\r
924unpk 16 mm . 1000...110001... .......... . . U U . . 13 13\r
925\r
926\r
927\r
928XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
929M68KMAKE_OPCODE_HANDLER_BODY\r
930\r
931M68KMAKE_OP(1010, 0, ., .)\r
932{\r
933 m68ki_exception_1010();\r
934}\r
935\r
936\r
937M68KMAKE_OP(1111, 0, ., .)\r
938{\r
939 m68ki_exception_1111();\r
940}\r
941\r
942\r
943M68KMAKE_OP(040fpu0, 32, ., .)\r
944{\r
945 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
946 {\r
947 m68040_fpu_op0();\r
948 return;\r
949 }\r
950 m68ki_exception_1111();\r
951}\r
952\r
953\r
954M68KMAKE_OP(040fpu1, 32, ., .)\r
955{\r
956 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
957 {\r
958 m68040_fpu_op1();\r
959 return;\r
960 }\r
961 m68ki_exception_1111();\r
962}\r
963\r
964\r
965\r
966M68KMAKE_OP(abcd, 8, rr, .)\r
967{\r
968 uint* r_dst = &DX;\r
969 uint src = DY;\r
970 uint dst = *r_dst;\r
971 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
972 uint corf = 0;\r
973\r
974 if(res > 9)\r
975 corf = 6;\r
976 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
977 FLAG_V = ~res; /* Undefined V behavior */\r
978\r
979 res += corf;\r
980 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
981 if(FLAG_C)\r
982 res -= 0xa0;\r
983\r
984 FLAG_V &= res; /* Undefined V behavior part II */\r
985 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
986\r
987 res = MASK_OUT_ABOVE_8(res);\r
988 FLAG_Z |= res;\r
989\r
990 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
991}\r
992\r
993\r
994M68KMAKE_OP(abcd, 8, mm, ax7)\r
995{\r
996 uint src = OPER_AY_PD_8();\r
997 uint ea = EA_A7_PD_8();\r
998 uint dst = m68ki_read_8(ea);\r
999 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
1000 uint corf = 0;\r
1001\r
1002 if(res > 9)\r
1003 corf = 6;\r
1004 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1005 FLAG_V = ~res; /* Undefined V behavior */\r
1006\r
1007 res += corf;\r
1008 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
1009 if(FLAG_C)\r
1010 res -= 0xa0;\r
1011\r
1012 FLAG_V &= res; /* Undefined V behavior part II */\r
1013 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1014\r
1015 res = MASK_OUT_ABOVE_8(res);\r
1016 FLAG_Z |= res;\r
1017\r
1018 m68ki_write_8(ea, res);\r
1019}\r
1020\r
1021\r
1022M68KMAKE_OP(abcd, 8, mm, ay7)\r
1023{\r
1024 uint src = OPER_A7_PD_8();\r
1025 uint ea = EA_AX_PD_8();\r
1026 uint dst = m68ki_read_8(ea);\r
1027 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
1028 uint corf = 0;\r
1029\r
1030 if(res > 9)\r
1031 corf = 6;\r
1032 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1033 FLAG_V = ~res; /* Undefined V behavior */\r
1034\r
1035 res += corf;\r
1036 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
1037 if(FLAG_C)\r
1038 res -= 0xa0;\r
1039\r
1040 FLAG_V &= res; /* Undefined V behavior part II */\r
1041 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1042\r
1043 res = MASK_OUT_ABOVE_8(res);\r
1044 FLAG_Z |= res;\r
1045\r
1046 m68ki_write_8(ea, res);\r
1047}\r
1048\r
1049\r
1050M68KMAKE_OP(abcd, 8, mm, axy7)\r
1051{\r
1052 uint src = OPER_A7_PD_8();\r
1053 uint ea = EA_A7_PD_8();\r
1054 uint dst = m68ki_read_8(ea);\r
1055 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
1056 uint corf = 0;\r
1057\r
1058 if(res > 9)\r
1059 corf = 6;\r
1060 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1061 FLAG_V = ~res; /* Undefined V behavior */\r
1062\r
1063 res += corf;\r
1064 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
1065 if(FLAG_C)\r
1066 res -= 0xa0;\r
1067\r
1068 FLAG_V &= res; /* Undefined V behavior part II */\r
1069 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1070\r
1071 res = MASK_OUT_ABOVE_8(res);\r
1072 FLAG_Z |= res;\r
1073\r
1074 m68ki_write_8(ea, res);\r
1075}\r
1076\r
1077\r
1078M68KMAKE_OP(abcd, 8, mm, .)\r
1079{\r
1080 uint src = OPER_AY_PD_8();\r
1081 uint ea = EA_AX_PD_8();\r
1082 uint dst = m68ki_read_8(ea);\r
1083 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
1084 uint corf = 0;\r
1085\r
1086 if(res > 9)\r
1087 corf = 6;\r
1088 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1089 FLAG_V = ~res; /* Undefined V behavior */\r
1090\r
1091 res += corf;\r
1092 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
1093 if(FLAG_C)\r
1094 res -= 0xa0;\r
1095\r
1096 FLAG_V &= res; /* Undefined V behavior part II */\r
1097 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1098\r
1099 res = MASK_OUT_ABOVE_8(res);\r
1100 FLAG_Z |= res;\r
1101\r
1102 m68ki_write_8(ea, res);\r
1103}\r
1104\r
1105\r
1106M68KMAKE_OP(add, 8, er, d)\r
1107{\r
1108 uint* r_dst = &DX;\r
1109 uint src = MASK_OUT_ABOVE_8(DY);\r
1110 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1111 uint res = src + dst;\r
1112\r
1113 FLAG_N = NFLAG_8(res);\r
1114 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1115 FLAG_X = FLAG_C = CFLAG_8(res);\r
1116 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1117\r
1118 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1119}\r
1120\r
1121\r
1122M68KMAKE_OP(add, 8, er, .)\r
1123{\r
1124 uint* r_dst = &DX;\r
1125 uint src = M68KMAKE_GET_OPER_AY_8;\r
1126 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1127 uint res = src + dst;\r
1128\r
1129 FLAG_N = NFLAG_8(res);\r
1130 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1131 FLAG_X = FLAG_C = CFLAG_8(res);\r
1132 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1133\r
1134 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1135}\r
1136\r
1137\r
1138M68KMAKE_OP(add, 16, er, d)\r
1139{\r
1140 uint* r_dst = &DX;\r
1141 uint src = MASK_OUT_ABOVE_16(DY);\r
1142 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1143 uint res = src + dst;\r
1144\r
1145 FLAG_N = NFLAG_16(res);\r
1146 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1147 FLAG_X = FLAG_C = CFLAG_16(res);\r
1148 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1149\r
1150 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1151}\r
1152\r
1153\r
1154M68KMAKE_OP(add, 16, er, a)\r
1155{\r
1156 uint* r_dst = &DX;\r
1157 uint src = MASK_OUT_ABOVE_16(AY);\r
1158 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1159 uint res = src + dst;\r
1160\r
1161 FLAG_N = NFLAG_16(res);\r
1162 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1163 FLAG_X = FLAG_C = CFLAG_16(res);\r
1164 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1165\r
1166 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1167}\r
1168\r
1169\r
1170M68KMAKE_OP(add, 16, er, .)\r
1171{\r
1172 uint* r_dst = &DX;\r
1173 uint src = M68KMAKE_GET_OPER_AY_16;\r
1174 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1175 uint res = src + dst;\r
1176\r
1177 FLAG_N = NFLAG_16(res);\r
1178 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1179 FLAG_X = FLAG_C = CFLAG_16(res);\r
1180 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1181\r
1182 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1183}\r
1184\r
1185\r
1186M68KMAKE_OP(add, 32, er, d)\r
1187{\r
1188 uint* r_dst = &DX;\r
1189 uint src = DY;\r
1190 uint dst = *r_dst;\r
1191 uint res = src + dst;\r
1192\r
1193 FLAG_N = NFLAG_32(res);\r
1194 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1195 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1196 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1197\r
1198 *r_dst = FLAG_Z;\r
1199}\r
1200\r
1201\r
1202M68KMAKE_OP(add, 32, er, a)\r
1203{\r
1204 uint* r_dst = &DX;\r
1205 uint src = AY;\r
1206 uint dst = *r_dst;\r
1207 uint res = src + dst;\r
1208\r
1209 FLAG_N = NFLAG_32(res);\r
1210 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1211 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1212 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1213\r
1214 *r_dst = FLAG_Z;\r
1215}\r
1216\r
1217\r
1218M68KMAKE_OP(add, 32, er, .)\r
1219{\r
1220 uint* r_dst = &DX;\r
1221 uint src = M68KMAKE_GET_OPER_AY_32;\r
1222 uint dst = *r_dst;\r
1223 uint res = src + dst;\r
1224\r
1225 FLAG_N = NFLAG_32(res);\r
1226 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1227 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1228 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1229\r
1230 *r_dst = FLAG_Z;\r
1231}\r
1232\r
1233\r
1234M68KMAKE_OP(add, 8, re, .)\r
1235{\r
1236 uint ea = M68KMAKE_GET_EA_AY_8;\r
1237 uint src = MASK_OUT_ABOVE_8(DX);\r
1238 uint dst = m68ki_read_8(ea);\r
1239 uint res = src + dst;\r
1240\r
1241 FLAG_N = NFLAG_8(res);\r
1242 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1243 FLAG_X = FLAG_C = CFLAG_8(res);\r
1244 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1245\r
1246 m68ki_write_8(ea, FLAG_Z);\r
1247}\r
1248\r
1249\r
1250M68KMAKE_OP(add, 16, re, .)\r
1251{\r
1252 uint ea = M68KMAKE_GET_EA_AY_16;\r
1253 uint src = MASK_OUT_ABOVE_16(DX);\r
1254 uint dst = m68ki_read_16(ea);\r
1255 uint res = src + dst;\r
1256\r
1257 FLAG_N = NFLAG_16(res);\r
1258 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1259 FLAG_X = FLAG_C = CFLAG_16(res);\r
1260 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1261\r
1262 m68ki_write_16(ea, FLAG_Z);\r
1263}\r
1264\r
1265\r
1266M68KMAKE_OP(add, 32, re, .)\r
1267{\r
1268 uint ea = M68KMAKE_GET_EA_AY_32;\r
1269 uint src = DX;\r
1270 uint dst = m68ki_read_32(ea);\r
1271 uint res = src + dst;\r
1272\r
1273 FLAG_N = NFLAG_32(res);\r
1274 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1275 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1276 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1277\r
1278 m68ki_write_32(ea, FLAG_Z);\r
1279}\r
1280\r
1281\r
1282M68KMAKE_OP(adda, 16, ., d)\r
1283{\r
1284 uint* r_dst = &AX;\r
1285\r
1286 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));\r
1287}\r
1288\r
1289\r
1290M68KMAKE_OP(adda, 16, ., a)\r
1291{\r
1292 uint* r_dst = &AX;\r
1293\r
1294 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));\r
1295}\r
1296\r
1297\r
1298M68KMAKE_OP(adda, 16, ., .)\r
1299{\r
1300 uint* r_dst = &AX;\r
1301 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
1302\r
1303 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
1304}\r
1305\r
1306\r
1307M68KMAKE_OP(adda, 32, ., d)\r
1308{\r
1309 uint* r_dst = &AX;\r
1310\r
1311 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);\r
1312}\r
1313\r
1314\r
1315M68KMAKE_OP(adda, 32, ., a)\r
1316{\r
1317 uint* r_dst = &AX;\r
1318\r
1319 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);\r
1320}\r
1321\r
1322\r
1323M68KMAKE_OP(adda, 32, ., .)\r
1324{\r
1325 uint* r_dst = &AX;\r
1326 uint src = M68KMAKE_GET_OPER_AY_32; // notaz\r
1327\r
1328 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
1329}\r
1330\r
1331\r
1332M68KMAKE_OP(addi, 8, ., d)\r
1333{\r
1334 uint* r_dst = &DY;\r
1335 uint src = OPER_I_8();\r
1336 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1337 uint res = src + dst;\r
1338\r
1339 FLAG_N = NFLAG_8(res);\r
1340 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1341 FLAG_X = FLAG_C = CFLAG_8(res);\r
1342 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1343\r
1344 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1345}\r
1346\r
1347\r
1348M68KMAKE_OP(addi, 8, ., .)\r
1349{\r
1350 uint src = OPER_I_8();\r
1351 uint ea = M68KMAKE_GET_EA_AY_8;\r
1352 uint dst = m68ki_read_8(ea);\r
1353 uint res = src + dst;\r
1354\r
1355 FLAG_N = NFLAG_8(res);\r
1356 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1357 FLAG_X = FLAG_C = CFLAG_8(res);\r
1358 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1359\r
1360 m68ki_write_8(ea, FLAG_Z);\r
1361}\r
1362\r
1363\r
1364M68KMAKE_OP(addi, 16, ., d)\r
1365{\r
1366 uint* r_dst = &DY;\r
1367 uint src = OPER_I_16();\r
1368 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1369 uint res = src + dst;\r
1370\r
1371 FLAG_N = NFLAG_16(res);\r
1372 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1373 FLAG_X = FLAG_C = CFLAG_16(res);\r
1374 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1375\r
1376 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1377}\r
1378\r
1379\r
1380M68KMAKE_OP(addi, 16, ., .)\r
1381{\r
1382 uint src = OPER_I_16();\r
1383 uint ea = M68KMAKE_GET_EA_AY_16;\r
1384 uint dst = m68ki_read_16(ea);\r
1385 uint res = src + dst;\r
1386\r
1387 FLAG_N = NFLAG_16(res);\r
1388 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1389 FLAG_X = FLAG_C = CFLAG_16(res);\r
1390 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1391\r
1392 m68ki_write_16(ea, FLAG_Z);\r
1393}\r
1394\r
1395\r
1396M68KMAKE_OP(addi, 32, ., d)\r
1397{\r
1398 uint* r_dst = &DY;\r
1399 uint src = OPER_I_32();\r
1400 uint dst = *r_dst;\r
1401 uint res = src + dst;\r
1402\r
1403 FLAG_N = NFLAG_32(res);\r
1404 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1405 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1406 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1407\r
1408 *r_dst = FLAG_Z;\r
1409}\r
1410\r
1411\r
1412M68KMAKE_OP(addi, 32, ., .)\r
1413{\r
1414 uint src = OPER_I_32();\r
1415 uint ea = M68KMAKE_GET_EA_AY_32;\r
1416 uint dst = m68ki_read_32(ea);\r
1417 uint res = src + dst;\r
1418\r
1419 FLAG_N = NFLAG_32(res);\r
1420 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1421 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1422 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1423\r
1424 m68ki_write_32(ea, FLAG_Z);\r
1425}\r
1426\r
1427\r
1428M68KMAKE_OP(addq, 8, ., d)\r
1429{\r
1430 uint* r_dst = &DY;\r
1431 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1432 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1433 uint res = src + dst;\r
1434\r
1435 FLAG_N = NFLAG_8(res);\r
1436 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1437 FLAG_X = FLAG_C = CFLAG_8(res);\r
1438 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1439\r
1440 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1441}\r
1442\r
1443\r
1444M68KMAKE_OP(addq, 8, ., .)\r
1445{\r
1446 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1447 uint ea = M68KMAKE_GET_EA_AY_8;\r
1448 uint dst = m68ki_read_8(ea);\r
1449 uint res = src + dst;\r
1450\r
1451 FLAG_N = NFLAG_8(res);\r
1452 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1453 FLAG_X = FLAG_C = CFLAG_8(res);\r
1454 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1455\r
1456 m68ki_write_8(ea, FLAG_Z);\r
1457}\r
1458\r
1459\r
1460M68KMAKE_OP(addq, 16, ., d)\r
1461{\r
1462 uint* r_dst = &DY;\r
1463 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1464 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1465 uint res = src + dst;\r
1466\r
1467 FLAG_N = NFLAG_16(res);\r
1468 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1469 FLAG_X = FLAG_C = CFLAG_16(res);\r
1470 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1471\r
1472 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1473}\r
1474\r
1475\r
1476M68KMAKE_OP(addq, 16, ., a)\r
1477{\r
1478 uint* r_dst = &AY;\r
1479\r
1480 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1481}\r
1482\r
1483\r
1484M68KMAKE_OP(addq, 16, ., .)\r
1485{\r
1486 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1487 uint ea = M68KMAKE_GET_EA_AY_16;\r
1488 uint dst = m68ki_read_16(ea);\r
1489 uint res = src + dst;\r
1490\r
1491 FLAG_N = NFLAG_16(res);\r
1492 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1493 FLAG_X = FLAG_C = CFLAG_16(res);\r
1494 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1495\r
1496 m68ki_write_16(ea, FLAG_Z);\r
1497}\r
1498\r
1499\r
1500M68KMAKE_OP(addq, 32, ., d)\r
1501{\r
1502 uint* r_dst = &DY;\r
1503 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1504 uint dst = *r_dst;\r
1505 uint res = src + dst;\r
1506\r
1507 FLAG_N = NFLAG_32(res);\r
1508 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1509 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1510 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1511\r
1512 *r_dst = FLAG_Z;\r
1513}\r
1514\r
1515\r
1516M68KMAKE_OP(addq, 32, ., a)\r
1517{\r
1518 uint* r_dst = &AY;\r
1519\r
1520 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1521}\r
1522\r
1523\r
1524M68KMAKE_OP(addq, 32, ., .)\r
1525{\r
1526 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1527 uint ea = M68KMAKE_GET_EA_AY_32;\r
1528 uint dst = m68ki_read_32(ea);\r
1529 uint res = src + dst;\r
1530\r
1531\r
1532 FLAG_N = NFLAG_32(res);\r
1533 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1534 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1535 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1536\r
1537 m68ki_write_32(ea, FLAG_Z);\r
1538}\r
1539\r
1540\r
1541M68KMAKE_OP(addx, 8, rr, .)\r
1542{\r
1543 uint* r_dst = &DX;\r
1544 uint src = MASK_OUT_ABOVE_8(DY);\r
1545 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1546 uint res = src + dst + XFLAG_AS_1();\r
1547\r
1548 FLAG_N = NFLAG_8(res);\r
1549 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1550 FLAG_X = FLAG_C = CFLAG_8(res);\r
1551\r
1552 res = MASK_OUT_ABOVE_8(res);\r
1553 FLAG_Z |= res;\r
1554\r
1555 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1556}\r
1557\r
1558\r
1559M68KMAKE_OP(addx, 16, rr, .)\r
1560{\r
1561 uint* r_dst = &DX;\r
1562 uint src = MASK_OUT_ABOVE_16(DY);\r
1563 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1564 uint res = src + dst + XFLAG_AS_1();\r
1565\r
1566 FLAG_N = NFLAG_16(res);\r
1567 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1568 FLAG_X = FLAG_C = CFLAG_16(res);\r
1569\r
1570 res = MASK_OUT_ABOVE_16(res);\r
1571 FLAG_Z |= res;\r
1572\r
1573 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1574}\r
1575\r
1576\r
1577M68KMAKE_OP(addx, 32, rr, .)\r
1578{\r
1579 uint* r_dst = &DX;\r
1580 uint src = DY;\r
1581 uint dst = *r_dst;\r
1582 uint res = src + dst + XFLAG_AS_1();\r
1583\r
1584 FLAG_N = NFLAG_32(res);\r
1585 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1586 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1587\r
1588 res = MASK_OUT_ABOVE_32(res);\r
1589 FLAG_Z |= res;\r
1590\r
1591 *r_dst = res;\r
1592}\r
1593\r
1594\r
1595M68KMAKE_OP(addx, 8, mm, ax7)\r
1596{\r
1597 uint src = OPER_AY_PD_8();\r
1598 uint ea = EA_A7_PD_8();\r
1599 uint dst = m68ki_read_8(ea);\r
1600 uint res = src + dst + XFLAG_AS_1();\r
1601\r
1602 FLAG_N = NFLAG_8(res);\r
1603 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1604 FLAG_X = FLAG_C = CFLAG_8(res);\r
1605\r
1606 res = MASK_OUT_ABOVE_8(res);\r
1607 FLAG_Z |= res;\r
1608\r
1609 m68ki_write_8(ea, res);\r
1610}\r
1611\r
1612\r
1613M68KMAKE_OP(addx, 8, mm, ay7)\r
1614{\r
1615 uint src = OPER_A7_PD_8();\r
1616 uint ea = EA_AX_PD_8();\r
1617 uint dst = m68ki_read_8(ea);\r
1618 uint res = src + dst + XFLAG_AS_1();\r
1619\r
1620 FLAG_N = NFLAG_8(res);\r
1621 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1622 FLAG_X = FLAG_C = CFLAG_8(res);\r
1623\r
1624 res = MASK_OUT_ABOVE_8(res);\r
1625 FLAG_Z |= res;\r
1626\r
1627 m68ki_write_8(ea, res);\r
1628}\r
1629\r
1630\r
1631M68KMAKE_OP(addx, 8, mm, axy7)\r
1632{\r
1633 uint src = OPER_A7_PD_8();\r
1634 uint ea = EA_A7_PD_8();\r
1635 uint dst = m68ki_read_8(ea);\r
1636 uint res = src + dst + XFLAG_AS_1();\r
1637\r
1638 FLAG_N = NFLAG_8(res);\r
1639 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1640 FLAG_X = FLAG_C = CFLAG_8(res);\r
1641\r
1642 res = MASK_OUT_ABOVE_8(res);\r
1643 FLAG_Z |= res;\r
1644\r
1645 m68ki_write_8(ea, res);\r
1646}\r
1647\r
1648\r
1649M68KMAKE_OP(addx, 8, mm, .)\r
1650{\r
1651 uint src = OPER_AY_PD_8();\r
1652 uint ea = EA_AX_PD_8();\r
1653 uint dst = m68ki_read_8(ea);\r
1654 uint res = src + dst + XFLAG_AS_1();\r
1655\r
1656 FLAG_N = NFLAG_8(res);\r
1657 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1658 FLAG_X = FLAG_C = CFLAG_8(res);\r
1659\r
1660 res = MASK_OUT_ABOVE_8(res);\r
1661 FLAG_Z |= res;\r
1662\r
1663 m68ki_write_8(ea, res);\r
1664}\r
1665\r
1666\r
1667M68KMAKE_OP(addx, 16, mm, .)\r
1668{\r
1669 uint src = OPER_AY_PD_16();\r
1670 uint ea = EA_AX_PD_16();\r
1671 uint dst = m68ki_read_16(ea);\r
1672 uint res = src + dst + XFLAG_AS_1();\r
1673\r
1674 FLAG_N = NFLAG_16(res);\r
1675 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1676 FLAG_X = FLAG_C = CFLAG_16(res);\r
1677\r
1678 res = MASK_OUT_ABOVE_16(res);\r
1679 FLAG_Z |= res;\r
1680\r
1681 m68ki_write_16(ea, res);\r
1682}\r
1683\r
1684\r
1685M68KMAKE_OP(addx, 32, mm, .)\r
1686{\r
1687 uint src = OPER_AY_PD_32();\r
1688 uint ea = EA_AX_PD_32();\r
1689 uint dst = m68ki_read_32(ea);\r
1690 uint res = src + dst + XFLAG_AS_1();\r
1691\r
1692 FLAG_N = NFLAG_32(res);\r
1693 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1694 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1695\r
1696 res = MASK_OUT_ABOVE_32(res);\r
1697 FLAG_Z |= res;\r
1698\r
1699 m68ki_write_32(ea, res);\r
1700}\r
1701\r
1702\r
1703M68KMAKE_OP(and, 8, er, d)\r
1704{\r
1705 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));\r
1706\r
1707 FLAG_N = NFLAG_8(FLAG_Z);\r
1708 FLAG_C = CFLAG_CLEAR;\r
1709 FLAG_V = VFLAG_CLEAR;\r
1710}\r
1711\r
1712\r
1713M68KMAKE_OP(and, 8, er, .)\r
1714{\r
1715 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));\r
1716\r
1717 FLAG_N = NFLAG_8(FLAG_Z);\r
1718 FLAG_C = CFLAG_CLEAR;\r
1719 FLAG_V = VFLAG_CLEAR;\r
1720}\r
1721\r
1722\r
1723M68KMAKE_OP(and, 16, er, d)\r
1724{\r
1725 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));\r
1726\r
1727 FLAG_N = NFLAG_16(FLAG_Z);\r
1728 FLAG_C = CFLAG_CLEAR;\r
1729 FLAG_V = VFLAG_CLEAR;\r
1730}\r
1731\r
1732\r
1733M68KMAKE_OP(and, 16, er, .)\r
1734{\r
1735 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));\r
1736\r
1737 FLAG_N = NFLAG_16(FLAG_Z);\r
1738 FLAG_C = CFLAG_CLEAR;\r
1739 FLAG_V = VFLAG_CLEAR;\r
1740}\r
1741\r
1742\r
1743M68KMAKE_OP(and, 32, er, d)\r
1744{\r
1745 FLAG_Z = DX &= DY;\r
1746\r
1747 FLAG_N = NFLAG_32(FLAG_Z);\r
1748 FLAG_C = CFLAG_CLEAR;\r
1749 FLAG_V = VFLAG_CLEAR;\r
1750}\r
1751\r
1752\r
1753M68KMAKE_OP(and, 32, er, .)\r
1754{\r
1755 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;\r
1756\r
1757 FLAG_N = NFLAG_32(FLAG_Z);\r
1758 FLAG_C = CFLAG_CLEAR;\r
1759 FLAG_V = VFLAG_CLEAR;\r
1760}\r
1761\r
1762\r
1763M68KMAKE_OP(and, 8, re, .)\r
1764{\r
1765 uint ea = M68KMAKE_GET_EA_AY_8;\r
1766 uint res = DX & m68ki_read_8(ea);\r
1767\r
1768 FLAG_N = NFLAG_8(res);\r
1769 FLAG_C = CFLAG_CLEAR;\r
1770 FLAG_V = VFLAG_CLEAR;\r
1771 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1772\r
1773 m68ki_write_8(ea, FLAG_Z);\r
1774}\r
1775\r
1776\r
1777M68KMAKE_OP(and, 16, re, .)\r
1778{\r
1779 uint ea = M68KMAKE_GET_EA_AY_16;\r
1780 uint res = DX & m68ki_read_16(ea);\r
1781\r
1782 FLAG_N = NFLAG_16(res);\r
1783 FLAG_C = CFLAG_CLEAR;\r
1784 FLAG_V = VFLAG_CLEAR;\r
1785 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1786\r
1787 m68ki_write_16(ea, FLAG_Z);\r
1788}\r
1789\r
1790\r
1791M68KMAKE_OP(and, 32, re, .)\r
1792{\r
1793 uint ea = M68KMAKE_GET_EA_AY_32;\r
1794 uint res = DX & m68ki_read_32(ea);\r
1795\r
1796 FLAG_N = NFLAG_32(res);\r
1797 FLAG_Z = res;\r
1798 FLAG_C = CFLAG_CLEAR;\r
1799 FLAG_V = VFLAG_CLEAR;\r
1800\r
1801 m68ki_write_32(ea, res);\r
1802}\r
1803\r
1804\r
1805M68KMAKE_OP(andi, 8, ., d)\r
1806{\r
1807 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));\r
1808\r
1809 FLAG_N = NFLAG_8(FLAG_Z);\r
1810 FLAG_C = CFLAG_CLEAR;\r
1811 FLAG_V = VFLAG_CLEAR;\r
1812}\r
1813\r
1814\r
1815M68KMAKE_OP(andi, 8, ., .)\r
1816{\r
1817 uint src = OPER_I_8();\r
1818 uint ea = M68KMAKE_GET_EA_AY_8;\r
1819 uint res = src & m68ki_read_8(ea);\r
1820\r
1821 FLAG_N = NFLAG_8(res);\r
1822 FLAG_Z = res;\r
1823 FLAG_C = CFLAG_CLEAR;\r
1824 FLAG_V = VFLAG_CLEAR;\r
1825\r
1826 m68ki_write_8(ea, res);\r
1827}\r
1828\r
1829\r
1830M68KMAKE_OP(andi, 16, ., d)\r
1831{\r
1832 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));\r
1833\r
1834 FLAG_N = NFLAG_16(FLAG_Z);\r
1835 FLAG_C = CFLAG_CLEAR;\r
1836 FLAG_V = VFLAG_CLEAR;\r
1837}\r
1838\r
1839\r
1840M68KMAKE_OP(andi, 16, ., .)\r
1841{\r
1842 uint src = OPER_I_16();\r
1843 uint ea = M68KMAKE_GET_EA_AY_16;\r
1844 uint res = src & m68ki_read_16(ea);\r
1845\r
1846 FLAG_N = NFLAG_16(res);\r
1847 FLAG_Z = res;\r
1848 FLAG_C = CFLAG_CLEAR;\r
1849 FLAG_V = VFLAG_CLEAR;\r
1850\r
1851 m68ki_write_16(ea, res);\r
1852}\r
1853\r
1854\r
1855M68KMAKE_OP(andi, 32, ., d)\r
1856{\r
1857 FLAG_Z = DY &= (OPER_I_32());\r
1858\r
1859 FLAG_N = NFLAG_32(FLAG_Z);\r
1860 FLAG_C = CFLAG_CLEAR;\r
1861 FLAG_V = VFLAG_CLEAR;\r
1862}\r
1863\r
1864\r
1865M68KMAKE_OP(andi, 32, ., .)\r
1866{\r
1867 uint src = OPER_I_32();\r
1868 uint ea = M68KMAKE_GET_EA_AY_32;\r
1869 uint res = src & m68ki_read_32(ea);\r
1870\r
1871 FLAG_N = NFLAG_32(res);\r
1872 FLAG_Z = res;\r
1873 FLAG_C = CFLAG_CLEAR;\r
1874 FLAG_V = VFLAG_CLEAR;\r
1875\r
1876 m68ki_write_32(ea, res);\r
1877}\r
1878\r
1879\r
1880M68KMAKE_OP(andi, 16, toc, .)\r
1881{\r
1882 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());\r
1883}\r
1884\r
1885\r
1886M68KMAKE_OP(andi, 16, tos, .)\r
1887{\r
1888 if(FLAG_S)\r
1889 {\r
1890 uint src = OPER_I_16();\r
1891 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
1892 m68ki_set_sr(m68ki_get_sr() & src);\r
1893 return;\r
1894 }\r
1895 m68ki_exception_privilege_violation();\r
1896}\r
1897\r
1898\r
1899M68KMAKE_OP(asr, 8, s, .)\r
1900{\r
1901 uint* r_dst = &DY;\r
1902 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1903 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1904 uint res = src >> shift;\r
1905\r
1906 if(shift != 0)\r
1907 USE_CYCLES(shift<<CYC_SHIFT);\r
1908\r
1909 if(GET_MSB_8(src))\r
1910 res |= m68ki_shift_8_table[shift];\r
1911\r
1912 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1913\r
1914 FLAG_N = NFLAG_8(res);\r
1915 FLAG_Z = res;\r
1916 FLAG_V = VFLAG_CLEAR;\r
1917 FLAG_X = FLAG_C = src << (9-shift);\r
1918}\r
1919\r
1920\r
1921M68KMAKE_OP(asr, 16, s, .)\r
1922{\r
1923 uint* r_dst = &DY;\r
1924 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1925 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1926 uint res = src >> shift;\r
1927\r
1928 if(shift != 0)\r
1929 USE_CYCLES(shift<<CYC_SHIFT);\r
1930\r
1931 if(GET_MSB_16(src))\r
1932 res |= m68ki_shift_16_table[shift];\r
1933\r
1934 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1935\r
1936 FLAG_N = NFLAG_16(res);\r
1937 FLAG_Z = res;\r
1938 FLAG_V = VFLAG_CLEAR;\r
1939 FLAG_X = FLAG_C = src << (9-shift);\r
1940}\r
1941\r
1942\r
1943M68KMAKE_OP(asr, 32, s, .)\r
1944{\r
1945 uint* r_dst = &DY;\r
1946 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1947 uint src = *r_dst;\r
1948 uint res = src >> shift;\r
1949\r
1950 if(shift != 0)\r
1951 USE_CYCLES(shift<<CYC_SHIFT);\r
1952\r
1953 if(GET_MSB_32(src))\r
1954 res |= m68ki_shift_32_table[shift];\r
1955\r
1956 *r_dst = res;\r
1957\r
1958 FLAG_N = NFLAG_32(res);\r
1959 FLAG_Z = res;\r
1960 FLAG_V = VFLAG_CLEAR;\r
1961 FLAG_X = FLAG_C = src << (9-shift);\r
1962}\r
1963\r
1964\r
1965M68KMAKE_OP(asr, 8, r, .)\r
1966{\r
1967 uint* r_dst = &DY;\r
1968 uint shift = DX & 0x3f;\r
1969 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1970 uint res = src >> shift;\r
1971\r
1972 if(shift != 0)\r
1973 {\r
1974 USE_CYCLES(shift<<CYC_SHIFT);\r
1975\r
1976 if(shift < 8)\r
1977 {\r
1978 if(GET_MSB_8(src))\r
1979 res |= m68ki_shift_8_table[shift];\r
1980\r
1981 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1982\r
1983 FLAG_X = FLAG_C = src << (9-shift);\r
1984 FLAG_N = NFLAG_8(res);\r
1985 FLAG_Z = res;\r
1986 FLAG_V = VFLAG_CLEAR;\r
1987 return;\r
1988 }\r
1989\r
1990 if(GET_MSB_8(src))\r
1991 {\r
1992 *r_dst |= 0xff;\r
1993 FLAG_C = CFLAG_SET;\r
1994 FLAG_X = XFLAG_SET;\r
1995 FLAG_N = NFLAG_SET;\r
1996 FLAG_Z = ZFLAG_CLEAR;\r
1997 FLAG_V = VFLAG_CLEAR;\r
1998 return;\r
1999 }\r
2000\r
2001 *r_dst &= 0xffffff00;\r
2002 FLAG_C = CFLAG_CLEAR;\r
2003 FLAG_X = XFLAG_CLEAR;\r
2004 FLAG_N = NFLAG_CLEAR;\r
2005 FLAG_Z = ZFLAG_SET;\r
2006 FLAG_V = VFLAG_CLEAR;\r
2007 return;\r
2008 }\r
2009\r
2010 FLAG_C = CFLAG_CLEAR;\r
2011 FLAG_N = NFLAG_8(src);\r
2012 FLAG_Z = src;\r
2013 FLAG_V = VFLAG_CLEAR;\r
2014}\r
2015\r
2016\r
2017M68KMAKE_OP(asr, 16, r, .)\r
2018{\r
2019 uint* r_dst = &DY;\r
2020 uint shift = DX & 0x3f;\r
2021 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2022 uint res = src >> shift;\r
2023\r
2024 if(shift != 0)\r
2025 {\r
2026 USE_CYCLES(shift<<CYC_SHIFT);\r
2027\r
2028 if(shift < 16)\r
2029 {\r
2030 if(GET_MSB_16(src))\r
2031 res |= m68ki_shift_16_table[shift];\r
2032\r
2033 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2034\r
2035 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
2036 FLAG_N = NFLAG_16(res);\r
2037 FLAG_Z = res;\r
2038 FLAG_V = VFLAG_CLEAR;\r
2039 return;\r
2040 }\r
2041\r
2042 if(GET_MSB_16(src))\r
2043 {\r
2044 *r_dst |= 0xffff;\r
2045 FLAG_C = CFLAG_SET;\r
2046 FLAG_X = XFLAG_SET;\r
2047 FLAG_N = NFLAG_SET;\r
2048 FLAG_Z = ZFLAG_CLEAR;\r
2049 FLAG_V = VFLAG_CLEAR;\r
2050 return;\r
2051 }\r
2052\r
2053 *r_dst &= 0xffff0000;\r
2054 FLAG_C = CFLAG_CLEAR;\r
2055 FLAG_X = XFLAG_CLEAR;\r
2056 FLAG_N = NFLAG_CLEAR;\r
2057 FLAG_Z = ZFLAG_SET;\r
2058 FLAG_V = VFLAG_CLEAR;\r
2059 return;\r
2060 }\r
2061\r
2062 FLAG_C = CFLAG_CLEAR;\r
2063 FLAG_N = NFLAG_16(src);\r
2064 FLAG_Z = src;\r
2065 FLAG_V = VFLAG_CLEAR;\r
2066}\r
2067\r
2068\r
2069M68KMAKE_OP(asr, 32, r, .)\r
2070{\r
2071 uint* r_dst = &DY;\r
2072 uint shift = DX & 0x3f;\r
2073 uint src = *r_dst;\r
2074 uint res = src >> shift;\r
2075\r
2076 if(shift != 0)\r
2077 {\r
2078 USE_CYCLES(shift<<CYC_SHIFT);\r
2079\r
2080 if(shift < 32)\r
2081 {\r
2082 if(GET_MSB_32(src))\r
2083 res |= m68ki_shift_32_table[shift];\r
2084\r
2085 *r_dst = res;\r
2086\r
2087 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
2088 FLAG_N = NFLAG_32(res);\r
2089 FLAG_Z = res;\r
2090 FLAG_V = VFLAG_CLEAR;\r
2091 return;\r
2092 }\r
2093\r
2094 if(GET_MSB_32(src))\r
2095 {\r
2096 *r_dst = 0xffffffff;\r
2097 FLAG_C = CFLAG_SET;\r
2098 FLAG_X = XFLAG_SET;\r
2099 FLAG_N = NFLAG_SET;\r
2100 FLAG_Z = ZFLAG_CLEAR;\r
2101 FLAG_V = VFLAG_CLEAR;\r
2102 return;\r
2103 }\r
2104\r
2105 *r_dst = 0;\r
2106 FLAG_C = CFLAG_CLEAR;\r
2107 FLAG_X = XFLAG_CLEAR;\r
2108 FLAG_N = NFLAG_CLEAR;\r
2109 FLAG_Z = ZFLAG_SET;\r
2110 FLAG_V = VFLAG_CLEAR;\r
2111 return;\r
2112 }\r
2113\r
2114 FLAG_C = CFLAG_CLEAR;\r
2115 FLAG_N = NFLAG_32(src);\r
2116 FLAG_Z = src;\r
2117 FLAG_V = VFLAG_CLEAR;\r
2118}\r
2119\r
2120\r
2121M68KMAKE_OP(asr, 16, ., .)\r
2122{\r
2123 uint ea = M68KMAKE_GET_EA_AY_16;\r
2124 uint src = m68ki_read_16(ea);\r
2125 uint res = src >> 1;\r
2126\r
2127 if(GET_MSB_16(src))\r
2128 res |= 0x8000;\r
2129\r
2130 m68ki_write_16(ea, res);\r
2131\r
2132 FLAG_N = NFLAG_16(res);\r
2133 FLAG_Z = res;\r
2134 FLAG_V = VFLAG_CLEAR;\r
2135 FLAG_C = FLAG_X = src << 8;\r
2136}\r
2137\r
2138\r
2139M68KMAKE_OP(asl, 8, s, .)\r
2140{\r
2141 uint* r_dst = &DY;\r
2142 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2143 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2144 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2145\r
2146 if(shift != 0)\r
2147 USE_CYCLES(shift<<CYC_SHIFT);\r
2148\r
2149 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2150\r
2151 FLAG_X = FLAG_C = src << shift;\r
2152 FLAG_N = NFLAG_8(res);\r
2153 FLAG_Z = res;\r
2154 src &= m68ki_shift_8_table[shift + 1];\r
2155 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;\r
2156}\r
2157\r
2158\r
2159M68KMAKE_OP(asl, 16, s, .)\r
2160{\r
2161 uint* r_dst = &DY;\r
2162 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2163 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2164 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2165\r
2166 if(shift != 0)\r
2167 USE_CYCLES(shift<<CYC_SHIFT);\r
2168\r
2169 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2170\r
2171 FLAG_N = NFLAG_16(res);\r
2172 FLAG_Z = res;\r
2173 FLAG_X = FLAG_C = src >> (8-shift);\r
2174 src &= m68ki_shift_16_table[shift + 1];\r
2175 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2176}\r
2177\r
2178\r
2179M68KMAKE_OP(asl, 32, s, .)\r
2180{\r
2181 uint* r_dst = &DY;\r
2182 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2183 uint src = *r_dst;\r
2184 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2185\r
2186 if(shift != 0)\r
2187 USE_CYCLES(shift<<CYC_SHIFT);\r
2188\r
2189 *r_dst = res;\r
2190\r
2191 FLAG_N = NFLAG_32(res);\r
2192 FLAG_Z = res;\r
2193 FLAG_X = FLAG_C = src >> (24-shift);\r
2194 src &= m68ki_shift_32_table[shift + 1];\r
2195 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2196}\r
2197\r
2198\r
2199M68KMAKE_OP(asl, 8, r, .)\r
2200{\r
2201 uint* r_dst = &DY;\r
2202 uint shift = DX & 0x3f;\r
2203 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2204 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2205\r
2206 if(shift != 0)\r
2207 {\r
2208 USE_CYCLES(shift<<CYC_SHIFT);\r
2209\r
2210 if(shift < 8)\r
2211 {\r
2212 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2213 FLAG_X = FLAG_C = src << shift;\r
2214 FLAG_N = NFLAG_8(res);\r
2215 FLAG_Z = res;\r
2216 src &= m68ki_shift_8_table[shift + 1];\r
2217 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;\r
2218 return;\r
2219 }\r
2220\r
2221 *r_dst &= 0xffffff00;\r
2222 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;\r
2223 FLAG_N = NFLAG_CLEAR;\r
2224 FLAG_Z = ZFLAG_SET;\r
2225 FLAG_V = (!(src == 0))<<7;\r
2226 return;\r
2227 }\r
2228\r
2229 FLAG_C = CFLAG_CLEAR;\r
2230 FLAG_N = NFLAG_8(src);\r
2231 FLAG_Z = src;\r
2232 FLAG_V = VFLAG_CLEAR;\r
2233}\r
2234\r
2235\r
2236M68KMAKE_OP(asl, 16, r, .)\r
2237{\r
2238 uint* r_dst = &DY;\r
2239 uint shift = DX & 0x3f;\r
2240 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2241 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2242\r
2243 if(shift != 0)\r
2244 {\r
2245 USE_CYCLES(shift<<CYC_SHIFT);\r
2246\r
2247 if(shift < 16)\r
2248 {\r
2249 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2250 FLAG_X = FLAG_C = (src << shift) >> 8;\r
2251 FLAG_N = NFLAG_16(res);\r
2252 FLAG_Z = res;\r
2253 src &= m68ki_shift_16_table[shift + 1];\r
2254 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2255 return;\r
2256 }\r
2257\r
2258 *r_dst &= 0xffff0000;\r
2259 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;\r
2260 FLAG_N = NFLAG_CLEAR;\r
2261 FLAG_Z = ZFLAG_SET;\r
2262 FLAG_V = (!(src == 0))<<7;\r
2263 return;\r
2264 }\r
2265\r
2266 FLAG_C = CFLAG_CLEAR;\r
2267 FLAG_N = NFLAG_16(src);\r
2268 FLAG_Z = src;\r
2269 FLAG_V = VFLAG_CLEAR;\r
2270}\r
2271\r
2272\r
2273M68KMAKE_OP(asl, 32, r, .)\r
2274{\r
2275 uint* r_dst = &DY;\r
2276 uint shift = DX & 0x3f;\r
2277 uint src = *r_dst;\r
2278 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2279\r
2280 if(shift != 0)\r
2281 {\r
2282 USE_CYCLES(shift<<CYC_SHIFT);\r
2283\r
2284 if(shift < 32)\r
2285 {\r
2286 *r_dst = res;\r
2287 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
2288 FLAG_N = NFLAG_32(res);\r
2289 FLAG_Z = res;\r
2290 src &= m68ki_shift_32_table[shift + 1];\r
2291 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2292 return;\r
2293 }\r
2294\r
2295 *r_dst = 0;\r
2296 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
2297 FLAG_N = NFLAG_CLEAR;\r
2298 FLAG_Z = ZFLAG_SET;\r
2299 FLAG_V = (!(src == 0))<<7;\r
2300 return;\r
2301 }\r
2302\r
2303 FLAG_C = CFLAG_CLEAR;\r
2304 FLAG_N = NFLAG_32(src);\r
2305 FLAG_Z = src;\r
2306 FLAG_V = VFLAG_CLEAR;\r
2307}\r
2308\r
2309\r
2310M68KMAKE_OP(asl, 16, ., .)\r
2311{\r
2312 uint ea = M68KMAKE_GET_EA_AY_16;\r
2313 uint src = m68ki_read_16(ea);\r
2314 uint res = MASK_OUT_ABOVE_16(src << 1);\r
2315\r
2316 m68ki_write_16(ea, res);\r
2317\r
2318 FLAG_N = NFLAG_16(res);\r
2319 FLAG_Z = res;\r
2320 FLAG_X = FLAG_C = src >> 7;\r
2321 src &= 0xc000;\r
2322 FLAG_V = (!(src == 0 || src == 0xc000))<<7;\r
2323}\r
2324\r
2325\r
2326M68KMAKE_OP(bcc, 8, ., .)\r
2327{\r
2328 if(M68KMAKE_CC)\r
2329 {\r
2330 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2331 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2332 return;\r
2333 }\r
2334 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2335}\r
2336\r
2337\r
2338M68KMAKE_OP(bcc, 16, ., .)\r
2339{\r
2340 if(M68KMAKE_CC)\r
2341 {\r
2342 uint offset = OPER_I_16();\r
2343 REG_PC -= 2;\r
2344 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2345 m68ki_branch_16(offset);\r
2346 return;\r
2347 }\r
2348 REG_PC += 2;\r
2349 USE_CYCLES(CYC_BCC_NOTAKE_W);\r
2350}\r
2351\r
2352\r
2353M68KMAKE_OP(bcc, 32, ., .)\r
2354{\r
2355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2356 {\r
2357 if(M68KMAKE_CC)\r
2358 {\r
2359 uint offset = OPER_I_32();\r
2360 REG_PC -= 4;\r
2361 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2362 m68ki_branch_32(offset);\r
2363 return;\r
2364 }\r
2365 REG_PC += 4;\r
2366 return;\r
2367 }\r
2368 else\r
2369 {\r
2370 if(M68KMAKE_CC)\r
2371 {\r
2372 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2373 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2374 return;\r
2375 }\r
2376 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2377 }\r
2378}\r
2379\r
2380\r
2381M68KMAKE_OP(bchg, 32, r, d)\r
2382{\r
2383 uint* r_dst = &DY;\r
2384 uint mask = 1 << (DX & 0x1f);\r
2385\r
2386 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)\r
2387 USE_CYCLES(2);\r
2388 FLAG_Z = *r_dst & mask;\r
2389 *r_dst ^= mask;\r
2390}\r
2391\r
2392\r
2393M68KMAKE_OP(bchg, 8, r, .)\r
2394{\r
2395 uint ea = M68KMAKE_GET_EA_AY_8;\r
2396 uint src = m68ki_read_8(ea);\r
2397 uint mask = 1 << (DX & 7);\r
2398\r
2399 FLAG_Z = src & mask;\r
2400 m68ki_write_8(ea, src ^ mask);\r
2401}\r
2402\r
2403\r
2404M68KMAKE_OP(bchg, 32, s, d)\r
2405{\r
2406 uint* r_dst = &DY;\r
2407 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2408\r
2409 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)\r
2410 USE_CYCLES(2);\r
2411 FLAG_Z = *r_dst & mask;\r
2412 *r_dst ^= mask;\r
2413}\r
2414\r
2415\r
2416M68KMAKE_OP(bchg, 8, s, .)\r
2417{\r
2418 uint mask = 1 << (OPER_I_8() & 7);\r
2419 uint ea = M68KMAKE_GET_EA_AY_8;\r
2420 uint src = m68ki_read_8(ea);\r
2421\r
2422 FLAG_Z = src & mask;\r
2423 m68ki_write_8(ea, src ^ mask);\r
2424}\r
2425\r
2426\r
2427M68KMAKE_OP(bclr, 32, r, d)\r
2428{\r
2429 uint* r_dst = &DY;\r
2430 uint mask = 1 << (DX & 0x1f);\r
2431\r
2432 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)\r
2433 USE_CYCLES(2);\r
2434 FLAG_Z = *r_dst & mask;\r
2435 *r_dst &= ~mask;\r
2436}\r
2437\r
2438\r
2439M68KMAKE_OP(bclr, 8, r, .)\r
2440{\r
2441 uint ea = M68KMAKE_GET_EA_AY_8;\r
2442 uint src = m68ki_read_8(ea);\r
2443 uint mask = 1 << (DX & 7);\r
2444\r
2445 FLAG_Z = src & mask;\r
2446 m68ki_write_8(ea, src & ~mask);\r
2447}\r
2448\r
2449\r
2450M68KMAKE_OP(bclr, 32, s, d)\r
2451{\r
2452 uint* r_dst = &DY;\r
2453 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2454\r
2455 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)\r
2456 USE_CYCLES(2);\r
2457 FLAG_Z = *r_dst & mask;\r
2458 *r_dst &= ~mask;\r
2459}\r
2460\r
2461\r
2462M68KMAKE_OP(bclr, 8, s, .)\r
2463{\r
2464 uint mask = 1 << (OPER_I_8() & 7);\r
2465 uint ea = M68KMAKE_GET_EA_AY_8;\r
2466 uint src = m68ki_read_8(ea);\r
2467\r
2468 FLAG_Z = src & mask;\r
2469 m68ki_write_8(ea, src & ~mask);\r
2470}\r
2471\r
2472\r
2473M68KMAKE_OP(bfchg, 32, ., d)\r
2474{\r
2475 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2476 {\r
2477 uint word2 = OPER_I_16();\r
2478 uint offset = (word2>>6)&31;\r
2479 uint width = word2;\r
2480 uint* data = &DY;\r
2481 uint64 mask;\r
2482\r
2483\r
2484 if(BIT_B(word2))\r
2485 offset = REG_D[offset&7];\r
2486 if(BIT_5(word2))\r
2487 width = REG_D[width&7];\r
2488\r
2489 offset &= 31;\r
2490 width = ((width-1) & 31) + 1;\r
2491\r
2492 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2493 mask = ROR_32(mask, offset);\r
2494\r
2495 FLAG_N = NFLAG_32(*data<<offset);\r
2496 FLAG_Z = *data & mask;\r
2497 FLAG_V = VFLAG_CLEAR;\r
2498 FLAG_C = CFLAG_CLEAR;\r
2499\r
2500 *data ^= mask;\r
2501\r
2502 return;\r
2503 }\r
2504 m68ki_exception_illegal();\r
2505}\r
2506\r
2507\r
2508M68KMAKE_OP(bfchg, 32, ., .)\r
2509{\r
2510 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2511 {\r
2512 uint word2 = OPER_I_16();\r
2513 sint offset = (word2>>6)&31;\r
2514 uint width = word2;\r
2515 uint mask_base;\r
2516 uint data_long;\r
2517 uint mask_long;\r
2518 uint data_byte = 0;\r
2519 uint mask_byte = 0;\r
2520 uint ea = M68KMAKE_GET_EA_AY_8;\r
2521\r
2522\r
2523 if(BIT_B(word2))\r
2524 offset = MAKE_INT_32(REG_D[offset&7]);\r
2525 if(BIT_5(word2))\r
2526 width = REG_D[width&7];\r
2527\r
2528 /* Offset is signed so we have to use ugly math =( */\r
2529 ea += offset / 8;\r
2530 offset %= 8;\r
2531 if(offset < 0)\r
2532 {\r
2533 offset += 8;\r
2534 ea--;\r
2535 }\r
2536 width = ((width-1) & 31) + 1;\r
2537\r
2538 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2539 mask_long = mask_base >> offset;\r
2540\r
2541 data_long = m68ki_read_32(ea);\r
2542 FLAG_N = NFLAG_32(data_long << offset);\r
2543 FLAG_Z = data_long & mask_long;\r
2544 FLAG_V = VFLAG_CLEAR;\r
2545 FLAG_C = CFLAG_CLEAR;\r
2546\r
2547 m68ki_write_32(ea, data_long ^ mask_long);\r
2548\r
2549 if((width + offset) > 32)\r
2550 {\r
2551 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2552 data_byte = m68ki_read_8(ea+4);\r
2553 FLAG_Z |= (data_byte & mask_byte);\r
2554 m68ki_write_8(ea+4, data_byte ^ mask_byte);\r
2555 }\r
2556 return;\r
2557 }\r
2558 m68ki_exception_illegal();\r
2559}\r
2560\r
2561\r
2562M68KMAKE_OP(bfclr, 32, ., d)\r
2563{\r
2564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2565 {\r
2566 uint word2 = OPER_I_16();\r
2567 uint offset = (word2>>6)&31;\r
2568 uint width = word2;\r
2569 uint* data = &DY;\r
2570 uint64 mask;\r
2571\r
2572\r
2573 if(BIT_B(word2))\r
2574 offset = REG_D[offset&7];\r
2575 if(BIT_5(word2))\r
2576 width = REG_D[width&7];\r
2577\r
2578\r
2579 offset &= 31;\r
2580 width = ((width-1) & 31) + 1;\r
2581\r
2582\r
2583 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2584 mask = ROR_32(mask, offset);\r
2585\r
2586 FLAG_N = NFLAG_32(*data<<offset);\r
2587 FLAG_Z = *data & mask;\r
2588 FLAG_V = VFLAG_CLEAR;\r
2589 FLAG_C = CFLAG_CLEAR;\r
2590\r
2591 *data &= ~mask;\r
2592\r
2593 return;\r
2594 }\r
2595 m68ki_exception_illegal();\r
2596}\r
2597\r
2598\r
2599M68KMAKE_OP(bfclr, 32, ., .)\r
2600{\r
2601 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2602 {\r
2603 uint word2 = OPER_I_16();\r
2604 sint offset = (word2>>6)&31;\r
2605 uint width = word2;\r
2606 uint mask_base;\r
2607 uint data_long;\r
2608 uint mask_long;\r
2609 uint data_byte = 0;\r
2610 uint mask_byte = 0;\r
2611 uint ea = M68KMAKE_GET_EA_AY_8;\r
2612\r
2613\r
2614 if(BIT_B(word2))\r
2615 offset = MAKE_INT_32(REG_D[offset&7]);\r
2616 if(BIT_5(word2))\r
2617 width = REG_D[width&7];\r
2618\r
2619 /* Offset is signed so we have to use ugly math =( */\r
2620 ea += offset / 8;\r
2621 offset %= 8;\r
2622 if(offset < 0)\r
2623 {\r
2624 offset += 8;\r
2625 ea--;\r
2626 }\r
2627 width = ((width-1) & 31) + 1;\r
2628\r
2629 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2630 mask_long = mask_base >> offset;\r
2631\r
2632 data_long = m68ki_read_32(ea);\r
2633 FLAG_N = NFLAG_32(data_long << offset);\r
2634 FLAG_Z = data_long & mask_long;\r
2635 FLAG_V = VFLAG_CLEAR;\r
2636 FLAG_C = CFLAG_CLEAR;\r
2637\r
2638 m68ki_write_32(ea, data_long & ~mask_long);\r
2639\r
2640 if((width + offset) > 32)\r
2641 {\r
2642 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2643 data_byte = m68ki_read_8(ea+4);\r
2644 FLAG_Z |= (data_byte & mask_byte);\r
2645 m68ki_write_8(ea+4, data_byte & ~mask_byte);\r
2646 }\r
2647 return;\r
2648 }\r
2649 m68ki_exception_illegal();\r
2650}\r
2651\r
2652\r
2653M68KMAKE_OP(bfexts, 32, ., d)\r
2654{\r
2655 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2656 {\r
2657 uint word2 = OPER_I_16();\r
2658 uint offset = (word2>>6)&31;\r
2659 uint width = word2;\r
2660 uint64 data = DY;\r
2661\r
2662\r
2663 if(BIT_B(word2))\r
2664 offset = REG_D[offset&7];\r
2665 if(BIT_5(word2))\r
2666 width = REG_D[width&7];\r
2667\r
2668 offset &= 31;\r
2669 width = ((width-1) & 31) + 1;\r
2670\r
2671 data = ROL_32(data, offset);\r
2672 FLAG_N = NFLAG_32(data);\r
2673 data = MAKE_INT_32(data) >> (32 - width);\r
2674\r
2675 FLAG_Z = data;\r
2676 FLAG_V = VFLAG_CLEAR;\r
2677 FLAG_C = CFLAG_CLEAR;\r
2678\r
2679 REG_D[(word2>>12)&7] = data;\r
2680\r
2681 return;\r
2682 }\r
2683 m68ki_exception_illegal();\r
2684}\r
2685\r
2686\r
2687M68KMAKE_OP(bfexts, 32, ., .)\r
2688{\r
2689 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2690 {\r
2691 uint word2 = OPER_I_16();\r
2692 sint offset = (word2>>6)&31;\r
2693 uint width = word2;\r
2694 uint data;\r
2695 uint ea = M68KMAKE_GET_EA_AY_8;\r
2696\r
2697\r
2698 if(BIT_B(word2))\r
2699 offset = MAKE_INT_32(REG_D[offset&7]);\r
2700 if(BIT_5(word2))\r
2701 width = REG_D[width&7];\r
2702\r
2703 /* Offset is signed so we have to use ugly math =( */\r
2704 ea += offset / 8;\r
2705 offset %= 8;\r
2706 if(offset < 0)\r
2707 {\r
2708 offset += 8;\r
2709 ea--;\r
2710 }\r
2711 width = ((width-1) & 31) + 1;\r
2712\r
2713 data = m68ki_read_32(ea);\r
2714\r
2715 data = MASK_OUT_ABOVE_32(data<<offset);\r
2716\r
2717 if((offset+width) > 32)\r
2718 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2719\r
2720 FLAG_N = NFLAG_32(data);\r
2721 data = MAKE_INT_32(data) >> (32 - width);\r
2722\r
2723 FLAG_Z = data;\r
2724 FLAG_V = VFLAG_CLEAR;\r
2725 FLAG_C = CFLAG_CLEAR;\r
2726\r
2727 REG_D[(word2 >> 12) & 7] = data;\r
2728\r
2729 return;\r
2730 }\r
2731 m68ki_exception_illegal();\r
2732}\r
2733\r
2734\r
2735M68KMAKE_OP(bfextu, 32, ., d)\r
2736{\r
2737 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2738 {\r
2739 uint word2 = OPER_I_16();\r
2740 uint offset = (word2>>6)&31;\r
2741 uint width = word2;\r
2742 uint64 data = DY;\r
2743\r
2744\r
2745 if(BIT_B(word2))\r
2746 offset = REG_D[offset&7];\r
2747 if(BIT_5(word2))\r
2748 width = REG_D[width&7];\r
2749\r
2750 offset &= 31;\r
2751 width = ((width-1) & 31) + 1;\r
2752\r
2753 data = ROL_32(data, offset);\r
2754 FLAG_N = NFLAG_32(data);\r
2755 data >>= 32 - width;\r
2756\r
2757 FLAG_Z = data;\r
2758 FLAG_V = VFLAG_CLEAR;\r
2759 FLAG_C = CFLAG_CLEAR;\r
2760\r
2761 REG_D[(word2>>12)&7] = data;\r
2762\r
2763 return;\r
2764 }\r
2765 m68ki_exception_illegal();\r
2766}\r
2767\r
2768\r
2769M68KMAKE_OP(bfextu, 32, ., .)\r
2770{\r
2771 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2772 {\r
2773 uint word2 = OPER_I_16();\r
2774 sint offset = (word2>>6)&31;\r
2775 uint width = word2;\r
2776 uint data;\r
2777 uint ea = M68KMAKE_GET_EA_AY_8;\r
2778\r
2779\r
2780 if(BIT_B(word2))\r
2781 offset = MAKE_INT_32(REG_D[offset&7]);\r
2782 if(BIT_5(word2))\r
2783 width = REG_D[width&7];\r
2784\r
2785 /* Offset is signed so we have to use ugly math =( */\r
2786 ea += offset / 8;\r
2787 offset %= 8;\r
2788 if(offset < 0)\r
2789 {\r
2790 offset += 8;\r
2791 ea--;\r
2792 }\r
2793 width = ((width-1) & 31) + 1;\r
2794\r
2795 data = m68ki_read_32(ea);\r
2796 data = MASK_OUT_ABOVE_32(data<<offset);\r
2797\r
2798 if((offset+width) > 32)\r
2799 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2800\r
2801 FLAG_N = NFLAG_32(data);\r
2802 data >>= (32 - width);\r
2803\r
2804 FLAG_Z = data;\r
2805 FLAG_V = VFLAG_CLEAR;\r
2806 FLAG_C = CFLAG_CLEAR;\r
2807\r
2808 REG_D[(word2 >> 12) & 7] = data;\r
2809\r
2810 return;\r
2811 }\r
2812 m68ki_exception_illegal();\r
2813}\r
2814\r
2815\r
2816M68KMAKE_OP(bfffo, 32, ., d)\r
2817{\r
2818 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2819 {\r
2820 uint word2 = OPER_I_16();\r
2821 uint offset = (word2>>6)&31;\r
2822 uint width = word2;\r
2823 uint64 data = DY;\r
2824 uint bit;\r
2825\r
2826\r
2827 if(BIT_B(word2))\r
2828 offset = REG_D[offset&7];\r
2829 if(BIT_5(word2))\r
2830 width = REG_D[width&7];\r
2831\r
2832 offset &= 31;\r
2833 width = ((width-1) & 31) + 1;\r
2834\r
2835 data = ROL_32(data, offset);\r
2836 FLAG_N = NFLAG_32(data);\r
2837 data >>= 32 - width;\r
2838\r
2839 FLAG_Z = data;\r
2840 FLAG_V = VFLAG_CLEAR;\r
2841 FLAG_C = CFLAG_CLEAR;\r
2842\r
2843 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2844 offset++;\r
2845\r
2846 REG_D[(word2>>12)&7] = offset;\r
2847\r
2848 return;\r
2849 }\r
2850 m68ki_exception_illegal();\r
2851}\r
2852\r
2853\r
2854M68KMAKE_OP(bfffo, 32, ., .)\r
2855{\r
2856 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2857 {\r
2858 uint word2 = OPER_I_16();\r
2859 sint offset = (word2>>6)&31;\r
2860 sint local_offset;\r
2861 uint width = word2;\r
2862 uint data;\r
2863 uint bit;\r
2864 uint ea = M68KMAKE_GET_EA_AY_8;\r
2865\r
2866\r
2867 if(BIT_B(word2))\r
2868 offset = MAKE_INT_32(REG_D[offset&7]);\r
2869 if(BIT_5(word2))\r
2870 width = REG_D[width&7];\r
2871\r
2872 /* Offset is signed so we have to use ugly math =( */\r
2873 ea += offset / 8;\r
2874 local_offset = offset % 8;\r
2875 if(local_offset < 0)\r
2876 {\r
2877 local_offset += 8;\r
2878 ea--;\r
2879 }\r
2880 width = ((width-1) & 31) + 1;\r
2881\r
2882 data = m68ki_read_32(ea);\r
2883 data = MASK_OUT_ABOVE_32(data<<local_offset);\r
2884\r
2885 if((local_offset+width) > 32)\r
2886 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;\r
2887\r
2888 FLAG_N = NFLAG_32(data);\r
2889 data >>= (32 - width);\r
2890\r
2891 FLAG_Z = data;\r
2892 FLAG_V = VFLAG_CLEAR;\r
2893 FLAG_C = CFLAG_CLEAR;\r
2894\r
2895 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2896 offset++;\r
2897\r
2898 REG_D[(word2>>12)&7] = offset;\r
2899\r
2900 return;\r
2901 }\r
2902 m68ki_exception_illegal();\r
2903}\r
2904\r
2905\r
2906M68KMAKE_OP(bfins, 32, ., d)\r
2907{\r
2908 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2909 {\r
2910 uint word2 = OPER_I_16();\r
2911 uint offset = (word2>>6)&31;\r
2912 uint width = word2;\r
2913 uint* data = &DY;\r
2914 uint64 mask;\r
2915 uint64 insert = REG_D[(word2>>12)&7];\r
2916\r
2917\r
2918 if(BIT_B(word2))\r
2919 offset = REG_D[offset&7];\r
2920 if(BIT_5(word2))\r
2921 width = REG_D[width&7];\r
2922\r
2923\r
2924 offset &= 31;\r
2925 width = ((width-1) & 31) + 1;\r
2926\r
2927\r
2928 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2929 mask = ROR_32(mask, offset);\r
2930\r
2931 insert = MASK_OUT_ABOVE_32(insert << (32 - width));\r
2932 FLAG_N = NFLAG_32(insert);\r
2933 FLAG_Z = insert;\r
2934 insert = ROR_32(insert, offset);\r
2935\r
2936 FLAG_V = VFLAG_CLEAR;\r
2937 FLAG_C = CFLAG_CLEAR;\r
2938\r
2939 *data &= ~mask;\r
2940 *data |= insert;\r
2941\r
2942 return;\r
2943 }\r
2944 m68ki_exception_illegal();\r
2945}\r
2946\r
2947\r
2948M68KMAKE_OP(bfins, 32, ., .)\r
2949{\r
2950 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2951 {\r
2952 uint word2 = OPER_I_16();\r
2953 sint offset = (word2>>6)&31;\r
2954 uint width = word2;\r
2955 uint insert_base = REG_D[(word2>>12)&7];\r
2956 uint insert_long;\r
2957 uint insert_byte;\r
2958 uint mask_base;\r
2959 uint data_long;\r
2960 uint mask_long;\r
2961 uint data_byte = 0;\r
2962 uint mask_byte = 0;\r
2963 uint ea = M68KMAKE_GET_EA_AY_8;\r
2964\r
2965\r
2966 if(BIT_B(word2))\r
2967 offset = MAKE_INT_32(REG_D[offset&7]);\r
2968 if(BIT_5(word2))\r
2969 width = REG_D[width&7];\r
2970\r
2971 /* Offset is signed so we have to use ugly math =( */\r
2972 ea += offset / 8;\r
2973 offset %= 8;\r
2974 if(offset < 0)\r
2975 {\r
2976 offset += 8;\r
2977 ea--;\r
2978 }\r
2979 width = ((width-1) & 31) + 1;\r
2980\r
2981 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2982 mask_long = mask_base >> offset;\r
2983\r
2984 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));\r
2985 FLAG_N = NFLAG_32(insert_base);\r
2986 FLAG_Z = insert_base;\r
2987 insert_long = insert_base >> offset;\r
2988\r
2989 data_long = m68ki_read_32(ea);\r
2990 FLAG_V = VFLAG_CLEAR;\r
2991 FLAG_C = CFLAG_CLEAR;\r
2992\r
2993 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);\r
2994\r
2995 if((width + offset) > 32)\r
2996 {\r
2997 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2998 insert_byte = MASK_OUT_ABOVE_8(insert_base);\r
2999 data_byte = m68ki_read_8(ea+4);\r
3000 FLAG_Z |= (data_byte & mask_byte);\r
3001 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);\r
3002 }\r
3003 return;\r
3004 }\r
3005 m68ki_exception_illegal();\r
3006}\r
3007\r
3008\r
3009M68KMAKE_OP(bfset, 32, ., d)\r
3010{\r
3011 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3012 {\r
3013 uint word2 = OPER_I_16();\r
3014 uint offset = (word2>>6)&31;\r
3015 uint width = word2;\r
3016 uint* data = &DY;\r
3017 uint64 mask;\r
3018\r
3019\r
3020 if(BIT_B(word2))\r
3021 offset = REG_D[offset&7];\r
3022 if(BIT_5(word2))\r
3023 width = REG_D[width&7];\r
3024\r
3025\r
3026 offset &= 31;\r
3027 width = ((width-1) & 31) + 1;\r
3028\r
3029\r
3030 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3031 mask = ROR_32(mask, offset);\r
3032\r
3033 FLAG_N = NFLAG_32(*data<<offset);\r
3034 FLAG_Z = *data & mask;\r
3035 FLAG_V = VFLAG_CLEAR;\r
3036 FLAG_C = CFLAG_CLEAR;\r
3037\r
3038 *data |= mask;\r
3039\r
3040 return;\r
3041 }\r
3042 m68ki_exception_illegal();\r
3043}\r
3044\r
3045\r
3046M68KMAKE_OP(bfset, 32, ., .)\r
3047{\r
3048 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3049 {\r
3050 uint word2 = OPER_I_16();\r
3051 sint offset = (word2>>6)&31;\r
3052 uint width = word2;\r
3053 uint mask_base;\r
3054 uint data_long;\r
3055 uint mask_long;\r
3056 uint data_byte = 0;\r
3057 uint mask_byte = 0;\r
3058 uint ea = M68KMAKE_GET_EA_AY_8;\r
3059\r
3060\r
3061 if(BIT_B(word2))\r
3062 offset = MAKE_INT_32(REG_D[offset&7]);\r
3063 if(BIT_5(word2))\r
3064 width = REG_D[width&7];\r
3065\r
3066 /* Offset is signed so we have to use ugly math =( */\r
3067 ea += offset / 8;\r
3068 offset %= 8;\r
3069 if(offset < 0)\r
3070 {\r
3071 offset += 8;\r
3072 ea--;\r
3073 }\r
3074 width = ((width-1) & 31) + 1;\r
3075\r
3076\r
3077 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3078 mask_long = mask_base >> offset;\r
3079\r
3080 data_long = m68ki_read_32(ea);\r
3081 FLAG_N = NFLAG_32(data_long << offset);\r
3082 FLAG_Z = data_long & mask_long;\r
3083 FLAG_V = VFLAG_CLEAR;\r
3084 FLAG_C = CFLAG_CLEAR;\r
3085\r
3086 m68ki_write_32(ea, data_long | mask_long);\r
3087\r
3088 if((width + offset) > 32)\r
3089 {\r
3090 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3091 data_byte = m68ki_read_8(ea+4);\r
3092 FLAG_Z |= (data_byte & mask_byte);\r
3093 m68ki_write_8(ea+4, data_byte | mask_byte);\r
3094 }\r
3095 return;\r
3096 }\r
3097 m68ki_exception_illegal();\r
3098}\r
3099\r
3100\r
3101M68KMAKE_OP(bftst, 32, ., d)\r
3102{\r
3103 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3104 {\r
3105 uint word2 = OPER_I_16();\r
3106 uint offset = (word2>>6)&31;\r
3107 uint width = word2;\r
3108 uint* data = &DY;\r
3109 uint64 mask;\r
3110\r
3111\r
3112 if(BIT_B(word2))\r
3113 offset = REG_D[offset&7];\r
3114 if(BIT_5(word2))\r
3115 width = REG_D[width&7];\r
3116\r
3117\r
3118 offset &= 31;\r
3119 width = ((width-1) & 31) + 1;\r
3120\r
3121\r
3122 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3123 mask = ROR_32(mask, offset);\r
3124\r
3125 FLAG_N = NFLAG_32(*data<<offset);\r
3126 FLAG_Z = *data & mask;\r
3127 FLAG_V = VFLAG_CLEAR;\r
3128 FLAG_C = CFLAG_CLEAR;\r
3129\r
3130 return;\r
3131 }\r
3132 m68ki_exception_illegal();\r
3133}\r
3134\r
3135\r
3136M68KMAKE_OP(bftst, 32, ., .)\r
3137{\r
3138 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3139 {\r
3140 uint word2 = OPER_I_16();\r
3141 sint offset = (word2>>6)&31;\r
3142 uint width = word2;\r
3143 uint mask_base;\r
3144 uint data_long;\r
3145 uint mask_long;\r
3146 uint data_byte = 0;\r
3147 uint mask_byte = 0;\r
3148 uint ea = M68KMAKE_GET_EA_AY_8;\r
3149\r
3150 if(BIT_B(word2))\r
3151 offset = MAKE_INT_32(REG_D[offset&7]);\r
3152 if(BIT_5(word2))\r
3153 width = REG_D[width&7];\r
3154\r
3155 /* Offset is signed so we have to use ugly math =( */\r
3156 ea += offset / 8;\r
3157 offset %= 8;\r
3158 if(offset < 0)\r
3159 {\r
3160 offset += 8;\r
3161 ea--;\r
3162 }\r
3163 width = ((width-1) & 31) + 1;\r
3164\r
3165\r
3166 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3167 mask_long = mask_base >> offset;\r
3168\r
3169 data_long = m68ki_read_32(ea);\r
3170 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;\r
3171 FLAG_Z = data_long & mask_long;\r
3172 FLAG_V = VFLAG_CLEAR;\r
3173 FLAG_C = CFLAG_CLEAR;\r
3174\r
3175 if((width + offset) > 32)\r
3176 {\r
3177 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3178 data_byte = m68ki_read_8(ea+4);\r
3179 FLAG_Z |= (data_byte & mask_byte);\r
3180 }\r
3181 return;\r
3182 }\r
3183 m68ki_exception_illegal();\r
3184}\r
3185\r
3186\r
3187M68KMAKE_OP(bkpt, 0, ., .)\r
3188{\r
3189 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
3190 {\r
3191 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */\r
3192 }\r
3193 m68ki_exception_illegal();\r
3194}\r
3195\r
3196\r
3197M68KMAKE_OP(bra, 8, ., .)\r
3198{\r
3199 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3200 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3201 if(REG_PC == REG_PPC)\r
3202 USE_ALL_CYCLES();\r
3203}\r
3204\r
3205\r
3206M68KMAKE_OP(bra, 16, ., .)\r
3207{\r
3208 uint offset = OPER_I_16();\r
3209 REG_PC -= 2;\r
3210 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3211 m68ki_branch_16(offset);\r
3212 if(REG_PC == REG_PPC)\r
3213 USE_ALL_CYCLES();\r
3214}\r
3215\r
3216\r
3217M68KMAKE_OP(bra, 32, ., .)\r
3218{\r
3219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3220 {\r
3221 uint offset = OPER_I_32();\r
3222 REG_PC -= 4;\r
3223 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3224 m68ki_branch_32(offset);\r
3225 if(REG_PC == REG_PPC)\r
3226 USE_ALL_CYCLES();\r
3227 return;\r
3228 }\r
3229 else\r
3230 {\r
3231 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3232 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3233 if(REG_PC == REG_PPC)\r
3234 USE_ALL_CYCLES();\r
3235 }\r
3236}\r
3237\r
3238\r
3239M68KMAKE_OP(bset, 32, r, d)\r
3240{\r
3241 uint* r_dst = &DY;\r
3242 uint mask = 1 << (DX & 0x1f);\r
3243\r
3244 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)\r
3245 USE_CYCLES(2);\r
3246 FLAG_Z = *r_dst & mask;\r
3247 *r_dst |= mask;\r
3248}\r
3249\r
3250\r
3251M68KMAKE_OP(bset, 8, r, .)\r
3252{\r
3253 uint ea = M68KMAKE_GET_EA_AY_8;\r
3254 uint src = m68ki_read_8(ea);\r
3255 uint mask = 1 << (DX & 7);\r
3256\r
3257 FLAG_Z = src & mask;\r
3258 m68ki_write_8(ea, src | mask);\r
3259}\r
3260\r
3261\r
3262M68KMAKE_OP(bset, 32, s, d)\r
3263{\r
3264 uint* r_dst = &DY;\r
3265 uint mask = 1 << (OPER_I_8() & 0x1f);\r
3266\r
3267 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)\r
3268 USE_CYCLES(2);\r
3269 FLAG_Z = *r_dst & mask;\r
3270 *r_dst |= mask;\r
3271}\r
3272\r
3273\r
3274M68KMAKE_OP(bset, 8, s, .)\r
3275{\r
3276 uint mask = 1 << (OPER_I_8() & 7);\r
3277 uint ea = M68KMAKE_GET_EA_AY_8;\r
3278 uint src = m68ki_read_8(ea);\r
3279\r
3280 FLAG_Z = src & mask;\r
3281 m68ki_write_8(ea, src | mask);\r
3282}\r
3283\r
3284\r
3285M68KMAKE_OP(bsr, 8, ., .)\r
3286{\r
3287 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3288 m68ki_push_32(REG_PC);\r
3289 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3290}\r
3291\r
3292\r
3293M68KMAKE_OP(bsr, 16, ., .)\r
3294{\r
3295 uint offset = OPER_I_16();\r
3296 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3297 m68ki_push_32(REG_PC);\r
3298 REG_PC -= 2;\r
3299 m68ki_branch_16(offset);\r
3300}\r
3301\r
3302\r
3303M68KMAKE_OP(bsr, 32, ., .)\r
3304{\r
3305 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3306 {\r
3307 uint offset = OPER_I_32();\r
3308 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3309 m68ki_push_32(REG_PC);\r
3310 REG_PC -= 4;\r
3311 m68ki_branch_32(offset);\r
3312 return;\r
3313 }\r
3314 else\r
3315 {\r
3316 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3317 m68ki_push_32(REG_PC);\r
3318 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3319 }\r
3320}\r
3321\r
3322\r
3323M68KMAKE_OP(btst, 32, r, d)\r
3324{\r
3325 FLAG_Z = DY & (1 << (DX & 0x1f));\r
3326}\r
3327\r
3328\r
3329M68KMAKE_OP(btst, 8, r, .)\r
3330{\r
3331 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));\r
3332}\r
3333\r
3334\r
3335M68KMAKE_OP(btst, 32, s, d)\r
3336{\r
3337 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));\r
3338}\r
3339\r
3340\r
3341M68KMAKE_OP(btst, 8, s, .)\r
3342{\r
3343 uint bit = OPER_I_8() & 7;\r
3344\r
3345 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);\r
3346}\r
3347\r
3348\r
3349M68KMAKE_OP(callm, 32, ., .)\r
3350{\r
3351 /* note: watch out for pcrelative modes */\r
3352 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
3353 {\r
3354 uint ea = M68KMAKE_GET_EA_AY_32;\r
3355\r
3356 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3357 REG_PC += 2;\r
3358(void)ea; /* just to avoid an 'unused variable' warning */\r
3359 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
3360 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
3361 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
3362 return;\r
3363 }\r
3364 m68ki_exception_illegal();\r
3365}\r
3366\r
3367\r
3368M68KMAKE_OP(cas, 8, ., .)\r
3369{\r
3370 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3371 {\r
3372 uint word2 = OPER_I_16();\r
3373 uint ea = M68KMAKE_GET_EA_AY_8;\r
3374 uint dest = m68ki_read_8(ea);\r
3375 uint* compare = &REG_D[word2 & 7];\r
3376 uint res = dest - MASK_OUT_ABOVE_8(*compare);\r
3377\r
3378 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3379 FLAG_N = NFLAG_8(res);\r
3380 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3381 FLAG_V = VFLAG_SUB_8(*compare, dest, res);\r
3382 FLAG_C = CFLAG_8(res);\r
3383\r
3384 if(COND_NE())\r
3385 *compare = MASK_OUT_BELOW_8(*compare) | dest;\r
3386 else\r
3387 {\r
3388 USE_CYCLES(3);\r
3389 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));\r
3390 }\r
3391 return;\r
3392 }\r
3393 m68ki_exception_illegal();\r
3394}\r
3395\r
3396\r
3397M68KMAKE_OP(cas, 16, ., .)\r
3398{\r
3399 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3400 {\r
3401 uint word2 = OPER_I_16();\r
3402 uint ea = M68KMAKE_GET_EA_AY_16;\r
3403 uint dest = m68ki_read_16(ea);\r
3404 uint* compare = &REG_D[word2 & 7];\r
3405 uint res = dest - MASK_OUT_ABOVE_16(*compare);\r
3406\r
3407 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3408 FLAG_N = NFLAG_16(res);\r
3409 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3410 FLAG_V = VFLAG_SUB_16(*compare, dest, res);\r
3411 FLAG_C = CFLAG_16(res);\r
3412\r
3413 if(COND_NE())\r
3414 *compare = MASK_OUT_BELOW_16(*compare) | dest;\r
3415 else\r
3416 {\r
3417 USE_CYCLES(3);\r
3418 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));\r
3419 }\r
3420 return;\r
3421 }\r
3422 m68ki_exception_illegal();\r
3423}\r
3424\r
3425\r
3426M68KMAKE_OP(cas, 32, ., .)\r
3427{\r
3428 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3429 {\r
3430 uint word2 = OPER_I_16();\r
3431 uint ea = M68KMAKE_GET_EA_AY_32;\r
3432 uint dest = m68ki_read_32(ea);\r
3433 uint* compare = &REG_D[word2 & 7];\r
3434 uint res = dest - *compare;\r
3435\r
3436 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3437 FLAG_N = NFLAG_32(res);\r
3438 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3439 FLAG_V = VFLAG_SUB_32(*compare, dest, res);\r
3440 FLAG_C = CFLAG_SUB_32(*compare, dest, res);\r
3441\r
3442 if(COND_NE())\r
3443 *compare = dest;\r
3444 else\r
3445 {\r
3446 USE_CYCLES(3);\r
3447 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);\r
3448 }\r
3449 return;\r
3450 }\r
3451 m68ki_exception_illegal();\r
3452}\r
3453\r
3454\r
3455M68KMAKE_OP(cas2, 16, ., .)\r
3456{\r
3457 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3458 {\r
3459 uint word2 = OPER_I_32();\r
3460 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3461 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3462 uint dest1 = m68ki_read_16(ea1);\r
3463 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);\r
3464 uint* compare2 = &REG_D[word2 & 7];\r
3465 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3466 uint dest2 = m68ki_read_16(ea2);\r
3467 uint res2;\r
3468\r
3469 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3470 FLAG_N = NFLAG_16(res1);\r
3471 FLAG_Z = MASK_OUT_ABOVE_16(res1);\r
3472 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);\r
3473 FLAG_C = CFLAG_16(res1);\r
3474\r
3475 if(COND_EQ())\r
3476 {\r
3477 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);\r
3478\r
3479 FLAG_N = NFLAG_16(res2);\r
3480 FLAG_Z = MASK_OUT_ABOVE_16(res2);\r
3481 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);\r
3482 FLAG_C = CFLAG_16(res2);\r
3483\r
3484 if(COND_EQ())\r
3485 {\r
3486 USE_CYCLES(3);\r
3487 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);\r
3488 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);\r
3489 return;\r
3490 }\r
3491 }\r
3492 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;\r
3493 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;\r
3494 return;\r
3495 }\r
3496 m68ki_exception_illegal();\r
3497}\r
3498\r
3499\r
3500M68KMAKE_OP(cas2, 32, ., .)\r
3501{\r
3502 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3503 {\r
3504 uint word2 = OPER_I_32();\r
3505 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3506 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3507 uint dest1 = m68ki_read_32(ea1);\r
3508 uint res1 = dest1 - *compare1;\r
3509 uint* compare2 = &REG_D[word2 & 7];\r
3510 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3511 uint dest2 = m68ki_read_32(ea2);\r
3512 uint res2;\r
3513\r
3514 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3515 FLAG_N = NFLAG_32(res1);\r
3516 FLAG_Z = MASK_OUT_ABOVE_32(res1);\r
3517 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);\r
3518 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);\r
3519\r
3520 if(COND_EQ())\r
3521 {\r
3522 res2 = dest2 - *compare2;\r
3523\r
3524 FLAG_N = NFLAG_32(res2);\r
3525 FLAG_Z = MASK_OUT_ABOVE_32(res2);\r
3526 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);\r
3527 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);\r
3528\r
3529 if(COND_EQ())\r
3530 {\r
3531 USE_CYCLES(3);\r
3532 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);\r
3533 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);\r
3534 return;\r
3535 }\r
3536 }\r
3537 *compare1 = dest1;\r
3538 *compare2 = dest2;\r
3539 return;\r
3540 }\r
3541 m68ki_exception_illegal();\r
3542}\r
3543\r
3544\r
3545M68KMAKE_OP(chk, 16, ., d)\r
3546{\r
3547 sint src = MAKE_INT_16(DX);\r
3548 sint bound = MAKE_INT_16(DY);\r
3549\r
3550 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3551 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3552 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3553\r
3554 if(src >= 0 && src <= bound)\r
3555 {\r
3556 USE_CYCLES(6);\r
3557 return;\r
3558 }\r
3559 FLAG_N = (src < 0)<<7;\r
3560 m68ki_exception_trap(EXCEPTION_CHK);\r
3561}\r
3562\r
3563\r
3564M68KMAKE_OP(chk, 16, ., .)\r
3565{\r
3566 sint src = MAKE_INT_16(DX);\r
3567 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
3568\r
3569 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3570 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3571 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3572\r
3573 if(src >= 0 && src <= bound)\r
3574 {\r
3575 USE_CYCLES(6);\r
3576 return;\r
3577 }\r
3578 FLAG_N = (src < 0)<<7;\r
3579 m68ki_exception_trap(EXCEPTION_CHK);\r
3580}\r
3581\r
3582\r
3583M68KMAKE_OP(chk, 32, ., d)\r
3584{\r
3585 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3586 {\r
3587 sint src = MAKE_INT_32(DX);\r
3588 sint bound = MAKE_INT_32(DY);\r
3589\r
3590 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3591 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3592 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3593\r
3594 if(src >= 0 && src <= bound)\r
3595 {\r
3596 return;\r
3597 }\r
3598 FLAG_N = (src < 0)<<7;\r
3599 m68ki_exception_trap(EXCEPTION_CHK);\r
3600 return;\r
3601 }\r
3602 m68ki_exception_illegal();\r
3603}\r
3604\r
3605\r
3606M68KMAKE_OP(chk, 32, ., .)\r
3607{\r
3608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3609 {\r
3610 sint src = MAKE_INT_32(DX);\r
3611 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);\r
3612\r
3613 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3614 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3615 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3616\r
3617 if(src >= 0 && src <= bound)\r
3618 {\r
3619 return;\r
3620 }\r
3621 FLAG_N = (src < 0)<<7;\r
3622 m68ki_exception_trap(EXCEPTION_CHK);\r
3623 return;\r
3624 }\r
3625 m68ki_exception_illegal();\r
3626}\r
3627\r
3628\r
3629M68KMAKE_OP(chk2cmp2, 8, ., pcdi)\r
3630{\r
3631 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3632 {\r
3633 uint word2 = OPER_I_16();\r
3634 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3635 uint ea = EA_PCDI_8();\r
3636 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3637 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3638\r
3639 if(!BIT_F(word2))\r
3640 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3641 else\r
3642 FLAG_C = compare - lower_bound;\r
3643 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3644 if(COND_CS())\r
3645 {\r
3646 if(BIT_B(word2))\r
3647 m68ki_exception_trap(EXCEPTION_CHK);\r
3648 return;\r
3649 }\r
3650\r
3651 FLAG_C = upper_bound - compare;\r
3652 if(COND_CS() && BIT_B(word2))\r
3653 m68ki_exception_trap(EXCEPTION_CHK);\r
3654 return;\r
3655 }\r
3656 m68ki_exception_illegal();\r
3657}\r
3658\r
3659\r
3660M68KMAKE_OP(chk2cmp2, 8, ., pcix)\r
3661{\r
3662 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3663 {\r
3664 uint word2 = OPER_I_16();\r
3665 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3666 uint ea = EA_PCIX_8();\r
3667 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3668 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3669\r
3670 if(!BIT_F(word2))\r
3671 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3672 else\r
3673 FLAG_C = compare - lower_bound;\r
3674 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3675 if(COND_CS())\r
3676 {\r
3677 if(BIT_B(word2))\r
3678 m68ki_exception_trap(EXCEPTION_CHK);\r
3679 return;\r
3680 }\r
3681\r
3682 FLAG_C = upper_bound - compare;\r
3683 if(COND_CS() && BIT_B(word2))\r
3684 m68ki_exception_trap(EXCEPTION_CHK);\r
3685 return;\r
3686 }\r
3687 m68ki_exception_illegal();\r
3688}\r
3689\r
3690\r
3691M68KMAKE_OP(chk2cmp2, 8, ., .)\r
3692{\r
3693 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3694 {\r
3695 uint word2 = OPER_I_16();\r
3696 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3697 uint ea = M68KMAKE_GET_EA_AY_8;\r
3698 uint lower_bound = m68ki_read_8(ea);\r
3699 uint upper_bound = m68ki_read_8(ea + 1);\r
3700\r
3701 if(!BIT_F(word2))\r
3702 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3703 else\r
3704 FLAG_C = compare - lower_bound;\r
3705 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3706 if(COND_CS())\r
3707 {\r
3708 if(BIT_B(word2))\r
3709 m68ki_exception_trap(EXCEPTION_CHK);\r
3710 return;\r
3711 }\r
3712\r
3713 FLAG_C = upper_bound - compare;\r
3714 if(COND_CS() && BIT_B(word2))\r
3715 m68ki_exception_trap(EXCEPTION_CHK);\r
3716 return;\r
3717 }\r
3718 m68ki_exception_illegal();\r
3719}\r
3720\r
3721\r
3722M68KMAKE_OP(chk2cmp2, 16, ., pcdi)\r
3723{\r
3724 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3725 {\r
3726 uint word2 = OPER_I_16();\r
3727 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3728 uint ea = EA_PCDI_16();\r
3729 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3730 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3731\r
3732 if(!BIT_F(word2))\r
3733 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3734 else\r
3735 FLAG_C = compare - lower_bound;\r
3736 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3737 FLAG_C = CFLAG_16(FLAG_C);\r
3738 if(COND_CS())\r
3739 {\r
3740 if(BIT_B(word2))\r
3741 m68ki_exception_trap(EXCEPTION_CHK);\r
3742 return;\r
3743 }\r
3744\r
3745 if(!BIT_F(word2))\r
3746 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3747 else\r
3748 FLAG_C = upper_bound - compare;\r
3749 FLAG_C = CFLAG_16(FLAG_C);\r
3750 if(COND_CS() && BIT_B(word2))\r
3751 m68ki_exception_trap(EXCEPTION_CHK);\r
3752 return;\r
3753 }\r
3754 m68ki_exception_illegal();\r
3755}\r
3756\r
3757\r
3758M68KMAKE_OP(chk2cmp2, 16, ., pcix)\r
3759{\r
3760 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3761 {\r
3762 uint word2 = OPER_I_16();\r
3763 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3764 uint ea = EA_PCIX_16();\r
3765 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3766 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3767\r
3768 if(!BIT_F(word2))\r
3769 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3770 else\r
3771 FLAG_C = compare - lower_bound;\r
3772 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3773 FLAG_C = CFLAG_16(FLAG_C);\r
3774 if(COND_CS())\r
3775 {\r
3776 if(BIT_B(word2))\r
3777 m68ki_exception_trap(EXCEPTION_CHK);\r
3778 return;\r
3779 }\r
3780\r
3781 if(!BIT_F(word2))\r
3782 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3783 else\r
3784 FLAG_C = upper_bound - compare;\r
3785 FLAG_C = CFLAG_16(FLAG_C);\r
3786 if(COND_CS() && BIT_B(word2))\r
3787 m68ki_exception_trap(EXCEPTION_CHK);\r
3788 return;\r
3789 }\r
3790 m68ki_exception_illegal();\r
3791}\r
3792\r
3793\r
3794M68KMAKE_OP(chk2cmp2, 16, ., .)\r
3795{\r
3796 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3797 {\r
3798 uint word2 = OPER_I_16();\r
3799 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3800 uint ea = M68KMAKE_GET_EA_AY_16;\r
3801 uint lower_bound = m68ki_read_16(ea);\r
3802 uint upper_bound = m68ki_read_16(ea + 2);\r
3803\r
3804 if(!BIT_F(word2))\r
3805 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3806 else\r
3807 FLAG_C = compare - lower_bound;\r
3808\r
3809 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3810 FLAG_C = CFLAG_16(FLAG_C);\r
3811 if(COND_CS())\r
3812 {\r
3813 if(BIT_B(word2))\r
3814 m68ki_exception_trap(EXCEPTION_CHK);\r
3815 return;\r
3816 }\r
3817 if(!BIT_F(word2))\r
3818 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3819 else\r
3820 FLAG_C = upper_bound - compare;\r
3821\r
3822 FLAG_C = CFLAG_16(FLAG_C);\r
3823 if(COND_CS() && BIT_B(word2))\r
3824 m68ki_exception_trap(EXCEPTION_CHK);\r
3825 return;\r
3826 }\r
3827 m68ki_exception_illegal();\r
3828}\r
3829\r
3830\r
3831M68KMAKE_OP(chk2cmp2, 32, ., pcdi)\r
3832{\r
3833 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3834 {\r
3835 uint word2 = OPER_I_16();\r
3836 uint compare = REG_DA[(word2 >> 12) & 15];\r
3837 uint ea = EA_PCDI_32();\r
3838 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3839 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3840\r
3841 FLAG_C = compare - lower_bound;\r
3842 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3843 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3844 if(COND_CS())\r
3845 {\r
3846 if(BIT_B(word2))\r
3847 m68ki_exception_trap(EXCEPTION_CHK);\r
3848 return;\r
3849 }\r
3850\r
3851 FLAG_C = upper_bound - compare;\r
3852 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3853 if(COND_CS() && BIT_B(word2))\r
3854 m68ki_exception_trap(EXCEPTION_CHK);\r
3855 return;\r
3856 }\r
3857 m68ki_exception_illegal();\r
3858}\r
3859\r
3860\r
3861M68KMAKE_OP(chk2cmp2, 32, ., pcix)\r
3862{\r
3863 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3864 {\r
3865 uint word2 = OPER_I_16();\r
3866 uint compare = REG_DA[(word2 >> 12) & 15];\r
3867 uint ea = EA_PCIX_32();\r
3868 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3869 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3870\r
3871 FLAG_C = compare - lower_bound;\r
3872 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3873 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3874 if(COND_CS())\r
3875 {\r
3876 if(BIT_B(word2))\r
3877 m68ki_exception_trap(EXCEPTION_CHK);\r
3878 return;\r
3879 }\r
3880\r
3881 FLAG_C = upper_bound - compare;\r
3882 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3883 if(COND_CS() && BIT_B(word2))\r
3884 m68ki_exception_trap(EXCEPTION_CHK);\r
3885 return;\r
3886 }\r
3887 m68ki_exception_illegal();\r
3888}\r
3889\r
3890\r
3891M68KMAKE_OP(chk2cmp2, 32, ., .)\r
3892{\r
3893 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3894 {\r
3895 uint word2 = OPER_I_16();\r
3896 uint compare = REG_DA[(word2 >> 12) & 15];\r
3897 uint ea = M68KMAKE_GET_EA_AY_32;\r
3898 uint lower_bound = m68ki_read_32(ea);\r
3899 uint upper_bound = m68ki_read_32(ea + 4);\r
3900\r
3901 FLAG_C = compare - lower_bound;\r
3902 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3903 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3904 if(COND_CS())\r
3905 {\r
3906 if(BIT_B(word2))\r
3907 m68ki_exception_trap(EXCEPTION_CHK);\r
3908 return;\r
3909 }\r
3910\r
3911 FLAG_C = upper_bound - compare;\r
3912 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3913 if(COND_CS() && BIT_B(word2))\r
3914 m68ki_exception_trap(EXCEPTION_CHK);\r
3915 return;\r
3916 }\r
3917 m68ki_exception_illegal();\r
3918}\r
3919\r
3920\r
3921M68KMAKE_OP(clr, 8, ., d)\r
3922{\r
3923 DY &= 0xffffff00;\r
3924\r
3925 FLAG_N = NFLAG_CLEAR;\r
3926 FLAG_V = VFLAG_CLEAR;\r
3927 FLAG_C = CFLAG_CLEAR;\r
3928 FLAG_Z = ZFLAG_SET;\r
3929}\r
3930\r
3931\r
3932M68KMAKE_OP(clr, 8, ., .)\r
3933{\r
3934 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
3935\r
3936 FLAG_N = NFLAG_CLEAR;\r
3937 FLAG_V = VFLAG_CLEAR;\r
3938 FLAG_C = CFLAG_CLEAR;\r
3939 FLAG_Z = ZFLAG_SET;\r
3940}\r
3941\r
3942\r
3943M68KMAKE_OP(clr, 16, ., d)\r
3944{\r
3945 DY &= 0xffff0000;\r
3946\r
3947 FLAG_N = NFLAG_CLEAR;\r
3948 FLAG_V = VFLAG_CLEAR;\r
3949 FLAG_C = CFLAG_CLEAR;\r
3950 FLAG_Z = ZFLAG_SET;\r
3951}\r
3952\r
3953\r
3954M68KMAKE_OP(clr, 16, ., .)\r
3955{\r
3956 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);\r
3957\r
3958 FLAG_N = NFLAG_CLEAR;\r
3959 FLAG_V = VFLAG_CLEAR;\r
3960 FLAG_C = CFLAG_CLEAR;\r
3961 FLAG_Z = ZFLAG_SET;\r
3962}\r
3963\r
3964\r
3965M68KMAKE_OP(clr, 32, ., d)\r
3966{\r
3967 DY = 0;\r
3968\r
3969 FLAG_N = NFLAG_CLEAR;\r
3970 FLAG_V = VFLAG_CLEAR;\r
3971 FLAG_C = CFLAG_CLEAR;\r
3972 FLAG_Z = ZFLAG_SET;\r
3973}\r
3974\r
3975\r
3976M68KMAKE_OP(clr, 32, ., .)\r
3977{\r
3978 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);\r
3979\r
3980 FLAG_N = NFLAG_CLEAR;\r
3981 FLAG_V = VFLAG_CLEAR;\r
3982 FLAG_C = CFLAG_CLEAR;\r
3983 FLAG_Z = ZFLAG_SET;\r
3984}\r
3985\r
3986\r
3987M68KMAKE_OP(cmp, 8, ., d)\r
3988{\r
3989 uint src = MASK_OUT_ABOVE_8(DY);\r
3990 uint dst = MASK_OUT_ABOVE_8(DX);\r
3991 uint res = dst - src;\r
3992\r
3993 FLAG_N = NFLAG_8(res);\r
3994 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3995 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3996 FLAG_C = CFLAG_8(res);\r
3997}\r
3998\r
3999\r
4000M68KMAKE_OP(cmp, 8, ., .)\r
4001{\r
4002 uint src = M68KMAKE_GET_OPER_AY_8;\r
4003 uint dst = MASK_OUT_ABOVE_8(DX);\r
4004 uint res = dst - src;\r
4005\r
4006 FLAG_N = NFLAG_8(res);\r
4007 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4008 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4009 FLAG_C = CFLAG_8(res);\r
4010}\r
4011\r
4012\r
4013M68KMAKE_OP(cmp, 16, ., d)\r
4014{\r
4015 uint src = MASK_OUT_ABOVE_16(DY);\r
4016 uint dst = MASK_OUT_ABOVE_16(DX);\r
4017 uint res = dst - src;\r
4018\r
4019 FLAG_N = NFLAG_16(res);\r
4020 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4021 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4022 FLAG_C = CFLAG_16(res);\r
4023}\r
4024\r
4025\r
4026M68KMAKE_OP(cmp, 16, ., a)\r
4027{\r
4028 uint src = MASK_OUT_ABOVE_16(AY);\r
4029 uint dst = MASK_OUT_ABOVE_16(DX);\r
4030 uint res = dst - src;\r
4031\r
4032 FLAG_N = NFLAG_16(res);\r
4033 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4034 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4035 FLAG_C = CFLAG_16(res);\r
4036}\r
4037\r
4038\r
4039M68KMAKE_OP(cmp, 16, ., .)\r
4040{\r
4041 uint src = M68KMAKE_GET_OPER_AY_16;\r
4042 uint dst = MASK_OUT_ABOVE_16(DX);\r
4043 uint res = dst - src;\r
4044\r
4045 FLAG_N = NFLAG_16(res);\r
4046 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4047 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4048 FLAG_C = CFLAG_16(res);\r
4049}\r
4050\r
4051\r
4052M68KMAKE_OP(cmp, 32, ., d)\r
4053{\r
4054 uint src = DY;\r
4055 uint dst = DX;\r
4056 uint res = dst - src;\r
4057\r
4058 FLAG_N = NFLAG_32(res);\r
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4062}\r
4063\r
4064\r
4065M68KMAKE_OP(cmp, 32, ., a)\r
4066{\r
4067 uint src = AY;\r
4068 uint dst = DX;\r
4069 uint res = dst - src;\r
4070\r
4071 FLAG_N = NFLAG_32(res);\r
4072 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4073 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4074 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4075}\r
4076\r
4077\r
4078M68KMAKE_OP(cmp, 32, ., .)\r
4079{\r
4080 uint src = M68KMAKE_GET_OPER_AY_32;\r
4081 uint dst = DX;\r
4082 uint res = dst - src;\r
4083\r
4084 FLAG_N = NFLAG_32(res);\r
4085 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4086 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4087 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4088}\r
4089\r
4090\r
4091M68KMAKE_OP(cmpa, 16, ., d)\r
4092{\r
4093 uint src = MAKE_INT_16(DY);\r
4094 uint dst = AX;\r
4095 uint res = dst - src;\r
4096\r
4097 FLAG_N = NFLAG_32(res);\r
4098 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4099 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4100 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4101}\r
4102\r
4103\r
4104M68KMAKE_OP(cmpa, 16, ., a)\r
4105{\r
4106 uint src = MAKE_INT_16(AY);\r
4107 uint dst = AX;\r
4108 uint res = dst - src;\r
4109\r
4110 FLAG_N = NFLAG_32(res);\r
4111 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4112 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4113 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4114}\r
4115\r
4116\r
4117M68KMAKE_OP(cmpa, 16, ., .)\r
4118{\r
4119 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4120 uint dst = AX;\r
4121 uint res = dst - src;\r
4122\r
4123 FLAG_N = NFLAG_32(res);\r
4124 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4125 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4126 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4127}\r
4128\r
4129\r
4130M68KMAKE_OP(cmpa, 32, ., d)\r
4131{\r
4132 uint src = DY;\r
4133 uint dst = AX;\r
4134 uint res = dst - src;\r
4135\r
4136 FLAG_N = NFLAG_32(res);\r
4137 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4138 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4139 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4140}\r
4141\r
4142\r
4143M68KMAKE_OP(cmpa, 32, ., a)\r
4144{\r
4145 uint src = AY;\r
4146 uint dst = AX;\r
4147 uint res = dst - src;\r
4148\r
4149 FLAG_N = NFLAG_32(res);\r
4150 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4151 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4152 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4153}\r
4154\r
4155\r
4156M68KMAKE_OP(cmpa, 32, ., .)\r
4157{\r
4158 uint src = M68KMAKE_GET_OPER_AY_32;\r
4159 uint dst = AX;\r
4160 uint res = dst - src;\r
4161\r
4162 FLAG_N = NFLAG_32(res);\r
4163 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4164 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4165 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4166}\r
4167\r
4168\r
4169M68KMAKE_OP(cmpi, 8, ., d)\r
4170{\r
4171 uint src = OPER_I_8();\r
4172 uint dst = MASK_OUT_ABOVE_8(DY);\r
4173 uint res = dst - src;\r
4174\r
4175 FLAG_N = NFLAG_8(res);\r
4176 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4177 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4178 FLAG_C = CFLAG_8(res);\r
4179}\r
4180\r
4181\r
4182M68KMAKE_OP(cmpi, 8, ., .)\r
4183{\r
4184 uint src = OPER_I_8();\r
4185 uint dst = M68KMAKE_GET_OPER_AY_8;\r
4186 uint res = dst - src;\r
4187\r
4188 FLAG_N = NFLAG_8(res);\r
4189 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4190 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4191 FLAG_C = CFLAG_8(res);\r
4192}\r
4193\r
4194\r
4195M68KMAKE_OP(cmpi, 8, ., pcdi)\r
4196{\r
4197 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4198 {\r
4199 uint src = OPER_I_8();\r
4200 uint dst = OPER_PCDI_8();\r
4201 uint res = dst - src;\r
4202\r
4203 FLAG_N = NFLAG_8(res);\r
4204 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4205 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4206 FLAG_C = CFLAG_8(res);\r
4207 return;\r
4208 }\r
4209 m68ki_exception_illegal();\r
4210}\r
4211\r
4212\r
4213M68KMAKE_OP(cmpi, 8, ., pcix)\r
4214{\r
4215 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4216 {\r
4217 uint src = OPER_I_8();\r
4218 uint dst = OPER_PCIX_8();\r
4219 uint res = dst - src;\r
4220\r
4221 FLAG_N = NFLAG_8(res);\r
4222 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4223 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4224 FLAG_C = CFLAG_8(res);\r
4225 return;\r
4226 }\r
4227 m68ki_exception_illegal();\r
4228}\r
4229\r
4230\r
4231M68KMAKE_OP(cmpi, 16, ., d)\r
4232{\r
4233 uint src = OPER_I_16();\r
4234 uint dst = MASK_OUT_ABOVE_16(DY);\r
4235 uint res = dst - src;\r
4236\r
4237 FLAG_N = NFLAG_16(res);\r
4238 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4239 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4240 FLAG_C = CFLAG_16(res);\r
4241}\r
4242\r
4243\r
4244M68KMAKE_OP(cmpi, 16, ., .)\r
4245{\r
4246 uint src = OPER_I_16();\r
4247 uint dst = M68KMAKE_GET_OPER_AY_16;\r
4248 uint res = dst - src;\r
4249\r
4250 FLAG_N = NFLAG_16(res);\r
4251 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4252 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4253 FLAG_C = CFLAG_16(res);\r
4254}\r
4255\r
4256\r
4257M68KMAKE_OP(cmpi, 16, ., pcdi)\r
4258{\r
4259 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4260 {\r
4261 uint src = OPER_I_16();\r
4262 uint dst = OPER_PCDI_16();\r
4263 uint res = dst - src;\r
4264\r
4265 FLAG_N = NFLAG_16(res);\r
4266 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4267 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4268 FLAG_C = CFLAG_16(res);\r
4269 return;\r
4270 }\r
4271 m68ki_exception_illegal();\r
4272}\r
4273\r
4274\r
4275M68KMAKE_OP(cmpi, 16, ., pcix)\r
4276{\r
4277 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4278 {\r
4279 uint src = OPER_I_16();\r
4280 uint dst = OPER_PCIX_16();\r
4281 uint res = dst - src;\r
4282\r
4283 FLAG_N = NFLAG_16(res);\r
4284 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4285 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4286 FLAG_C = CFLAG_16(res);\r
4287 return;\r
4288 }\r
4289 m68ki_exception_illegal();\r
4290}\r
4291\r
4292\r
4293M68KMAKE_OP(cmpi, 32, ., d)\r
4294{\r
4295 uint src = OPER_I_32();\r
4296 uint dst = DY;\r
4297 uint res = dst - src;\r
4298\r
4299 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */\r
4300\r
4301 FLAG_N = NFLAG_32(res);\r
4302 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4303 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4304 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4305}\r
4306\r
4307\r
4308M68KMAKE_OP(cmpi, 32, ., .)\r
4309{\r
4310 uint src = OPER_I_32();\r
4311 uint dst = M68KMAKE_GET_OPER_AY_32;\r
4312 uint res = dst - src;\r
4313\r
4314 FLAG_N = NFLAG_32(res);\r
4315 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4316 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4317 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4318}\r
4319\r
4320\r
4321M68KMAKE_OP(cmpi, 32, ., pcdi)\r
4322{\r
4323 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4324 {\r
4325 uint src = OPER_I_32();\r
4326 uint dst = OPER_PCDI_32();\r
4327 uint res = dst - src;\r
4328\r
4329 FLAG_N = NFLAG_32(res);\r
4330 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4331 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4332 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4333 return;\r
4334 }\r
4335 m68ki_exception_illegal();\r
4336}\r
4337\r
4338\r
4339M68KMAKE_OP(cmpi, 32, ., pcix)\r
4340{\r
4341 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4342 {\r
4343 uint src = OPER_I_32();\r
4344 uint dst = OPER_PCIX_32();\r
4345 uint res = dst - src;\r
4346\r
4347 FLAG_N = NFLAG_32(res);\r
4348 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4349 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4350 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4351 return;\r
4352 }\r
4353 m68ki_exception_illegal();\r
4354}\r
4355\r
4356\r
4357M68KMAKE_OP(cmpm, 8, ., ax7)\r
4358{\r
4359 uint src = OPER_AY_PI_8();\r
4360 uint dst = OPER_A7_PI_8();\r
4361 uint res = dst - src;\r
4362\r
4363 FLAG_N = NFLAG_8(res);\r
4364 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4365 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4366 FLAG_C = CFLAG_8(res);\r
4367}\r
4368\r
4369\r
4370M68KMAKE_OP(cmpm, 8, ., ay7)\r
4371{\r
4372 uint src = OPER_A7_PI_8();\r
4373 uint dst = OPER_AX_PI_8();\r
4374 uint res = dst - src;\r
4375\r
4376 FLAG_N = NFLAG_8(res);\r
4377 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4378 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4379 FLAG_C = CFLAG_8(res);\r
4380}\r
4381\r
4382\r
4383M68KMAKE_OP(cmpm, 8, ., axy7)\r
4384{\r
4385 uint src = OPER_A7_PI_8();\r
4386 uint dst = OPER_A7_PI_8();\r
4387 uint res = dst - src;\r
4388\r
4389 FLAG_N = NFLAG_8(res);\r
4390 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4391 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4392 FLAG_C = CFLAG_8(res);\r
4393}\r
4394\r
4395\r
4396M68KMAKE_OP(cmpm, 8, ., .)\r
4397{\r
4398 uint src = OPER_AY_PI_8();\r
4399 uint dst = OPER_AX_PI_8();\r
4400 uint res = dst - src;\r
4401\r
4402 FLAG_N = NFLAG_8(res);\r
4403 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4404 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4405 FLAG_C = CFLAG_8(res);\r
4406}\r
4407\r
4408\r
4409M68KMAKE_OP(cmpm, 16, ., .)\r
4410{\r
4411 uint src = OPER_AY_PI_16();\r
4412 uint dst = OPER_AX_PI_16();\r
4413 uint res = dst - src;\r
4414\r
4415 FLAG_N = NFLAG_16(res);\r
4416 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4417 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4418 FLAG_C = CFLAG_16(res);\r
4419}\r
4420\r
4421\r
4422M68KMAKE_OP(cmpm, 32, ., .)\r
4423{\r
4424 uint src = OPER_AY_PI_32();\r
4425 uint dst = OPER_AX_PI_32();\r
4426 uint res = dst - src;\r
4427\r
4428 FLAG_N = NFLAG_32(res);\r
4429 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4430 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4431 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4432}\r
4433\r
4434\r
4435M68KMAKE_OP(cpbcc, 32, ., .)\r
4436{\r
4437 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4438 {\r
4439 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4440 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4441 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4442 return;\r
4443 }\r
4444 m68ki_exception_1111();\r
4445}\r
4446\r
4447\r
4448M68KMAKE_OP(cpdbcc, 32, ., .)\r
4449{\r
4450 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4451 {\r
4452 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4453 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4454 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4455 return;\r
4456 }\r
4457 m68ki_exception_1111();\r
4458}\r
4459\r
4460\r
4461M68KMAKE_OP(cpgen, 32, ., .)\r
4462{\r
4463 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4464 {\r
4465 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4466 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4467 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4468 return;\r
4469 }\r
4470 m68ki_exception_1111();\r
4471}\r
4472\r
4473\r
4474M68KMAKE_OP(cpscc, 32, ., .)\r
4475{\r
4476 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4477 {\r
4478 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4479 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4480 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4481 return;\r
4482 }\r
4483 m68ki_exception_1111();\r
4484}\r
4485\r
4486\r
4487M68KMAKE_OP(cptrapcc, 32, ., .)\r
4488{\r
4489 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4490 {\r
4491 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4492 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4493 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4494 return;\r
4495 }\r
4496 m68ki_exception_1111();\r
4497}\r
4498\r
4499\r
4500M68KMAKE_OP(dbt, 16, ., .)\r
4501{\r
4502 REG_PC += 2;\r
4503}\r
4504\r
4505\r
4506M68KMAKE_OP(dbf, 16, ., .)\r
4507{\r
4508 uint* r_dst = &DY;\r
4509 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4510\r
4511 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4512 if(res != 0xffff)\r
4513 {\r
4514 uint offset = OPER_I_16();\r
4515 REG_PC -= 2;\r
4516 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4517 m68ki_branch_16(offset);\r
4518 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4519 return;\r
4520 }\r
4521 REG_PC += 2;\r
4522 USE_CYCLES(CYC_DBCC_F_EXP);\r
4523}\r
4524\r
4525\r
4526M68KMAKE_OP(dbcc, 16, ., .)\r
4527{\r
4528 if(M68KMAKE_NOT_CC)\r
4529 {\r
4530 uint* r_dst = &DY;\r
4531 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4532\r
4533 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4534 if(res != 0xffff)\r
4535 {\r
4536 uint offset = OPER_I_16();\r
4537 REG_PC -= 2;\r
4538 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4539 m68ki_branch_16(offset);\r
4540 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4541 return;\r
4542 }\r
4543 REG_PC += 2;\r
4544 USE_CYCLES(CYC_DBCC_F_EXP);\r
4545 return;\r
4546 }\r
4547 REG_PC += 2;\r
4548}\r
4549\r
4550\r
4551M68KMAKE_OP(divs, 16, ., d)\r
4552{\r
4553 uint* r_dst = &DX;\r
4554 sint src = MAKE_INT_16(DY);\r
4555 sint dst = MAKE_INT_32(*r_dst);\r
4556 sint quotient;\r
4557 sint remainder;\r
4558 int cycles;\r
4559\r
4560 if(src != 0)\r
4561 {\r
4562 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4563 {\r
4564 FLAG_Z = 0;\r
4565 FLAG_N = NFLAG_CLEAR;\r
4566 FLAG_V = VFLAG_CLEAR;\r
4567 FLAG_C = CFLAG_CLEAR;\r
4568 *r_dst = 0;\r
4569 USE_CYCLES(m68ki_divs_cycles(2, 0));\r
4570 return;\r
4571 }\r
4572\r
4573 if(abs(dst) >= abs(src<<16))\r
4574 {\r
4575 FLAG_V = VFLAG_SET;\r
4576 USE_CYCLES(2*(dst < 0));\r
4577 return;\r
4578 }\r
4579\r
4580 quotient = dst / src;\r
4581 remainder = dst % src;\r
4582\r
4583 cycles = m68ki_divs_cycles(2*(dst < 0) + (quotient < 0), quotient);\r
4584 if(quotient == MAKE_INT_16(quotient))\r
4585 {\r
4586 FLAG_Z = quotient;\r
4587 FLAG_N = NFLAG_16(quotient);\r
4588 FLAG_V = VFLAG_CLEAR;\r
4589 FLAG_C = CFLAG_CLEAR;\r
4590 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4591 USE_CYCLES(cycles);\r
4592 return;\r
4593 }\r
4594 FLAG_V = VFLAG_SET;\r
4595 USE_CYCLES(cycles);\r
4596 return;\r
4597 }\r
4598 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4599 ADD_CYCLES(12);\r
4600}\r
4601\r
4602\r
4603M68KMAKE_OP(divs, 16, ., .)\r
4604{\r
4605 uint* r_dst = &DX;\r
4606 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4607 sint dst = MAKE_INT_32(*r_dst);\r
4608 sint quotient;\r
4609 sint remainder;\r
4610 int cycles;\r
4611\r
4612 if(src != 0)\r
4613 {\r
4614 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4615 {\r
4616 FLAG_Z = 0;\r
4617 FLAG_N = NFLAG_CLEAR;\r
4618 FLAG_V = VFLAG_CLEAR;\r
4619 FLAG_C = CFLAG_CLEAR;\r
4620 *r_dst = 0;\r
4621 USE_CYCLES(m68ki_divs_cycles(2, 0));\r
4622 return;\r
4623 }\r
4624\r
4625 if(abs(dst) >= abs(src<<16))\r
4626 {\r
4627 FLAG_V = VFLAG_SET;\r
4628 USE_CYCLES(2*(dst < 0));\r
4629 return;\r
4630 }\r
4631\r
4632 quotient = dst / src;\r
4633 remainder = dst % src;\r
4634\r
4635 cycles = m68ki_divs_cycles(2*(dst < 0) + (quotient < 0), quotient);\r
4636 if(quotient == MAKE_INT_16(quotient))\r
4637 {\r
4638 FLAG_Z = quotient;\r
4639 FLAG_N = NFLAG_16(quotient);\r
4640 FLAG_V = VFLAG_CLEAR;\r
4641 FLAG_C = CFLAG_CLEAR;\r
4642 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4643 USE_CYCLES(cycles);\r
4644 return;\r
4645 }\r
4646 FLAG_V = VFLAG_SET;\r
4647 USE_CYCLES(cycles);\r
4648 return;\r
4649 }\r
4650 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4651 ADD_CYCLES(12);\r
4652}\r
4653\r
4654\r
4655M68KMAKE_OP(divu, 16, ., d)\r
4656{\r
4657 uint* r_dst = &DX;\r
4658 uint src = MASK_OUT_ABOVE_16(DY);\r
4659\r
4660 if(src != 0)\r
4661 {\r
4662 uint quotient = *r_dst / src;\r
4663 uint remainder = *r_dst % src;\r
4664\r
4665 if(quotient < 0x10000)\r
4666 {\r
4667 FLAG_Z = quotient;\r
4668 FLAG_N = NFLAG_16(quotient);\r
4669 FLAG_V = VFLAG_CLEAR;\r
4670 FLAG_C = CFLAG_CLEAR;\r
4671 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4672 USE_CYCLES(m68ki_divu_cycles(quotient));\r
4673 return;\r
4674 }\r
4675 FLAG_V = VFLAG_SET;\r
4676 return;\r
4677 }\r
4678 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4679 ADD_CYCLES(6);\r
4680}\r
4681\r
4682\r
4683M68KMAKE_OP(divu, 16, ., .)\r
4684{\r
4685 uint* r_dst = &DX;\r
4686 uint src = M68KMAKE_GET_OPER_AY_16;\r
4687\r
4688 if(src != 0)\r
4689 {\r
4690 uint quotient = *r_dst / src;\r
4691 uint remainder = *r_dst % src;\r
4692\r
4693 if(quotient < 0x10000)\r
4694 {\r
4695 FLAG_Z = quotient;\r
4696 FLAG_N = NFLAG_16(quotient);\r
4697 FLAG_V = VFLAG_CLEAR;\r
4698 FLAG_C = CFLAG_CLEAR;\r
4699 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4700 USE_CYCLES(m68ki_divu_cycles(quotient));\r
4701 return;\r
4702 }\r
4703 FLAG_V = VFLAG_SET;\r
4704 return;\r
4705 }\r
4706 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4707 ADD_CYCLES(6);\r
4708}\r
4709\r
4710\r
4711M68KMAKE_OP(divl, 32, ., d)\r
4712{\r
4713#if M68K_USE_64_BIT\r
4714\r
4715 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4716 {\r
4717 uint word2 = OPER_I_16();\r
4718 uint64 divisor = DY;\r
4719 uint64 dividend = 0;\r
4720 uint64 quotient = 0;\r
4721 uint64 remainder = 0;\r
4722\r
4723 if(divisor != 0)\r
4724 {\r
4725 if(BIT_A(word2)) /* 64 bit */\r
4726 {\r
4727 dividend = REG_D[word2 & 7];\r
4728 dividend <<= 32;\r
4729 dividend |= REG_D[(word2 >> 12) & 7];\r
4730\r
4731 if(BIT_B(word2)) /* signed */\r
4732 {\r
4733 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4734 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4735 if((sint64)quotient != (sint64)((sint32)quotient))\r
4736 {\r
4737 FLAG_V = VFLAG_SET;\r
4738 return;\r
4739 }\r
4740 }\r
4741 else /* unsigned */\r
4742 {\r
4743 quotient = dividend / divisor;\r
4744 if(quotient > 0xffffffff)\r
4745 {\r
4746 FLAG_V = VFLAG_SET;\r
4747 return;\r
4748 }\r
4749 remainder = dividend % divisor;\r
4750 }\r
4751 }\r
4752 else /* 32 bit */\r
4753 {\r
4754 dividend = REG_D[(word2 >> 12) & 7];\r
4755 if(BIT_B(word2)) /* signed */\r
4756 {\r
4757 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4758 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4759 }\r
4760 else /* unsigned */\r
4761 {\r
4762 quotient = dividend / divisor;\r
4763 remainder = dividend % divisor;\r
4764 }\r
4765 }\r
4766\r
4767 REG_D[word2 & 7] = remainder;\r
4768 REG_D[(word2 >> 12) & 7] = quotient;\r
4769\r
4770 FLAG_N = NFLAG_32(quotient);\r
4771 FLAG_Z = quotient;\r
4772 FLAG_V = VFLAG_CLEAR;\r
4773 FLAG_C = CFLAG_CLEAR;\r
4774 return;\r
4775 }\r
4776 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4777 return;\r
4778 }\r
4779 m68ki_exception_illegal();\r
4780\r
4781#else\r
4782\r
4783 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4784 {\r
4785 uint word2 = OPER_I_16();\r
4786 uint divisor = DY;\r
4787 uint dividend_hi = REG_D[word2 & 7];\r
4788 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4789 uint quotient = 0;\r
4790 uint remainder = 0;\r
4791 uint dividend_neg = 0;\r
4792 uint divisor_neg = 0;\r
4793 sint i;\r
4794 uint overflow;\r
4795\r
4796 if(divisor != 0)\r
4797 {\r
4798 /* quad / long : long quotient, long remainder */\r
4799 if(BIT_A(word2))\r
4800 {\r
4801 if(BIT_B(word2)) /* signed */\r
4802 {\r
4803 /* special case in signed divide */\r
4804 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4805 {\r
4806 REG_D[word2 & 7] = 0;\r
4807 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4808\r
4809 FLAG_N = NFLAG_SET;\r
4810 FLAG_Z = ZFLAG_CLEAR;\r
4811 FLAG_V = VFLAG_CLEAR;\r
4812 FLAG_C = CFLAG_CLEAR;\r
4813 return;\r
4814 }\r
4815 if(GET_MSB_32(dividend_hi))\r
4816 {\r
4817 dividend_neg = 1;\r
4818 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4819 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4820 }\r
4821 if(GET_MSB_32(divisor))\r
4822 {\r
4823 divisor_neg = 1;\r
4824 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4825\r
4826 }\r
4827 }\r
4828\r
4829 /* if the upper long is greater than the divisor, we're overflowing. */\r
4830 if(dividend_hi >= divisor)\r
4831 {\r
4832 FLAG_V = VFLAG_SET;\r
4833 return;\r
4834 }\r
4835\r
4836 for(i = 31; i >= 0; i--)\r
4837 {\r
4838 quotient <<= 1;\r
4839 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4840 if(remainder >= divisor)\r
4841 {\r
4842 remainder -= divisor;\r
4843 quotient++;\r
4844 }\r
4845 }\r
4846 for(i = 31; i >= 0; i--)\r
4847 {\r
4848 quotient <<= 1;\r
4849 overflow = GET_MSB_32(remainder);\r
4850 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4851 if(remainder >= divisor || overflow)\r
4852 {\r
4853 remainder -= divisor;\r
4854 quotient++;\r
4855 }\r
4856 }\r
4857\r
4858 if(BIT_B(word2)) /* signed */\r
4859 {\r
4860 if(quotient > 0x7fffffff)\r
4861 {\r
4862 FLAG_V = VFLAG_SET;\r
4863 return;\r
4864 }\r
4865 if(dividend_neg)\r
4866 {\r
4867 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4868 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4869 }\r
4870 if(divisor_neg)\r
4871 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4872 }\r
4873\r
4874 REG_D[word2 & 7] = remainder;\r
4875 REG_D[(word2 >> 12) & 7] = quotient;\r
4876\r
4877 FLAG_N = NFLAG_32(quotient);\r
4878 FLAG_Z = quotient;\r
4879 FLAG_V = VFLAG_CLEAR;\r
4880 FLAG_C = CFLAG_CLEAR;\r
4881 return;\r
4882 }\r
4883\r
4884 /* long / long: long quotient, maybe long remainder */\r
4885 if(BIT_B(word2)) /* signed */\r
4886 {\r
4887 /* Special case in divide */\r
4888 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4889 {\r
4890 FLAG_N = NFLAG_SET;\r
4891 FLAG_Z = ZFLAG_CLEAR;\r
4892 FLAG_V = VFLAG_CLEAR;\r
4893 FLAG_C = CFLAG_CLEAR;\r
4894 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4895 REG_D[word2 & 7] = 0;\r
4896 return;\r
4897 }\r
4898 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
4899 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
4900 }\r
4901 else\r
4902 {\r
4903 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
4904 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
4905 }\r
4906\r
4907 FLAG_N = NFLAG_32(quotient);\r
4908 FLAG_Z = quotient;\r
4909 FLAG_V = VFLAG_CLEAR;\r
4910 FLAG_C = CFLAG_CLEAR;\r
4911 return;\r
4912 }\r
4913 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4914 return;\r
4915 }\r
4916 m68ki_exception_illegal();\r
4917\r
4918#endif\r
4919}\r
4920\r
4921\r
4922M68KMAKE_OP(divl, 32, ., .)\r
4923{\r
4924#if M68K_USE_64_BIT\r
4925\r
4926 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4927 {\r
4928 uint word2 = OPER_I_16();\r
4929 uint64 divisor = M68KMAKE_GET_OPER_AY_32;\r
4930 uint64 dividend = 0;\r
4931 uint64 quotient = 0;\r
4932 uint64 remainder = 0;\r
4933\r
4934 if(divisor != 0)\r
4935 {\r
4936 if(BIT_A(word2)) /* 64 bit */\r
4937 {\r
4938 dividend = REG_D[word2 & 7];\r
4939 dividend <<= 32;\r
4940 dividend |= REG_D[(word2 >> 12) & 7];\r
4941\r
4942 if(BIT_B(word2)) /* signed */\r
4943 {\r
4944 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4945 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4946 if((sint64)quotient != (sint64)((sint32)quotient))\r
4947 {\r
4948 FLAG_V = VFLAG_SET;\r
4949 return;\r
4950 }\r
4951 }\r
4952 else /* unsigned */\r
4953 {\r
4954 quotient = dividend / divisor;\r
4955 if(quotient > 0xffffffff)\r
4956 {\r
4957 FLAG_V = VFLAG_SET;\r
4958 return;\r
4959 }\r
4960 remainder = dividend % divisor;\r
4961 }\r
4962 }\r
4963 else /* 32 bit */\r
4964 {\r
4965 dividend = REG_D[(word2 >> 12) & 7];\r
4966 if(BIT_B(word2)) /* signed */\r
4967 {\r
4968 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4969 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4970 }\r
4971 else /* unsigned */\r
4972 {\r
4973 quotient = dividend / divisor;\r
4974 remainder = dividend % divisor;\r
4975 }\r
4976 }\r
4977\r
4978 REG_D[word2 & 7] = remainder;\r
4979 REG_D[(word2 >> 12) & 7] = quotient;\r
4980\r
4981 FLAG_N = NFLAG_32(quotient);\r
4982 FLAG_Z = quotient;\r
4983 FLAG_V = VFLAG_CLEAR;\r
4984 FLAG_C = CFLAG_CLEAR;\r
4985 return;\r
4986 }\r
4987 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4988 return;\r
4989 }\r
4990 m68ki_exception_illegal();\r
4991\r
4992#else\r
4993\r
4994 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4995 {\r
4996 uint word2 = OPER_I_16();\r
4997 uint divisor = M68KMAKE_GET_OPER_AY_32;\r
4998 uint dividend_hi = REG_D[word2 & 7];\r
4999 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
5000 uint quotient = 0;\r
5001 uint remainder = 0;\r
5002 uint dividend_neg = 0;\r
5003 uint divisor_neg = 0;\r
5004 sint i;\r
5005 uint overflow;\r
5006\r
5007 if(divisor != 0)\r
5008 {\r
5009 /* quad / long : long quotient, long remainder */\r
5010 if(BIT_A(word2))\r
5011 {\r
5012 if(BIT_B(word2)) /* signed */\r
5013 {\r
5014 /* special case in signed divide */\r
5015 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
5016 {\r
5017 REG_D[word2 & 7] = 0;\r
5018 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
5019\r
5020 FLAG_N = NFLAG_SET;\r
5021 FLAG_Z = ZFLAG_CLEAR;\r
5022 FLAG_V = VFLAG_CLEAR;\r
5023 FLAG_C = CFLAG_CLEAR;\r
5024 return;\r
5025 }\r
5026 if(GET_MSB_32(dividend_hi))\r
5027 {\r
5028 dividend_neg = 1;\r
5029 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
5030 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
5031 }\r
5032 if(GET_MSB_32(divisor))\r
5033 {\r
5034 divisor_neg = 1;\r
5035 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
5036\r
5037 }\r
5038 }\r
5039\r
5040 /* if the upper long is greater than the divisor, we're overflowing. */\r
5041 if(dividend_hi >= divisor)\r
5042 {\r
5043 FLAG_V = VFLAG_SET;\r
5044 return;\r
5045 }\r
5046\r
5047 for(i = 31; i >= 0; i--)\r
5048 {\r
5049 quotient <<= 1;\r
5050 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
5051 if(remainder >= divisor)\r
5052 {\r
5053 remainder -= divisor;\r
5054 quotient++;\r
5055 }\r
5056 }\r
5057 for(i = 31; i >= 0; i--)\r
5058 {\r
5059 quotient <<= 1;\r
5060 overflow = GET_MSB_32(remainder);\r
5061 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
5062 if(remainder >= divisor || overflow)\r
5063 {\r
5064 remainder -= divisor;\r
5065 quotient++;\r
5066 }\r
5067 }\r
5068\r
5069 if(BIT_B(word2)) /* signed */\r
5070 {\r
5071 if(quotient > 0x7fffffff)\r
5072 {\r
5073 FLAG_V = VFLAG_SET;\r
5074 return;\r
5075 }\r
5076 if(dividend_neg)\r
5077 {\r
5078 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
5079 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
5080 }\r
5081 if(divisor_neg)\r
5082 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
5083 }\r
5084\r
5085 REG_D[word2 & 7] = remainder;\r
5086 REG_D[(word2 >> 12) & 7] = quotient;\r
5087\r
5088 FLAG_N = NFLAG_32(quotient);\r
5089 FLAG_Z = quotient;\r
5090 FLAG_V = VFLAG_CLEAR;\r
5091 FLAG_C = CFLAG_CLEAR;\r
5092 return;\r
5093 }\r
5094\r
5095 /* long / long: long quotient, maybe long remainder */\r
5096 if(BIT_B(word2)) /* signed */\r
5097 {\r
5098 /* Special case in divide */\r
5099 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
5100 {\r
5101 FLAG_N = NFLAG_SET;\r
5102 FLAG_Z = ZFLAG_CLEAR;\r
5103 FLAG_V = VFLAG_CLEAR;\r
5104 FLAG_C = CFLAG_CLEAR;\r
5105 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
5106 REG_D[word2 & 7] = 0;\r
5107 return;\r
5108 }\r
5109 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
5110 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
5111 }\r
5112 else\r
5113 {\r
5114 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
5115 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
5116 }\r
5117\r
5118 FLAG_N = NFLAG_32(quotient);\r
5119 FLAG_Z = quotient;\r
5120 FLAG_V = VFLAG_CLEAR;\r
5121 FLAG_C = CFLAG_CLEAR;\r
5122 return;\r
5123 }\r
5124 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
5125 return;\r
5126 }\r
5127 m68ki_exception_illegal();\r
5128\r
5129#endif\r
5130}\r
5131\r
5132\r
5133M68KMAKE_OP(eor, 8, ., d)\r
5134{\r
5135 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));\r
5136\r
5137 FLAG_N = NFLAG_8(res);\r
5138 FLAG_Z = res;\r
5139 FLAG_C = CFLAG_CLEAR;\r
5140 FLAG_V = VFLAG_CLEAR;\r
5141}\r
5142\r
5143\r
5144M68KMAKE_OP(eor, 8, ., .)\r
5145{\r
5146 uint ea = M68KMAKE_GET_EA_AY_8;\r
5147 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));\r
5148\r
5149 m68ki_write_8(ea, res);\r
5150\r
5151 FLAG_N = NFLAG_8(res);\r
5152 FLAG_Z = res;\r
5153 FLAG_C = CFLAG_CLEAR;\r
5154 FLAG_V = VFLAG_CLEAR;\r
5155}\r
5156\r
5157\r
5158M68KMAKE_OP(eor, 16, ., d)\r
5159{\r
5160 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));\r
5161\r
5162 FLAG_N = NFLAG_16(res);\r
5163 FLAG_Z = res;\r
5164 FLAG_C = CFLAG_CLEAR;\r
5165 FLAG_V = VFLAG_CLEAR;\r
5166}\r
5167\r
5168\r
5169M68KMAKE_OP(eor, 16, ., .)\r
5170{\r
5171 uint ea = M68KMAKE_GET_EA_AY_16;\r
5172 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));\r
5173\r
5174 m68ki_write_16(ea, res);\r
5175\r
5176 FLAG_N = NFLAG_16(res);\r
5177 FLAG_Z = res;\r
5178 FLAG_C = CFLAG_CLEAR;\r
5179 FLAG_V = VFLAG_CLEAR;\r
5180}\r
5181\r
5182\r
5183M68KMAKE_OP(eor, 32, ., d)\r
5184{\r
5185 uint res = DY ^= DX;\r
5186\r
5187 FLAG_N = NFLAG_32(res);\r
5188 FLAG_Z = res;\r
5189 FLAG_C = CFLAG_CLEAR;\r
5190 FLAG_V = VFLAG_CLEAR;\r
5191}\r
5192\r
5193\r
5194M68KMAKE_OP(eor, 32, ., .)\r
5195{\r
5196 uint ea = M68KMAKE_GET_EA_AY_32;\r
5197 uint res = DX ^ m68ki_read_32(ea);\r
5198\r
5199 m68ki_write_32(ea, res);\r
5200\r
5201 FLAG_N = NFLAG_32(res);\r
5202 FLAG_Z = res;\r
5203 FLAG_C = CFLAG_CLEAR;\r
5204 FLAG_V = VFLAG_CLEAR;\r
5205}\r
5206\r
5207\r
5208M68KMAKE_OP(eori, 8, ., d)\r
5209{\r
5210 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());\r
5211\r
5212 FLAG_N = NFLAG_8(res);\r
5213 FLAG_Z = res;\r
5214 FLAG_C = CFLAG_CLEAR;\r
5215 FLAG_V = VFLAG_CLEAR;\r
5216}\r
5217\r
5218\r
5219M68KMAKE_OP(eori, 8, ., .)\r
5220{\r
5221 uint src = OPER_I_8();\r
5222 uint ea = M68KMAKE_GET_EA_AY_8;\r
5223 uint res = src ^ m68ki_read_8(ea);\r
5224\r
5225 m68ki_write_8(ea, res);\r
5226\r
5227 FLAG_N = NFLAG_8(res);\r
5228 FLAG_Z = res;\r
5229 FLAG_C = CFLAG_CLEAR;\r
5230 FLAG_V = VFLAG_CLEAR;\r
5231}\r
5232\r
5233\r
5234M68KMAKE_OP(eori, 16, ., d)\r
5235{\r
5236 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());\r
5237\r
5238 FLAG_N = NFLAG_16(res);\r
5239 FLAG_Z = res;\r
5240 FLAG_C = CFLAG_CLEAR;\r
5241 FLAG_V = VFLAG_CLEAR;\r
5242}\r
5243\r
5244\r
5245M68KMAKE_OP(eori, 16, ., .)\r
5246{\r
5247 uint src = OPER_I_16();\r
5248 uint ea = M68KMAKE_GET_EA_AY_16;\r
5249 uint res = src ^ m68ki_read_16(ea);\r
5250\r
5251 m68ki_write_16(ea, res);\r
5252\r
5253 FLAG_N = NFLAG_16(res);\r
5254 FLAG_Z = res;\r
5255 FLAG_C = CFLAG_CLEAR;\r
5256 FLAG_V = VFLAG_CLEAR;\r
5257}\r
5258\r
5259\r
5260M68KMAKE_OP(eori, 32, ., d)\r
5261{\r
5262 uint res = DY ^= OPER_I_32();\r
5263\r
5264 FLAG_N = NFLAG_32(res);\r
5265 FLAG_Z = res;\r
5266 FLAG_C = CFLAG_CLEAR;\r
5267 FLAG_V = VFLAG_CLEAR;\r
5268}\r
5269\r
5270\r
5271M68KMAKE_OP(eori, 32, ., .)\r
5272{\r
5273 uint src = OPER_I_32();\r
5274 uint ea = M68KMAKE_GET_EA_AY_32;\r
5275 uint res = src ^ m68ki_read_32(ea);\r
5276\r
5277 m68ki_write_32(ea, res);\r
5278\r
5279 FLAG_N = NFLAG_32(res);\r
5280 FLAG_Z = res;\r
5281 FLAG_C = CFLAG_CLEAR;\r
5282 FLAG_V = VFLAG_CLEAR;\r
5283}\r
5284\r
5285\r
5286M68KMAKE_OP(eori, 16, toc, .)\r
5287{\r
5288 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());\r
5289}\r
5290\r
5291\r
5292M68KMAKE_OP(eori, 16, tos, .)\r
5293{\r
5294 if(FLAG_S)\r
5295 {\r
5296 uint src = OPER_I_16();\r
5297 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5298 m68ki_set_sr(m68ki_get_sr() ^ src);\r
5299 return;\r
5300 }\r
5301 m68ki_exception_privilege_violation();\r
5302}\r
5303\r
5304\r
5305M68KMAKE_OP(exg, 32, dd, .)\r
5306{\r
5307 uint* reg_a = &DX;\r
5308 uint* reg_b = &DY;\r
5309 uint tmp = *reg_a;\r
5310 *reg_a = *reg_b;\r
5311 *reg_b = tmp;\r
5312}\r
5313\r
5314\r
5315M68KMAKE_OP(exg, 32, aa, .)\r
5316{\r
5317 uint* reg_a = &AX;\r
5318 uint* reg_b = &AY;\r
5319 uint tmp = *reg_a;\r
5320 *reg_a = *reg_b;\r
5321 *reg_b = tmp;\r
5322}\r
5323\r
5324\r
5325M68KMAKE_OP(exg, 32, da, .)\r
5326{\r
5327 uint* reg_a = &DX;\r
5328 uint* reg_b = &AY;\r
5329 uint tmp = *reg_a;\r
5330 *reg_a = *reg_b;\r
5331 *reg_b = tmp;\r
5332}\r
5333\r
5334\r
5335M68KMAKE_OP(ext, 16, ., .)\r
5336{\r
5337 uint* r_dst = &DY;\r
5338\r
5339 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);\r
5340\r
5341 FLAG_N = NFLAG_16(*r_dst);\r
5342 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
5343 FLAG_V = VFLAG_CLEAR;\r
5344 FLAG_C = CFLAG_CLEAR;\r
5345}\r
5346\r
5347\r
5348M68KMAKE_OP(ext, 32, ., .)\r
5349{\r
5350 uint* r_dst = &DY;\r
5351\r
5352 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);\r
5353\r
5354 FLAG_N = NFLAG_32(*r_dst);\r
5355 FLAG_Z = *r_dst;\r
5356 FLAG_V = VFLAG_CLEAR;\r
5357 FLAG_C = CFLAG_CLEAR;\r
5358}\r
5359\r
5360\r
5361M68KMAKE_OP(extb, 32, ., .)\r
5362{\r
5363 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5364 {\r
5365 uint* r_dst = &DY;\r
5366\r
5367 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);\r
5368\r
5369 FLAG_N = NFLAG_32(*r_dst);\r
5370 FLAG_Z = *r_dst;\r
5371 FLAG_V = VFLAG_CLEAR;\r
5372 FLAG_C = CFLAG_CLEAR;\r
5373 return;\r
5374 }\r
5375 m68ki_exception_illegal();\r
5376}\r
5377\r
5378\r
5379M68KMAKE_OP(illegal, 0, ., .)\r
5380{\r
5381 m68ki_exception_illegal();\r
5382}\r
5383\r
5384M68KMAKE_OP(jmp, 32, ., .)\r
5385{\r
5386 m68ki_jump(M68KMAKE_GET_EA_AY_32);\r
5387 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5388 if(REG_PC == REG_PPC)\r
5389 USE_ALL_CYCLES();\r
5390}\r
5391\r
5392\r
5393M68KMAKE_OP(jsr, 32, ., .)\r
5394{\r
5395 uint ea = M68KMAKE_GET_EA_AY_32;\r
5396 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5397 m68ki_push_32(REG_PC);\r
5398 m68ki_jump(ea);\r
5399}\r
5400\r
5401\r
5402M68KMAKE_OP(lea, 32, ., .)\r
5403{\r
5404 AX = M68KMAKE_GET_EA_AY_32;\r
5405}\r
5406\r
5407\r
5408M68KMAKE_OP(link, 16, ., a7)\r
5409{\r
5410 REG_A[7] -= 4;\r
5411 m68ki_write_32(REG_A[7], REG_A[7]);\r
5412 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5413}\r
5414\r
5415\r
5416M68KMAKE_OP(link, 16, ., .)\r
5417{\r
5418 uint* r_dst = &AY;\r
5419\r
5420 m68ki_push_32(*r_dst);\r
5421 *r_dst = REG_A[7];\r
5422 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5423}\r
5424\r
5425\r
5426M68KMAKE_OP(link, 32, ., a7)\r
5427{\r
5428 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5429 {\r
5430 REG_A[7] -= 4;\r
5431 m68ki_write_32(REG_A[7], REG_A[7]);\r
5432 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5433 return;\r
5434 }\r
5435 m68ki_exception_illegal();\r
5436}\r
5437\r
5438\r
5439M68KMAKE_OP(link, 32, ., .)\r
5440{\r
5441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5442 {\r
5443 uint* r_dst = &AY;\r
5444\r
5445 m68ki_push_32(*r_dst);\r
5446 *r_dst = REG_A[7];\r
5447 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5448 return;\r
5449 }\r
5450 m68ki_exception_illegal();\r
5451}\r
5452\r
5453\r
5454M68KMAKE_OP(lsr, 8, s, .)\r
5455{\r
5456 uint* r_dst = &DY;\r
5457 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5458 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5459 uint res = src >> shift;\r
5460\r
5461 if(shift != 0)\r
5462 USE_CYCLES(shift<<CYC_SHIFT);\r
5463\r
5464 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5465\r
5466 FLAG_N = NFLAG_CLEAR;\r
5467 FLAG_Z = res;\r
5468 FLAG_X = FLAG_C = src << (9-shift);\r
5469 FLAG_V = VFLAG_CLEAR;\r
5470}\r
5471\r
5472\r
5473M68KMAKE_OP(lsr, 16, s, .)\r
5474{\r
5475 uint* r_dst = &DY;\r
5476 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5477 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5478 uint res = src >> shift;\r
5479\r
5480 if(shift != 0)\r
5481 USE_CYCLES(shift<<CYC_SHIFT);\r
5482\r
5483 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5484\r
5485 FLAG_N = NFLAG_CLEAR;\r
5486 FLAG_Z = res;\r
5487 FLAG_X = FLAG_C = src << (9-shift);\r
5488 FLAG_V = VFLAG_CLEAR;\r
5489}\r
5490\r
5491\r
5492M68KMAKE_OP(lsr, 32, s, .)\r
5493{\r
5494 uint* r_dst = &DY;\r
5495 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5496 uint src = *r_dst;\r
5497 uint res = src >> shift;\r
5498\r
5499 if(shift != 0)\r
5500 USE_CYCLES(shift<<CYC_SHIFT);\r
5501\r
5502 *r_dst = res;\r
5503\r
5504 FLAG_N = NFLAG_CLEAR;\r
5505 FLAG_Z = res;\r
5506 FLAG_X = FLAG_C = src << (9-shift);\r
5507 FLAG_V = VFLAG_CLEAR;\r
5508}\r
5509\r
5510\r
5511M68KMAKE_OP(lsr, 8, r, .)\r
5512{\r
5513 uint* r_dst = &DY;\r
5514 uint shift = DX & 0x3f;\r
5515 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5516 uint res = src >> shift;\r
5517\r
5518 if(shift != 0)\r
5519 {\r
5520 USE_CYCLES(shift<<CYC_SHIFT);\r
5521\r
5522 if(shift <= 8)\r
5523 {\r
5524 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5525 FLAG_X = FLAG_C = src << (9-shift);\r
5526 FLAG_N = NFLAG_CLEAR;\r
5527 FLAG_Z = res;\r
5528 FLAG_V = VFLAG_CLEAR;\r
5529 return;\r
5530 }\r
5531\r
5532 *r_dst &= 0xffffff00;\r
5533 FLAG_X = XFLAG_CLEAR;\r
5534 FLAG_C = CFLAG_CLEAR;\r
5535 FLAG_N = NFLAG_CLEAR;\r
5536 FLAG_Z = ZFLAG_SET;\r
5537 FLAG_V = VFLAG_CLEAR;\r
5538 return;\r
5539 }\r
5540\r
5541 FLAG_C = CFLAG_CLEAR;\r
5542 FLAG_N = NFLAG_8(src);\r
5543 FLAG_Z = src;\r
5544 FLAG_V = VFLAG_CLEAR;\r
5545}\r
5546\r
5547\r
5548M68KMAKE_OP(lsr, 16, r, .)\r
5549{\r
5550 uint* r_dst = &DY;\r
5551 uint shift = DX & 0x3f;\r
5552 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5553 uint res = src >> shift;\r
5554\r
5555 if(shift != 0)\r
5556 {\r
5557 USE_CYCLES(shift<<CYC_SHIFT);\r
5558\r
5559 if(shift <= 16)\r
5560 {\r
5561 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5562 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5563 FLAG_N = NFLAG_CLEAR;\r
5564 FLAG_Z = res;\r
5565 FLAG_V = VFLAG_CLEAR;\r
5566 return;\r
5567 }\r
5568\r
5569 *r_dst &= 0xffff0000;\r
5570 FLAG_X = XFLAG_CLEAR;\r
5571 FLAG_C = CFLAG_CLEAR;\r
5572 FLAG_N = NFLAG_CLEAR;\r
5573 FLAG_Z = ZFLAG_SET;\r
5574 FLAG_V = VFLAG_CLEAR;\r
5575 return;\r
5576 }\r
5577\r
5578 FLAG_C = CFLAG_CLEAR;\r
5579 FLAG_N = NFLAG_16(src);\r
5580 FLAG_Z = src;\r
5581 FLAG_V = VFLAG_CLEAR;\r
5582}\r
5583\r
5584\r
5585M68KMAKE_OP(lsr, 32, r, .)\r
5586{\r
5587 uint* r_dst = &DY;\r
5588 uint shift = DX & 0x3f;\r
5589 uint src = *r_dst;\r
5590 uint res = src >> shift;\r
5591\r
5592 if(shift != 0)\r
5593 {\r
5594 USE_CYCLES(shift<<CYC_SHIFT);\r
5595\r
5596 if(shift < 32)\r
5597 {\r
5598 *r_dst = res;\r
5599 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5600 FLAG_N = NFLAG_CLEAR;\r
5601 FLAG_Z = res;\r
5602 FLAG_V = VFLAG_CLEAR;\r
5603 return;\r
5604 }\r
5605\r
5606 *r_dst = 0;\r
5607 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);\r
5608 FLAG_N = NFLAG_CLEAR;\r
5609 FLAG_Z = ZFLAG_SET;\r
5610 FLAG_V = VFLAG_CLEAR;\r
5611 return;\r
5612 }\r
5613\r
5614 FLAG_C = CFLAG_CLEAR;\r
5615 FLAG_N = NFLAG_32(src);\r
5616 FLAG_Z = src;\r
5617 FLAG_V = VFLAG_CLEAR;\r
5618}\r
5619\r
5620\r
5621M68KMAKE_OP(lsr, 16, ., .)\r
5622{\r
5623 uint ea = M68KMAKE_GET_EA_AY_16;\r
5624 uint src = m68ki_read_16(ea);\r
5625 uint res = src >> 1;\r
5626\r
5627 m68ki_write_16(ea, res);\r
5628\r
5629 FLAG_N = NFLAG_CLEAR;\r
5630 FLAG_Z = res;\r
5631 FLAG_C = FLAG_X = src << 8;\r
5632 FLAG_V = VFLAG_CLEAR;\r
5633}\r
5634\r
5635\r
5636M68KMAKE_OP(lsl, 8, s, .)\r
5637{\r
5638 uint* r_dst = &DY;\r
5639 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5640 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5641 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5642\r
5643 if(shift != 0)\r
5644 USE_CYCLES(shift<<CYC_SHIFT);\r
5645\r
5646 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5647\r
5648 FLAG_N = NFLAG_8(res);\r
5649 FLAG_Z = res;\r
5650 FLAG_X = FLAG_C = src << shift;\r
5651 FLAG_V = VFLAG_CLEAR;\r
5652}\r
5653\r
5654\r
5655M68KMAKE_OP(lsl, 16, s, .)\r
5656{\r
5657 uint* r_dst = &DY;\r
5658 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5659 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5660 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5661\r
5662 if(shift != 0)\r
5663 USE_CYCLES(shift<<CYC_SHIFT);\r
5664\r
5665 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5666\r
5667 FLAG_N = NFLAG_16(res);\r
5668 FLAG_Z = res;\r
5669 FLAG_X = FLAG_C = src >> (8-shift);\r
5670 FLAG_V = VFLAG_CLEAR;\r
5671}\r
5672\r
5673\r
5674M68KMAKE_OP(lsl, 32, s, .)\r
5675{\r
5676 uint* r_dst = &DY;\r
5677 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5678 uint src = *r_dst;\r
5679 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5680\r
5681 if(shift != 0)\r
5682 USE_CYCLES(shift<<CYC_SHIFT);\r
5683\r
5684 *r_dst = res;\r
5685\r
5686 FLAG_N = NFLAG_32(res);\r
5687 FLAG_Z = res;\r
5688 FLAG_X = FLAG_C = src >> (24-shift);\r
5689 FLAG_V = VFLAG_CLEAR;\r
5690}\r
5691\r
5692\r
5693M68KMAKE_OP(lsl, 8, r, .)\r
5694{\r
5695 uint* r_dst = &DY;\r
5696 uint shift = DX & 0x3f;\r
5697 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5698 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5699\r
5700 if(shift != 0)\r
5701 {\r
5702 USE_CYCLES(shift<<CYC_SHIFT);\r
5703\r
5704 if(shift <= 8)\r
5705 {\r
5706 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5707 FLAG_X = FLAG_C = src << shift;\r
5708 FLAG_N = NFLAG_8(res);\r
5709 FLAG_Z = res;\r
5710 FLAG_V = VFLAG_CLEAR;\r
5711 return;\r
5712 }\r
5713\r
5714 *r_dst &= 0xffffff00;\r
5715 FLAG_X = XFLAG_CLEAR;\r
5716 FLAG_C = CFLAG_CLEAR;\r
5717 FLAG_N = NFLAG_CLEAR;\r
5718 FLAG_Z = ZFLAG_SET;\r
5719 FLAG_V = VFLAG_CLEAR;\r
5720 return;\r
5721 }\r
5722\r
5723 FLAG_C = CFLAG_CLEAR;\r
5724 FLAG_N = NFLAG_8(src);\r
5725 FLAG_Z = src;\r
5726 FLAG_V = VFLAG_CLEAR;\r
5727}\r
5728\r
5729\r
5730M68KMAKE_OP(lsl, 16, r, .)\r
5731{\r
5732 uint* r_dst = &DY;\r
5733 uint shift = DX & 0x3f;\r
5734 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5735 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5736\r
5737 if(shift != 0)\r
5738 {\r
5739 USE_CYCLES(shift<<CYC_SHIFT);\r
5740\r
5741 if(shift <= 16)\r
5742 {\r
5743 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5744 FLAG_X = FLAG_C = (src << shift) >> 8;\r
5745 FLAG_N = NFLAG_16(res);\r
5746 FLAG_Z = res;\r
5747 FLAG_V = VFLAG_CLEAR;\r
5748 return;\r
5749 }\r
5750\r
5751 *r_dst &= 0xffff0000;\r
5752 FLAG_X = XFLAG_CLEAR;\r
5753 FLAG_C = CFLAG_CLEAR;\r
5754 FLAG_N = NFLAG_CLEAR;\r
5755 FLAG_Z = ZFLAG_SET;\r
5756 FLAG_V = VFLAG_CLEAR;\r
5757 return;\r
5758 }\r
5759\r
5760 FLAG_C = CFLAG_CLEAR;\r
5761 FLAG_N = NFLAG_16(src);\r
5762 FLAG_Z = src;\r
5763 FLAG_V = VFLAG_CLEAR;\r
5764}\r
5765\r
5766\r
5767M68KMAKE_OP(lsl, 32, r, .)\r
5768{\r
5769 uint* r_dst = &DY;\r
5770 uint shift = DX & 0x3f;\r
5771 uint src = *r_dst;\r
5772 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5773\r
5774 if(shift != 0)\r
5775 {\r
5776 USE_CYCLES(shift<<CYC_SHIFT);\r
5777\r
5778 if(shift < 32)\r
5779 {\r
5780 *r_dst = res;\r
5781 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
5782 FLAG_N = NFLAG_32(res);\r
5783 FLAG_Z = res;\r
5784 FLAG_V = VFLAG_CLEAR;\r
5785 return;\r
5786 }\r
5787\r
5788 *r_dst = 0;\r
5789 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
5790 FLAG_N = NFLAG_CLEAR;\r
5791 FLAG_Z = ZFLAG_SET;\r
5792 FLAG_V = VFLAG_CLEAR;\r
5793 return;\r
5794 }\r
5795\r
5796 FLAG_C = CFLAG_CLEAR;\r
5797 FLAG_N = NFLAG_32(src);\r
5798 FLAG_Z = src;\r
5799 FLAG_V = VFLAG_CLEAR;\r
5800}\r
5801\r
5802\r
5803M68KMAKE_OP(lsl, 16, ., .)\r
5804{\r
5805 uint ea = M68KMAKE_GET_EA_AY_16;\r
5806 uint src = m68ki_read_16(ea);\r
5807 uint res = MASK_OUT_ABOVE_16(src << 1);\r
5808\r
5809 m68ki_write_16(ea, res);\r
5810\r
5811 FLAG_N = NFLAG_16(res);\r
5812 FLAG_Z = res;\r
5813 FLAG_X = FLAG_C = src >> 7;\r
5814 FLAG_V = VFLAG_CLEAR;\r
5815}\r
5816\r
5817\r
5818M68KMAKE_OP(move, 8, d, d)\r
5819{\r
5820 uint res = MASK_OUT_ABOVE_8(DY);\r
5821 uint* r_dst = &DX;\r
5822\r
5823 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5824\r
5825 FLAG_N = NFLAG_8(res);\r
5826 FLAG_Z = res;\r
5827 FLAG_V = VFLAG_CLEAR;\r
5828 FLAG_C = CFLAG_CLEAR;\r
5829}\r
5830\r
5831\r
5832M68KMAKE_OP(move, 8, d, .)\r
5833{\r
5834 uint res = M68KMAKE_GET_OPER_AY_8;\r
5835 uint* r_dst = &DX;\r
5836\r
5837 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5838\r
5839 FLAG_N = NFLAG_8(res);\r
5840 FLAG_Z = res;\r
5841 FLAG_V = VFLAG_CLEAR;\r
5842 FLAG_C = CFLAG_CLEAR;\r
5843}\r
5844\r
5845\r
5846M68KMAKE_OP(move, 8, ai, d)\r
5847{\r
5848 uint res = MASK_OUT_ABOVE_8(DY);\r
5849 uint ea = EA_AX_AI_8();\r
5850\r
5851 m68ki_write_8(ea, res);\r
5852\r
5853 FLAG_N = NFLAG_8(res);\r
5854 FLAG_Z = res;\r
5855 FLAG_V = VFLAG_CLEAR;\r
5856 FLAG_C = CFLAG_CLEAR;\r
5857}\r
5858\r
5859\r
5860M68KMAKE_OP(move, 8, ai, .)\r
5861{\r
5862 uint res = M68KMAKE_GET_OPER_AY_8;\r
5863 uint ea = EA_AX_AI_8();\r
5864\r
5865 m68ki_write_8(ea, res);\r
5866\r
5867 FLAG_N = NFLAG_8(res);\r
5868 FLAG_Z = res;\r
5869 FLAG_V = VFLAG_CLEAR;\r
5870 FLAG_C = CFLAG_CLEAR;\r
5871}\r
5872\r
5873\r
5874M68KMAKE_OP(move, 8, pi7, d)\r
5875{\r
5876 uint res = MASK_OUT_ABOVE_8(DY);\r
5877 uint ea = EA_A7_PI_8();\r
5878\r
5879 m68ki_write_8(ea, res);\r
5880\r
5881 FLAG_N = NFLAG_8(res);\r
5882 FLAG_Z = res;\r
5883 FLAG_V = VFLAG_CLEAR;\r
5884 FLAG_C = CFLAG_CLEAR;\r
5885}\r
5886\r
5887\r
5888M68KMAKE_OP(move, 8, pi, d)\r
5889{\r
5890 uint res = MASK_OUT_ABOVE_8(DY);\r
5891 uint ea = EA_AX_PI_8();\r
5892\r
5893 m68ki_write_8(ea, res);\r
5894\r
5895 FLAG_N = NFLAG_8(res);\r
5896 FLAG_Z = res;\r
5897 FLAG_V = VFLAG_CLEAR;\r
5898 FLAG_C = CFLAG_CLEAR;\r
5899}\r
5900\r
5901\r
5902M68KMAKE_OP(move, 8, pi7, .)\r
5903{\r
5904 uint res = M68KMAKE_GET_OPER_AY_8;\r
5905 uint ea = EA_A7_PI_8();\r
5906\r
5907 m68ki_write_8(ea, res);\r
5908\r
5909 FLAG_N = NFLAG_8(res);\r
5910 FLAG_Z = res;\r
5911 FLAG_V = VFLAG_CLEAR;\r
5912 FLAG_C = CFLAG_CLEAR;\r
5913}\r
5914\r
5915\r
5916M68KMAKE_OP(move, 8, pi, .)\r
5917{\r
5918 uint res = M68KMAKE_GET_OPER_AY_8;\r
5919 uint ea = EA_AX_PI_8();\r
5920\r
5921 m68ki_write_8(ea, res);\r
5922\r
5923 FLAG_N = NFLAG_8(res);\r
5924 FLAG_Z = res;\r
5925 FLAG_V = VFLAG_CLEAR;\r
5926 FLAG_C = CFLAG_CLEAR;\r
5927}\r
5928\r
5929\r
5930M68KMAKE_OP(move, 8, pd7, d)\r
5931{\r
5932 uint res = MASK_OUT_ABOVE_8(DY);\r
5933 uint ea = EA_A7_PD_8();\r
5934\r
5935 m68ki_write_8(ea, res);\r
5936\r
5937 FLAG_N = NFLAG_8(res);\r
5938 FLAG_Z = res;\r
5939 FLAG_V = VFLAG_CLEAR;\r
5940 FLAG_C = CFLAG_CLEAR;\r
5941}\r
5942\r
5943\r
5944M68KMAKE_OP(move, 8, pd, d)\r
5945{\r
5946 uint res = MASK_OUT_ABOVE_8(DY);\r
5947 uint ea = EA_AX_PD_8();\r
5948\r
5949 m68ki_write_8(ea, res);\r
5950\r
5951 FLAG_N = NFLAG_8(res);\r
5952 FLAG_Z = res;\r
5953 FLAG_V = VFLAG_CLEAR;\r
5954 FLAG_C = CFLAG_CLEAR;\r
5955}\r
5956\r
5957\r
5958M68KMAKE_OP(move, 8, pd7, .)\r
5959{\r
5960 uint res = M68KMAKE_GET_OPER_AY_8;\r
5961 uint ea = EA_A7_PD_8();\r
5962\r
5963 m68ki_write_8(ea, res);\r
5964\r
5965 FLAG_N = NFLAG_8(res);\r
5966 FLAG_Z = res;\r
5967 FLAG_V = VFLAG_CLEAR;\r
5968 FLAG_C = CFLAG_CLEAR;\r
5969}\r
5970\r
5971\r
5972M68KMAKE_OP(move, 8, pd, .)\r
5973{\r
5974 uint res = M68KMAKE_GET_OPER_AY_8;\r
5975 uint ea = EA_AX_PD_8();\r
5976\r
5977 m68ki_write_8(ea, res);\r
5978\r
5979 FLAG_N = NFLAG_8(res);\r
5980 FLAG_Z = res;\r
5981 FLAG_V = VFLAG_CLEAR;\r
5982 FLAG_C = CFLAG_CLEAR;\r
5983}\r
5984\r
5985\r
5986M68KMAKE_OP(move, 8, di, d)\r
5987{\r
5988 uint res = MASK_OUT_ABOVE_8(DY);\r
5989 uint ea = EA_AX_DI_8();\r
5990\r
5991 m68ki_write_8(ea, res);\r
5992\r
5993 FLAG_N = NFLAG_8(res);\r
5994 FLAG_Z = res;\r
5995 FLAG_V = VFLAG_CLEAR;\r
5996 FLAG_C = CFLAG_CLEAR;\r
5997}\r
5998\r
5999\r
6000M68KMAKE_OP(move, 8, di, .)\r
6001{\r
6002 uint res = M68KMAKE_GET_OPER_AY_8;\r
6003 uint ea = EA_AX_DI_8();\r
6004\r
6005 m68ki_write_8(ea, res);\r
6006\r
6007 FLAG_N = NFLAG_8(res);\r
6008 FLAG_Z = res;\r
6009 FLAG_V = VFLAG_CLEAR;\r
6010 FLAG_C = CFLAG_CLEAR;\r
6011}\r
6012\r
6013\r
6014M68KMAKE_OP(move, 8, ix, d)\r
6015{\r
6016 uint res = MASK_OUT_ABOVE_8(DY);\r
6017 uint ea = EA_AX_IX_8();\r
6018\r
6019 m68ki_write_8(ea, res);\r
6020\r
6021 FLAG_N = NFLAG_8(res);\r
6022 FLAG_Z = res;\r
6023 FLAG_V = VFLAG_CLEAR;\r
6024 FLAG_C = CFLAG_CLEAR;\r
6025}\r
6026\r
6027\r
6028M68KMAKE_OP(move, 8, ix, .)\r
6029{\r
6030 uint res = M68KMAKE_GET_OPER_AY_8;\r
6031 uint ea = EA_AX_IX_8();\r
6032\r
6033 m68ki_write_8(ea, res);\r
6034\r
6035 FLAG_N = NFLAG_8(res);\r
6036 FLAG_Z = res;\r
6037 FLAG_V = VFLAG_CLEAR;\r
6038 FLAG_C = CFLAG_CLEAR;\r
6039}\r
6040\r
6041\r
6042M68KMAKE_OP(move, 8, aw, d)\r
6043{\r
6044 uint res = MASK_OUT_ABOVE_8(DY);\r
6045 uint ea = EA_AW_8();\r
6046\r
6047 m68ki_write_8(ea, res);\r
6048\r
6049 FLAG_N = NFLAG_8(res);\r
6050 FLAG_Z = res;\r
6051 FLAG_V = VFLAG_CLEAR;\r
6052 FLAG_C = CFLAG_CLEAR;\r
6053}\r
6054\r
6055\r
6056M68KMAKE_OP(move, 8, aw, .)\r
6057{\r
6058 uint res = M68KMAKE_GET_OPER_AY_8;\r
6059 uint ea = EA_AW_8();\r
6060\r
6061 m68ki_write_8(ea, res);\r
6062\r
6063 FLAG_N = NFLAG_8(res);\r
6064 FLAG_Z = res;\r
6065 FLAG_V = VFLAG_CLEAR;\r
6066 FLAG_C = CFLAG_CLEAR;\r
6067}\r
6068\r
6069\r
6070M68KMAKE_OP(move, 8, al, d)\r
6071{\r
6072 uint res = MASK_OUT_ABOVE_8(DY);\r
6073 uint ea = EA_AL_8();\r
6074\r
6075 m68ki_write_8(ea, res);\r
6076\r
6077 FLAG_N = NFLAG_8(res);\r
6078 FLAG_Z = res;\r
6079 FLAG_V = VFLAG_CLEAR;\r
6080 FLAG_C = CFLAG_CLEAR;\r
6081}\r
6082\r
6083\r
6084M68KMAKE_OP(move, 8, al, .)\r
6085{\r
6086 uint res = M68KMAKE_GET_OPER_AY_8;\r
6087 uint ea = EA_AL_8();\r
6088\r
6089 m68ki_write_8(ea, res);\r
6090\r
6091 FLAG_N = NFLAG_8(res);\r
6092 FLAG_Z = res;\r
6093 FLAG_V = VFLAG_CLEAR;\r
6094 FLAG_C = CFLAG_CLEAR;\r
6095}\r
6096\r
6097\r
6098M68KMAKE_OP(move, 16, d, d)\r
6099{\r
6100 uint res = MASK_OUT_ABOVE_16(DY);\r
6101 uint* r_dst = &DX;\r
6102\r
6103 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6104\r
6105 FLAG_N = NFLAG_16(res);\r
6106 FLAG_Z = res;\r
6107 FLAG_V = VFLAG_CLEAR;\r
6108 FLAG_C = CFLAG_CLEAR;\r
6109}\r
6110\r
6111\r
6112M68KMAKE_OP(move, 16, d, a)\r
6113{\r
6114 uint res = MASK_OUT_ABOVE_16(AY);\r
6115 uint* r_dst = &DX;\r
6116\r
6117 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6118\r
6119 FLAG_N = NFLAG_16(res);\r
6120 FLAG_Z = res;\r
6121 FLAG_V = VFLAG_CLEAR;\r
6122 FLAG_C = CFLAG_CLEAR;\r
6123}\r
6124\r
6125\r
6126M68KMAKE_OP(move, 16, d, .)\r
6127{\r
6128 uint res = M68KMAKE_GET_OPER_AY_16;\r
6129 uint* r_dst = &DX;\r
6130\r
6131 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6132\r
6133 FLAG_N = NFLAG_16(res);\r
6134 FLAG_Z = res;\r
6135 FLAG_V = VFLAG_CLEAR;\r
6136 FLAG_C = CFLAG_CLEAR;\r
6137}\r
6138\r
6139\r
6140M68KMAKE_OP(move, 16, ai, d)\r
6141{\r
6142 uint res = MASK_OUT_ABOVE_16(DY);\r
6143 uint ea = EA_AX_AI_16();\r
6144\r
6145 m68ki_write_16(ea, res);\r
6146\r
6147 FLAG_N = NFLAG_16(res);\r
6148 FLAG_Z = res;\r
6149 FLAG_V = VFLAG_CLEAR;\r
6150 FLAG_C = CFLAG_CLEAR;\r
6151}\r
6152\r
6153\r
6154M68KMAKE_OP(move, 16, ai, a)\r
6155{\r
6156 uint res = MASK_OUT_ABOVE_16(AY);\r
6157 uint ea = EA_AX_AI_16();\r
6158\r
6159 m68ki_write_16(ea, res);\r
6160\r
6161 FLAG_N = NFLAG_16(res);\r
6162 FLAG_Z = res;\r
6163 FLAG_V = VFLAG_CLEAR;\r
6164 FLAG_C = CFLAG_CLEAR;\r
6165}\r
6166\r
6167\r
6168M68KMAKE_OP(move, 16, ai, .)\r
6169{\r
6170 uint res = M68KMAKE_GET_OPER_AY_16;\r
6171 uint ea = EA_AX_AI_16();\r
6172\r
6173 m68ki_write_16(ea, res);\r
6174\r
6175 FLAG_N = NFLAG_16(res);\r
6176 FLAG_Z = res;\r
6177 FLAG_V = VFLAG_CLEAR;\r
6178 FLAG_C = CFLAG_CLEAR;\r
6179}\r
6180\r
6181\r
6182M68KMAKE_OP(move, 16, pi, d)\r
6183{\r
6184 uint res = MASK_OUT_ABOVE_16(DY);\r
6185 uint ea = EA_AX_PI_16();\r
6186\r
6187 m68ki_write_16(ea, res);\r
6188\r
6189 FLAG_N = NFLAG_16(res);\r
6190 FLAG_Z = res;\r
6191 FLAG_V = VFLAG_CLEAR;\r
6192 FLAG_C = CFLAG_CLEAR;\r
6193}\r
6194\r
6195\r
6196M68KMAKE_OP(move, 16, pi, a)\r
6197{\r
6198 uint res = MASK_OUT_ABOVE_16(AY);\r
6199 uint ea = EA_AX_PI_16();\r
6200\r
6201 m68ki_write_16(ea, res);\r
6202\r
6203 FLAG_N = NFLAG_16(res);\r
6204 FLAG_Z = res;\r
6205 FLAG_V = VFLAG_CLEAR;\r
6206 FLAG_C = CFLAG_CLEAR;\r
6207}\r
6208\r
6209\r
6210M68KMAKE_OP(move, 16, pi, .)\r
6211{\r
6212 uint res = M68KMAKE_GET_OPER_AY_16;\r
6213 uint ea = EA_AX_PI_16();\r
6214\r
6215 m68ki_write_16(ea, res);\r
6216\r
6217 FLAG_N = NFLAG_16(res);\r
6218 FLAG_Z = res;\r
6219 FLAG_V = VFLAG_CLEAR;\r
6220 FLAG_C = CFLAG_CLEAR;\r
6221}\r
6222\r
6223\r
6224M68KMAKE_OP(move, 16, pd, d)\r
6225{\r
6226 uint res = MASK_OUT_ABOVE_16(DY);\r
6227 uint ea = EA_AX_PD_16();\r
6228\r
6229 m68ki_write_16(ea, res);\r
6230\r
6231 FLAG_N = NFLAG_16(res);\r
6232 FLAG_Z = res;\r
6233 FLAG_V = VFLAG_CLEAR;\r
6234 FLAG_C = CFLAG_CLEAR;\r
6235}\r
6236\r
6237\r
6238M68KMAKE_OP(move, 16, pd, a)\r
6239{\r
6240 uint res = MASK_OUT_ABOVE_16(AY);\r
6241 uint ea = EA_AX_PD_16();\r
6242\r
6243 m68ki_write_16(ea, res);\r
6244\r
6245 FLAG_N = NFLAG_16(res);\r
6246 FLAG_Z = res;\r
6247 FLAG_V = VFLAG_CLEAR;\r
6248 FLAG_C = CFLAG_CLEAR;\r
6249}\r
6250\r
6251\r
6252M68KMAKE_OP(move, 16, pd, .)\r
6253{\r
6254 uint res = M68KMAKE_GET_OPER_AY_16;\r
6255 uint ea = EA_AX_PD_16();\r
6256\r
6257 m68ki_write_16(ea, res);\r
6258\r
6259 FLAG_N = NFLAG_16(res);\r
6260 FLAG_Z = res;\r
6261 FLAG_V = VFLAG_CLEAR;\r
6262 FLAG_C = CFLAG_CLEAR;\r
6263}\r
6264\r
6265\r
6266M68KMAKE_OP(move, 16, di, d)\r
6267{\r
6268 uint res = MASK_OUT_ABOVE_16(DY);\r
6269 uint ea = EA_AX_DI_16();\r
6270\r
6271 m68ki_write_16(ea, res);\r
6272\r
6273 FLAG_N = NFLAG_16(res);\r
6274 FLAG_Z = res;\r
6275 FLAG_V = VFLAG_CLEAR;\r
6276 FLAG_C = CFLAG_CLEAR;\r
6277}\r
6278\r
6279\r
6280M68KMAKE_OP(move, 16, di, a)\r
6281{\r
6282 uint res = MASK_OUT_ABOVE_16(AY);\r
6283 uint ea = EA_AX_DI_16();\r
6284\r
6285 m68ki_write_16(ea, res);\r
6286\r
6287 FLAG_N = NFLAG_16(res);\r
6288 FLAG_Z = res;\r
6289 FLAG_V = VFLAG_CLEAR;\r
6290 FLAG_C = CFLAG_CLEAR;\r
6291}\r
6292\r
6293\r
6294M68KMAKE_OP(move, 16, di, .)\r
6295{\r
6296 uint res = M68KMAKE_GET_OPER_AY_16;\r
6297 uint ea = EA_AX_DI_16();\r
6298\r
6299 m68ki_write_16(ea, res);\r
6300\r
6301 FLAG_N = NFLAG_16(res);\r
6302 FLAG_Z = res;\r
6303 FLAG_V = VFLAG_CLEAR;\r
6304 FLAG_C = CFLAG_CLEAR;\r
6305}\r
6306\r
6307\r
6308M68KMAKE_OP(move, 16, ix, d)\r
6309{\r
6310 uint res = MASK_OUT_ABOVE_16(DY);\r
6311 uint ea = EA_AX_IX_16();\r
6312\r
6313 m68ki_write_16(ea, res);\r
6314\r
6315 FLAG_N = NFLAG_16(res);\r
6316 FLAG_Z = res;\r
6317 FLAG_V = VFLAG_CLEAR;\r
6318 FLAG_C = CFLAG_CLEAR;\r
6319}\r
6320\r
6321\r
6322M68KMAKE_OP(move, 16, ix, a)\r
6323{\r
6324 uint res = MASK_OUT_ABOVE_16(AY);\r
6325 uint ea = EA_AX_IX_16();\r
6326\r
6327 m68ki_write_16(ea, res);\r
6328\r
6329 FLAG_N = NFLAG_16(res);\r
6330 FLAG_Z = res;\r
6331 FLAG_V = VFLAG_CLEAR;\r
6332 FLAG_C = CFLAG_CLEAR;\r
6333}\r
6334\r
6335\r
6336M68KMAKE_OP(move, 16, ix, .)\r
6337{\r
6338 uint res = M68KMAKE_GET_OPER_AY_16;\r
6339 uint ea = EA_AX_IX_16();\r
6340\r
6341 m68ki_write_16(ea, res);\r
6342\r
6343 FLAG_N = NFLAG_16(res);\r
6344 FLAG_Z = res;\r
6345 FLAG_V = VFLAG_CLEAR;\r
6346 FLAG_C = CFLAG_CLEAR;\r
6347}\r
6348\r
6349\r
6350M68KMAKE_OP(move, 16, aw, d)\r
6351{\r
6352 uint res = MASK_OUT_ABOVE_16(DY);\r
6353 uint ea = EA_AW_16();\r
6354\r
6355 m68ki_write_16(ea, res);\r
6356\r
6357 FLAG_N = NFLAG_16(res);\r
6358 FLAG_Z = res;\r
6359 FLAG_V = VFLAG_CLEAR;\r
6360 FLAG_C = CFLAG_CLEAR;\r
6361}\r
6362\r
6363\r
6364M68KMAKE_OP(move, 16, aw, a)\r
6365{\r
6366 uint res = MASK_OUT_ABOVE_16(AY);\r
6367 uint ea = EA_AW_16();\r
6368\r
6369 m68ki_write_16(ea, res);\r
6370\r
6371 FLAG_N = NFLAG_16(res);\r
6372 FLAG_Z = res;\r
6373 FLAG_V = VFLAG_CLEAR;\r
6374 FLAG_C = CFLAG_CLEAR;\r
6375}\r
6376\r
6377\r
6378M68KMAKE_OP(move, 16, aw, .)\r
6379{\r
6380 uint res = M68KMAKE_GET_OPER_AY_16;\r
6381 uint ea = EA_AW_16();\r
6382\r
6383 m68ki_write_16(ea, res);\r
6384\r
6385 FLAG_N = NFLAG_16(res);\r
6386 FLAG_Z = res;\r
6387 FLAG_V = VFLAG_CLEAR;\r
6388 FLAG_C = CFLAG_CLEAR;\r
6389}\r
6390\r
6391\r
6392M68KMAKE_OP(move, 16, al, d)\r
6393{\r
6394 uint res = MASK_OUT_ABOVE_16(DY);\r
6395 uint ea = EA_AL_16();\r
6396\r
6397 m68ki_write_16(ea, res);\r
6398\r
6399 FLAG_N = NFLAG_16(res);\r
6400 FLAG_Z = res;\r
6401 FLAG_V = VFLAG_CLEAR;\r
6402 FLAG_C = CFLAG_CLEAR;\r
6403}\r
6404\r
6405\r
6406M68KMAKE_OP(move, 16, al, a)\r
6407{\r
6408 uint res = MASK_OUT_ABOVE_16(AY);\r
6409 uint ea = EA_AL_16();\r
6410\r
6411 m68ki_write_16(ea, res);\r
6412\r
6413 FLAG_N = NFLAG_16(res);\r
6414 FLAG_Z = res;\r
6415 FLAG_V = VFLAG_CLEAR;\r
6416 FLAG_C = CFLAG_CLEAR;\r
6417}\r
6418\r
6419\r
6420M68KMAKE_OP(move, 16, al, .)\r
6421{\r
6422 uint res = M68KMAKE_GET_OPER_AY_16;\r
6423 uint ea = EA_AL_16();\r
6424\r
6425 m68ki_write_16(ea, res);\r
6426\r
6427 FLAG_N = NFLAG_16(res);\r
6428 FLAG_Z = res;\r
6429 FLAG_V = VFLAG_CLEAR;\r
6430 FLAG_C = CFLAG_CLEAR;\r
6431}\r
6432\r
6433\r
6434M68KMAKE_OP(move, 32, d, d)\r
6435{\r
6436 uint res = DY;\r
6437 uint* r_dst = &DX;\r
6438\r
6439 *r_dst = res;\r
6440\r
6441 FLAG_N = NFLAG_32(res);\r
6442 FLAG_Z = res;\r
6443 FLAG_V = VFLAG_CLEAR;\r
6444 FLAG_C = CFLAG_CLEAR;\r
6445}\r
6446\r
6447\r
6448M68KMAKE_OP(move, 32, d, a)\r
6449{\r
6450 uint res = AY;\r
6451 uint* r_dst = &DX;\r
6452\r
6453 *r_dst = res;\r
6454\r
6455 FLAG_N = NFLAG_32(res);\r
6456 FLAG_Z = res;\r
6457 FLAG_V = VFLAG_CLEAR;\r
6458 FLAG_C = CFLAG_CLEAR;\r
6459}\r
6460\r
6461\r
6462M68KMAKE_OP(move, 32, d, .)\r
6463{\r
6464 uint res = M68KMAKE_GET_OPER_AY_32;\r
6465 uint* r_dst = &DX;\r
6466\r
6467 *r_dst = res;\r
6468\r
6469 FLAG_N = NFLAG_32(res);\r
6470 FLAG_Z = res;\r
6471 FLAG_V = VFLAG_CLEAR;\r
6472 FLAG_C = CFLAG_CLEAR;\r
6473}\r
6474\r
6475\r
6476M68KMAKE_OP(move, 32, ai, d)\r
6477{\r
6478 uint res = DY;\r
6479 uint ea = EA_AX_AI_32();\r
6480\r
6481 m68ki_write_32(ea, res);\r
6482\r
6483 FLAG_N = NFLAG_32(res);\r
6484 FLAG_Z = res;\r
6485 FLAG_V = VFLAG_CLEAR;\r
6486 FLAG_C = CFLAG_CLEAR;\r
6487}\r
6488\r
6489\r
6490M68KMAKE_OP(move, 32, ai, a)\r
6491{\r
6492 uint res = AY;\r
6493 uint ea = EA_AX_AI_32();\r
6494\r
6495 m68ki_write_32(ea, res);\r
6496\r
6497 FLAG_N = NFLAG_32(res);\r
6498 FLAG_Z = res;\r
6499 FLAG_V = VFLAG_CLEAR;\r
6500 FLAG_C = CFLAG_CLEAR;\r
6501}\r
6502\r
6503\r
6504M68KMAKE_OP(move, 32, ai, .)\r
6505{\r
6506 uint res = M68KMAKE_GET_OPER_AY_32;\r
6507 uint ea = EA_AX_AI_32();\r
6508\r
6509 m68ki_write_32(ea, res);\r
6510\r
6511 FLAG_N = NFLAG_32(res);\r
6512 FLAG_Z = res;\r
6513 FLAG_V = VFLAG_CLEAR;\r
6514 FLAG_C = CFLAG_CLEAR;\r
6515}\r
6516\r
6517\r
6518M68KMAKE_OP(move, 32, pi, d)\r
6519{\r
6520 uint res = DY;\r
6521 uint ea = EA_AX_PI_32();\r
6522\r
6523 m68ki_write_32(ea, res);\r
6524\r
6525 FLAG_N = NFLAG_32(res);\r
6526 FLAG_Z = res;\r
6527 FLAG_V = VFLAG_CLEAR;\r
6528 FLAG_C = CFLAG_CLEAR;\r
6529}\r
6530\r
6531\r
6532M68KMAKE_OP(move, 32, pi, a)\r
6533{\r
6534 uint res = AY;\r
6535 uint ea = EA_AX_PI_32();\r
6536\r
6537 m68ki_write_32(ea, res);\r
6538\r
6539 FLAG_N = NFLAG_32(res);\r
6540 FLAG_Z = res;\r
6541 FLAG_V = VFLAG_CLEAR;\r
6542 FLAG_C = CFLAG_CLEAR;\r
6543}\r
6544\r
6545\r
6546M68KMAKE_OP(move, 32, pi, .)\r
6547{\r
6548 uint res = M68KMAKE_GET_OPER_AY_32;\r
6549 uint ea = EA_AX_PI_32();\r
6550\r
6551 m68ki_write_32(ea, res);\r
6552\r
6553 FLAG_N = NFLAG_32(res);\r
6554 FLAG_Z = res;\r
6555 FLAG_V = VFLAG_CLEAR;\r
6556 FLAG_C = CFLAG_CLEAR;\r
6557}\r
6558\r
6559\r
6560M68KMAKE_OP(move, 32, pd, d)\r
6561{\r
6562 uint res = DY;\r
6563 uint ea = EA_AX_PD_32();\r
6564\r
6565 m68ki_write_16(ea+2, res & 0xFFFF );\r
6566 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
6567\r
6568 FLAG_N = NFLAG_32(res);\r
6569 FLAG_Z = res;\r
6570 FLAG_V = VFLAG_CLEAR;\r
6571 FLAG_C = CFLAG_CLEAR;\r
6572}\r
6573\r
6574\r
6575M68KMAKE_OP(move, 32, pd, a)\r
6576{\r
6577 uint res = AY;\r
6578 uint ea = EA_AX_PD_32();\r
6579\r
6580 m68ki_write_16(ea+2, res & 0xFFFF );\r
6581 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
6582\r
6583 FLAG_N = NFLAG_32(res);\r
6584 FLAG_Z = res;\r
6585 FLAG_V = VFLAG_CLEAR;\r
6586 FLAG_C = CFLAG_CLEAR;\r
6587}\r
6588\r
6589\r
6590M68KMAKE_OP(move, 32, pd, .)\r
6591{\r
6592 uint res = M68KMAKE_GET_OPER_AY_32;\r
6593 uint ea = EA_AX_PD_32();\r
6594\r
6595 m68ki_write_16(ea+2, res & 0xFFFF );\r
6596 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
6597\r
6598 FLAG_N = NFLAG_32(res);\r
6599 FLAG_Z = res;\r
6600 FLAG_V = VFLAG_CLEAR;\r
6601 FLAG_C = CFLAG_CLEAR;\r
6602}\r
6603\r
6604\r
6605M68KMAKE_OP(move, 32, di, d)\r
6606{\r
6607 uint res = DY;\r
6608 uint ea = EA_AX_DI_32();\r
6609\r
6610 m68ki_write_32(ea, res);\r
6611\r
6612 FLAG_N = NFLAG_32(res);\r
6613 FLAG_Z = res;\r
6614 FLAG_V = VFLAG_CLEAR;\r
6615 FLAG_C = CFLAG_CLEAR;\r
6616}\r
6617\r
6618\r
6619M68KMAKE_OP(move, 32, di, a)\r
6620{\r
6621 uint res = AY;\r
6622 uint ea = EA_AX_DI_32();\r
6623\r
6624 m68ki_write_32(ea, res);\r
6625\r
6626 FLAG_N = NFLAG_32(res);\r
6627 FLAG_Z = res;\r
6628 FLAG_V = VFLAG_CLEAR;\r
6629 FLAG_C = CFLAG_CLEAR;\r
6630}\r
6631\r
6632\r
6633M68KMAKE_OP(move, 32, di, .)\r
6634{\r
6635 uint res = M68KMAKE_GET_OPER_AY_32;\r
6636 uint ea = EA_AX_DI_32();\r
6637\r
6638 m68ki_write_32(ea, res);\r
6639\r
6640 FLAG_N = NFLAG_32(res);\r
6641 FLAG_Z = res;\r
6642 FLAG_V = VFLAG_CLEAR;\r
6643 FLAG_C = CFLAG_CLEAR;\r
6644}\r
6645\r
6646\r
6647M68KMAKE_OP(move, 32, ix, d)\r
6648{\r
6649 uint res = DY;\r
6650 uint ea = EA_AX_IX_32();\r
6651\r
6652 m68ki_write_32(ea, res);\r
6653\r
6654 FLAG_N = NFLAG_32(res);\r
6655 FLAG_Z = res;\r
6656 FLAG_V = VFLAG_CLEAR;\r
6657 FLAG_C = CFLAG_CLEAR;\r
6658}\r
6659\r
6660\r
6661M68KMAKE_OP(move, 32, ix, a)\r
6662{\r
6663 uint res = AY;\r
6664 uint ea = EA_AX_IX_32();\r
6665\r
6666 m68ki_write_32(ea, res);\r
6667\r
6668 FLAG_N = NFLAG_32(res);\r
6669 FLAG_Z = res;\r
6670 FLAG_V = VFLAG_CLEAR;\r
6671 FLAG_C = CFLAG_CLEAR;\r
6672}\r
6673\r
6674\r
6675M68KMAKE_OP(move, 32, ix, .)\r
6676{\r
6677 uint res = M68KMAKE_GET_OPER_AY_32;\r
6678 uint ea = EA_AX_IX_32();\r
6679\r
6680 m68ki_write_32(ea, res);\r
6681\r
6682 FLAG_N = NFLAG_32(res);\r
6683 FLAG_Z = res;\r
6684 FLAG_V = VFLAG_CLEAR;\r
6685 FLAG_C = CFLAG_CLEAR;\r
6686}\r
6687\r
6688\r
6689M68KMAKE_OP(move, 32, aw, d)\r
6690{\r
6691 uint res = DY;\r
6692 uint ea = EA_AW_32();\r
6693\r
6694 m68ki_write_32(ea, res);\r
6695\r
6696 FLAG_N = NFLAG_32(res);\r
6697 FLAG_Z = res;\r
6698 FLAG_V = VFLAG_CLEAR;\r
6699 FLAG_C = CFLAG_CLEAR;\r
6700}\r
6701\r
6702\r
6703M68KMAKE_OP(move, 32, aw, a)\r
6704{\r
6705 uint res = AY;\r
6706 uint ea = EA_AW_32();\r
6707\r
6708 m68ki_write_32(ea, res);\r
6709\r
6710 FLAG_N = NFLAG_32(res);\r
6711 FLAG_Z = res;\r
6712 FLAG_V = VFLAG_CLEAR;\r
6713 FLAG_C = CFLAG_CLEAR;\r
6714}\r
6715\r
6716\r
6717M68KMAKE_OP(move, 32, aw, .)\r
6718{\r
6719 uint res = M68KMAKE_GET_OPER_AY_32;\r
6720 uint ea = EA_AW_32();\r
6721\r
6722 m68ki_write_32(ea, res);\r
6723\r
6724 FLAG_N = NFLAG_32(res);\r
6725 FLAG_Z = res;\r
6726 FLAG_V = VFLAG_CLEAR;\r
6727 FLAG_C = CFLAG_CLEAR;\r
6728}\r
6729\r
6730\r
6731M68KMAKE_OP(move, 32, al, d)\r
6732{\r
6733 uint res = DY;\r
6734 uint ea = EA_AL_32();\r
6735\r
6736 m68ki_write_32(ea, res);\r
6737\r
6738 FLAG_N = NFLAG_32(res);\r
6739 FLAG_Z = res;\r
6740 FLAG_V = VFLAG_CLEAR;\r
6741 FLAG_C = CFLAG_CLEAR;\r
6742}\r
6743\r
6744\r
6745M68KMAKE_OP(move, 32, al, a)\r
6746{\r
6747 uint res = AY;\r
6748 uint ea = EA_AL_32();\r
6749\r
6750 m68ki_write_32(ea, res);\r
6751\r
6752 FLAG_N = NFLAG_32(res);\r
6753 FLAG_Z = res;\r
6754 FLAG_V = VFLAG_CLEAR;\r
6755 FLAG_C = CFLAG_CLEAR;\r
6756}\r
6757\r
6758\r
6759M68KMAKE_OP(move, 32, al, .)\r
6760{\r
6761 uint res = M68KMAKE_GET_OPER_AY_32;\r
6762 uint ea = EA_AL_32();\r
6763\r
6764 m68ki_write_32(ea, res);\r
6765\r
6766 FLAG_N = NFLAG_32(res);\r
6767 FLAG_Z = res;\r
6768 FLAG_V = VFLAG_CLEAR;\r
6769 FLAG_C = CFLAG_CLEAR;\r
6770}\r
6771\r
6772\r
6773M68KMAKE_OP(movea, 16, ., d)\r
6774{\r
6775 AX = MAKE_INT_16(DY);\r
6776}\r
6777\r
6778\r
6779M68KMAKE_OP(movea, 16, ., a)\r
6780{\r
6781 AX = MAKE_INT_16(AY);\r
6782}\r
6783\r
6784\r
6785M68KMAKE_OP(movea, 16, ., .)\r
6786{\r
6787 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
6788}\r
6789\r
6790\r
6791M68KMAKE_OP(movea, 32, ., d)\r
6792{\r
6793 AX = DY;\r
6794}\r
6795\r
6796\r
6797M68KMAKE_OP(movea, 32, ., a)\r
6798{\r
6799 AX = AY;\r
6800}\r
6801\r
6802\r
6803M68KMAKE_OP(movea, 32, ., .)\r
6804{\r
6805 AX = M68KMAKE_GET_OPER_AY_32;\r
6806}\r
6807\r
6808\r
6809M68KMAKE_OP(move, 16, frc, d)\r
6810{\r
6811 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6812 {\r
6813 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();\r
6814 return;\r
6815 }\r
6816 m68ki_exception_illegal();\r
6817}\r
6818\r
6819\r
6820M68KMAKE_OP(move, 16, frc, .)\r
6821{\r
6822 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6823 {\r
6824 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());\r
6825 return;\r
6826 }\r
6827 m68ki_exception_illegal();\r
6828}\r
6829\r
6830\r
6831M68KMAKE_OP(move, 16, toc, d)\r
6832{\r
6833 m68ki_set_ccr(DY);\r
6834}\r
6835\r
6836\r
6837M68KMAKE_OP(move, 16, toc, .)\r
6838{\r
6839 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);\r
6840}\r
6841\r
6842\r
6843M68KMAKE_OP(move, 16, frs, d)\r
6844{\r
6845 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6846 {\r
6847 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();\r
6848 return;\r
6849 }\r
6850 m68ki_exception_privilege_violation();\r
6851}\r
6852\r
6853\r
6854M68KMAKE_OP(move, 16, frs, .)\r
6855{\r
6856 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6857 {\r
6858 uint ea = M68KMAKE_GET_EA_AY_16;\r
6859 m68ki_write_16(ea, m68ki_get_sr());\r
6860 return;\r
6861 }\r
6862 m68ki_exception_privilege_violation();\r
6863}\r
6864\r
6865\r
6866M68KMAKE_OP(move, 16, tos, d)\r
6867{\r
6868 if(FLAG_S)\r
6869 {\r
6870 m68ki_set_sr(DY);\r
6871 return;\r
6872 }\r
6873 m68ki_exception_privilege_violation();\r
6874}\r
6875\r
6876\r
6877M68KMAKE_OP(move, 16, tos, .)\r
6878{\r
6879 if(FLAG_S)\r
6880 {\r
6881 uint new_sr = M68KMAKE_GET_OPER_AY_16;\r
6882 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6883 m68ki_set_sr(new_sr);\r
6884 return;\r
6885 }\r
6886 m68ki_exception_privilege_violation();\r
6887}\r
6888\r
6889\r
6890M68KMAKE_OP(move, 32, fru, .)\r
6891{\r
6892 if(FLAG_S)\r
6893 {\r
6894 AY = REG_USP;\r
6895 return;\r
6896 }\r
6897 m68ki_exception_privilege_violation();\r
6898}\r
6899\r
6900\r
6901M68KMAKE_OP(move, 32, tou, .)\r
6902{\r
6903 if(FLAG_S)\r
6904 {\r
6905 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6906 REG_USP = AY;\r
6907 return;\r
6908 }\r
6909 m68ki_exception_privilege_violation();\r
6910}\r
6911\r
6912\r
6913M68KMAKE_OP(movec, 32, cr, .)\r
6914{\r
6915 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6916 {\r
6917 if(FLAG_S)\r
6918 {\r
6919 uint word2 = OPER_I_16();\r
6920\r
6921 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6922 switch (word2 & 0xfff)\r
6923 {\r
6924 case 0x000: /* SFC */\r
6925 REG_DA[(word2 >> 12) & 15] = REG_SFC;\r
6926 return;\r
6927 case 0x001: /* DFC */\r
6928 REG_DA[(word2 >> 12) & 15] = REG_DFC;\r
6929 return;\r
6930 case 0x002: /* CACR */\r
6931 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6932 {\r
6933 REG_DA[(word2 >> 12) & 15] = REG_CACR;\r
6934 return;\r
6935 }\r
6936 return;\r
6937 case 0x800: /* USP */\r
6938 REG_DA[(word2 >> 12) & 15] = REG_USP;\r
6939 return;\r
6940 case 0x801: /* VBR */\r
6941 REG_DA[(word2 >> 12) & 15] = REG_VBR;\r
6942 return;\r
6943 case 0x802: /* CAAR */\r
6944 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6945 {\r
6946 REG_DA[(word2 >> 12) & 15] = REG_CAAR;\r
6947 return;\r
6948 }\r
6949 m68ki_exception_illegal();\r
6950 break;\r
6951 case 0x803: /* MSP */\r
6952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6953 {\r
6954 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;\r
6955 return;\r
6956 }\r
6957 m68ki_exception_illegal();\r
6958 return;\r
6959 case 0x804: /* ISP */\r
6960 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6961 {\r
6962 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;\r
6963 return;\r
6964 }\r
6965 m68ki_exception_illegal();\r
6966 return;\r
6967 case 0x003: /* TC */\r
6968 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6969 {\r
6970 /* TODO */\r
6971 return;\r
6972 }\r
6973 m68ki_exception_illegal();\r
6974 return;\r
6975 case 0x004: /* ITT0 */\r
6976 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6977 {\r
6978 /* TODO */\r
6979 return;\r
6980 }\r
6981 m68ki_exception_illegal();\r
6982 return;\r
6983 case 0x005: /* ITT1 */\r
6984 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6985 {\r
6986 /* TODO */\r
6987 return;\r
6988 }\r
6989 m68ki_exception_illegal();\r
6990 return;\r
6991 case 0x006: /* DTT0 */\r
6992 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6993 {\r
6994 /* TODO */\r
6995 return;\r
6996 }\r
6997 m68ki_exception_illegal();\r
6998 return;\r
6999 case 0x007: /* DTT1 */\r
7000 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7001 {\r
7002 /* TODO */\r
7003 return;\r
7004 }\r
7005 m68ki_exception_illegal();\r
7006 return;\r
7007 case 0x805: /* MMUSR */\r
7008 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7009 {\r
7010 /* TODO */\r
7011 return;\r
7012 }\r
7013 m68ki_exception_illegal();\r
7014 return;\r
7015 case 0x806: /* URP */\r
7016 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7017 {\r
7018 /* TODO */\r
7019 return;\r
7020 }\r
7021 m68ki_exception_illegal();\r
7022 return;\r
7023 case 0x807: /* SRP */\r
7024 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7025 {\r
7026 /* TODO */\r
7027 return;\r
7028 }\r
7029 m68ki_exception_illegal();\r
7030 return;\r
7031 default:\r
7032 m68ki_exception_illegal();\r
7033 return;\r
7034 }\r
7035 }\r
7036 m68ki_exception_privilege_violation();\r
7037 return;\r
7038 }\r
7039 m68ki_exception_illegal();\r
7040}\r
7041\r
7042\r
7043M68KMAKE_OP(movec, 32, rc, .)\r
7044{\r
7045 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7046 {\r
7047 if(FLAG_S)\r
7048 {\r
7049 uint word2 = OPER_I_16();\r
7050\r
7051 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7052 switch (word2 & 0xfff)\r
7053 {\r
7054 case 0x000: /* SFC */\r
7055 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;\r
7056 return;\r
7057 case 0x001: /* DFC */\r
7058 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;\r
7059 return;\r
7060 case 0x002: /* CACR */\r
7061 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7062 {\r
7063 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7064 {\r
7065 REG_CACR = REG_DA[(word2 >> 12) & 15];\r
7066 }\r
7067 else\r
7068 {\r
7069 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */\r
7070 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;\r
7071 }\r
7072 return;\r
7073 }\r
7074 m68ki_exception_illegal();\r
7075 return;\r
7076 case 0x800: /* USP */\r
7077 REG_USP = REG_DA[(word2 >> 12) & 15];\r
7078 return;\r
7079 case 0x801: /* VBR */\r
7080 REG_VBR = REG_DA[(word2 >> 12) & 15];\r
7081 return;\r
7082 case 0x802: /* CAAR */\r
7083 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7084 {\r
7085 REG_CAAR = REG_DA[(word2 >> 12) & 15];\r
7086 return;\r
7087 }\r
7088 m68ki_exception_illegal();\r
7089 return;\r
7090 case 0x803: /* MSP */\r
7091 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7092 {\r
7093 /* we are in supervisor mode so just check for M flag */\r
7094 if(!FLAG_M)\r
7095 {\r
7096 REG_MSP = REG_DA[(word2 >> 12) & 15];\r
7097 return;\r
7098 }\r
7099 REG_SP = REG_DA[(word2 >> 12) & 15];\r
7100 return;\r
7101 }\r
7102 m68ki_exception_illegal();\r
7103 return;\r
7104 case 0x804: /* ISP */\r
7105 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7106 {\r
7107 if(!FLAG_M)\r
7108 {\r
7109 REG_SP = REG_DA[(word2 >> 12) & 15];\r
7110 return;\r
7111 }\r
7112 REG_ISP = REG_DA[(word2 >> 12) & 15];\r
7113 return;\r
7114 }\r
7115 m68ki_exception_illegal();\r
7116 return;\r
7117 case 0x003: /* TC */\r
7118 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7119 {\r
7120 /* TODO */\r
7121 return;\r
7122 }\r
7123 m68ki_exception_illegal();\r
7124 return;\r
7125 case 0x004: /* ITT0 */\r
7126 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7127 {\r
7128 /* TODO */\r
7129 return;\r
7130 }\r
7131 m68ki_exception_illegal();\r
7132 return;\r
7133 case 0x005: /* ITT1 */\r
7134 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7135 {\r
7136 /* TODO */\r
7137 return;\r
7138 }\r
7139 m68ki_exception_illegal();\r
7140 return;\r
7141 case 0x006: /* DTT0 */\r
7142 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7143 {\r
7144 /* TODO */\r
7145 return;\r
7146 }\r
7147 m68ki_exception_illegal();\r
7148 return;\r
7149 case 0x007: /* DTT1 */\r
7150 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7151 {\r
7152 /* TODO */\r
7153 return;\r
7154 }\r
7155 m68ki_exception_illegal();\r
7156 return;\r
7157 case 0x805: /* MMUSR */\r
7158 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7159 {\r
7160 /* TODO */\r
7161 return;\r
7162 }\r
7163 m68ki_exception_illegal();\r
7164 return;\r
7165 case 0x806: /* URP */\r
7166 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7167 {\r
7168 /* TODO */\r
7169 return;\r
7170 }\r
7171 m68ki_exception_illegal();\r
7172 return;\r
7173 case 0x807: /* SRP */\r
7174 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7175 {\r
7176 /* TODO */\r
7177 return;\r
7178 }\r
7179 m68ki_exception_illegal();\r
7180 return;\r
7181 default:\r
7182 m68ki_exception_illegal();\r
7183 return;\r
7184 }\r
7185 }\r
7186 m68ki_exception_privilege_violation();\r
7187 return;\r
7188 }\r
7189 m68ki_exception_illegal();\r
7190}\r
7191\r
7192\r
7193M68KMAKE_OP(movem, 16, re, pd)\r
7194{\r
7195 uint i = 0;\r
7196 uint register_list = OPER_I_16();\r
7197 uint ea = AY;\r
7198 uint count = 0;\r
7199\r
7200 for(; i < 16; i++)\r
7201 if(register_list & (1 << i))\r
7202 {\r
7203 ea -= 2;\r
7204 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));\r
7205 count++;\r
7206 }\r
7207 AY = ea;\r
7208\r
7209 USE_CYCLES(count<<CYC_MOVEM_W);\r
7210}\r
7211\r
7212\r
7213M68KMAKE_OP(movem, 16, re, .)\r
7214{\r
7215 uint i = 0;\r
7216 uint register_list = OPER_I_16();\r
7217 uint ea = M68KMAKE_GET_EA_AY_16;\r
7218 uint count = 0;\r
7219\r
7220 for(; i < 16; i++)\r
7221 if(register_list & (1 << i))\r
7222 {\r
7223 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));\r
7224 ea += 2;\r
7225 count++;\r
7226 }\r
7227\r
7228 USE_CYCLES(count<<CYC_MOVEM_W);\r
7229}\r
7230\r
7231\r
7232M68KMAKE_OP(movem, 32, re, pd)\r
7233{\r
7234 uint i = 0;\r
7235 uint register_list = OPER_I_16();\r
7236 uint ea = AY;\r
7237 uint count = 0;\r
7238\r
7239 for(; i < 16; i++)\r
7240 if(register_list & (1 << i))\r
7241 {\r
7242 ea -= 4;\r
7243#if 0\r
7244 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack\r
7245#else\r
7246 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );\r
7247 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );\r
7248#endif\r
7249 count++;\r
7250 }\r
7251 AY = ea;\r
7252\r
7253 USE_CYCLES(count<<CYC_MOVEM_L);\r
7254}\r
7255\r
7256\r
7257M68KMAKE_OP(movem, 32, re, .)\r
7258{\r
7259 uint i = 0;\r
7260 uint register_list = OPER_I_16();\r
7261 uint ea = M68KMAKE_GET_EA_AY_32;\r
7262 uint count = 0;\r
7263\r
7264 for(; i < 16; i++)\r
7265 if(register_list & (1 << i))\r
7266 {\r
7267 m68ki_write_32(ea, REG_DA[i]);\r
7268 ea += 4;\r
7269 count++;\r
7270 }\r
7271\r
7272 USE_CYCLES(count<<CYC_MOVEM_L);\r
7273}\r
7274\r
7275\r
7276M68KMAKE_OP(movem, 16, er, pi)\r
7277{\r
7278 uint i = 0;\r
7279 uint register_list = OPER_I_16();\r
7280 uint ea = AY;\r
7281 uint count = 0;\r
7282\r
7283 for(; i < 16; i++)\r
7284 if(register_list & (1 << i))\r
7285 {\r
7286 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7287 ea += 2;\r
7288 count++;\r
7289 }\r
7290 AY = ea;\r
7291\r
7292 USE_CYCLES(count<<CYC_MOVEM_W);\r
7293}\r
7294\r
7295\r
7296M68KMAKE_OP(movem, 16, er, pcdi)\r
7297{\r
7298 uint i = 0;\r
7299 uint register_list = OPER_I_16();\r
7300 uint ea = EA_PCDI_16();\r
7301 uint count = 0;\r
7302\r
7303 for(; i < 16; i++)\r
7304 if(register_list & (1 << i))\r
7305 {\r
7306 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7307 ea += 2;\r
7308 count++;\r
7309 }\r
7310\r
7311 USE_CYCLES(count<<CYC_MOVEM_W);\r
7312}\r
7313\r
7314\r
7315M68KMAKE_OP(movem, 16, er, pcix)\r
7316{\r
7317 uint i = 0;\r
7318 uint register_list = OPER_I_16();\r
7319 uint ea = EA_PCIX_16();\r
7320 uint count = 0;\r
7321\r
7322 for(; i < 16; i++)\r
7323 if(register_list & (1 << i))\r
7324 {\r
7325 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7326 ea += 2;\r
7327 count++;\r
7328 }\r
7329\r
7330 USE_CYCLES(count<<CYC_MOVEM_W);\r
7331}\r
7332\r
7333\r
7334M68KMAKE_OP(movem, 16, er, .)\r
7335{\r
7336 uint i = 0;\r
7337 uint register_list = OPER_I_16();\r
7338 uint ea = M68KMAKE_GET_EA_AY_16;\r
7339 uint count = 0;\r
7340\r
7341 for(; i < 16; i++)\r
7342 if(register_list & (1 << i))\r
7343 {\r
7344 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7345 ea += 2;\r
7346 count++;\r
7347 }\r
7348\r
7349 USE_CYCLES(count<<CYC_MOVEM_W);\r
7350}\r
7351\r
7352\r
7353M68KMAKE_OP(movem, 32, er, pi)\r
7354{\r
7355 uint i = 0;\r
7356 uint register_list = OPER_I_16();\r
7357 uint ea = AY;\r
7358 uint count = 0;\r
7359\r
7360 for(; i < 16; i++)\r
7361 if(register_list & (1 << i))\r
7362 {\r
7363 REG_DA[i] = m68ki_read_32(ea);\r
7364 ea += 4;\r
7365 count++;\r
7366 }\r
7367 AY = ea;\r
7368\r
7369 USE_CYCLES(count<<CYC_MOVEM_L);\r
7370}\r
7371\r
7372\r
7373M68KMAKE_OP(movem, 32, er, pcdi)\r
7374{\r
7375 uint i = 0;\r
7376 uint register_list = OPER_I_16();\r
7377 uint ea = EA_PCDI_32();\r
7378 uint count = 0;\r
7379\r
7380 for(; i < 16; i++)\r
7381 if(register_list & (1 << i))\r
7382 {\r
7383 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7384 ea += 4;\r
7385 count++;\r
7386 }\r
7387\r
7388 USE_CYCLES(count<<CYC_MOVEM_L);\r
7389}\r
7390\r
7391\r
7392M68KMAKE_OP(movem, 32, er, pcix)\r
7393{\r
7394 uint i = 0;\r
7395 uint register_list = OPER_I_16();\r
7396 uint ea = EA_PCIX_32();\r
7397 uint count = 0;\r
7398\r
7399 for(; i < 16; i++)\r
7400 if(register_list & (1 << i))\r
7401 {\r
7402 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7403 ea += 4;\r
7404 count++;\r
7405 }\r
7406\r
7407 USE_CYCLES(count<<CYC_MOVEM_L);\r
7408}\r
7409\r
7410\r
7411M68KMAKE_OP(movem, 32, er, .)\r
7412{\r
7413 uint i = 0;\r
7414 uint register_list = OPER_I_16();\r
7415 uint ea = M68KMAKE_GET_EA_AY_32;\r
7416 uint count = 0;\r
7417\r
7418 for(; i < 16; i++)\r
7419 if(register_list & (1 << i))\r
7420 {\r
7421 REG_DA[i] = m68ki_read_32(ea);\r
7422 ea += 4;\r
7423 count++;\r
7424 }\r
7425\r
7426 USE_CYCLES(count<<CYC_MOVEM_L);\r
7427}\r
7428\r
7429\r
7430M68KMAKE_OP(movep, 16, re, .)\r
7431{\r
7432 uint ea = EA_AY_DI_16();\r
7433 uint src = DX;\r
7434\r
7435 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));\r
7436 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7437}\r
7438\r
7439\r
7440M68KMAKE_OP(movep, 32, re, .)\r
7441{\r
7442 uint ea = EA_AY_DI_32();\r
7443 uint src = DX;\r
7444\r
7445 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));\r
7446 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));\r
7447 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));\r
7448 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7449}\r
7450\r
7451\r
7452M68KMAKE_OP(movep, 16, er, .)\r
7453{\r
7454 uint ea = EA_AY_DI_16();\r
7455 uint* r_dst = &DX;\r
7456\r
7457 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));\r
7458}\r
7459\r
7460\r
7461M68KMAKE_OP(movep, 32, er, .)\r
7462{\r
7463 uint ea = EA_AY_DI_32();\r
7464\r
7465 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)\r
7466 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);\r
7467}\r
7468\r
7469\r
7470M68KMAKE_OP(moves, 8, ., .)\r
7471{\r
7472 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7473 {\r
7474 if(FLAG_S)\r
7475 {\r
7476 uint word2 = OPER_I_16();\r
7477 uint ea = M68KMAKE_GET_EA_AY_8;\r
7478\r
7479 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7480 if(BIT_B(word2)) /* Register to memory */\r
7481 {\r
7482 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));\r
7483 return;\r
7484 }\r
7485 if(BIT_F(word2)) /* Memory to address register */\r
7486 {\r
7487 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));\r
7488 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7489 USE_CYCLES(2);\r
7490 return;\r
7491 }\r
7492 /* Memory to data register */\r
7493 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);\r
7494 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7495 USE_CYCLES(2);\r
7496 return;\r
7497 }\r
7498 m68ki_exception_privilege_violation();\r
7499 return;\r
7500 }\r
7501 m68ki_exception_illegal();\r
7502}\r
7503\r
7504\r
7505M68KMAKE_OP(moves, 16, ., .)\r
7506{\r
7507 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7508 {\r
7509 if(FLAG_S)\r
7510 {\r
7511 uint word2 = OPER_I_16();\r
7512 uint ea = M68KMAKE_GET_EA_AY_16;\r
7513\r
7514 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7515 if(BIT_B(word2)) /* Register to memory */\r
7516 {\r
7517 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));\r
7518 return;\r
7519 }\r
7520 if(BIT_F(word2)) /* Memory to address register */\r
7521 {\r
7522 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));\r
7523 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7524 USE_CYCLES(2);\r
7525 return;\r
7526 }\r
7527 /* Memory to data register */\r
7528 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);\r
7529 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7530 USE_CYCLES(2);\r
7531 return;\r
7532 }\r
7533 m68ki_exception_privilege_violation();\r
7534 return;\r
7535 }\r
7536 m68ki_exception_illegal();\r
7537}\r
7538\r
7539\r
7540M68KMAKE_OP(moves, 32, ., .)\r
7541{\r
7542 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7543 {\r
7544 if(FLAG_S)\r
7545 {\r
7546 uint word2 = OPER_I_16();\r
7547 uint ea = M68KMAKE_GET_EA_AY_32;\r
7548\r
7549 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7550 if(BIT_B(word2)) /* Register to memory */\r
7551 {\r
7552 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);\r
7553 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7554 USE_CYCLES(2);\r
7555 return;\r
7556 }\r
7557 /* Memory to register */\r
7558 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);\r
7559 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7560 USE_CYCLES(2);\r
7561 return;\r
7562 }\r
7563 m68ki_exception_privilege_violation();\r
7564 return;\r
7565 }\r
7566 m68ki_exception_illegal();\r
7567}\r
7568\r
7569\r
7570M68KMAKE_OP(moveq, 32, ., .)\r
7571{\r
7572 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));\r
7573\r
7574 FLAG_N = NFLAG_32(res);\r
7575 FLAG_Z = res;\r
7576 FLAG_V = VFLAG_CLEAR;\r
7577 FLAG_C = CFLAG_CLEAR;\r
7578}\r
7579\r
7580\r
7581M68KMAKE_OP(move16, 32, ., .)\r
7582{\r
7583 UINT16 w2 = OPER_I_16();\r
7584 int ax = REG_IR & 7;\r
7585 int ay = (w2 >> 12) & 7;\r
7586\r
7587 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));\r
7588 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));\r
7589 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));\r
7590 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));\r
7591\r
7592 REG_A[ax] += 16;\r
7593 REG_A[ay] += 16;\r
7594}\r
7595\r
7596\r
7597M68KMAKE_OP(muls, 16, ., d)\r
7598{\r
7599 uint* r_dst = &DX;\r
7600 uint x = MAKE_INT_16(DY);\r
7601 uint res = MASK_OUT_ABOVE_32(x * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7602\r
7603 *r_dst = res;\r
7604 USE_CYCLES(m68ki_muls_cycles(x));\r
7605\r
7606 FLAG_Z = res;\r
7607 FLAG_N = NFLAG_32(res);\r
7608 FLAG_V = VFLAG_CLEAR;\r
7609 FLAG_C = CFLAG_CLEAR;\r
7610}\r
7611\r
7612\r
7613M68KMAKE_OP(muls, 16, ., .)\r
7614{\r
7615 uint* r_dst = &DX;\r
7616 uint x = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
7617 uint res = MASK_OUT_ABOVE_32(x * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7618\r
7619 *r_dst = res;\r
7620 USE_CYCLES(m68ki_muls_cycles(x));\r
7621\r
7622 FLAG_Z = res;\r
7623 FLAG_N = NFLAG_32(res);\r
7624 FLAG_V = VFLAG_CLEAR;\r
7625 FLAG_C = CFLAG_CLEAR;\r
7626}\r
7627\r
7628\r
7629M68KMAKE_OP(mulu, 16, ., d)\r
7630{\r
7631 uint* r_dst = &DX;\r
7632 uint x = MASK_OUT_ABOVE_16(DY);\r
7633 uint res = x * MASK_OUT_ABOVE_16(*r_dst);\r
7634\r
7635 *r_dst = res;\r
7636 USE_CYCLES(m68ki_mulu_cycles(x));\r
7637\r
7638 FLAG_Z = res;\r
7639 FLAG_N = NFLAG_32(res);\r
7640 FLAG_V = VFLAG_CLEAR;\r
7641 FLAG_C = CFLAG_CLEAR;\r
7642}\r
7643\r
7644\r
7645M68KMAKE_OP(mulu, 16, ., .)\r
7646{\r
7647 uint* r_dst = &DX;\r
7648 uint x = M68KMAKE_GET_OPER_AY_16;\r
7649 uint res = x * MASK_OUT_ABOVE_16(*r_dst);\r
7650\r
7651 *r_dst = res;\r
7652 USE_CYCLES(m68ki_mulu_cycles(x));\r
7653\r
7654 FLAG_Z = res;\r
7655 FLAG_N = NFLAG_32(res);\r
7656 FLAG_V = VFLAG_CLEAR;\r
7657 FLAG_C = CFLAG_CLEAR;\r
7658}\r
7659\r
7660\r
7661M68KMAKE_OP(mull, 32, ., d)\r
7662{\r
7663#if M68K_USE_64_BIT\r
7664\r
7665 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7666 {\r
7667 uint word2 = OPER_I_16();\r
7668 uint64 src = DY;\r
7669 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7670 uint64 res;\r
7671\r
7672 FLAG_C = CFLAG_CLEAR;\r
7673\r
7674 if(BIT_B(word2)) /* signed */\r
7675 {\r
7676 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7677 if(!BIT_A(word2))\r
7678 {\r
7679 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7680 FLAG_N = NFLAG_32(res);\r
7681 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7682 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7683 return;\r
7684 }\r
7685 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7686 FLAG_N = NFLAG_64(res);\r
7687 FLAG_V = VFLAG_CLEAR;\r
7688 REG_D[word2 & 7] = (res >> 32);\r
7689 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7690 return;\r
7691 }\r
7692\r
7693 res = src * dst;\r
7694 if(!BIT_A(word2))\r
7695 {\r
7696 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7697 FLAG_N = NFLAG_32(res);\r
7698 FLAG_V = (res > 0xffffffff)<<7;\r
7699 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7700 return;\r
7701 }\r
7702 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7703 FLAG_N = NFLAG_64(res);\r
7704 FLAG_V = VFLAG_CLEAR;\r
7705 REG_D[word2 & 7] = (res >> 32);\r
7706 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7707 return;\r
7708 }\r
7709 m68ki_exception_illegal();\r
7710\r
7711#else\r
7712\r
7713 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7714 {\r
7715 uint word2 = OPER_I_16();\r
7716 uint src = DY;\r
7717 uint dst = REG_D[(word2 >> 12) & 7];\r
7718 uint neg = GET_MSB_32(src ^ dst);\r
7719 uint src1;\r
7720 uint src2;\r
7721 uint dst1;\r
7722 uint dst2;\r
7723 uint r1;\r
7724 uint r2;\r
7725 uint r3;\r
7726 uint r4;\r
7727 uint lo;\r
7728 uint hi;\r
7729\r
7730 FLAG_C = CFLAG_CLEAR;\r
7731\r
7732 if(BIT_B(word2)) /* signed */\r
7733 {\r
7734 if(GET_MSB_32(src))\r
7735 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7736 if(GET_MSB_32(dst))\r
7737 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7738 }\r
7739\r
7740 src1 = MASK_OUT_ABOVE_16(src);\r
7741 src2 = src>>16;\r
7742 dst1 = MASK_OUT_ABOVE_16(dst);\r
7743 dst2 = dst>>16;\r
7744\r
7745\r
7746 r1 = src1 * dst1;\r
7747 r2 = src1 * dst2;\r
7748 r3 = src2 * dst1;\r
7749 r4 = src2 * dst2;\r
7750\r
7751 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7752 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7753\r
7754 if(BIT_B(word2) && neg)\r
7755 {\r
7756 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7757 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7758 }\r
7759\r
7760 if(BIT_A(word2))\r
7761 {\r
7762 REG_D[word2 & 7] = hi;\r
7763 REG_D[(word2 >> 12) & 7] = lo;\r
7764 FLAG_N = NFLAG_32(hi);\r
7765 FLAG_Z = hi | lo;\r
7766 FLAG_V = VFLAG_CLEAR;\r
7767 return;\r
7768 }\r
7769\r
7770 REG_D[(word2 >> 12) & 7] = lo;\r
7771 FLAG_N = NFLAG_32(lo);\r
7772 FLAG_Z = lo;\r
7773 if(BIT_B(word2))\r
7774 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7775 else\r
7776 FLAG_V = (hi != 0) << 7;\r
7777 return;\r
7778 }\r
7779 m68ki_exception_illegal();\r
7780\r
7781#endif\r
7782}\r
7783\r
7784\r
7785M68KMAKE_OP(mull, 32, ., .)\r
7786{\r
7787#if M68K_USE_64_BIT\r
7788\r
7789 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7790 {\r
7791 uint word2 = OPER_I_16();\r
7792 uint64 src = M68KMAKE_GET_OPER_AY_32;\r
7793 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7794 uint64 res;\r
7795\r
7796 FLAG_C = CFLAG_CLEAR;\r
7797\r
7798 if(BIT_B(word2)) /* signed */\r
7799 {\r
7800 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7801 if(!BIT_A(word2))\r
7802 {\r
7803 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7804 FLAG_N = NFLAG_32(res);\r
7805 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7806 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7807 return;\r
7808 }\r
7809 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7810 FLAG_N = NFLAG_64(res);\r
7811 FLAG_V = VFLAG_CLEAR;\r
7812 REG_D[word2 & 7] = (res >> 32);\r
7813 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7814 return;\r
7815 }\r
7816\r
7817 res = src * dst;\r
7818 if(!BIT_A(word2))\r
7819 {\r
7820 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7821 FLAG_N = NFLAG_32(res);\r
7822 FLAG_V = (res > 0xffffffff)<<7;\r
7823 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7824 return;\r
7825 }\r
7826 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7827 FLAG_N = NFLAG_64(res);\r
7828 FLAG_V = VFLAG_CLEAR;\r
7829 REG_D[word2 & 7] = (res >> 32);\r
7830 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7831 return;\r
7832 }\r
7833 m68ki_exception_illegal();\r
7834\r
7835#else\r
7836\r
7837 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7838 {\r
7839 uint word2 = OPER_I_16();\r
7840 uint src = M68KMAKE_GET_OPER_AY_32;\r
7841 uint dst = REG_D[(word2 >> 12) & 7];\r
7842 uint neg = GET_MSB_32(src ^ dst);\r
7843 uint src1;\r
7844 uint src2;\r
7845 uint dst1;\r
7846 uint dst2;\r
7847 uint r1;\r
7848 uint r2;\r
7849 uint r3;\r
7850 uint r4;\r
7851 uint lo;\r
7852 uint hi;\r
7853\r
7854 FLAG_C = CFLAG_CLEAR;\r
7855\r
7856 if(BIT_B(word2)) /* signed */\r
7857 {\r
7858 if(GET_MSB_32(src))\r
7859 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7860 if(GET_MSB_32(dst))\r
7861 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7862 }\r
7863\r
7864 src1 = MASK_OUT_ABOVE_16(src);\r
7865 src2 = src>>16;\r
7866 dst1 = MASK_OUT_ABOVE_16(dst);\r
7867 dst2 = dst>>16;\r
7868\r
7869\r
7870 r1 = src1 * dst1;\r
7871 r2 = src1 * dst2;\r
7872 r3 = src2 * dst1;\r
7873 r4 = src2 * dst2;\r
7874\r
7875 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7876 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7877\r
7878 if(BIT_B(word2) && neg)\r
7879 {\r
7880 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7881 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7882 }\r
7883\r
7884 if(BIT_A(word2))\r
7885 {\r
7886 REG_D[word2 & 7] = hi;\r
7887 REG_D[(word2 >> 12) & 7] = lo;\r
7888 FLAG_N = NFLAG_32(hi);\r
7889 FLAG_Z = hi | lo;\r
7890 FLAG_V = VFLAG_CLEAR;\r
7891 return;\r
7892 }\r
7893\r
7894 REG_D[(word2 >> 12) & 7] = lo;\r
7895 FLAG_N = NFLAG_32(lo);\r
7896 FLAG_Z = lo;\r
7897 if(BIT_B(word2))\r
7898 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7899 else\r
7900 FLAG_V = (hi != 0) << 7;\r
7901 return;\r
7902 }\r
7903 m68ki_exception_illegal();\r
7904\r
7905#endif\r
7906}\r
7907\r
7908\r
7909M68KMAKE_OP(nbcd, 8, ., d)\r
7910{\r
7911 uint* r_dst = &DY;\r
7912 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
7913 uint res = -dst - XFLAG_AS_1();\r
7914\r
7915 if(res != 0)\r
7916 {\r
7917 FLAG_V = res; /* Undefined V behavior */\r
7918\r
7919 if(((res|dst) & 0x0f) == 0)\r
7920 res = (res & 0xf0) + 6;\r
7921\r
7922 res = MASK_OUT_ABOVE_8(res + 0x9a);\r
7923\r
7924 FLAG_V &= ~res; /* Undefined V behavior part II */\r
7925\r
7926 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7927\r
7928 FLAG_Z |= res;\r
7929 FLAG_C = CFLAG_SET;\r
7930 FLAG_X = XFLAG_SET;\r
7931 }\r
7932 else\r
7933 {\r
7934 FLAG_V = VFLAG_CLEAR;\r
7935 FLAG_C = CFLAG_CLEAR;\r
7936 FLAG_X = XFLAG_CLEAR;\r
7937 }\r
7938 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7939}\r
7940\r
7941\r
7942M68KMAKE_OP(nbcd, 8, ., .)\r
7943{\r
7944 uint ea = M68KMAKE_GET_EA_AY_8;\r
7945 uint dst = m68ki_read_8(ea);\r
7946 uint res = -dst - XFLAG_AS_1();\r
7947\r
7948 if(res != 0)\r
7949 {\r
7950 FLAG_V = res; /* Undefined V behavior */\r
7951\r
7952 if(((res|dst) & 0x0f) == 0)\r
7953 res = (res & 0xf0) + 6;\r
7954\r
7955 res = MASK_OUT_ABOVE_8(res + 0x9a);\r
7956\r
7957 FLAG_V &= ~res; /* Undefined V behavior part II */\r
7958\r
7959 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));\r
7960\r
7961 FLAG_Z |= res;\r
7962 FLAG_C = CFLAG_SET;\r
7963 FLAG_X = XFLAG_SET;\r
7964 }\r
7965 else\r
7966 {\r
7967 FLAG_V = VFLAG_CLEAR;\r
7968 FLAG_C = CFLAG_CLEAR;\r
7969 FLAG_X = XFLAG_CLEAR;\r
7970 }\r
7971 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7972}\r
7973\r
7974\r
7975M68KMAKE_OP(neg, 8, ., d)\r
7976{\r
7977 uint* r_dst = &DY;\r
7978 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);\r
7979\r
7980 FLAG_N = NFLAG_8(res);\r
7981 FLAG_C = FLAG_X = CFLAG_8(res);\r
7982 FLAG_V = *r_dst & res;\r
7983 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7984\r
7985 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
7986}\r
7987\r
7988\r
7989M68KMAKE_OP(neg, 8, ., .)\r
7990{\r
7991 uint ea = M68KMAKE_GET_EA_AY_8;\r
7992 uint src = m68ki_read_8(ea);\r
7993 uint res = 0 - src;\r
7994\r
7995 FLAG_N = NFLAG_8(res);\r
7996 FLAG_C = FLAG_X = CFLAG_8(res);\r
7997 FLAG_V = src & res;\r
7998 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7999\r
8000 m68ki_write_8(ea, FLAG_Z);\r
8001}\r
8002\r
8003\r
8004M68KMAKE_OP(neg, 16, ., d)\r
8005{\r
8006 uint* r_dst = &DY;\r
8007 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);\r
8008\r
8009 FLAG_N = NFLAG_16(res);\r
8010 FLAG_C = FLAG_X = CFLAG_16(res);\r
8011 FLAG_V = (*r_dst & res)>>8;\r
8012 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
8013\r
8014 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
8015}\r
8016\r
8017\r
8018M68KMAKE_OP(neg, 16, ., .)\r
8019{\r
8020 uint ea = M68KMAKE_GET_EA_AY_16;\r
8021 uint src = m68ki_read_16(ea);\r
8022 uint res = 0 - src;\r
8023\r
8024 FLAG_N = NFLAG_16(res);\r
8025 FLAG_C = FLAG_X = CFLAG_16(res);\r
8026 FLAG_V = (src & res)>>8;\r
8027 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
8028\r
8029 m68ki_write_16(ea, FLAG_Z);\r
8030}\r
8031\r
8032\r
8033M68KMAKE_OP(neg, 32, ., d)\r
8034{\r
8035 uint* r_dst = &DY;\r
8036 uint res = 0 - *r_dst;\r
8037\r
8038 FLAG_N = NFLAG_32(res);\r
8039 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);\r
8040 FLAG_V = (*r_dst & res)>>24;\r
8041 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
8042\r
8043 *r_dst = FLAG_Z;\r
8044}\r
8045\r
8046\r
8047M68KMAKE_OP(neg, 32, ., .)\r
8048{\r
8049 uint ea = M68KMAKE_GET_EA_AY_32;\r
8050 uint src = m68ki_read_32(ea);\r
8051 uint res = 0 - src;\r
8052\r
8053 FLAG_N = NFLAG_32(res);\r
8054 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);\r
8055 FLAG_V = (src & res)>>24;\r
8056 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
8057\r
8058 m68ki_write_32(ea, FLAG_Z);\r
8059}\r
8060\r
8061\r
8062M68KMAKE_OP(negx, 8, ., d)\r
8063{\r
8064 uint* r_dst = &DY;\r
8065 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();\r
8066\r
8067 FLAG_N = NFLAG_8(res);\r
8068 FLAG_X = FLAG_C = CFLAG_8(res);\r
8069 FLAG_V = *r_dst & res;\r
8070\r
8071 res = MASK_OUT_ABOVE_8(res);\r
8072 FLAG_Z |= res;\r
8073\r
8074 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8075}\r
8076\r
8077\r
8078M68KMAKE_OP(negx, 8, ., .)\r
8079{\r
8080 uint ea = M68KMAKE_GET_EA_AY_8;\r
8081 uint src = m68ki_read_8(ea);\r
8082 uint res = 0 - src - XFLAG_AS_1();\r
8083\r
8084 FLAG_N = NFLAG_8(res);\r
8085 FLAG_X = FLAG_C = CFLAG_8(res);\r
8086 FLAG_V = src & res;\r
8087\r
8088 res = MASK_OUT_ABOVE_8(res);\r
8089 FLAG_Z |= res;\r
8090\r
8091 m68ki_write_8(ea, res);\r
8092}\r
8093\r
8094\r
8095M68KMAKE_OP(negx, 16, ., d)\r
8096{\r
8097 uint* r_dst = &DY;\r
8098 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();\r
8099\r
8100 FLAG_N = NFLAG_16(res);\r
8101 FLAG_X = FLAG_C = CFLAG_16(res);\r
8102 FLAG_V = (*r_dst & res)>>8;\r
8103\r
8104 res = MASK_OUT_ABOVE_16(res);\r
8105 FLAG_Z |= res;\r
8106\r
8107 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8108}\r
8109\r
8110\r
8111M68KMAKE_OP(negx, 16, ., .)\r
8112{\r
8113 uint ea = M68KMAKE_GET_EA_AY_16;\r
8114 uint src = m68ki_read_16(ea);\r
8115 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();\r
8116\r
8117 FLAG_N = NFLAG_16(res);\r
8118 FLAG_X = FLAG_C = CFLAG_16(res);\r
8119 FLAG_V = (src & res)>>8;\r
8120\r
8121 res = MASK_OUT_ABOVE_16(res);\r
8122 FLAG_Z |= res;\r
8123\r
8124 m68ki_write_16(ea, res);\r
8125}\r
8126\r
8127\r
8128M68KMAKE_OP(negx, 32, ., d)\r
8129{\r
8130 uint* r_dst = &DY;\r
8131 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();\r
8132\r
8133 FLAG_N = NFLAG_32(res);\r
8134 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);\r
8135 FLAG_V = (*r_dst & res)>>24;\r
8136\r
8137 res = MASK_OUT_ABOVE_32(res);\r
8138 FLAG_Z |= res;\r
8139\r
8140 *r_dst = res;\r
8141}\r
8142\r
8143\r
8144M68KMAKE_OP(negx, 32, ., .)\r
8145{\r
8146 uint ea = M68KMAKE_GET_EA_AY_32;\r
8147 uint src = m68ki_read_32(ea);\r
8148 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();\r
8149\r
8150 FLAG_N = NFLAG_32(res);\r
8151 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);\r
8152 FLAG_V = (src & res)>>24;\r
8153\r
8154 res = MASK_OUT_ABOVE_32(res);\r
8155 FLAG_Z |= res;\r
8156\r
8157 m68ki_write_32(ea, res);\r
8158}\r
8159\r
8160\r
8161M68KMAKE_OP(nop, 0, ., .)\r
8162{\r
8163 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8164}\r
8165\r
8166\r
8167M68KMAKE_OP(not, 8, ., d)\r
8168{\r
8169 uint* r_dst = &DY;\r
8170 uint res = MASK_OUT_ABOVE_8(~*r_dst);\r
8171\r
8172 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8173\r
8174 FLAG_N = NFLAG_8(res);\r
8175 FLAG_Z = res;\r
8176 FLAG_C = CFLAG_CLEAR;\r
8177 FLAG_V = VFLAG_CLEAR;\r
8178}\r
8179\r
8180\r
8181M68KMAKE_OP(not, 8, ., .)\r
8182{\r
8183 uint ea = M68KMAKE_GET_EA_AY_8;\r
8184 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));\r
8185\r
8186 m68ki_write_8(ea, res);\r
8187\r
8188 FLAG_N = NFLAG_8(res);\r
8189 FLAG_Z = res;\r
8190 FLAG_C = CFLAG_CLEAR;\r
8191 FLAG_V = VFLAG_CLEAR;\r
8192}\r
8193\r
8194\r
8195M68KMAKE_OP(not, 16, ., d)\r
8196{\r
8197 uint* r_dst = &DY;\r
8198 uint res = MASK_OUT_ABOVE_16(~*r_dst);\r
8199\r
8200 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8201\r
8202 FLAG_N = NFLAG_16(res);\r
8203 FLAG_Z = res;\r
8204 FLAG_C = CFLAG_CLEAR;\r
8205 FLAG_V = VFLAG_CLEAR;\r
8206}\r
8207\r
8208\r
8209M68KMAKE_OP(not, 16, ., .)\r
8210{\r
8211 uint ea = M68KMAKE_GET_EA_AY_16;\r
8212 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));\r
8213\r
8214 m68ki_write_16(ea, res);\r
8215\r
8216 FLAG_N = NFLAG_16(res);\r
8217 FLAG_Z = res;\r
8218 FLAG_C = CFLAG_CLEAR;\r
8219 FLAG_V = VFLAG_CLEAR;\r
8220}\r
8221\r
8222\r
8223M68KMAKE_OP(not, 32, ., d)\r
8224{\r
8225 uint* r_dst = &DY;\r
8226 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);\r
8227\r
8228 FLAG_N = NFLAG_32(res);\r
8229 FLAG_Z = res;\r
8230 FLAG_C = CFLAG_CLEAR;\r
8231 FLAG_V = VFLAG_CLEAR;\r
8232}\r
8233\r
8234\r
8235M68KMAKE_OP(not, 32, ., .)\r
8236{\r
8237 uint ea = M68KMAKE_GET_EA_AY_32;\r
8238 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));\r
8239\r
8240 m68ki_write_32(ea, res);\r
8241\r
8242 FLAG_N = NFLAG_32(res);\r
8243 FLAG_Z = res;\r
8244 FLAG_C = CFLAG_CLEAR;\r
8245 FLAG_V = VFLAG_CLEAR;\r
8246}\r
8247\r
8248\r
8249M68KMAKE_OP(or, 8, er, d)\r
8250{\r
8251 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));\r
8252\r
8253 FLAG_N = NFLAG_8(res);\r
8254 FLAG_Z = res;\r
8255 FLAG_C = CFLAG_CLEAR;\r
8256 FLAG_V = VFLAG_CLEAR;\r
8257}\r
8258\r
8259\r
8260M68KMAKE_OP(or, 8, er, .)\r
8261{\r
8262 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));\r
8263\r
8264 FLAG_N = NFLAG_8(res);\r
8265 FLAG_Z = res;\r
8266 FLAG_C = CFLAG_CLEAR;\r
8267 FLAG_V = VFLAG_CLEAR;\r
8268}\r
8269\r
8270\r
8271M68KMAKE_OP(or, 16, er, d)\r
8272{\r
8273 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));\r
8274\r
8275 FLAG_N = NFLAG_16(res);\r
8276 FLAG_Z = res;\r
8277 FLAG_C = CFLAG_CLEAR;\r
8278 FLAG_V = VFLAG_CLEAR;\r
8279}\r
8280\r
8281\r
8282M68KMAKE_OP(or, 16, er, .)\r
8283{\r
8284 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));\r
8285\r
8286 FLAG_N = NFLAG_16(res);\r
8287 FLAG_Z = res;\r
8288 FLAG_C = CFLAG_CLEAR;\r
8289 FLAG_V = VFLAG_CLEAR;\r
8290}\r
8291\r
8292\r
8293M68KMAKE_OP(or, 32, er, d)\r
8294{\r
8295 uint res = DX |= DY;\r
8296\r
8297 FLAG_N = NFLAG_32(res);\r
8298 FLAG_Z = res;\r
8299 FLAG_C = CFLAG_CLEAR;\r
8300 FLAG_V = VFLAG_CLEAR;\r
8301}\r
8302\r
8303\r
8304M68KMAKE_OP(or, 32, er, .)\r
8305{\r
8306 uint res = DX |= M68KMAKE_GET_OPER_AY_32;\r
8307\r
8308 FLAG_N = NFLAG_32(res);\r
8309 FLAG_Z = res;\r
8310 FLAG_C = CFLAG_CLEAR;\r
8311 FLAG_V = VFLAG_CLEAR;\r
8312}\r
8313\r
8314\r
8315M68KMAKE_OP(or, 8, re, .)\r
8316{\r
8317 uint ea = M68KMAKE_GET_EA_AY_8;\r
8318 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));\r
8319\r
8320 m68ki_write_8(ea, res);\r
8321\r
8322 FLAG_N = NFLAG_8(res);\r
8323 FLAG_Z = res;\r
8324 FLAG_C = CFLAG_CLEAR;\r
8325 FLAG_V = VFLAG_CLEAR;\r
8326}\r
8327\r
8328\r
8329M68KMAKE_OP(or, 16, re, .)\r
8330{\r
8331 uint ea = M68KMAKE_GET_EA_AY_16;\r
8332 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));\r
8333\r
8334 m68ki_write_16(ea, res);\r
8335\r
8336 FLAG_N = NFLAG_16(res);\r
8337 FLAG_Z = res;\r
8338 FLAG_C = CFLAG_CLEAR;\r
8339 FLAG_V = VFLAG_CLEAR;\r
8340}\r
8341\r
8342\r
8343M68KMAKE_OP(or, 32, re, .)\r
8344{\r
8345 uint ea = M68KMAKE_GET_EA_AY_32;\r
8346 uint res = DX | m68ki_read_32(ea);\r
8347\r
8348 m68ki_write_32(ea, res);\r
8349\r
8350 FLAG_N = NFLAG_32(res);\r
8351 FLAG_Z = res;\r
8352 FLAG_C = CFLAG_CLEAR;\r
8353 FLAG_V = VFLAG_CLEAR;\r
8354}\r
8355\r
8356\r
8357M68KMAKE_OP(ori, 8, ., d)\r
8358{\r
8359 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));\r
8360\r
8361 FLAG_N = NFLAG_8(res);\r
8362 FLAG_Z = res;\r
8363 FLAG_C = CFLAG_CLEAR;\r
8364 FLAG_V = VFLAG_CLEAR;\r
8365}\r
8366\r
8367\r
8368M68KMAKE_OP(ori, 8, ., .)\r
8369{\r
8370 uint src = OPER_I_8();\r
8371 uint ea = M68KMAKE_GET_EA_AY_8;\r
8372 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));\r
8373\r
8374 m68ki_write_8(ea, res);\r
8375\r
8376 FLAG_N = NFLAG_8(res);\r
8377 FLAG_Z = res;\r
8378 FLAG_C = CFLAG_CLEAR;\r
8379 FLAG_V = VFLAG_CLEAR;\r
8380}\r
8381\r
8382\r
8383M68KMAKE_OP(ori, 16, ., d)\r
8384{\r
8385 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());\r
8386\r
8387 FLAG_N = NFLAG_16(res);\r
8388 FLAG_Z = res;\r
8389 FLAG_C = CFLAG_CLEAR;\r
8390 FLAG_V = VFLAG_CLEAR;\r
8391}\r
8392\r
8393\r
8394M68KMAKE_OP(ori, 16, ., .)\r
8395{\r
8396 uint src = OPER_I_16();\r
8397 uint ea = M68KMAKE_GET_EA_AY_16;\r
8398 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));\r
8399\r
8400 m68ki_write_16(ea, res);\r
8401\r
8402 FLAG_N = NFLAG_16(res);\r
8403 FLAG_Z = res;\r
8404 FLAG_C = CFLAG_CLEAR;\r
8405 FLAG_V = VFLAG_CLEAR;\r
8406}\r
8407\r
8408\r
8409M68KMAKE_OP(ori, 32, ., d)\r
8410{\r
8411 uint res = DY |= OPER_I_32();\r
8412\r
8413 FLAG_N = NFLAG_32(res);\r
8414 FLAG_Z = res;\r
8415 FLAG_C = CFLAG_CLEAR;\r
8416 FLAG_V = VFLAG_CLEAR;\r
8417}\r
8418\r
8419\r
8420M68KMAKE_OP(ori, 32, ., .)\r
8421{\r
8422 uint src = OPER_I_32();\r
8423 uint ea = M68KMAKE_GET_EA_AY_32;\r
8424 uint res = src | m68ki_read_32(ea);\r
8425\r
8426 m68ki_write_32(ea, res);\r
8427\r
8428 FLAG_N = NFLAG_32(res);\r
8429 FLAG_Z = res;\r
8430 FLAG_C = CFLAG_CLEAR;\r
8431 FLAG_V = VFLAG_CLEAR;\r
8432}\r
8433\r
8434\r
8435M68KMAKE_OP(ori, 16, toc, .)\r
8436{\r
8437 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());\r
8438}\r
8439\r
8440\r
8441M68KMAKE_OP(ori, 16, tos, .)\r
8442{\r
8443 if(FLAG_S)\r
8444 {\r
8445 uint src = OPER_I_16();\r
8446 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8447 m68ki_set_sr(m68ki_get_sr() | src);\r
8448 return;\r
8449 }\r
8450 m68ki_exception_privilege_violation();\r
8451}\r
8452\r
8453\r
8454M68KMAKE_OP(pack, 16, rr, .)\r
8455{\r
8456 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8457 {\r
8458 /* Note: DX and DY are reversed in Motorola's docs */\r
8459 uint src = DY + OPER_I_16();\r
8460 uint* r_dst = &DX;\r
8461\r
8462 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);\r
8463 return;\r
8464 }\r
8465 m68ki_exception_illegal();\r
8466}\r
8467\r
8468\r
8469M68KMAKE_OP(pack, 16, mm, ax7)\r
8470{\r
8471 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8472 {\r
8473 /* Note: AX and AY are reversed in Motorola's docs */\r
8474 uint ea_src = EA_AY_PD_8();\r
8475 uint src = m68ki_read_8(ea_src);\r
8476 ea_src = EA_AY_PD_8();\r
8477 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8478\r
8479 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8480 return;\r
8481 }\r
8482 m68ki_exception_illegal();\r
8483}\r
8484\r
8485\r
8486M68KMAKE_OP(pack, 16, mm, ay7)\r
8487{\r
8488 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8489 {\r
8490 /* Note: AX and AY are reversed in Motorola's docs */\r
8491 uint ea_src = EA_A7_PD_8();\r
8492 uint src = m68ki_read_8(ea_src);\r
8493 ea_src = EA_A7_PD_8();\r
8494 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8495\r
8496 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8497 return;\r
8498 }\r
8499 m68ki_exception_illegal();\r
8500}\r
8501\r
8502\r
8503M68KMAKE_OP(pack, 16, mm, axy7)\r
8504{\r
8505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8506 {\r
8507 uint ea_src = EA_A7_PD_8();\r
8508 uint src = m68ki_read_8(ea_src);\r
8509 ea_src = EA_A7_PD_8();\r
8510 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8511\r
8512 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8513 return;\r
8514 }\r
8515 m68ki_exception_illegal();\r
8516}\r
8517\r
8518\r
8519M68KMAKE_OP(pack, 16, mm, .)\r
8520{\r
8521 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8522 {\r
8523 /* Note: AX and AY are reversed in Motorola's docs */\r
8524 uint ea_src = EA_AY_PD_8();\r
8525 uint src = m68ki_read_8(ea_src);\r
8526 ea_src = EA_AY_PD_8();\r
8527 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8528\r
8529 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8530 return;\r
8531 }\r
8532 m68ki_exception_illegal();\r
8533}\r
8534\r
8535\r
8536M68KMAKE_OP(pea, 32, ., .)\r
8537{\r
8538 uint ea = M68KMAKE_GET_EA_AY_32;\r
8539\r
8540 m68ki_push_32(ea);\r
8541}\r
8542\r
8543\r
8544M68KMAKE_OP(pflush, 32, ., .)\r
8545{\r
8546 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
8547 {\r
8548 // Nothing to do, unless address translation cache is emulated\r
8549 return;\r
8550 }\r
8551 m68ki_exception_illegal();\r
8552}\r
8553\r
8554\r
8555M68KMAKE_OP(reset, 0, ., .)\r
8556{\r
8557 if(FLAG_S)\r
8558 {\r
8559 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */\r
8560 USE_CYCLES(CYC_RESET);\r
8561 return;\r
8562 }\r
8563 m68ki_exception_privilege_violation();\r
8564}\r
8565\r
8566\r
8567M68KMAKE_OP(ror, 8, s, .)\r
8568{\r
8569 uint* r_dst = &DY;\r
8570 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8571 uint shift = orig_shift & 7;\r
8572 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8573 uint res = ROR_8(src, shift);\r
8574\r
8575 if(orig_shift != 0)\r
8576 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8577\r
8578 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8579\r
8580 FLAG_N = NFLAG_8(res);\r
8581 FLAG_Z = res;\r
8582 FLAG_C = src << (9-orig_shift);\r
8583 FLAG_V = VFLAG_CLEAR;\r
8584}\r
8585\r
8586\r
8587M68KMAKE_OP(ror, 16, s, .)\r
8588{\r
8589 uint* r_dst = &DY;\r
8590 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8591 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8592 uint res = ROR_16(src, shift);\r
8593\r
8594 if(shift != 0)\r
8595 USE_CYCLES(shift<<CYC_SHIFT);\r
8596\r
8597 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8598\r
8599 FLAG_N = NFLAG_16(res);\r
8600 FLAG_Z = res;\r
8601 FLAG_C = src << (9-shift);\r
8602 FLAG_V = VFLAG_CLEAR;\r
8603}\r
8604\r
8605\r
8606M68KMAKE_OP(ror, 32, s, .)\r
8607{\r
8608 uint* r_dst = &DY;\r
8609 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8610 uint64 src = *r_dst;\r
8611 uint res = ROR_32(src, shift);\r
8612\r
8613 if(shift != 0)\r
8614 USE_CYCLES(shift<<CYC_SHIFT);\r
8615\r
8616 *r_dst = res;\r
8617\r
8618 FLAG_N = NFLAG_32(res);\r
8619 FLAG_Z = res;\r
8620 FLAG_C = src << (9-shift);\r
8621 FLAG_V = VFLAG_CLEAR;\r
8622}\r
8623\r
8624\r
8625M68KMAKE_OP(ror, 8, r, .)\r
8626{\r
8627 uint* r_dst = &DY;\r
8628 uint orig_shift = DX & 0x3f;\r
8629 uint shift = orig_shift & 7;\r
8630 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8631 uint res = ROR_8(src, shift);\r
8632\r
8633 if(orig_shift != 0)\r
8634 {\r
8635 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8636\r
8637 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8638 FLAG_C = src << (8-((shift-1)&7));\r
8639 FLAG_N = NFLAG_8(res);\r
8640 FLAG_Z = res;\r
8641 FLAG_V = VFLAG_CLEAR;\r
8642 return;\r
8643 }\r
8644\r
8645 FLAG_C = CFLAG_CLEAR;\r
8646 FLAG_N = NFLAG_8(src);\r
8647 FLAG_Z = src;\r
8648 FLAG_V = VFLAG_CLEAR;\r
8649}\r
8650\r
8651\r
8652M68KMAKE_OP(ror, 16, r, .)\r
8653{\r
8654 uint* r_dst = &DY;\r
8655 uint orig_shift = DX & 0x3f;\r
8656 uint shift = orig_shift & 15;\r
8657 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8658 uint res = ROR_16(src, shift);\r
8659\r
8660 if(orig_shift != 0)\r
8661 {\r
8662 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8663\r
8664 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8665 FLAG_C = (src >> ((shift - 1) & 15)) << 8;\r
8666 FLAG_N = NFLAG_16(res);\r
8667 FLAG_Z = res;\r
8668 FLAG_V = VFLAG_CLEAR;\r
8669 return;\r
8670 }\r
8671\r
8672 FLAG_C = CFLAG_CLEAR;\r
8673 FLAG_N = NFLAG_16(src);\r
8674 FLAG_Z = src;\r
8675 FLAG_V = VFLAG_CLEAR;\r
8676}\r
8677\r
8678\r
8679M68KMAKE_OP(ror, 32, r, .)\r
8680{\r
8681 uint* r_dst = &DY;\r
8682 uint orig_shift = DX & 0x3f;\r
8683 uint shift = orig_shift & 31;\r
8684 uint64 src = *r_dst;\r
8685 uint res = ROR_32(src, shift);\r
8686\r
8687 if(orig_shift != 0)\r
8688 {\r
8689 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8690\r
8691 *r_dst = res;\r
8692 FLAG_C = (src >> ((shift - 1) & 31)) << 8;\r
8693 FLAG_N = NFLAG_32(res);\r
8694 FLAG_Z = res;\r
8695 FLAG_V = VFLAG_CLEAR;\r
8696 return;\r
8697 }\r
8698\r
8699 FLAG_C = CFLAG_CLEAR;\r
8700 FLAG_N = NFLAG_32(src);\r
8701 FLAG_Z = src;\r
8702 FLAG_V = VFLAG_CLEAR;\r
8703}\r
8704\r
8705\r
8706M68KMAKE_OP(ror, 16, ., .)\r
8707{\r
8708 uint ea = M68KMAKE_GET_EA_AY_16;\r
8709 uint src = m68ki_read_16(ea);\r
8710 uint res = ROR_16(src, 1);\r
8711\r
8712 m68ki_write_16(ea, res);\r
8713\r
8714 FLAG_N = NFLAG_16(res);\r
8715 FLAG_Z = res;\r
8716 FLAG_C = src << 8;\r
8717 FLAG_V = VFLAG_CLEAR;\r
8718}\r
8719\r
8720\r
8721M68KMAKE_OP(rol, 8, s, .)\r
8722{\r
8723 uint* r_dst = &DY;\r
8724 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8725 uint shift = orig_shift & 7;\r
8726 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8727 uint res = ROL_8(src, shift);\r
8728\r
8729 if(orig_shift != 0)\r
8730 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8731\r
8732 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8733\r
8734 FLAG_N = NFLAG_8(res);\r
8735 FLAG_Z = res;\r
8736 FLAG_C = src << orig_shift;\r
8737 FLAG_V = VFLAG_CLEAR;\r
8738}\r
8739\r
8740\r
8741M68KMAKE_OP(rol, 16, s, .)\r
8742{\r
8743 uint* r_dst = &DY;\r
8744 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8745 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8746 uint res = ROL_16(src, shift);\r
8747\r
8748 if(shift != 0)\r
8749 USE_CYCLES(shift<<CYC_SHIFT);\r
8750\r
8751 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8752\r
8753 FLAG_N = NFLAG_16(res);\r
8754 FLAG_Z = res;\r
8755 FLAG_C = src >> (8-shift);\r
8756 FLAG_V = VFLAG_CLEAR;\r
8757}\r
8758\r
8759\r
8760M68KMAKE_OP(rol, 32, s, .)\r
8761{\r
8762 uint* r_dst = &DY;\r
8763 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8764 uint64 src = *r_dst;\r
8765 uint res = ROL_32(src, shift);\r
8766\r
8767 if(shift != 0)\r
8768 USE_CYCLES(shift<<CYC_SHIFT);\r
8769\r
8770 *r_dst = res;\r
8771\r
8772 FLAG_N = NFLAG_32(res);\r
8773 FLAG_Z = res;\r
8774 FLAG_C = src >> (24-shift);\r
8775 FLAG_V = VFLAG_CLEAR;\r
8776}\r
8777\r
8778\r
8779M68KMAKE_OP(rol, 8, r, .)\r
8780{\r
8781 uint* r_dst = &DY;\r
8782 uint orig_shift = DX & 0x3f;\r
8783 uint shift = orig_shift & 7;\r
8784 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8785 uint res = ROL_8(src, shift);\r
8786\r
8787 if(orig_shift != 0)\r
8788 {\r
8789 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8790\r
8791 if(shift != 0)\r
8792 {\r
8793 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8794 FLAG_C = src << shift;\r
8795 FLAG_N = NFLAG_8(res);\r
8796 FLAG_Z = res;\r
8797 FLAG_V = VFLAG_CLEAR;\r
8798 return;\r
8799 }\r
8800 FLAG_C = (src & 1)<<8;\r
8801 FLAG_N = NFLAG_8(src);\r
8802 FLAG_Z = src;\r
8803 FLAG_V = VFLAG_CLEAR;\r
8804 return;\r
8805 }\r
8806\r
8807 FLAG_C = CFLAG_CLEAR;\r
8808 FLAG_N = NFLAG_8(src);\r
8809 FLAG_Z = src;\r
8810 FLAG_V = VFLAG_CLEAR;\r
8811}\r
8812\r
8813\r
8814M68KMAKE_OP(rol, 16, r, .)\r
8815{\r
8816 uint* r_dst = &DY;\r
8817 uint orig_shift = DX & 0x3f;\r
8818 uint shift = orig_shift & 15;\r
8819 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8820 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));\r
8821\r
8822 if(orig_shift != 0)\r
8823 {\r
8824 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8825\r
8826 if(shift != 0)\r
8827 {\r
8828 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8829 FLAG_C = (src << shift) >> 8;\r
8830 FLAG_N = NFLAG_16(res);\r
8831 FLAG_Z = res;\r
8832 FLAG_V = VFLAG_CLEAR;\r
8833 return;\r
8834 }\r
8835 FLAG_C = (src & 1)<<8;\r
8836 FLAG_N = NFLAG_16(src);\r
8837 FLAG_Z = src;\r
8838 FLAG_V = VFLAG_CLEAR;\r
8839 return;\r
8840 }\r
8841\r
8842 FLAG_C = CFLAG_CLEAR;\r
8843 FLAG_N = NFLAG_16(src);\r
8844 FLAG_Z = src;\r
8845 FLAG_V = VFLAG_CLEAR;\r
8846}\r
8847\r
8848\r
8849M68KMAKE_OP(rol, 32, r, .)\r
8850{\r
8851 uint* r_dst = &DY;\r
8852 uint orig_shift = DX & 0x3f;\r
8853 uint shift = orig_shift & 31;\r
8854 uint64 src = *r_dst;\r
8855 uint res = ROL_32(src, shift);\r
8856\r
8857 if(orig_shift != 0)\r
8858 {\r
8859 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8860\r
8861 *r_dst = res;\r
8862\r
8863 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;\r
8864 FLAG_N = NFLAG_32(res);\r
8865 FLAG_Z = res;\r
8866 FLAG_V = VFLAG_CLEAR;\r
8867 return;\r
8868 }\r
8869\r
8870 FLAG_C = CFLAG_CLEAR;\r
8871 FLAG_N = NFLAG_32(src);\r
8872 FLAG_Z = src;\r
8873 FLAG_V = VFLAG_CLEAR;\r
8874}\r
8875\r
8876\r
8877M68KMAKE_OP(rol, 16, ., .)\r
8878{\r
8879 uint ea = M68KMAKE_GET_EA_AY_16;\r
8880 uint src = m68ki_read_16(ea);\r
8881 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));\r
8882\r
8883 m68ki_write_16(ea, res);\r
8884\r
8885 FLAG_N = NFLAG_16(res);\r
8886 FLAG_Z = res;\r
8887 FLAG_C = src >> 7;\r
8888 FLAG_V = VFLAG_CLEAR;\r
8889}\r
8890\r
8891\r
8892M68KMAKE_OP(roxr, 8, s, .)\r
8893{\r
8894 uint* r_dst = &DY;\r
8895 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8896 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8897 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8898\r
8899 if(shift != 0)\r
8900 USE_CYCLES(shift<<CYC_SHIFT);\r
8901\r
8902 FLAG_C = FLAG_X = res;\r
8903 res = MASK_OUT_ABOVE_8(res);\r
8904\r
8905 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8906\r
8907 FLAG_N = NFLAG_8(res);\r
8908 FLAG_Z = res;\r
8909 FLAG_V = VFLAG_CLEAR;\r
8910}\r
8911\r
8912\r
8913M68KMAKE_OP(roxr, 16, s, .)\r
8914{\r
8915 uint* r_dst = &DY;\r
8916 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8917 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8918 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8919\r
8920 if(shift != 0)\r
8921 USE_CYCLES(shift<<CYC_SHIFT);\r
8922\r
8923 FLAG_C = FLAG_X = res >> 8;\r
8924 res = MASK_OUT_ABOVE_16(res);\r
8925\r
8926 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8927\r
8928 FLAG_N = NFLAG_16(res);\r
8929 FLAG_Z = res;\r
8930 FLAG_V = VFLAG_CLEAR;\r
8931}\r
8932\r
8933\r
8934M68KMAKE_OP(roxr, 32, s, .)\r
8935{\r
8936#if M68K_USE_64_BIT\r
8937\r
8938 uint* r_dst = &DY;\r
8939 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8940 uint64 src = *r_dst;\r
8941 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8942\r
8943 if(shift != 0)\r
8944 USE_CYCLES(shift<<CYC_SHIFT);\r
8945\r
8946 res = ROR_33_64(res, shift);\r
8947\r
8948 FLAG_C = FLAG_X = res >> 24;\r
8949 res = MASK_OUT_ABOVE_32(res);\r
8950\r
8951 *r_dst = res;\r
8952\r
8953 FLAG_N = NFLAG_32(res);\r
8954 FLAG_Z = res;\r
8955 FLAG_V = VFLAG_CLEAR;\r
8956\r
8957#else\r
8958\r
8959 uint* r_dst = &DY;\r
8960 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8961 uint src = *r_dst;\r
8962 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8963 uint new_x_flag = src & (1 << (shift - 1));\r
8964\r
8965 if(shift != 0)\r
8966 USE_CYCLES(shift<<CYC_SHIFT);\r
8967\r
8968 *r_dst = res;\r
8969\r
8970 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
8971 FLAG_N = NFLAG_32(res);\r
8972 FLAG_Z = res;\r
8973 FLAG_V = VFLAG_CLEAR;\r
8974\r
8975#endif\r
8976}\r
8977\r
8978\r
8979M68KMAKE_OP(roxr, 8, r, .)\r
8980{\r
8981 uint* r_dst = &DY;\r
8982 uint orig_shift = DX & 0x3f;\r
8983\r
8984 if(orig_shift != 0)\r
8985 {\r
8986 uint shift = orig_shift % 9;\r
8987 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8988 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8989\r
8990 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8991\r
8992 FLAG_C = FLAG_X = res;\r
8993 res = MASK_OUT_ABOVE_8(res);\r
8994\r
8995 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8996 FLAG_N = NFLAG_8(res);\r
8997 FLAG_Z = res;\r
8998 FLAG_V = VFLAG_CLEAR;\r
8999 return;\r
9000 }\r
9001\r
9002 FLAG_C = FLAG_X;\r
9003 FLAG_N = NFLAG_8(*r_dst);\r
9004 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
9005 FLAG_V = VFLAG_CLEAR;\r
9006}\r
9007\r
9008\r
9009M68KMAKE_OP(roxr, 16, r, .)\r
9010{\r
9011 uint* r_dst = &DY;\r
9012 uint orig_shift = DX & 0x3f;\r
9013\r
9014 if(orig_shift != 0)\r
9015 {\r
9016 uint shift = orig_shift % 17;\r
9017 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9018 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
9019\r
9020 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9021\r
9022 FLAG_C = FLAG_X = res >> 8;\r
9023 res = MASK_OUT_ABOVE_16(res);\r
9024\r
9025 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9026 FLAG_N = NFLAG_16(res);\r
9027 FLAG_Z = res;\r
9028 FLAG_V = VFLAG_CLEAR;\r
9029 return;\r
9030 }\r
9031\r
9032 FLAG_C = FLAG_X;\r
9033 FLAG_N = NFLAG_16(*r_dst);\r
9034 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
9035 FLAG_V = VFLAG_CLEAR;\r
9036}\r
9037\r
9038\r
9039M68KMAKE_OP(roxr, 32, r, .)\r
9040{\r
9041#if M68K_USE_64_BIT\r
9042\r
9043 uint* r_dst = &DY;\r
9044 uint orig_shift = DX & 0x3f;\r
9045\r
9046 if(orig_shift != 0)\r
9047 {\r
9048 uint shift = orig_shift % 33;\r
9049 uint64 src = *r_dst;\r
9050 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9051\r
9052 res = ROR_33_64(res, shift);\r
9053\r
9054 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9055\r
9056 FLAG_C = FLAG_X = res >> 24;\r
9057 res = MASK_OUT_ABOVE_32(res);\r
9058\r
9059 *r_dst = res;\r
9060 FLAG_N = NFLAG_32(res);\r
9061 FLAG_Z = res;\r
9062 FLAG_V = VFLAG_CLEAR;\r
9063 return;\r
9064 }\r
9065\r
9066 FLAG_C = FLAG_X;\r
9067 FLAG_N = NFLAG_32(*r_dst);\r
9068 FLAG_Z = *r_dst;\r
9069 FLAG_V = VFLAG_CLEAR;\r
9070\r
9071#else\r
9072\r
9073 uint* r_dst = &DY;\r
9074 uint orig_shift = DX & 0x3f;\r
9075 uint shift = orig_shift % 33;\r
9076 uint src = *r_dst;\r
9077 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
9078 uint new_x_flag = src & (1 << (shift - 1));\r
9079\r
9080 if(orig_shift != 0)\r
9081 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9082\r
9083 if(shift != 0)\r
9084 {\r
9085 *r_dst = res;\r
9086 FLAG_X = (new_x_flag != 0)<<8;\r
9087 }\r
9088 else\r
9089 res = src;\r
9090 FLAG_C = FLAG_X;\r
9091 FLAG_N = NFLAG_32(res);\r
9092 FLAG_Z = res;\r
9093 FLAG_V = VFLAG_CLEAR;\r
9094\r
9095#endif\r
9096}\r
9097\r
9098\r
9099M68KMAKE_OP(roxr, 16, ., .)\r
9100{\r
9101 uint ea = M68KMAKE_GET_EA_AY_16;\r
9102 uint src = m68ki_read_16(ea);\r
9103 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);\r
9104\r
9105 FLAG_C = FLAG_X = res >> 8;\r
9106 res = MASK_OUT_ABOVE_16(res);\r
9107\r
9108 m68ki_write_16(ea, res);\r
9109\r
9110 FLAG_N = NFLAG_16(res);\r
9111 FLAG_Z = res;\r
9112 FLAG_V = VFLAG_CLEAR;\r
9113}\r
9114\r
9115\r
9116M68KMAKE_OP(roxl, 8, s, .)\r
9117{\r
9118 uint* r_dst = &DY;\r
9119 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9120 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9121 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9122\r
9123 if(shift != 0)\r
9124 USE_CYCLES(shift<<CYC_SHIFT);\r
9125\r
9126 FLAG_C = FLAG_X = res;\r
9127 res = MASK_OUT_ABOVE_8(res);\r
9128\r
9129 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9130\r
9131 FLAG_N = NFLAG_8(res);\r
9132 FLAG_Z = res;\r
9133 FLAG_V = VFLAG_CLEAR;\r
9134}\r
9135\r
9136\r
9137M68KMAKE_OP(roxl, 16, s, .)\r
9138{\r
9139 uint* r_dst = &DY;\r
9140 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9141 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9142 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9143\r
9144 if(shift != 0)\r
9145 USE_CYCLES(shift<<CYC_SHIFT);\r
9146\r
9147 FLAG_C = FLAG_X = res >> 8;\r
9148 res = MASK_OUT_ABOVE_16(res);\r
9149\r
9150 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9151\r
9152 FLAG_N = NFLAG_16(res);\r
9153 FLAG_Z = res;\r
9154 FLAG_V = VFLAG_CLEAR;\r
9155}\r
9156\r
9157\r
9158M68KMAKE_OP(roxl, 32, s, .)\r
9159{\r
9160#if M68K_USE_64_BIT\r
9161\r
9162 uint* r_dst = &DY;\r
9163 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9164 uint64 src = *r_dst;\r
9165 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9166\r
9167 if(shift != 0)\r
9168 USE_CYCLES(shift<<CYC_SHIFT);\r
9169\r
9170 res = ROL_33_64(res, shift);\r
9171\r
9172 FLAG_C = FLAG_X = res >> 24;\r
9173 res = MASK_OUT_ABOVE_32(res);\r
9174\r
9175 *r_dst = res;\r
9176\r
9177 FLAG_N = NFLAG_32(res);\r
9178 FLAG_Z = res;\r
9179 FLAG_V = VFLAG_CLEAR;\r
9180\r
9181#else\r
9182\r
9183 uint* r_dst = &DY;\r
9184 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9185 uint src = *r_dst;\r
9186 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9187 uint new_x_flag = src & (1 << (32 - shift));\r
9188\r
9189 if(shift != 0)\r
9190 USE_CYCLES(shift<<CYC_SHIFT);\r
9191\r
9192 *r_dst = res;\r
9193\r
9194 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
9195 FLAG_N = NFLAG_32(res);\r
9196 FLAG_Z = res;\r
9197 FLAG_V = VFLAG_CLEAR;\r
9198\r
9199#endif\r
9200}\r
9201\r
9202\r
9203M68KMAKE_OP(roxl, 8, r, .)\r
9204{\r
9205 uint* r_dst = &DY;\r
9206 uint orig_shift = DX & 0x3f;\r
9207\r
9208\r
9209 if(orig_shift != 0)\r
9210 {\r
9211 uint shift = orig_shift % 9;\r
9212 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9213 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9214\r
9215 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9216\r
9217 FLAG_C = FLAG_X = res;\r
9218 res = MASK_OUT_ABOVE_8(res);\r
9219\r
9220 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9221 FLAG_N = NFLAG_8(res);\r
9222 FLAG_Z = res;\r
9223 FLAG_V = VFLAG_CLEAR;\r
9224 return;\r
9225 }\r
9226\r
9227 FLAG_C = FLAG_X;\r
9228 FLAG_N = NFLAG_8(*r_dst);\r
9229 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
9230 FLAG_V = VFLAG_CLEAR;\r
9231}\r
9232\r
9233\r
9234M68KMAKE_OP(roxl, 16, r, .)\r
9235{\r
9236 uint* r_dst = &DY;\r
9237 uint orig_shift = DX & 0x3f;\r
9238\r
9239 if(orig_shift != 0)\r
9240 {\r
9241 uint shift = orig_shift % 17;\r
9242 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9243 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9244\r
9245 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9246\r
9247 FLAG_C = FLAG_X = res >> 8;\r
9248 res = MASK_OUT_ABOVE_16(res);\r
9249\r
9250 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9251 FLAG_N = NFLAG_16(res);\r
9252 FLAG_Z = res;\r
9253 FLAG_V = VFLAG_CLEAR;\r
9254 return;\r
9255 }\r
9256\r
9257 FLAG_C = FLAG_X;\r
9258 FLAG_N = NFLAG_16(*r_dst);\r
9259 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
9260 FLAG_V = VFLAG_CLEAR;\r
9261}\r
9262\r
9263\r
9264M68KMAKE_OP(roxl, 32, r, .)\r
9265{\r
9266#if M68K_USE_64_BIT\r
9267\r
9268 uint* r_dst = &DY;\r
9269 uint orig_shift = DX & 0x3f;\r
9270\r
9271 if(orig_shift != 0)\r
9272 {\r
9273 uint shift = orig_shift % 33;\r
9274 uint64 src = *r_dst;\r
9275 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9276\r
9277 res = ROL_33_64(res, shift);\r
9278\r
9279 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9280\r
9281 FLAG_C = FLAG_X = res >> 24;\r
9282 res = MASK_OUT_ABOVE_32(res);\r
9283\r
9284 *r_dst = res;\r
9285 FLAG_N = NFLAG_32(res);\r
9286 FLAG_Z = res;\r
9287 FLAG_V = VFLAG_CLEAR;\r
9288 return;\r
9289 }\r
9290\r
9291 FLAG_C = FLAG_X;\r
9292 FLAG_N = NFLAG_32(*r_dst);\r
9293 FLAG_Z = *r_dst;\r
9294 FLAG_V = VFLAG_CLEAR;\r
9295\r
9296#else\r
9297\r
9298 uint* r_dst = &DY;\r
9299 uint orig_shift = DX & 0x3f;\r
9300 uint shift = orig_shift % 33;\r
9301 uint src = *r_dst;\r
9302 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9303 uint new_x_flag = src & (1 << (32 - shift));\r
9304\r
9305 if(orig_shift != 0)\r
9306 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9307\r
9308 if(shift != 0)\r
9309 {\r
9310 *r_dst = res;\r
9311 FLAG_X = (new_x_flag != 0)<<8;\r
9312 }\r
9313 else\r
9314 res = src;\r
9315 FLAG_C = FLAG_X;\r
9316 FLAG_N = NFLAG_32(res);\r
9317 FLAG_Z = res;\r
9318 FLAG_V = VFLAG_CLEAR;\r
9319\r
9320#endif\r
9321}\r
9322\r
9323\r
9324M68KMAKE_OP(roxl, 16, ., .)\r
9325{\r
9326 uint ea = M68KMAKE_GET_EA_AY_16;\r
9327 uint src = m68ki_read_16(ea);\r
9328 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);\r
9329\r
9330 FLAG_C = FLAG_X = res >> 8;\r
9331 res = MASK_OUT_ABOVE_16(res);\r
9332\r
9333 m68ki_write_16(ea, res);\r
9334\r
9335 FLAG_N = NFLAG_16(res);\r
9336 FLAG_Z = res;\r
9337 FLAG_V = VFLAG_CLEAR;\r
9338}\r
9339\r
9340\r
9341M68KMAKE_OP(rtd, 32, ., .)\r
9342{\r
9343 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
9344 {\r
9345 uint new_pc = m68ki_pull_32();\r
9346\r
9347 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9348 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
9349 m68ki_jump(new_pc);\r
9350 return;\r
9351 }\r
9352 m68ki_exception_illegal();\r
9353}\r
9354\r
9355\r
9356M68KMAKE_OP(rte, 32, ., .)\r
9357{\r
9358 if(FLAG_S)\r
9359 {\r
9360 uint new_sr;\r
9361 uint new_pc;\r
9362 uint format_word;\r
9363\r
9364 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */\r
9365 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9366\r
9367 if(CPU_TYPE_IS_000(CPU_TYPE))\r
9368 {\r
9369 new_sr = m68ki_pull_16();\r
9370 new_pc = m68ki_pull_32();\r
9371 m68ki_jump(new_pc);\r
9372 m68ki_set_sr(new_sr);\r
9373\r
9374 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9375 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9376\r
9377 return;\r
9378 }\r
9379\r
9380 if(CPU_TYPE_IS_010(CPU_TYPE))\r
9381 {\r
9382 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9383 if(format_word == 0)\r
9384 {\r
9385 new_sr = m68ki_pull_16();\r
9386 new_pc = m68ki_pull_32();\r
9387 m68ki_fake_pull_16(); /* format word */\r
9388 m68ki_jump(new_pc);\r
9389 m68ki_set_sr(new_sr);\r
9390 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9391 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9392 return;\r
9393 }\r
9394 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9395 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9396 /* Not handling bus fault (9) */\r
9397 m68ki_exception_format_error();\r
9398 return;\r
9399 }\r
9400\r
9401 /* Otherwise it's 020 */\r
9402rte_loop:\r
9403 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9404 switch(format_word)\r
9405 {\r
9406 case 0: /* Normal */\r
9407 new_sr = m68ki_pull_16();\r
9408 new_pc = m68ki_pull_32();\r
9409 m68ki_fake_pull_16(); /* format word */\r
9410 m68ki_jump(new_pc);\r
9411 m68ki_set_sr(new_sr);\r
9412 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9413 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9414 return;\r
9415 case 1: /* Throwaway */\r
9416 new_sr = m68ki_pull_16();\r
9417 m68ki_fake_pull_32(); /* program counter */\r
9418 m68ki_fake_pull_16(); /* format word */\r
9419 m68ki_set_sr_noint(new_sr);\r
9420 goto rte_loop;\r
9421 case 2: /* Trap */\r
9422 new_sr = m68ki_pull_16();\r
9423 new_pc = m68ki_pull_32();\r
9424 m68ki_fake_pull_16(); /* format word */\r
9425 m68ki_fake_pull_32(); /* address */\r
9426 m68ki_jump(new_pc);\r
9427 m68ki_set_sr(new_sr);\r
9428 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9429 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9430 return;\r
9431 }\r
9432 /* Not handling long or short bus fault */\r
9433 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9434 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9435 m68ki_exception_format_error();\r
9436 return;\r
9437 }\r
9438 m68ki_exception_privilege_violation();\r
9439}\r
9440\r
9441\r
9442M68KMAKE_OP(rtm, 32, ., .)\r
9443{\r
9444 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
9445 {\r
9446 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9447 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
9448 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
9449 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
9450 return;\r
9451 }\r
9452 m68ki_exception_illegal();\r
9453}\r
9454\r
9455\r
9456M68KMAKE_OP(rtr, 32, ., .)\r
9457{\r
9458 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9459 m68ki_set_ccr(m68ki_pull_16());\r
9460 m68ki_jump(m68ki_pull_32());\r
9461}\r
9462\r
9463\r
9464M68KMAKE_OP(rts, 32, ., .)\r
9465{\r
9466 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9467 m68ki_jump(m68ki_pull_32());\r
9468}\r
9469\r
9470\r
9471M68KMAKE_OP(sbcd, 8, rr, .)\r
9472{\r
9473 uint* r_dst = &DX;\r
9474 uint src = DY;\r
9475 uint dst = *r_dst;\r
9476 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9477 uint corf = 0;\r
9478\r
9479 if(res > 0xf)\r
9480 corf = 6;\r
9481 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9482 FLAG_V = res; /* Undefined V behavior */\r
9483 if(res > 0xff)\r
9484 {\r
9485 res += 0xa0;\r
9486 FLAG_X = FLAG_C = CFLAG_SET;\r
9487 }\r
9488 else if(res < corf)\r
9489 FLAG_X = FLAG_C = CFLAG_SET;\r
9490 else\r
9491 FLAG_X = FLAG_C = 0;\r
9492\r
9493 res = MASK_OUT_ABOVE_8(res - corf);\r
9494\r
9495 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9496 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9497 FLAG_Z |= res;\r
9498\r
9499 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9500}\r
9501\r
9502\r
9503M68KMAKE_OP(sbcd, 8, mm, ax7)\r
9504{\r
9505 uint src = OPER_AY_PD_8();\r
9506 uint ea = EA_A7_PD_8();\r
9507 uint dst = m68ki_read_8(ea);\r
9508 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9509 uint corf = 0;\r
9510\r
9511 if(res > 0xf)\r
9512 corf = 6;\r
9513 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9514 FLAG_V = res; /* Undefined V behavior */\r
9515 if(res > 0xff)\r
9516 {\r
9517 res += 0xa0;\r
9518 FLAG_X = FLAG_C = CFLAG_SET;\r
9519 }\r
9520 else if(res < corf)\r
9521 FLAG_X = FLAG_C = CFLAG_SET;\r
9522 else\r
9523 FLAG_X = FLAG_C = 0;\r
9524\r
9525 res = MASK_OUT_ABOVE_8(res - corf);\r
9526\r
9527 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9528 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9529 FLAG_Z |= res;\r
9530\r
9531 m68ki_write_8(ea, res);\r
9532}\r
9533\r
9534\r
9535M68KMAKE_OP(sbcd, 8, mm, ay7)\r
9536{\r
9537 uint src = OPER_A7_PD_8();\r
9538 uint ea = EA_AX_PD_8();\r
9539 uint dst = m68ki_read_8(ea);\r
9540 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9541 uint corf = 0;\r
9542\r
9543 if(res > 0xf)\r
9544 corf = 6;\r
9545 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9546 FLAG_V = res; /* Undefined V behavior */\r
9547 if(res > 0xff)\r
9548 {\r
9549 res += 0xa0;\r
9550 FLAG_X = FLAG_C = CFLAG_SET;\r
9551 }\r
9552 else if(res < corf)\r
9553 FLAG_X = FLAG_C = CFLAG_SET;\r
9554 else\r
9555 FLAG_X = FLAG_C = 0;\r
9556\r
9557 res = MASK_OUT_ABOVE_8(res - corf);\r
9558\r
9559 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9560 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9561 FLAG_Z |= res;\r
9562\r
9563 m68ki_write_8(ea, res);\r
9564}\r
9565\r
9566\r
9567M68KMAKE_OP(sbcd, 8, mm, axy7)\r
9568{\r
9569 uint src = OPER_A7_PD_8();\r
9570 uint ea = EA_A7_PD_8();\r
9571 uint dst = m68ki_read_8(ea);\r
9572 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9573 uint corf = 0;\r
9574\r
9575 if(res > 0xf)\r
9576 corf = 6;\r
9577 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9578 FLAG_V = res; /* Undefined V behavior */\r
9579 if(res > 0xff)\r
9580 {\r
9581 res += 0xa0;\r
9582 FLAG_X = FLAG_C = CFLAG_SET;\r
9583 }\r
9584 else if(res < corf)\r
9585 FLAG_X = FLAG_C = CFLAG_SET;\r
9586 else\r
9587 FLAG_X = FLAG_C = 0;\r
9588\r
9589 res = MASK_OUT_ABOVE_8(res - corf);\r
9590\r
9591 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9592 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9593 FLAG_Z |= res;\r
9594\r
9595 m68ki_write_8(ea, res);\r
9596}\r
9597\r
9598\r
9599M68KMAKE_OP(sbcd, 8, mm, .)\r
9600{\r
9601 uint src = OPER_AY_PD_8();\r
9602 uint ea = EA_AX_PD_8();\r
9603 uint dst = m68ki_read_8(ea);\r
9604 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9605 uint corf = 0;\r
9606\r
9607 if(res > 0xf)\r
9608 corf = 6;\r
9609 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9610 FLAG_V = res; /* Undefined V behavior */\r
9611 if(res > 0xff)\r
9612 {\r
9613 res += 0xa0;\r
9614 FLAG_X = FLAG_C = CFLAG_SET;\r
9615 }\r
9616 else if(res < corf)\r
9617 FLAG_X = FLAG_C = CFLAG_SET;\r
9618 else\r
9619 FLAG_X = FLAG_C = 0;\r
9620\r
9621 res = MASK_OUT_ABOVE_8(res - corf);\r
9622\r
9623 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9624 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9625 FLAG_Z |= res;\r
9626\r
9627 m68ki_write_8(ea, res);\r
9628}\r
9629\r
9630\r
9631M68KMAKE_OP(st, 8, ., d)\r
9632{\r
9633 DY |= 0xff;\r
9634}\r
9635\r
9636\r
9637M68KMAKE_OP(st, 8, ., .)\r
9638{\r
9639 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);\r
9640}\r
9641\r
9642\r
9643M68KMAKE_OP(sf, 8, ., d)\r
9644{\r
9645 DY &= 0xffffff00;\r
9646}\r
9647\r
9648\r
9649M68KMAKE_OP(sf, 8, ., .)\r
9650{\r
9651 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
9652}\r
9653\r
9654\r
9655M68KMAKE_OP(scc, 8, ., d)\r
9656{\r
9657 if(M68KMAKE_CC)\r
9658 {\r
9659 DY |= 0xff;\r
9660 USE_CYCLES(CYC_SCC_R_TRUE);\r
9661 return;\r
9662 }\r
9663 DY &= 0xffffff00;\r
9664}\r
9665\r
9666\r
9667M68KMAKE_OP(scc, 8, ., .)\r
9668{\r
9669 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);\r
9670}\r
9671\r
9672\r
9673M68KMAKE_OP(stop, 0, ., .)\r
9674{\r
9675 if(FLAG_S)\r
9676 {\r
9677 uint new_sr = OPER_I_16();\r
9678 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9679 CPU_STOPPED |= STOP_LEVEL_STOP;\r
9680 m68ki_set_sr(new_sr);\r
9681 m68ki_remaining_cycles = 0;\r
9682 return;\r
9683 }\r
9684 m68ki_exception_privilege_violation();\r
9685}\r
9686\r
9687\r
9688M68KMAKE_OP(sub, 8, er, d)\r
9689{\r
9690 uint* r_dst = &DX;\r
9691 uint src = MASK_OUT_ABOVE_8(DY);\r
9692 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9693 uint res = dst - src;\r
9694\r
9695 FLAG_N = NFLAG_8(res);\r
9696 FLAG_X = FLAG_C = CFLAG_8(res);\r
9697 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9698 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9699\r
9700 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9701}\r
9702\r
9703\r
9704M68KMAKE_OP(sub, 8, er, .)\r
9705{\r
9706 uint* r_dst = &DX;\r
9707 uint src = M68KMAKE_GET_OPER_AY_8;\r
9708 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9709 uint res = dst - src;\r
9710\r
9711 FLAG_N = NFLAG_8(res);\r
9712 FLAG_X = FLAG_C = CFLAG_8(res);\r
9713 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9714 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9715\r
9716 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9717}\r
9718\r
9719\r
9720M68KMAKE_OP(sub, 16, er, d)\r
9721{\r
9722 uint* r_dst = &DX;\r
9723 uint src = MASK_OUT_ABOVE_16(DY);\r
9724 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9725 uint res = dst - src;\r
9726\r
9727 FLAG_N = NFLAG_16(res);\r
9728 FLAG_X = FLAG_C = CFLAG_16(res);\r
9729 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9730 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9731\r
9732 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9733}\r
9734\r
9735\r
9736M68KMAKE_OP(sub, 16, er, a)\r
9737{\r
9738 uint* r_dst = &DX;\r
9739 uint src = MASK_OUT_ABOVE_16(AY);\r
9740 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9741 uint res = dst - src;\r
9742\r
9743 FLAG_N = NFLAG_16(res);\r
9744 FLAG_X = FLAG_C = CFLAG_16(res);\r
9745 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9746 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9747\r
9748 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9749}\r
9750\r
9751\r
9752M68KMAKE_OP(sub, 16, er, .)\r
9753{\r
9754 uint* r_dst = &DX;\r
9755 uint src = M68KMAKE_GET_OPER_AY_16;\r
9756 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9757 uint res = dst - src;\r
9758\r
9759 FLAG_N = NFLAG_16(res);\r
9760 FLAG_X = FLAG_C = CFLAG_16(res);\r
9761 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9762 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9763\r
9764 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9765}\r
9766\r
9767\r
9768M68KMAKE_OP(sub, 32, er, d)\r
9769{\r
9770 uint* r_dst = &DX;\r
9771 uint src = DY;\r
9772 uint dst = *r_dst;\r
9773 uint res = dst - src;\r
9774\r
9775 FLAG_N = NFLAG_32(res);\r
9776 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9777 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9778 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9779\r
9780 *r_dst = FLAG_Z;\r
9781}\r
9782\r
9783\r
9784M68KMAKE_OP(sub, 32, er, a)\r
9785{\r
9786 uint* r_dst = &DX;\r
9787 uint src = AY;\r
9788 uint dst = *r_dst;\r
9789 uint res = dst - src;\r
9790\r
9791 FLAG_N = NFLAG_32(res);\r
9792 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9793 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9794 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9795\r
9796 *r_dst = FLAG_Z;\r
9797}\r
9798\r
9799\r
9800M68KMAKE_OP(sub, 32, er, .)\r
9801{\r
9802 uint* r_dst = &DX;\r
9803 uint src = M68KMAKE_GET_OPER_AY_32;\r
9804 uint dst = *r_dst;\r
9805 uint res = dst - src;\r
9806\r
9807 FLAG_N = NFLAG_32(res);\r
9808 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9809 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9810 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9811\r
9812 *r_dst = FLAG_Z;\r
9813}\r
9814\r
9815\r
9816M68KMAKE_OP(sub, 8, re, .)\r
9817{\r
9818 uint ea = M68KMAKE_GET_EA_AY_8;\r
9819 uint src = MASK_OUT_ABOVE_8(DX);\r
9820 uint dst = m68ki_read_8(ea);\r
9821 uint res = dst - src;\r
9822\r
9823 FLAG_N = NFLAG_8(res);\r
9824 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9825 FLAG_X = FLAG_C = CFLAG_8(res);\r
9826 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9827\r
9828 m68ki_write_8(ea, FLAG_Z);\r
9829}\r
9830\r
9831\r
9832M68KMAKE_OP(sub, 16, re, .)\r
9833{\r
9834 uint ea = M68KMAKE_GET_EA_AY_16;\r
9835 uint src = MASK_OUT_ABOVE_16(DX);\r
9836 uint dst = m68ki_read_16(ea);\r
9837 uint res = dst - src;\r
9838\r
9839 FLAG_N = NFLAG_16(res);\r
9840 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9841 FLAG_X = FLAG_C = CFLAG_16(res);\r
9842 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9843\r
9844 m68ki_write_16(ea, FLAG_Z);\r
9845}\r
9846\r
9847\r
9848M68KMAKE_OP(sub, 32, re, .)\r
9849{\r
9850 uint ea = M68KMAKE_GET_EA_AY_32;\r
9851 uint src = DX;\r
9852 uint dst = m68ki_read_32(ea);\r
9853 uint res = dst - src;\r
9854\r
9855 FLAG_N = NFLAG_32(res);\r
9856 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9857 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9858 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9859\r
9860 m68ki_write_32(ea, FLAG_Z);\r
9861}\r
9862\r
9863\r
9864M68KMAKE_OP(suba, 16, ., d)\r
9865{\r
9866 uint* r_dst = &AX;\r
9867\r
9868 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));\r
9869}\r
9870\r
9871\r
9872M68KMAKE_OP(suba, 16, ., a)\r
9873{\r
9874 uint* r_dst = &AX;\r
9875\r
9876 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));\r
9877}\r
9878\r
9879\r
9880M68KMAKE_OP(suba, 16, ., .)\r
9881{\r
9882 uint* r_dst = &AX;\r
9883 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
9884\r
9885 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
9886}\r
9887\r
9888\r
9889M68KMAKE_OP(suba, 32, ., d)\r
9890{\r
9891 uint* r_dst = &AX;\r
9892\r
9893 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);\r
9894}\r
9895\r
9896\r
9897M68KMAKE_OP(suba, 32, ., a)\r
9898{\r
9899 uint* r_dst = &AX;\r
9900\r
9901 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);\r
9902}\r
9903\r
9904\r
9905M68KMAKE_OP(suba, 32, ., .)\r
9906{\r
9907 uint* r_dst = &AX;\r
9908 uint src = M68KMAKE_GET_OPER_AY_32; // notaz\r
9909\r
9910 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
9911}\r
9912\r
9913\r
9914M68KMAKE_OP(subi, 8, ., d)\r
9915{\r
9916 uint* r_dst = &DY;\r
9917 uint src = OPER_I_8();\r
9918 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9919 uint res = dst - src;\r
9920\r
9921 FLAG_N = NFLAG_8(res);\r
9922 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9923 FLAG_X = FLAG_C = CFLAG_8(res);\r
9924 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9925\r
9926 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9927}\r
9928\r
9929\r
9930M68KMAKE_OP(subi, 8, ., .)\r
9931{\r
9932 uint src = OPER_I_8();\r
9933 uint ea = M68KMAKE_GET_EA_AY_8;\r
9934 uint dst = m68ki_read_8(ea);\r
9935 uint res = dst - src;\r
9936\r
9937 FLAG_N = NFLAG_8(res);\r
9938 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9939 FLAG_X = FLAG_C = CFLAG_8(res);\r
9940 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9941\r
9942 m68ki_write_8(ea, FLAG_Z);\r
9943}\r
9944\r
9945\r
9946M68KMAKE_OP(subi, 16, ., d)\r
9947{\r
9948 uint* r_dst = &DY;\r
9949 uint src = OPER_I_16();\r
9950 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9951 uint res = dst - src;\r
9952\r
9953 FLAG_N = NFLAG_16(res);\r
9954 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9955 FLAG_X = FLAG_C = CFLAG_16(res);\r
9956 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9957\r
9958 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9959}\r
9960\r
9961\r
9962M68KMAKE_OP(subi, 16, ., .)\r
9963{\r
9964 uint src = OPER_I_16();\r
9965 uint ea = M68KMAKE_GET_EA_AY_16;\r
9966 uint dst = m68ki_read_16(ea);\r
9967 uint res = dst - src;\r
9968\r
9969 FLAG_N = NFLAG_16(res);\r
9970 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9971 FLAG_X = FLAG_C = CFLAG_16(res);\r
9972 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9973\r
9974 m68ki_write_16(ea, FLAG_Z);\r
9975}\r
9976\r
9977\r
9978M68KMAKE_OP(subi, 32, ., d)\r
9979{\r
9980 uint* r_dst = &DY;\r
9981 uint src = OPER_I_32();\r
9982 uint dst = *r_dst;\r
9983 uint res = dst - src;\r
9984\r
9985 FLAG_N = NFLAG_32(res);\r
9986 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9987 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9988 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9989\r
9990 *r_dst = FLAG_Z;\r
9991}\r
9992\r
9993\r
9994M68KMAKE_OP(subi, 32, ., .)\r
9995{\r
9996 uint src = OPER_I_32();\r
9997 uint ea = M68KMAKE_GET_EA_AY_32;\r
9998 uint dst = m68ki_read_32(ea);\r
9999 uint res = dst - src;\r
10000\r
10001 FLAG_N = NFLAG_32(res);\r
10002 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
10003 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10004 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10005\r
10006 m68ki_write_32(ea, FLAG_Z);\r
10007}\r
10008\r
10009\r
10010M68KMAKE_OP(subq, 8, ., d)\r
10011{\r
10012 uint* r_dst = &DY;\r
10013 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10014 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
10015 uint res = dst - src;\r
10016\r
10017 FLAG_N = NFLAG_8(res);\r
10018 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
10019 FLAG_X = FLAG_C = CFLAG_8(res);\r
10020 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10021\r
10022 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
10023}\r
10024\r
10025\r
10026M68KMAKE_OP(subq, 8, ., .)\r
10027{\r
10028 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10029 uint ea = M68KMAKE_GET_EA_AY_8;\r
10030 uint dst = m68ki_read_8(ea);\r
10031 uint res = dst - src;\r
10032\r
10033 FLAG_N = NFLAG_8(res);\r
10034 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
10035 FLAG_X = FLAG_C = CFLAG_8(res);\r
10036 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10037\r
10038 m68ki_write_8(ea, FLAG_Z);\r
10039}\r
10040\r
10041\r
10042M68KMAKE_OP(subq, 16, ., d)\r
10043{\r
10044 uint* r_dst = &DY;\r
10045 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10046 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
10047 uint res = dst - src;\r
10048\r
10049 FLAG_N = NFLAG_16(res);\r
10050 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
10051 FLAG_X = FLAG_C = CFLAG_16(res);\r
10052 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10053\r
10054 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
10055}\r
10056\r
10057\r
10058M68KMAKE_OP(subq, 16, ., a)\r
10059{\r
10060 uint* r_dst = &AY;\r
10061\r
10062 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
10063}\r
10064\r
10065\r
10066M68KMAKE_OP(subq, 16, ., .)\r
10067{\r
10068 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10069 uint ea = M68KMAKE_GET_EA_AY_16;\r
10070 uint dst = m68ki_read_16(ea);\r
10071 uint res = dst - src;\r
10072\r
10073 FLAG_N = NFLAG_16(res);\r
10074 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
10075 FLAG_X = FLAG_C = CFLAG_16(res);\r
10076 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10077\r
10078 m68ki_write_16(ea, FLAG_Z);\r
10079}\r
10080\r
10081\r
10082M68KMAKE_OP(subq, 32, ., d)\r
10083{\r
10084 uint* r_dst = &DY;\r
10085 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10086 uint dst = *r_dst;\r
10087 uint res = dst - src;\r
10088\r
10089 FLAG_N = NFLAG_32(res);\r
10090 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
10091 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10092 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10093\r
10094 *r_dst = FLAG_Z;\r
10095}\r
10096\r
10097\r
10098M68KMAKE_OP(subq, 32, ., a)\r
10099{\r
10100 uint* r_dst = &AY;\r
10101\r
10102 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
10103}\r
10104\r
10105\r
10106M68KMAKE_OP(subq, 32, ., .)\r
10107{\r
10108 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10109 uint ea = M68KMAKE_GET_EA_AY_32;\r
10110 uint dst = m68ki_read_32(ea);\r
10111 uint res = dst - src;\r
10112\r
10113 FLAG_N = NFLAG_32(res);\r
10114 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
10115 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10116 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10117\r
10118 m68ki_write_32(ea, FLAG_Z);\r
10119}\r
10120\r
10121\r
10122M68KMAKE_OP(subx, 8, rr, .)\r
10123{\r
10124 uint* r_dst = &DX;\r
10125 uint src = MASK_OUT_ABOVE_8(DY);\r
10126 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
10127 uint res = dst - src - XFLAG_AS_1();\r
10128\r
10129 FLAG_N = NFLAG_8(res);\r
10130 FLAG_X = FLAG_C = CFLAG_8(res);\r
10131 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10132\r
10133 res = MASK_OUT_ABOVE_8(res);\r
10134 FLAG_Z |= res;\r
10135\r
10136 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
10137}\r
10138\r
10139\r
10140M68KMAKE_OP(subx, 16, rr, .)\r
10141{\r
10142 uint* r_dst = &DX;\r
10143 uint src = MASK_OUT_ABOVE_16(DY);\r
10144 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
10145 uint res = dst - src - XFLAG_AS_1();\r
10146\r
10147 FLAG_N = NFLAG_16(res);\r
10148 FLAG_X = FLAG_C = CFLAG_16(res);\r
10149 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10150\r
10151 res = MASK_OUT_ABOVE_16(res);\r
10152 FLAG_Z |= res;\r
10153\r
10154 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
10155}\r
10156\r
10157\r
10158M68KMAKE_OP(subx, 32, rr, .)\r
10159{\r
10160 uint* r_dst = &DX;\r
10161 uint src = DY;\r
10162 uint dst = *r_dst;\r
10163 uint res = dst - src - XFLAG_AS_1();\r
10164\r
10165 FLAG_N = NFLAG_32(res);\r
10166 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10167 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10168\r
10169 res = MASK_OUT_ABOVE_32(res);\r
10170 FLAG_Z |= res;\r
10171\r
10172 *r_dst = res;\r
10173}\r
10174\r
10175\r
10176M68KMAKE_OP(subx, 8, mm, ax7)\r
10177{\r
10178 uint src = OPER_AY_PD_8();\r
10179 uint ea = EA_A7_PD_8();\r
10180 uint dst = m68ki_read_8(ea);\r
10181 uint res = dst - src - XFLAG_AS_1();\r
10182\r
10183 FLAG_N = NFLAG_8(res);\r
10184 FLAG_X = FLAG_C = CFLAG_8(res);\r
10185 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10186\r
10187 res = MASK_OUT_ABOVE_8(res);\r
10188 FLAG_Z |= res;\r
10189\r
10190 m68ki_write_8(ea, res);\r
10191}\r
10192\r
10193\r
10194M68KMAKE_OP(subx, 8, mm, ay7)\r
10195{\r
10196 uint src = OPER_A7_PD_8();\r
10197 uint ea = EA_AX_PD_8();\r
10198 uint dst = m68ki_read_8(ea);\r
10199 uint res = dst - src - XFLAG_AS_1();\r
10200\r
10201 FLAG_N = NFLAG_8(res);\r
10202 FLAG_X = FLAG_C = CFLAG_8(res);\r
10203 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10204\r
10205 res = MASK_OUT_ABOVE_8(res);\r
10206 FLAG_Z |= res;\r
10207\r
10208 m68ki_write_8(ea, res);\r
10209}\r
10210\r
10211\r
10212M68KMAKE_OP(subx, 8, mm, axy7)\r
10213{\r
10214 uint src = OPER_A7_PD_8();\r
10215 uint ea = EA_A7_PD_8();\r
10216 uint dst = m68ki_read_8(ea);\r
10217 uint res = dst - src - XFLAG_AS_1();\r
10218\r
10219 FLAG_N = NFLAG_8(res);\r
10220 FLAG_X = FLAG_C = CFLAG_8(res);\r
10221 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10222\r
10223 res = MASK_OUT_ABOVE_8(res);\r
10224 FLAG_Z |= res;\r
10225\r
10226 m68ki_write_8(ea, res);\r
10227}\r
10228\r
10229\r
10230M68KMAKE_OP(subx, 8, mm, .)\r
10231{\r
10232 uint src = OPER_AY_PD_8();\r
10233 uint ea = EA_AX_PD_8();\r
10234 uint dst = m68ki_read_8(ea);\r
10235 uint res = dst - src - XFLAG_AS_1();\r
10236\r
10237 FLAG_N = NFLAG_8(res);\r
10238 FLAG_X = FLAG_C = CFLAG_8(res);\r
10239 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10240\r
10241 res = MASK_OUT_ABOVE_8(res);\r
10242 FLAG_Z |= res;\r
10243\r
10244 m68ki_write_8(ea, res);\r
10245}\r
10246\r
10247\r
10248M68KMAKE_OP(subx, 16, mm, .)\r
10249{\r
10250 uint src = OPER_AY_PD_16();\r
10251 uint ea = EA_AX_PD_16();\r
10252 uint dst = m68ki_read_16(ea);\r
10253 uint res = dst - src - XFLAG_AS_1();\r
10254\r
10255 FLAG_N = NFLAG_16(res);\r
10256 FLAG_X = FLAG_C = CFLAG_16(res);\r
10257 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10258\r
10259 res = MASK_OUT_ABOVE_16(res);\r
10260 FLAG_Z |= res;\r
10261\r
10262 m68ki_write_16(ea, res);\r
10263}\r
10264\r
10265\r
10266M68KMAKE_OP(subx, 32, mm, .)\r
10267{\r
10268 uint src = OPER_AY_PD_32();\r
10269 uint ea = EA_AX_PD_32();\r
10270 uint dst = m68ki_read_32(ea);\r
10271 uint res = dst - src - XFLAG_AS_1();\r
10272\r
10273 FLAG_N = NFLAG_32(res);\r
10274 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10275 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10276\r
10277 res = MASK_OUT_ABOVE_32(res);\r
10278 FLAG_Z |= res;\r
10279\r
10280 m68ki_write_32(ea, res);\r
10281}\r
10282\r
10283\r
10284M68KMAKE_OP(swap, 32, ., .)\r
10285{\r
10286 uint* r_dst = &DY;\r
10287\r
10288 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);\r
10289 *r_dst = (*r_dst>>16) | FLAG_Z;\r
10290\r
10291 FLAG_Z = *r_dst;\r
10292 FLAG_N = NFLAG_32(*r_dst);\r
10293 FLAG_C = CFLAG_CLEAR;\r
10294 FLAG_V = VFLAG_CLEAR;\r
10295}\r
10296\r
10297\r
10298M68KMAKE_OP(tas, 8, ., d)\r
10299{\r
10300 uint* r_dst = &DY;\r
10301\r
10302 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
10303 FLAG_N = NFLAG_8(*r_dst);\r
10304 FLAG_V = VFLAG_CLEAR;\r
10305 FLAG_C = CFLAG_CLEAR;\r
10306 *r_dst |= 0x80;\r
10307}\r
10308\r
10309\r
10310M68KMAKE_OP(tas, 8, ., .)\r
10311{\r
10312 uint ea = M68KMAKE_GET_EA_AY_8;\r
10313 uint dst = m68ki_read_8(ea);\r
10314 uint allow_writeback;\r
10315\r
10316 FLAG_Z = dst;\r
10317 FLAG_N = NFLAG_8(dst);\r
10318 FLAG_V = VFLAG_CLEAR;\r
10319 FLAG_C = CFLAG_CLEAR;\r
10320\r
10321 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback\r
10322 disabled in order to function properly. Some Amiga software may also rely\r
10323 on this, but only when accessing specific addresses so additional functionality\r
10324 will be needed. */\r
10325 allow_writeback = m68ki_tas_callback();\r
10326\r
10327 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);\r
10328}\r
10329\r
10330\r
10331M68KMAKE_OP(trap, 0, ., .)\r
10332{\r
10333 /* Trap#n stacks exception frame type 0 */\r
10334 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */\r
10335}\r
10336\r
10337\r
10338M68KMAKE_OP(trapt, 0, ., .)\r
10339{\r
10340 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10341 {\r
10342 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10343 return;\r
10344 }\r
10345 m68ki_exception_illegal();\r
10346}\r
10347\r
10348\r
10349M68KMAKE_OP(trapt, 16, ., .)\r
10350{\r
10351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10352 {\r
10353 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10354 return;\r
10355 }\r
10356 m68ki_exception_illegal();\r
10357}\r
10358\r
10359\r
10360M68KMAKE_OP(trapt, 32, ., .)\r
10361{\r
10362 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10363 {\r
10364 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10365 return;\r
10366 }\r
10367 m68ki_exception_illegal();\r
10368}\r
10369\r
10370\r
10371M68KMAKE_OP(trapf, 0, ., .)\r
10372{\r
10373 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10374 {\r
10375 return;\r
10376 }\r
10377 m68ki_exception_illegal();\r
10378}\r
10379\r
10380\r
10381M68KMAKE_OP(trapf, 16, ., .)\r
10382{\r
10383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10384 {\r
10385 REG_PC += 2;\r
10386 return;\r
10387 }\r
10388 m68ki_exception_illegal();\r
10389}\r
10390\r
10391\r
10392M68KMAKE_OP(trapf, 32, ., .)\r
10393{\r
10394 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10395 {\r
10396 REG_PC += 4;\r
10397 return;\r
10398 }\r
10399 m68ki_exception_illegal();\r
10400}\r
10401\r
10402\r
10403M68KMAKE_OP(trapcc, 0, ., .)\r
10404{\r
10405 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10406 {\r
10407 if(M68KMAKE_CC)\r
10408 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10409 return;\r
10410 }\r
10411 m68ki_exception_illegal();\r
10412}\r
10413\r
10414\r
10415M68KMAKE_OP(trapcc, 16, ., .)\r
10416{\r
10417 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10418 {\r
10419 if(M68KMAKE_CC)\r
10420 {\r
10421 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10422 return;\r
10423 }\r
10424 REG_PC += 2;\r
10425 return;\r
10426 }\r
10427 m68ki_exception_illegal();\r
10428}\r
10429\r
10430\r
10431M68KMAKE_OP(trapcc, 32, ., .)\r
10432{\r
10433 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10434 {\r
10435 if(M68KMAKE_CC)\r
10436 {\r
10437 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10438 return;\r
10439 }\r
10440 REG_PC += 4;\r
10441 return;\r
10442 }\r
10443 m68ki_exception_illegal();\r
10444}\r
10445\r
10446\r
10447M68KMAKE_OP(trapv, 0, ., .)\r
10448{\r
10449 if(COND_VC())\r
10450 {\r
10451 return;\r
10452 }\r
10453 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10454}\r
10455\r
10456\r
10457M68KMAKE_OP(tst, 8, ., d)\r
10458{\r
10459 uint res = MASK_OUT_ABOVE_8(DY);\r
10460\r
10461 FLAG_N = NFLAG_8(res);\r
10462 FLAG_Z = res;\r
10463 FLAG_V = VFLAG_CLEAR;\r
10464 FLAG_C = CFLAG_CLEAR;\r
10465}\r
10466\r
10467\r
10468M68KMAKE_OP(tst, 8, ., .)\r
10469{\r
10470 uint res = M68KMAKE_GET_OPER_AY_8;\r
10471\r
10472 FLAG_N = NFLAG_8(res);\r
10473 FLAG_Z = res;\r
10474 FLAG_V = VFLAG_CLEAR;\r
10475 FLAG_C = CFLAG_CLEAR;\r
10476}\r
10477\r
10478\r
10479M68KMAKE_OP(tst, 8, ., pcdi)\r
10480{\r
10481 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10482 {\r
10483 uint res = OPER_PCDI_8();\r
10484\r
10485 FLAG_N = NFLAG_8(res);\r
10486 FLAG_Z = res;\r
10487 FLAG_V = VFLAG_CLEAR;\r
10488 FLAG_C = CFLAG_CLEAR;\r
10489 return;\r
10490 }\r
10491 m68ki_exception_illegal();\r
10492}\r
10493\r
10494\r
10495M68KMAKE_OP(tst, 8, ., pcix)\r
10496{\r
10497 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10498 {\r
10499 uint res = OPER_PCIX_8();\r
10500\r
10501 FLAG_N = NFLAG_8(res);\r
10502 FLAG_Z = res;\r
10503 FLAG_V = VFLAG_CLEAR;\r
10504 FLAG_C = CFLAG_CLEAR;\r
10505 return;\r
10506 }\r
10507 m68ki_exception_illegal();\r
10508}\r
10509\r
10510\r
10511M68KMAKE_OP(tst, 8, ., i)\r
10512{\r
10513 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10514 {\r
10515 uint res = OPER_I_8();\r
10516\r
10517 FLAG_N = NFLAG_8(res);\r
10518 FLAG_Z = res;\r
10519 FLAG_V = VFLAG_CLEAR;\r
10520 FLAG_C = CFLAG_CLEAR;\r
10521 return;\r
10522 }\r
10523 m68ki_exception_illegal();\r
10524}\r
10525\r
10526\r
10527M68KMAKE_OP(tst, 16, ., d)\r
10528{\r
10529 uint res = MASK_OUT_ABOVE_16(DY);\r
10530\r
10531 FLAG_N = NFLAG_16(res);\r
10532 FLAG_Z = res;\r
10533 FLAG_V = VFLAG_CLEAR;\r
10534 FLAG_C = CFLAG_CLEAR;\r
10535}\r
10536\r
10537\r
10538M68KMAKE_OP(tst, 16, ., a)\r
10539{\r
10540 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10541 {\r
10542 uint res = MAKE_INT_16(AY);\r
10543\r
10544 FLAG_N = NFLAG_16(res);\r
10545 FLAG_Z = res;\r
10546 FLAG_V = VFLAG_CLEAR;\r
10547 FLAG_C = CFLAG_CLEAR;\r
10548 return;\r
10549 }\r
10550 m68ki_exception_illegal();\r
10551}\r
10552\r
10553\r
10554M68KMAKE_OP(tst, 16, ., .)\r
10555{\r
10556 uint res = M68KMAKE_GET_OPER_AY_16;\r
10557\r
10558 FLAG_N = NFLAG_16(res);\r
10559 FLAG_Z = res;\r
10560 FLAG_V = VFLAG_CLEAR;\r
10561 FLAG_C = CFLAG_CLEAR;\r
10562}\r
10563\r
10564\r
10565M68KMAKE_OP(tst, 16, ., pcdi)\r
10566{\r
10567 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10568 {\r
10569 uint res = OPER_PCDI_16();\r
10570\r
10571 FLAG_N = NFLAG_16(res);\r
10572 FLAG_Z = res;\r
10573 FLAG_V = VFLAG_CLEAR;\r
10574 FLAG_C = CFLAG_CLEAR;\r
10575 return;\r
10576 }\r
10577 m68ki_exception_illegal();\r
10578}\r
10579\r
10580\r
10581M68KMAKE_OP(tst, 16, ., pcix)\r
10582{\r
10583 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10584 {\r
10585 uint res = OPER_PCIX_16();\r
10586\r
10587 FLAG_N = NFLAG_16(res);\r
10588 FLAG_Z = res;\r
10589 FLAG_V = VFLAG_CLEAR;\r
10590 FLAG_C = CFLAG_CLEAR;\r
10591 return;\r
10592 }\r
10593 m68ki_exception_illegal();\r
10594}\r
10595\r
10596\r
10597M68KMAKE_OP(tst, 16, ., i)\r
10598{\r
10599 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10600 {\r
10601 uint res = OPER_I_16();\r
10602\r
10603 FLAG_N = NFLAG_16(res);\r
10604 FLAG_Z = res;\r
10605 FLAG_V = VFLAG_CLEAR;\r
10606 FLAG_C = CFLAG_CLEAR;\r
10607 return;\r
10608 }\r
10609 m68ki_exception_illegal();\r
10610}\r
10611\r
10612\r
10613M68KMAKE_OP(tst, 32, ., d)\r
10614{\r
10615 uint res = DY;\r
10616\r
10617 FLAG_N = NFLAG_32(res);\r
10618 FLAG_Z = res;\r
10619 FLAG_V = VFLAG_CLEAR;\r
10620 FLAG_C = CFLAG_CLEAR;\r
10621}\r
10622\r
10623\r
10624M68KMAKE_OP(tst, 32, ., a)\r
10625{\r
10626 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10627 {\r
10628 uint res = AY;\r
10629\r
10630 FLAG_N = NFLAG_32(res);\r
10631 FLAG_Z = res;\r
10632 FLAG_V = VFLAG_CLEAR;\r
10633 FLAG_C = CFLAG_CLEAR;\r
10634 return;\r
10635 }\r
10636 m68ki_exception_illegal();\r
10637}\r
10638\r
10639\r
10640M68KMAKE_OP(tst, 32, ., .)\r
10641{\r
10642 uint res = M68KMAKE_GET_OPER_AY_32;\r
10643\r
10644 FLAG_N = NFLAG_32(res);\r
10645 FLAG_Z = res;\r
10646 FLAG_V = VFLAG_CLEAR;\r
10647 FLAG_C = CFLAG_CLEAR;\r
10648}\r
10649\r
10650\r
10651M68KMAKE_OP(tst, 32, ., pcdi)\r
10652{\r
10653 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10654 {\r
10655 uint res = OPER_PCDI_32();\r
10656\r
10657 FLAG_N = NFLAG_32(res);\r
10658 FLAG_Z = res;\r
10659 FLAG_V = VFLAG_CLEAR;\r
10660 FLAG_C = CFLAG_CLEAR;\r
10661 return;\r
10662 }\r
10663 m68ki_exception_illegal();\r
10664}\r
10665\r
10666\r
10667M68KMAKE_OP(tst, 32, ., pcix)\r
10668{\r
10669 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10670 {\r
10671 uint res = OPER_PCIX_32();\r
10672\r
10673 FLAG_N = NFLAG_32(res);\r
10674 FLAG_Z = res;\r
10675 FLAG_V = VFLAG_CLEAR;\r
10676 FLAG_C = CFLAG_CLEAR;\r
10677 return;\r
10678 }\r
10679 m68ki_exception_illegal();\r
10680}\r
10681\r
10682\r
10683M68KMAKE_OP(tst, 32, ., i)\r
10684{\r
10685 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10686 {\r
10687 uint res = OPER_I_32();\r
10688\r
10689 FLAG_N = NFLAG_32(res);\r
10690 FLAG_Z = res;\r
10691 FLAG_V = VFLAG_CLEAR;\r
10692 FLAG_C = CFLAG_CLEAR;\r
10693 return;\r
10694 }\r
10695 m68ki_exception_illegal();\r
10696}\r
10697\r
10698\r
10699M68KMAKE_OP(unlk, 32, ., a7)\r
10700{\r
10701 REG_A[7] = m68ki_read_32(REG_A[7]);\r
10702}\r
10703\r
10704\r
10705M68KMAKE_OP(unlk, 32, ., .)\r
10706{\r
10707 uint* r_dst = &AY;\r
10708\r
10709 REG_A[7] = *r_dst;\r
10710 *r_dst = m68ki_pull_32();\r
10711}\r
10712\r
10713\r
10714M68KMAKE_OP(unpk, 16, rr, .)\r
10715{\r
10716 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10717 {\r
10718 /* Note: DX and DY are reversed in Motorola's docs */\r
10719 uint src = DY;\r
10720 uint* r_dst = &DX;\r
10721\r
10722 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);\r
10723 return;\r
10724 }\r
10725 m68ki_exception_illegal();\r
10726}\r
10727\r
10728\r
10729M68KMAKE_OP(unpk, 16, mm, ax7)\r
10730{\r
10731 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10732 {\r
10733 /* Note: AX and AY are reversed in Motorola's docs */\r
10734 uint src = OPER_AY_PD_8();\r
10735 uint ea_dst;\r
10736\r
10737 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10738 ea_dst = EA_A7_PD_8();\r
10739 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10740 ea_dst = EA_A7_PD_8();\r
10741 m68ki_write_8(ea_dst, src & 0xff);\r
10742 return;\r
10743 }\r
10744 m68ki_exception_illegal();\r
10745}\r
10746\r
10747\r
10748M68KMAKE_OP(unpk, 16, mm, ay7)\r
10749{\r
10750 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10751 {\r
10752 /* Note: AX and AY are reversed in Motorola's docs */\r
10753 uint src = OPER_A7_PD_8();\r
10754 uint ea_dst;\r
10755\r
10756 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10757 ea_dst = EA_AX_PD_8();\r
10758 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10759 ea_dst = EA_AX_PD_8();\r
10760 m68ki_write_8(ea_dst, src & 0xff);\r
10761 return;\r
10762 }\r
10763 m68ki_exception_illegal();\r
10764}\r
10765\r
10766\r
10767M68KMAKE_OP(unpk, 16, mm, axy7)\r
10768{\r
10769 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10770 {\r
10771 uint src = OPER_A7_PD_8();\r
10772 uint ea_dst;\r
10773\r
10774 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10775 ea_dst = EA_A7_PD_8();\r
10776 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10777 ea_dst = EA_A7_PD_8();\r
10778 m68ki_write_8(ea_dst, src & 0xff);\r
10779 return;\r
10780 }\r
10781 m68ki_exception_illegal();\r
10782}\r
10783\r
10784\r
10785M68KMAKE_OP(unpk, 16, mm, .)\r
10786{\r
10787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10788 {\r
10789 /* Note: AX and AY are reversed in Motorola's docs */\r
10790 uint src = OPER_AY_PD_8();\r
10791 uint ea_dst;\r
10792\r
10793 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10794 ea_dst = EA_AX_PD_8();\r
10795 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10796 ea_dst = EA_AX_PD_8();\r
10797 m68ki_write_8(ea_dst, src & 0xff);\r
10798 return;\r
10799 }\r
10800 m68ki_exception_illegal();\r
10801}\r
10802\r
10803\r
10804\r
10805XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
10806M68KMAKE_END\r
fast MegaDrive/MegaCD/32X emulator