| 1 | /* |
| 2 | * vim:shiftwidth=2:expandtab |
| 3 | */ |
| 4 | #include <stdio.h> |
| 5 | #include <stdlib.h> |
| 6 | #include <assert.h> |
| 7 | |
| 8 | #include "../../pico/pico_int.h" |
| 9 | #include "sh2.h" |
| 10 | #include "compiler.h" |
| 11 | #include "../drc/cmn.h" |
| 12 | |
| 13 | #ifndef DRC_DEBUG |
| 14 | #define DRC_DEBUG 0 |
| 15 | #endif |
| 16 | |
| 17 | #if DRC_DEBUG |
| 18 | #define dbg(l,...) { \ |
| 19 | if ((l) & DRC_DEBUG) \ |
| 20 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
| 21 | } |
| 22 | |
| 23 | #include "mame/sh2dasm.h" |
| 24 | #include <platform/linux/host_dasm.h> |
| 25 | static int insns_compiled, hash_collisions, host_insn_count; |
| 26 | #define COUNT_OP \ |
| 27 | host_insn_count++ |
| 28 | #else // !DRC_DEBUG |
| 29 | #define COUNT_OP |
| 30 | #define dbg(...) |
| 31 | #endif |
| 32 | |
| 33 | #if (DRC_DEBUG & 2) |
| 34 | static u8 *tcache_dsm_ptrs[3]; |
| 35 | static char sh2dasm_buff[64]; |
| 36 | #define do_host_disasm(tcid) \ |
| 37 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
| 38 | tcache_dsm_ptrs[tcid] = tcache_ptr |
| 39 | #else |
| 40 | #define do_host_disasm(x) |
| 41 | #endif |
| 42 | |
| 43 | #define BLOCK_CYCLE_LIMIT 100 |
| 44 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
| 45 | |
| 46 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
| 47 | // BIOS shares tcache with data array because it's only used for init |
| 48 | // and can be discarded early |
| 49 | static const int tcache_sizes[3] = { |
| 50 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
| 51 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
| 52 | DRC_TCACHE_SIZE / 8, // ... slave |
| 53 | }; |
| 54 | |
| 55 | static u8 *tcache_bases[3]; |
| 56 | static u8 *tcache_ptrs[3]; |
| 57 | |
| 58 | // ptr for code emiters |
| 59 | static u8 *tcache_ptr; |
| 60 | |
| 61 | // host register tracking |
| 62 | enum { |
| 63 | HR_FREE, |
| 64 | HR_CACHED, // 'val' has sh2_reg_e |
| 65 | HR_CACHED_DIRTY, |
| 66 | HR_CONST, // 'val' has constant |
| 67 | HR_TEMP, // reg used for temp storage |
| 68 | }; |
| 69 | |
| 70 | typedef struct { |
| 71 | u8 reg; |
| 72 | u8 type; |
| 73 | u16 stamp; // kind of a timestamp |
| 74 | u32 val; |
| 75 | } temp_reg_t; |
| 76 | |
| 77 | #ifdef ARM |
| 78 | #include "../drc/emit_arm.c" |
| 79 | |
| 80 | static const int reg_map_g2h[] = { |
| 81 | -1, -1, -1, -1, |
| 82 | -1, -1, -1, -1, |
| 83 | -1, -1, -1, -1, |
| 84 | -1, -1, -1, -1, |
| 85 | -1, -1, -1, -1, |
| 86 | -1, -1, -1, -1, |
| 87 | }; |
| 88 | |
| 89 | static temp_reg_t reg_temp[] = { |
| 90 | { 0, }, |
| 91 | { 1, }, |
| 92 | { 12, }, |
| 93 | { 14, }, |
| 94 | { 2, }, |
| 95 | { 3, }, |
| 96 | }; |
| 97 | |
| 98 | #else |
| 99 | #include "../drc/emit_x86.c" |
| 100 | |
| 101 | static const int reg_map_g2h[] = { |
| 102 | -1, -1, -1, -1, |
| 103 | -1, -1, -1, -1, |
| 104 | -1, -1, -1, -1, |
| 105 | -1, -1, -1, -1, |
| 106 | -1, -1, -1, -1, |
| 107 | -1, -1, -1, -1, |
| 108 | }; |
| 109 | |
| 110 | // ax, cx, dx are usually temporaries |
| 111 | static temp_reg_t reg_temp[] = { |
| 112 | { xAX, }, |
| 113 | { xCX, }, |
| 114 | { xDX, }, |
| 115 | }; |
| 116 | |
| 117 | #endif |
| 118 | |
| 119 | typedef enum { |
| 120 | SHR_R0 = 0, SHR_R15 = 15, |
| 121 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR, |
| 122 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL, |
| 123 | } sh2_reg_e; |
| 124 | |
| 125 | typedef struct block_desc_ { |
| 126 | u32 addr; // SH2 PC address |
| 127 | u32 end_addr; // TODO rm? |
| 128 | void *tcache_ptr; // translated block for above PC |
| 129 | struct block_desc_ *next; // next block with the same PC hash |
| 130 | #if (DRC_DEBUG & 1) |
| 131 | int refcount; |
| 132 | #endif |
| 133 | } block_desc; |
| 134 | |
| 135 | static const int block_max_counts[3] = { |
| 136 | 4*1024, |
| 137 | 256, |
| 138 | 256, |
| 139 | }; |
| 140 | static block_desc *block_tables[3]; |
| 141 | static int block_counts[3]; |
| 142 | |
| 143 | // ROM hash table |
| 144 | #define MAX_HASH_ENTRIES 1024 |
| 145 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
| 146 | static void **hash_table; |
| 147 | |
| 148 | extern void sh2_drc_entry(SH2 *sh2, void *block); |
| 149 | extern void sh2_drc_exit(void); |
| 150 | |
| 151 | // tmp |
| 152 | extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); |
| 153 | static void REGPARM(1) sh2_test_irq(SH2 *sh2); |
| 154 | |
| 155 | static void flush_tcache(int tcid) |
| 156 | { |
| 157 | dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, |
| 158 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
| 159 | block_counts[tcid], block_max_counts[tcid]); |
| 160 | |
| 161 | block_counts[tcid] = 0; |
| 162 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
| 163 | if (tcid == 0) { // ROM, RAM |
| 164 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
| 165 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
| 166 | } |
| 167 | else |
| 168 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
| 169 | #if (DRC_DEBUG & 2) |
| 170 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
| 171 | #endif |
| 172 | } |
| 173 | |
| 174 | static void *dr_find_block(block_desc *tab, u32 addr) |
| 175 | { |
| 176 | for (tab = tab->next; tab != NULL; tab = tab->next) |
| 177 | if (tab->addr == addr) |
| 178 | break; |
| 179 | |
| 180 | if (tab != NULL) |
| 181 | return tab->tcache_ptr; |
| 182 | |
| 183 | printf("block miss for %08x\n", addr); |
| 184 | return NULL; |
| 185 | } |
| 186 | |
| 187 | static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) |
| 188 | { |
| 189 | int *bcount = &block_counts[tcache_id]; |
| 190 | block_desc *bd; |
| 191 | |
| 192 | if (*bcount >= block_max_counts[tcache_id]) |
| 193 | return NULL; |
| 194 | |
| 195 | bd = &block_tables[tcache_id][*bcount]; |
| 196 | bd->addr = addr; |
| 197 | bd->tcache_ptr = tcache_ptr; |
| 198 | *blk_id = *bcount; |
| 199 | (*bcount)++; |
| 200 | |
| 201 | return bd; |
| 202 | } |
| 203 | |
| 204 | #define HASH_FUNC(hash_tab, addr) \ |
| 205 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
| 206 | |
| 207 | // --------------------------------------------------------------- |
| 208 | |
| 209 | // register chache |
| 210 | static u16 rcache_counter; |
| 211 | |
| 212 | static temp_reg_t *rcache_evict(void) |
| 213 | { |
| 214 | // evict reg with oldest stamp |
| 215 | int i, oldest = -1; |
| 216 | u16 min_stamp = (u16)-1; |
| 217 | |
| 218 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
| 219 | if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) |
| 220 | if (reg_temp[i].stamp <= min_stamp) { |
| 221 | min_stamp = reg_temp[i].stamp; |
| 222 | oldest = i; |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | if (oldest == -1) { |
| 227 | printf("no registers to ec=vict, aborting\n"); |
| 228 | exit(1); |
| 229 | } |
| 230 | |
| 231 | i = oldest; |
| 232 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
| 233 | // writeback |
| 234 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
| 235 | } |
| 236 | |
| 237 | return ®_temp[i]; |
| 238 | } |
| 239 | |
| 240 | typedef enum { |
| 241 | RC_GR_READ, |
| 242 | RC_GR_WRITE, |
| 243 | RC_GR_RMW, |
| 244 | } rc_gr_mode; |
| 245 | |
| 246 | static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode) |
| 247 | { |
| 248 | temp_reg_t *tr; |
| 249 | int i; |
| 250 | |
| 251 | // maybe already statically mapped? |
| 252 | i = reg_map_g2h[r]; |
| 253 | if (i != -1) |
| 254 | return i; |
| 255 | |
| 256 | rcache_counter++; |
| 257 | |
| 258 | // maybe already cached? |
| 259 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
| 260 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
| 261 | reg_temp[i].val == r) |
| 262 | { |
| 263 | reg_temp[i].stamp = rcache_counter; |
| 264 | if (mode != RC_GR_READ) |
| 265 | reg_temp[i].type = HR_CACHED_DIRTY; |
| 266 | return reg_temp[i].reg; |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | // use any free reg |
| 271 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
| 272 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
| 273 | tr = ®_temp[i]; |
| 274 | goto do_alloc; |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | tr = rcache_evict(); |
| 279 | |
| 280 | do_alloc: |
| 281 | if (mode != RC_GR_WRITE) |
| 282 | emith_ctx_read(tr->reg, r * 4); |
| 283 | |
| 284 | tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED; |
| 285 | tr->val = r; |
| 286 | tr->stamp = rcache_counter; |
| 287 | return tr->reg; |
| 288 | } |
| 289 | |
| 290 | static int rcache_get_tmp(void) |
| 291 | { |
| 292 | temp_reg_t *tr; |
| 293 | int i; |
| 294 | |
| 295 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
| 296 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
| 297 | tr = ®_temp[i]; |
| 298 | goto do_alloc; |
| 299 | } |
| 300 | |
| 301 | tr = rcache_evict(); |
| 302 | |
| 303 | do_alloc: |
| 304 | tr->type = HR_TEMP; |
| 305 | return tr->reg; |
| 306 | } |
| 307 | |
| 308 | static void rcache_free_tmp(int hr) |
| 309 | { |
| 310 | int i; |
| 311 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
| 312 | if (reg_temp[i].reg == hr) |
| 313 | break; |
| 314 | |
| 315 | if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) |
| 316 | printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type); |
| 317 | } |
| 318 | |
| 319 | static void rcache_flush(void) |
| 320 | { |
| 321 | int i; |
| 322 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
| 323 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
| 324 | // writeback |
| 325 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
| 326 | } |
| 327 | reg_temp[i].type = HR_FREE; |
| 328 | } |
| 329 | rcache_counter = 0; |
| 330 | } |
| 331 | |
| 332 | // --------------------------------------------------------------- |
| 333 | |
| 334 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
| 335 | { |
| 336 | int hr = rcache_get_reg(dst, RC_GR_WRITE); |
| 337 | emith_move_r_imm(hr, imm); |
| 338 | } |
| 339 | |
| 340 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
| 341 | { |
| 342 | int hr_d = rcache_get_reg(dst, RC_GR_WRITE); |
| 343 | int hr_s = rcache_get_reg(src, RC_GR_READ); |
| 344 | |
| 345 | emith_move_r_r(hr_d, hr_s); |
| 346 | } |
| 347 | |
| 348 | /* |
| 349 | static int sh2_translate_op4(int op) |
| 350 | { |
| 351 | switch (op & 0x000f) |
| 352 | { |
| 353 | case 0x0b: |
| 354 | default: |
| 355 | emith_pass_arg(2, sh2, op); |
| 356 | emith_call(sh2_do_op); |
| 357 | break; |
| 358 | } |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | */ |
| 363 | |
| 364 | #define DELAYED_OP \ |
| 365 | delayed_op = 2 |
| 366 | |
| 367 | #define CHECK_UNHANDLED_BITS(mask) { \ |
| 368 | if ((op & (mask)) != 0) \ |
| 369 | goto default_; \ |
| 370 | } |
| 371 | |
| 372 | static void *sh2_translate(SH2 *sh2, block_desc *other_block) |
| 373 | { |
| 374 | void *block_entry; |
| 375 | block_desc *this_block; |
| 376 | unsigned int pc = sh2->pc; |
| 377 | int op, delayed_op = 0, test_irq = 0; |
| 378 | int tcache_id = 0, blkid = 0; |
| 379 | int cycles = 0; |
| 380 | u32 tmp, tmp2; |
| 381 | |
| 382 | // validate PC |
| 383 | tmp = sh2->pc >> 29; |
| 384 | if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { |
| 385 | printf("invalid PC, aborting: %08x\n", sh2->pc); |
| 386 | // FIXME: be less destructive |
| 387 | exit(1); |
| 388 | } |
| 389 | |
| 390 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
| 391 | // data_array, BIOS have separate tcache (shared) |
| 392 | tcache_id = 1 + sh2->is_slave; |
| 393 | } |
| 394 | |
| 395 | tcache_ptr = tcache_ptrs[tcache_id]; |
| 396 | this_block = dr_add_block(pc, tcache_id, &blkid); |
| 397 | |
| 398 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
| 399 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { |
| 400 | flush_tcache(tcache_id); |
| 401 | tcache_ptr = tcache_ptrs[tcache_id]; |
| 402 | other_block = NULL; // also gone too due to flush |
| 403 | this_block = dr_add_block(pc, tcache_id, &blkid); |
| 404 | } |
| 405 | |
| 406 | this_block->next = other_block; |
| 407 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
| 408 | HASH_FUNC(hash_table, pc) = this_block; |
| 409 | |
| 410 | block_entry = tcache_ptr; |
| 411 | #if (DRC_DEBUG & 1) |
| 412 | printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', |
| 413 | tcache_id, block_counts[tcache_id], pc, block_entry); |
| 414 | if (other_block != NULL) { |
| 415 | printf(" hash collision with %08x\n", other_block->addr); |
| 416 | hash_collisions++; |
| 417 | } |
| 418 | #endif |
| 419 | |
| 420 | while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) |
| 421 | { |
| 422 | if (delayed_op > 0) |
| 423 | delayed_op--; |
| 424 | |
| 425 | op = p32x_sh2_read16(pc, sh2); |
| 426 | |
| 427 | #if (DRC_DEBUG & 3) |
| 428 | insns_compiled++; |
| 429 | #if (DRC_DEBUG & 2) |
| 430 | DasmSH2(sh2dasm_buff, pc, op); |
| 431 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
| 432 | #endif |
| 433 | #endif |
| 434 | |
| 435 | pc += 2; |
| 436 | cycles++; |
| 437 | |
| 438 | switch ((op >> 12) & 0x0f) |
| 439 | { |
| 440 | case 0x00: |
| 441 | switch (op & 0x0f) { |
| 442 | case 0x03: |
| 443 | CHECK_UNHANDLED_BITS(0xd0); |
| 444 | // BRAF Rm 0000mmmm00100011 |
| 445 | // BSRF Rm 0000mmmm00000011 |
| 446 | DELAYED_OP; |
| 447 | if (!(op & 0x20)) |
| 448 | emit_move_r_imm32(SHR_PR, pc + 2); |
| 449 | tmp = rcache_get_reg(SHR_PPC, RC_GR_WRITE); |
| 450 | tmp2 = rcache_get_reg((op >> 8) & 0x0f, RC_GR_READ); |
| 451 | emith_move_r_r(tmp, tmp2); |
| 452 | emith_add_r_imm(tmp, pc + 2); |
| 453 | cycles++; |
| 454 | goto end_op; |
| 455 | case 0x09: |
| 456 | CHECK_UNHANDLED_BITS(0xf0); |
| 457 | // NOP 0000000000001001 |
| 458 | goto end_op; |
| 459 | case 0x0b: |
| 460 | CHECK_UNHANDLED_BITS(0xd0); |
| 461 | DELAYED_OP; |
| 462 | if (!(op & 0x20)) { |
| 463 | // RTS 0000000000001011 |
| 464 | emit_move_r_r(SHR_PPC, SHR_PR); |
| 465 | cycles++; |
| 466 | } else { |
| 467 | // RTE 0000000000101011 |
| 468 | //emit_move_r_r(SHR_PC, SHR_PR); |
| 469 | emit_move_r_imm32(SHR_PC, pc - 2); |
| 470 | rcache_flush(); |
| 471 | emith_pass_arg_r(0, CONTEXT_REG); |
| 472 | emith_pass_arg_imm(1, op); |
| 473 | emith_call(sh2_do_op); |
| 474 | emit_move_r_r(SHR_PPC, SHR_PC); |
| 475 | test_irq = 1; |
| 476 | cycles += 3; |
| 477 | } |
| 478 | goto end_op; |
| 479 | } |
| 480 | goto default_; |
| 481 | |
| 482 | case 0x04: |
| 483 | switch (op & 0x0f) { |
| 484 | case 0x00: |
| 485 | if ((op & 0xf0) != 1) |
| 486 | goto default_; |
| 487 | // DT Rn 0100nnnn00010000 |
| 488 | goto default_; |
| 489 | case 0x07: |
| 490 | if ((op & 0xf0) != 0) |
| 491 | goto default_; |
| 492 | // LDC.L @Rm+,SR 0100mmmm00000111 |
| 493 | test_irq = 1; |
| 494 | goto default_; |
| 495 | case 0x0b: |
| 496 | if ((op & 0xd0) != 0) |
| 497 | goto default_; |
| 498 | // JMP @Rm 0100mmmm00101011 |
| 499 | // JSR @Rm 0100mmmm00001011 |
| 500 | DELAYED_OP; |
| 501 | if (!(op & 0x20)) |
| 502 | emit_move_r_imm32(SHR_PR, pc + 2); |
| 503 | emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); |
| 504 | cycles++; |
| 505 | goto end_op; |
| 506 | case 0x0e: |
| 507 | if ((op & 0xf0) != 0) |
| 508 | goto default_; |
| 509 | // LDC Rm,SR 0100mmmm00001110 |
| 510 | test_irq = 1; |
| 511 | goto default_; |
| 512 | } |
| 513 | goto default_; |
| 514 | |
| 515 | case 0x08: |
| 516 | switch (op & 0x0f00) { |
| 517 | // BT/S label 10001101dddddddd |
| 518 | case 0x0d00: |
| 519 | // BF/S label 10001111dddddddd |
| 520 | case 0x0f00: |
| 521 | DELAYED_OP; |
| 522 | cycles--; |
| 523 | // fallthrough |
| 524 | // BT label 10001001dddddddd |
| 525 | case 0x0900: |
| 526 | // BF label 10001011dddddddd |
| 527 | case 0x0b00: |
| 528 | tmp = ((signed int)(op << 24) >> 23); |
| 529 | tmp2 = delayed_op ? SHR_PPC : SHR_PC; |
| 530 | emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0)); |
| 531 | emith_test_t(); |
| 532 | EMITH_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0); |
| 533 | cycles += 2; |
| 534 | if (!delayed_op) |
| 535 | goto end_block; |
| 536 | goto end_op; |
| 537 | } |
| 538 | goto default_; |
| 539 | |
| 540 | case 0x0a: |
| 541 | // BRA label 1010dddddddddddd |
| 542 | DELAYED_OP; |
| 543 | do_bra: |
| 544 | tmp = ((signed int)(op << 20) >> 19); |
| 545 | emit_move_r_imm32(SHR_PPC, pc + tmp + 2); |
| 546 | cycles++; |
| 547 | break; |
| 548 | |
| 549 | case 0x0b: |
| 550 | // BSR label 1011dddddddddddd |
| 551 | DELAYED_OP; |
| 552 | emit_move_r_imm32(SHR_PR, pc + 2); |
| 553 | goto do_bra; |
| 554 | |
| 555 | default: |
| 556 | default_: |
| 557 | emit_move_r_imm32(SHR_PC, pc - 2); |
| 558 | rcache_flush(); |
| 559 | emith_pass_arg_r(0, CONTEXT_REG); |
| 560 | emith_pass_arg_imm(1, op); |
| 561 | emith_call(sh2_do_op); |
| 562 | break; |
| 563 | } |
| 564 | |
| 565 | end_op: |
| 566 | if (delayed_op == 1) |
| 567 | emit_move_r_r(SHR_PC, SHR_PPC); |
| 568 | |
| 569 | if (test_irq && delayed_op != 2) { |
| 570 | rcache_flush(); |
| 571 | emith_pass_arg_r(0, CONTEXT_REG); |
| 572 | emith_call(sh2_test_irq); |
| 573 | break; |
| 574 | } |
| 575 | if (delayed_op == 1) |
| 576 | break; |
| 577 | |
| 578 | do_host_disasm(tcache_id); |
| 579 | } |
| 580 | |
| 581 | end_block: |
| 582 | this_block->end_addr = pc; |
| 583 | |
| 584 | // mark memory blocks as containing compiled code |
| 585 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
| 586 | // data array, BIOS |
| 587 | u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
| 588 | tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
| 589 | tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
| 590 | Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; |
| 591 | for (++tmp; tmp < tmp2; tmp++) { |
| 592 | if (drcblk[tmp]) |
| 593 | break; // dont overwrite overlay block |
| 594 | drcblk[tmp] = blkid << 1; |
| 595 | } |
| 596 | } |
| 597 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
| 598 | tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
| 599 | tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
| 600 | Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; |
| 601 | for (++tmp; tmp < tmp2; tmp++) { |
| 602 | if (Pico32xMem->drcblk_ram[tmp]) |
| 603 | break; |
| 604 | Pico32xMem->drcblk_ram[tmp] = blkid << 1; |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
| 609 | emith_sub_r_imm(tmp, cycles << 12); |
| 610 | rcache_flush(); |
| 611 | emith_jump(sh2_drc_exit); |
| 612 | tcache_ptrs[tcache_id] = tcache_ptr; |
| 613 | |
| 614 | #ifdef ARM |
| 615 | cache_flush_d_inval_i(block_entry, tcache_ptr); |
| 616 | #endif |
| 617 | |
| 618 | do_host_disasm(tcache_id); |
| 619 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
| 620 | tcache_id, block_counts[tcache_id], |
| 621 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
| 622 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
| 623 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
| 624 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
| 625 | #if (DRC_DEBUG & 2) |
| 626 | fflush(stdout); |
| 627 | #endif |
| 628 | |
| 629 | return block_entry; |
| 630 | /* |
| 631 | unimplemented: |
| 632 | // last op |
| 633 | do_host_disasm(tcache_id); |
| 634 | exit(1); |
| 635 | */ |
| 636 | } |
| 637 | |
| 638 | void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) |
| 639 | { |
| 640 | while (((signed int)sh2->sr >> 12) > 0) |
| 641 | { |
| 642 | void *block = NULL; |
| 643 | block_desc *bd = NULL; |
| 644 | |
| 645 | // FIXME: must avoid doing it so often.. |
| 646 | sh2_test_irq(sh2); |
| 647 | |
| 648 | // we have full block id tables for data_array and RAM |
| 649 | // BIOS goes to data_array table too |
| 650 | if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
| 651 | int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
| 652 | if (blkid & 1) { |
| 653 | bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; |
| 654 | block = bd->tcache_ptr; |
| 655 | } |
| 656 | } |
| 657 | // RAM |
| 658 | else if ((sh2->pc & 0xc6000000) == 0x06000000) { |
| 659 | int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
| 660 | if (blkid & 1) { |
| 661 | bd = &block_tables[0][blkid >> 1]; |
| 662 | block = bd->tcache_ptr; |
| 663 | } |
| 664 | } |
| 665 | // ROM |
| 666 | else if ((sh2->pc & 0xc6000000) == 0x02000000) { |
| 667 | bd = HASH_FUNC(hash_table, sh2->pc); |
| 668 | |
| 669 | if (bd != NULL) { |
| 670 | if (bd->addr == sh2->pc) |
| 671 | block = bd->tcache_ptr; |
| 672 | else |
| 673 | block = dr_find_block(bd, sh2->pc); |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | if (block == NULL) |
| 678 | block = sh2_translate(sh2, bd); |
| 679 | |
| 680 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
| 681 | sh2->pc, block, (signed int)sh2->sr >> 12); |
| 682 | #if (DRC_DEBUG & 1) |
| 683 | if (bd != NULL) |
| 684 | bd->refcount++; |
| 685 | #endif |
| 686 | sh2_drc_entry(sh2, block); |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) |
| 691 | { |
| 692 | u16 id = *p >> 1; |
| 693 | block_desc *bd = btab + id; |
| 694 | |
| 695 | dbg(1, " killing block %08x", bd->addr); |
| 696 | bd->addr = bd->end_addr = 0; |
| 697 | |
| 698 | while (p > drcblk && (p[-1] >> 1) == id) |
| 699 | p--; |
| 700 | |
| 701 | // check for possible overlay block |
| 702 | if (p > 0 && p[-1] != 0) { |
| 703 | bd = btab + (p[-1] >> 1); |
| 704 | if (bd->addr <= a && a < bd->end_addr) |
| 705 | sh2_smc_rm_block(drcblk, p - 1, btab, a); |
| 706 | } |
| 707 | |
| 708 | do { |
| 709 | *p++ = 0; |
| 710 | } |
| 711 | while ((*p >> 1) == id); |
| 712 | } |
| 713 | |
| 714 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
| 715 | { |
| 716 | u16 *drcblk = Pico32xMem->drcblk_ram; |
| 717 | u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); |
| 718 | |
| 719 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
| 720 | sh2_smc_rm_block(drcblk, p, block_tables[0], a); |
| 721 | } |
| 722 | |
| 723 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
| 724 | { |
| 725 | u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; |
| 726 | u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); |
| 727 | |
| 728 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
| 729 | sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); |
| 730 | } |
| 731 | |
| 732 | void sh2_execute(SH2 *sh2, int cycles) |
| 733 | { |
| 734 | sh2->cycles_aim += cycles; |
| 735 | cycles = sh2->cycles_aim - sh2->cycles_done; |
| 736 | |
| 737 | // cycles are kept in SHR_SR unused bits (upper 20) |
| 738 | sh2->sr &= 0x3f3; |
| 739 | sh2->sr |= cycles << 12; |
| 740 | sh2_drc_dispatcher(sh2); |
| 741 | |
| 742 | sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12); |
| 743 | } |
| 744 | |
| 745 | static void REGPARM(1) sh2_test_irq(SH2 *sh2) |
| 746 | { |
| 747 | if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) |
| 748 | { |
| 749 | if (sh2->pending_irl > sh2->pending_int_irq) |
| 750 | sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2); |
| 751 | else { |
| 752 | sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); |
| 753 | sh2->pending_int_irq = 0; // auto-clear |
| 754 | sh2->pending_level = sh2->pending_irl; |
| 755 | } |
| 756 | } |
| 757 | } |
| 758 | |
| 759 | #if (DRC_DEBUG & 1) |
| 760 | static void block_stats(void) |
| 761 | { |
| 762 | int c, b, i, total = 0; |
| 763 | |
| 764 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
| 765 | for (i = 0; i < block_counts[b]; i++) |
| 766 | if (block_tables[b][i].addr != 0) |
| 767 | total += block_tables[b][i].refcount; |
| 768 | |
| 769 | for (c = 0; c < 10; c++) { |
| 770 | block_desc *blk, *maxb = NULL; |
| 771 | int max = 0; |
| 772 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
| 773 | for (i = 0; i < block_counts[b]; i++) { |
| 774 | blk = &block_tables[b][i]; |
| 775 | if (blk->addr != 0 && blk->refcount > max) { |
| 776 | max = blk->refcount; |
| 777 | maxb = blk; |
| 778 | } |
| 779 | } |
| 780 | } |
| 781 | if (maxb == NULL) |
| 782 | break; |
| 783 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
| 784 | (double)maxb->refcount / total * 100.0); |
| 785 | maxb->refcount = 0; |
| 786 | } |
| 787 | |
| 788 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
| 789 | for (i = 0; i < block_counts[b]; i++) |
| 790 | block_tables[b][i].refcount = 0; |
| 791 | } |
| 792 | #else |
| 793 | #define block_stats() |
| 794 | #endif |
| 795 | |
| 796 | void sh2_drc_flush_all(void) |
| 797 | { |
| 798 | block_stats(); |
| 799 | flush_tcache(0); |
| 800 | flush_tcache(1); |
| 801 | flush_tcache(2); |
| 802 | } |
| 803 | |
| 804 | int sh2_drc_init(SH2 *sh2) |
| 805 | { |
| 806 | if (block_tables[0] == NULL) { |
| 807 | int i, cnt; |
| 808 | |
| 809 | drc_cmn_init(); |
| 810 | |
| 811 | cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2]; |
| 812 | block_tables[0] = calloc(cnt, sizeof(*block_tables[0])); |
| 813 | if (block_tables[0] == NULL) |
| 814 | return -1; |
| 815 | |
| 816 | memset(block_counts, 0, sizeof(block_counts)); |
| 817 | tcache_bases[0] = tcache_ptrs[0] = tcache; |
| 818 | |
| 819 | for (i = 1; i < ARRAY_SIZE(block_tables); i++) { |
| 820 | block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; |
| 821 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
| 822 | } |
| 823 | |
| 824 | // tmp |
| 825 | PicoOpt |= POPT_DIS_VDP_FIFO; |
| 826 | |
| 827 | #if (DRC_DEBUG & 2) |
| 828 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
| 829 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
| 830 | #endif |
| 831 | #if (DRC_DEBUG & 1) |
| 832 | hash_collisions = 0; |
| 833 | #endif |
| 834 | } |
| 835 | |
| 836 | if (hash_table == NULL) { |
| 837 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
| 838 | if (hash_table == NULL) |
| 839 | return -1; |
| 840 | } |
| 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | void sh2_drc_finish(SH2 *sh2) |
| 846 | { |
| 847 | if (block_tables[0] != NULL) { |
| 848 | block_stats(); |
| 849 | free(block_tables[0]); |
| 850 | memset(block_tables, 0, sizeof(block_tables)); |
| 851 | |
| 852 | drc_cmn_cleanup(); |
| 853 | } |
| 854 | |
| 855 | if (hash_table != NULL) { |
| 856 | free(hash_table); |
| 857 | hash_table = NULL; |
| 858 | } |
| 859 | } |