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minor frontend fixes
[picodrive.git] / cpu / sh2 / compiler.c
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1/*
2 * SH2 recompiler
3 * (C) notaz, 2009,2010
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 *
8 * notes:
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_links[]),
12 * except jumps between different tcaches
13 * - non-main block entries are called subblocks, as they have same tracking
14 * structures that main blocks have.
15 *
16 * implemented:
17 * - static register allocation
18 * - remaining register caching and tracking in temporaries
19 * - block-local branch linking
20 * - block linking (except between tcaches)
21 * - some constant propagation
22 *
23 * TODO:
24 * - better constant propagation
25 * - stack caching?
26 * - bug fixing
27 */
28#include <stddef.h>
29#include <stdio.h>
30#include <stdlib.h>
31#include <assert.h>
32
33#include "../../pico/pico_int.h"
34#include "sh2.h"
35#include "compiler.h"
36#include "../drc/cmn.h"
37#include "../debug.h"
38
39// features
40#define PROPAGATE_CONSTANTS 1
41#define LINK_BRANCHES 1
42
43// limits (per block)
44#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
45
46// max literal offset from the block end
47#define MAX_LITERAL_OFFSET 32*2
48#define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4)
49#define MAX_LOCAL_BRANCHES 32
50
51///
52#define FETCH_OP(pc) \
53 dr_pc_base[(pc) / 2]
54
55#define FETCH32(a) \
56 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
57
58#ifdef DRC_SH2
59
60// debug stuff
61// 1 - ?
62// 2 - ?
63// 4 - log asm
64// {
65#ifndef DRC_DEBUG
66#define DRC_DEBUG 0
67#endif
68
69#if DRC_DEBUG
70#define dbg(l,...) { \
71 if ((l) & DRC_DEBUG) \
72 elprintf(EL_STATUS, ##__VA_ARGS__); \
73}
74
75#include "mame/sh2dasm.h"
76#include <platform/libpicofe/linux/host_dasm.h>
77static int insns_compiled, hash_collisions, host_insn_count;
78#define COUNT_OP \
79 host_insn_count++
80#else // !DRC_DEBUG
81#define COUNT_OP
82#define dbg(...)
83#endif
84
85#if (DRC_DEBUG & 4)
86static u8 *tcache_dsm_ptrs[3];
87static char sh2dasm_buff[64];
88#define do_host_disasm(tcid) \
89 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
90 tcache_dsm_ptrs[tcid] = tcache_ptr
91#else
92#define do_host_disasm(x)
93#endif
94
95#if (DRC_DEBUG & 8) || defined(PDB)
96static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
97{
98 if (block != NULL) {
99 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
100 sh2->pc, block, (signed int)sr >> 12);
101 pdb_step(sh2, sh2->pc);
102 }
103 return block;
104}
105#endif
106// } debug
107
108#define TCACHE_BUFFERS 3
109
110// we have 3 translation cache buffers, split from one drc/cmn buffer.
111// BIOS shares tcache with data array because it's only used for init
112// and can be discarded early
113// XXX: need to tune sizes
114static const int tcache_sizes[TCACHE_BUFFERS] = {
115 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
116 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
117 DRC_TCACHE_SIZE / 8, // ... slave
118};
119
120static u8 *tcache_bases[TCACHE_BUFFERS];
121static u8 *tcache_ptrs[TCACHE_BUFFERS];
122
123// ptr for code emiters
124static u8 *tcache_ptr;
125
126typedef struct block_desc_ {
127 u32 addr; // SH2 PC address
128 void *tcache_ptr; // translated block for above PC
129 struct block_desc_ *next; // next block with the same PC hash
130#if (DRC_DEBUG & 2)
131 int refcount;
132#endif
133} block_desc;
134
135typedef struct block_link_ {
136 u32 target_pc;
137 void *jump; // insn address
138// struct block_link_ *next;
139} block_link;
140
141static const int block_max_counts[TCACHE_BUFFERS] = {
142 4*1024,
143 256,
144 256,
145};
146static block_desc *block_tables[TCACHE_BUFFERS];
147static block_link *block_links[TCACHE_BUFFERS];
148static int block_counts[TCACHE_BUFFERS];
149static int block_link_counts[TCACHE_BUFFERS];
150
151// host register tracking
152enum {
153 HR_FREE,
154 HR_CACHED, // 'val' has sh2_reg_e
155// HR_CONST, // 'val' has a constant
156 HR_TEMP, // reg used for temp storage
157};
158
159enum {
160 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
161 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
162};
163
164typedef struct {
165 u32 hreg:5; // "host" reg
166 u32 greg:5; // "guest" reg
167 u32 type:3;
168 u32 flags:3;
169 u32 stamp:16; // kind of a timestamp
170} temp_reg_t;
171
172// note: reg_temp[] must have at least the amount of
173// registers used by handlers in worst case (currently 4)
174#ifdef __arm__
175#include "../drc/emit_arm.c"
176
177static const int reg_map_g2h[] = {
178 4, 5, 6, 7,
179 8, -1, -1, -1,
180 -1, -1, -1, -1,
181 -1, -1, -1, 9, // r12 .. sp
182 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
183 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
184};
185
186static temp_reg_t reg_temp[] = {
187 { 0, },
188 { 1, },
189 { 12, },
190 { 14, },
191 { 2, },
192 { 3, },
193};
194
195#elif defined(__i386__)
196#include "../drc/emit_x86.c"
197
198static const int reg_map_g2h[] = {
199 xSI,-1, -1, -1,
200 -1, -1, -1, -1,
201 -1, -1, -1, -1,
202 -1, -1, -1, -1,
203 -1, -1, -1, xDI,
204 -1, -1, -1, -1,
205};
206
207// ax, cx, dx are usually temporaries by convention
208static temp_reg_t reg_temp[] = {
209 { xAX, },
210 { xBX, },
211 { xCX, },
212 { xDX, },
213};
214
215#else
216#error unsupported arch
217#endif
218
219#define T 0x00000001
220#define S 0x00000002
221#define I 0x000000f0
222#define Q 0x00000100
223#define M 0x00000200
224#define T_save 0x00000800
225
226#define I_SHIFT 4
227#define Q_SHIFT 8
228#define M_SHIFT 9
229
230// ROM hash table
231#define MAX_HASH_ENTRIES 1024
232#define HASH_MASK (MAX_HASH_ENTRIES - 1)
233static void **hash_table;
234
235#define HASH_FUNC(hash_tab, addr) \
236 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
237
238static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
239static void (*sh2_drc_dispatcher)(void);
240static void (*sh2_drc_exit)(void);
241static void (*sh2_drc_test_irq)(void);
242
243static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
244static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
245static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
246static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
247static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
248static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
249static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
250static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
251
252// address space stuff
253static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
254{
255 int poffs = -1;
256
257 if ((a & ~0x7ff) == 0) {
258 // BIOS
259 poffs = offsetof(SH2, p_bios);
260 *mask = 0x7ff;
261 }
262 else if ((a & 0xfffff000) == 0xc0000000) {
263 // data array
264 poffs = offsetof(SH2, p_da);
265 *mask = 0xfff;
266 }
267 else if ((a & 0xc6000000) == 0x06000000) {
268 // SDRAM
269 poffs = offsetof(SH2, p_sdram);
270 *mask = 0x03ffff;
271 }
272 else if ((a & 0xc6000000) == 0x02000000) {
273 // ROM
274 poffs = offsetof(SH2, p_rom);
275 *mask = 0x3fffff;
276 }
277
278 return poffs;
279}
280
281static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id)
282{
283 *tcache_id = 0;
284
285 // we have full block id tables for data_array and RAM
286 // BIOS goes to data_array table too
287 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
288 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
289 *tcache_id = 1 + is_slave;
290 if (blkid & 1)
291 return &block_tables[*tcache_id][blkid >> 1];
292 }
293 // RAM
294 else if ((pc & 0xc6000000) == 0x06000000) {
295 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
296 if (blkid & 1)
297 return &block_tables[0][blkid >> 1];
298 }
299 // ROM
300 else if ((pc & 0xc6000000) == 0x02000000) {
301 block_desc *bd = HASH_FUNC(hash_table, pc);
302
303 for (; bd != NULL; bd = bd->next)
304 if (bd->addr == pc)
305 return bd;
306 }
307
308 return NULL;
309}
310
311// ---------------------------------------------------------------
312
313// block management
314static void REGPARM(1) flush_tcache(int tcid)
315{
316 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
317 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
318 block_counts[tcid], block_max_counts[tcid]);
319
320 block_counts[tcid] = 0;
321 block_link_counts[tcid] = 0;
322 tcache_ptrs[tcid] = tcache_bases[tcid];
323 if (tcid == 0) { // ROM, RAM
324 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
325 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
326 }
327 else
328 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
329#if (DRC_DEBUG & 4)
330 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
331#endif
332}
333
334#if LINK_BRANCHES
335// add block links (tracked branches)
336static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id)
337{
338 block_link *bl = block_links[tcache_id];
339 int cnt = block_link_counts[tcache_id];
340
341 if (cnt >= block_max_counts[tcache_id] * 2) {
342 dbg(1, "bl overflow for tcache %d\n", tcache_id);
343 return -1;
344 }
345
346 bl[cnt].target_pc = target_pc;
347 bl[cnt].jump = jump;
348 block_link_counts[tcache_id]++;
349
350 return 0;
351}
352#endif
353
354static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id)
355{
356 block_desc *bd;
357 int tcache_id;
358 int *bcount;
359
360 bd = dr_get_bd(addr, is_slave, &tcache_id);
361 if (bd != NULL) {
362 dbg(2, "block override for %08x", addr);
363 bd->tcache_ptr = tcache_ptr;
364 *blk_id = bd - block_tables[tcache_id];
365 return bd;
366 }
367
368 bcount = &block_counts[tcache_id];
369 if (*bcount >= block_max_counts[tcache_id]) {
370 dbg(1, "bd overflow for tcache %d", tcache_id);
371 return NULL;
372 }
373 if (*bcount == 0)
374 (*bcount)++; // not using descriptor 0
375
376 bd = &block_tables[tcache_id][*bcount];
377 bd->addr = addr;
378 bd->tcache_ptr = tcache_ptr;
379 *blk_id = *bcount;
380 (*bcount)++;
381
382 if ((addr & 0xc6000000) == 0x02000000) { // ROM
383 bd->next = HASH_FUNC(hash_table, addr);
384 HASH_FUNC(hash_table, addr) = bd;
385#if (DRC_DEBUG & 2)
386 if (bd->next != NULL) {
387 printf(" hash collision with %08x\n", bd->next->addr);
388 hash_collisions++;
389 }
390#endif
391 }
392
393 return bd;
394}
395
396static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
397{
398 block_desc *bd = NULL;
399 void *block = NULL;
400
401 bd = dr_get_bd(pc, is_slave, tcache_id);
402 if (bd != NULL)
403 block = bd->tcache_ptr;
404
405#if (DRC_DEBUG & 2)
406 if (bd != NULL)
407 bd->refcount++;
408#endif
409 return block;
410}
411
412static void *dr_failure(void)
413{
414 lprintf("recompilation failed\n");
415 exit(1);
416}
417
418static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id)
419{
420#if LINK_BRANCHES
421 int target_tcache_id;
422 void *target;
423 int ret;
424
425 target = dr_lookup_block(pc, sh2->is_slave, &target_tcache_id);
426 if (target_tcache_id == tcache_id) {
427 // allow linking blocks only from local cache
428 ret = dr_add_block_link(pc, tcache_ptr, tcache_id);
429 if (ret < 0)
430 return NULL;
431 }
432 if (target == NULL || target_tcache_id != tcache_id)
433 target = sh2_drc_dispatcher;
434
435 return target;
436#else
437 return sh2_drc_dispatcher;
438#endif
439}
440
441static void dr_link_blocks(void *target, u32 pc, int tcache_id)
442{
443#if LINK_BRANCHES
444 block_link *bl = block_links[tcache_id];
445 int cnt = block_link_counts[tcache_id];
446 int i;
447
448 for (i = 0; i < cnt; i++) {
449 if (bl[i].target_pc == pc) {
450 dbg(2, "- link from %p", bl[i].jump);
451 emith_jump_patch(bl[i].jump, target);
452 // XXX: sync ARM caches (old jump should be fine)?
453 }
454 }
455#endif
456}
457
458#define ADD_TO_ARRAY(array, count, item, failcode) \
459 array[count++] = item; \
460 if (count >= ARRAY_SIZE(array)) { \
461 dbg(1, "warning: " #array " overflow"); \
462 failcode; \
463 }
464
465static int find_in_array(u32 *array, size_t size, u32 what)
466{
467 size_t i;
468 for (i = 0; i < size; i++)
469 if (what == array[i])
470 return i;
471
472 return -1;
473}
474
475// ---------------------------------------------------------------
476
477// register cache / constant propagation stuff
478typedef enum {
479 RC_GR_READ,
480 RC_GR_WRITE,
481 RC_GR_RMW,
482} rc_gr_mode;
483
484static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
485
486// guest regs with constants
487static u32 dr_gcregs[24];
488// a mask of constant/dirty regs
489static u32 dr_gcregs_mask;
490static u32 dr_gcregs_dirty;
491
492#if PROPAGATE_CONSTANTS
493static void gconst_new(sh2_reg_e r, u32 val)
494{
495 int i;
496
497 dr_gcregs_mask |= 1 << r;
498 dr_gcregs_dirty |= 1 << r;
499 dr_gcregs[r] = val;
500
501 // throw away old r that we might have cached
502 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
503 if ((reg_temp[i].type == HR_CACHED) &&
504 reg_temp[i].greg == r) {
505 reg_temp[i].type = HR_FREE;
506 reg_temp[i].flags = 0;
507 }
508 }
509}
510#endif
511
512static int gconst_get(sh2_reg_e r, u32 *val)
513{
514 if (dr_gcregs_mask & (1 << r)) {
515 *val = dr_gcregs[r];
516 return 1;
517 }
518 return 0;
519}
520
521static int gconst_check(sh2_reg_e r)
522{
523 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
524 return 1;
525 return 0;
526}
527
528// update hr if dirty, else do nothing
529static int gconst_try_read(int hr, sh2_reg_e r)
530{
531 if (dr_gcregs_dirty & (1 << r)) {
532 emith_move_r_imm(hr, dr_gcregs[r]);
533 dr_gcregs_dirty &= ~(1 << r);
534 return 1;
535 }
536 return 0;
537}
538
539static void gconst_check_evict(sh2_reg_e r)
540{
541 if (dr_gcregs_mask & (1 << r))
542 // no longer cached in reg, make dirty again
543 dr_gcregs_dirty |= 1 << r;
544}
545
546static void gconst_kill(sh2_reg_e r)
547{
548 dr_gcregs_mask &= ~(1 << r);
549 dr_gcregs_dirty &= ~(1 << r);
550}
551
552static void gconst_clean(void)
553{
554 int i;
555
556 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
557 if (dr_gcregs_dirty & (1 << i)) {
558 // using RC_GR_READ here: it will call gconst_try_read,
559 // cache the reg and mark it dirty.
560 rcache_get_reg_(i, RC_GR_READ, 0);
561 }
562}
563
564static void gconst_invalidate(void)
565{
566 dr_gcregs_mask = dr_gcregs_dirty = 0;
567}
568
569static u16 rcache_counter;
570
571static temp_reg_t *rcache_evict(void)
572{
573 // evict reg with oldest stamp
574 int i, oldest = -1;
575 u16 min_stamp = (u16)-1;
576
577 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
578 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
579 reg_temp[i].stamp <= min_stamp) {
580 min_stamp = reg_temp[i].stamp;
581 oldest = i;
582 }
583 }
584
585 if (oldest == -1) {
586 printf("no registers to evict, aborting\n");
587 exit(1);
588 }
589
590 i = oldest;
591 if (reg_temp[i].type == HR_CACHED) {
592 if (reg_temp[i].flags & HRF_DIRTY)
593 // writeback
594 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
595 gconst_check_evict(reg_temp[i].greg);
596 }
597
598 reg_temp[i].type = HR_FREE;
599 reg_temp[i].flags = 0;
600 return &reg_temp[i];
601}
602
603static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
604{
605 int i = reg_map_g2h[r];
606 if (i != -1) {
607 if (mode != RC_GR_WRITE)
608 gconst_try_read(i, r);
609 }
610 return i;
611}
612
613// note: must not be called when doing conditional code
614static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
615{
616 temp_reg_t *tr;
617 int i, ret;
618
619 // maybe statically mapped?
620 ret = get_reg_static(r, mode);
621 if (ret != -1)
622 goto end;
623
624 rcache_counter++;
625
626 // maybe already cached?
627 // if so, prefer against gconst (they must be in sync)
628 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
629 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
630 reg_temp[i].stamp = rcache_counter;
631 if (mode != RC_GR_READ)
632 reg_temp[i].flags |= HRF_DIRTY;
633 ret = reg_temp[i].hreg;
634 goto end;
635 }
636 }
637
638 // use any free reg
639 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
640 if (reg_temp[i].type == HR_FREE) {
641 tr = &reg_temp[i];
642 goto do_alloc;
643 }
644 }
645
646 tr = rcache_evict();
647
648do_alloc:
649 tr->type = HR_CACHED;
650 if (do_locking)
651 tr->flags |= HRF_LOCKED;
652 if (mode != RC_GR_READ)
653 tr->flags |= HRF_DIRTY;
654 tr->greg = r;
655 tr->stamp = rcache_counter;
656 ret = tr->hreg;
657
658 if (mode != RC_GR_WRITE) {
659 if (gconst_check(r)) {
660 if (gconst_try_read(ret, r))
661 tr->flags |= HRF_DIRTY;
662 }
663 else
664 emith_ctx_read(tr->hreg, r * 4);
665 }
666
667end:
668 if (mode != RC_GR_READ)
669 gconst_kill(r);
670
671 return ret;
672}
673
674static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
675{
676 return rcache_get_reg_(r, mode, 1);
677}
678
679static int rcache_get_tmp(void)
680{
681 temp_reg_t *tr;
682 int i;
683
684 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
685 if (reg_temp[i].type == HR_FREE) {
686 tr = &reg_temp[i];
687 goto do_alloc;
688 }
689
690 tr = rcache_evict();
691
692do_alloc:
693 tr->type = HR_TEMP;
694 return tr->hreg;
695}
696
697static int rcache_get_arg_id(int arg)
698{
699 int i, r = 0;
700 host_arg2reg(r, arg);
701
702 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
703 if (reg_temp[i].hreg == r)
704 break;
705
706 if (i == ARRAY_SIZE(reg_temp)) // can't happen
707 exit(1);
708
709 if (reg_temp[i].type == HR_CACHED) {
710 // writeback
711 if (reg_temp[i].flags & HRF_DIRTY)
712 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
713 gconst_check_evict(reg_temp[i].greg);
714 }
715 else if (reg_temp[i].type == HR_TEMP) {
716 printf("arg %d reg %d already used, aborting\n", arg, r);
717 exit(1);
718 }
719
720 reg_temp[i].type = HR_FREE;
721 reg_temp[i].flags = 0;
722
723 return i;
724}
725
726// get a reg to be used as function arg
727static int rcache_get_tmp_arg(int arg)
728{
729 int id = rcache_get_arg_id(arg);
730 reg_temp[id].type = HR_TEMP;
731
732 return reg_temp[id].hreg;
733}
734
735// same but caches a reg. RC_GR_READ only.
736static int rcache_get_reg_arg(int arg, sh2_reg_e r)
737{
738 int i, srcr, dstr, dstid;
739 int dirty = 0, src_dirty = 0;
740
741 dstid = rcache_get_arg_id(arg);
742 dstr = reg_temp[dstid].hreg;
743
744 // maybe already statically mapped?
745 srcr = get_reg_static(r, RC_GR_READ);
746 if (srcr != -1)
747 goto do_cache;
748
749 // maybe already cached?
750 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
751 if ((reg_temp[i].type == HR_CACHED) &&
752 reg_temp[i].greg == r)
753 {
754 srcr = reg_temp[i].hreg;
755 if (reg_temp[i].flags & HRF_DIRTY)
756 src_dirty = 1;
757 goto do_cache;
758 }
759 }
760
761 // must read
762 srcr = dstr;
763 if (gconst_check(r)) {
764 if (gconst_try_read(srcr, r))
765 dirty = 1;
766 }
767 else
768 emith_ctx_read(srcr, r * 4);
769
770do_cache:
771 if (dstr != srcr)
772 emith_move_r_r(dstr, srcr);
773#if 1
774 else
775 dirty |= src_dirty;
776
777 if (dirty)
778 // must clean, callers might want to modify the arg before call
779 emith_ctx_write(dstr, r * 4);
780#else
781 if (dirty)
782 reg_temp[dstid].flags |= HRF_DIRTY;
783#endif
784
785 reg_temp[dstid].stamp = ++rcache_counter;
786 reg_temp[dstid].type = HR_CACHED;
787 reg_temp[dstid].greg = r;
788 reg_temp[dstid].flags |= HRF_LOCKED;
789 return dstr;
790}
791
792static void rcache_free_tmp(int hr)
793{
794 int i;
795 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
796 if (reg_temp[i].hreg == hr)
797 break;
798
799 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
800 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
801 return;
802 }
803
804 reg_temp[i].type = HR_FREE;
805 reg_temp[i].flags = 0;
806}
807
808static void rcache_unlock(int hr)
809{
810 int i;
811 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
812 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
813 reg_temp[i].flags &= ~HRF_LOCKED;
814}
815
816static void rcache_unlock_all(void)
817{
818 int i;
819 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
820 reg_temp[i].flags &= ~HRF_LOCKED;
821}
822
823static void rcache_clean(void)
824{
825 int i;
826 gconst_clean();
827
828 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
829 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
830 // writeback
831 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
832 reg_temp[i].flags &= ~HRF_DIRTY;
833 }
834}
835
836static void rcache_invalidate(void)
837{
838 int i;
839 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
840 reg_temp[i].type = HR_FREE;
841 reg_temp[i].flags = 0;
842 }
843 rcache_counter = 0;
844
845 gconst_invalidate();
846}
847
848static void rcache_flush(void)
849{
850 rcache_clean();
851 rcache_invalidate();
852}
853
854// ---------------------------------------------------------------
855
856static int emit_get_rbase_and_offs(u32 a, u32 *offs)
857{
858 u32 mask = 0;
859 int poffs;
860 int hr;
861
862 poffs = dr_ctx_get_mem_ptr(a, &mask);
863 if (poffs == -1)
864 return -1;
865
866 // XXX: could use some related reg
867 hr = rcache_get_tmp();
868 emith_ctx_read(hr, poffs);
869 emith_add_r_imm(hr, a & mask & ~0xff);
870 *offs = a & 0xff; // XXX: ARM oriented..
871 return hr;
872}
873
874static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
875{
876#if PROPAGATE_CONSTANTS
877 gconst_new(dst, imm);
878#else
879 int hr = rcache_get_reg(dst, RC_GR_WRITE);
880 emith_move_r_imm(hr, imm);
881#endif
882}
883
884static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
885{
886 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
887 int hr_s = rcache_get_reg(src, RC_GR_READ);
888
889 emith_move_r_r(hr_d, hr_s);
890}
891
892// T must be clear, and comparison done just before this
893static void emit_or_t_if_eq(int srr)
894{
895 EMITH_SJMP_START(DCOND_NE);
896 emith_or_r_imm_c(DCOND_EQ, srr, T);
897 EMITH_SJMP_END(DCOND_NE);
898}
899
900// arguments must be ready
901// reg cache must be clean before call
902static int emit_memhandler_read_(int size, int ram_check)
903{
904 int arg0, arg1;
905 host_arg2reg(arg0, 0);
906
907 rcache_clean();
908
909 // must writeback cycles for poll detection stuff
910 // FIXME: rm
911 if (reg_map_g2h[SHR_SR] != -1)
912 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
913
914 arg1 = rcache_get_tmp_arg(1);
915 emith_move_r_r(arg1, CONTEXT_REG);
916
917#ifndef PDB_NET
918 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
919 int tmp = rcache_get_tmp();
920 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
921 emith_cmp_r_imm(tmp, 0x02000000);
922 switch (size) {
923 case 0: // 8
924 EMITH_SJMP3_START(DCOND_NE);
925 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
926 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
927 EMITH_SJMP3_MID(DCOND_NE);
928 emith_call_cond(DCOND_NE, sh2_drc_read8);
929 EMITH_SJMP3_END();
930 break;
931 case 1: // 16
932 EMITH_SJMP3_START(DCOND_NE);
933 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
934 EMITH_SJMP3_MID(DCOND_NE);
935 emith_call_cond(DCOND_NE, sh2_drc_read16);
936 EMITH_SJMP3_END();
937 break;
938 case 2: // 32
939 EMITH_SJMP3_START(DCOND_NE);
940 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
941 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
942 EMITH_SJMP3_MID(DCOND_NE);
943 emith_call_cond(DCOND_NE, sh2_drc_read32);
944 EMITH_SJMP3_END();
945 break;
946 }
947 }
948 else
949#endif
950 {
951 switch (size) {
952 case 0: // 8
953 emith_call(sh2_drc_read8);
954 break;
955 case 1: // 16
956 emith_call(sh2_drc_read16);
957 break;
958 case 2: // 32
959 emith_call(sh2_drc_read32);
960 break;
961 }
962 }
963 rcache_invalidate();
964
965 if (reg_map_g2h[SHR_SR] != -1)
966 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
967
968 // assuming arg0 and retval reg matches
969 return rcache_get_tmp_arg(0);
970}
971
972static int emit_memhandler_read(int size)
973{
974 return emit_memhandler_read_(size, 1);
975}
976
977static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
978{
979 int hr, hr2, ram_check = 1;
980 u32 val, offs2;
981
982 if (gconst_get(rs, &val)) {
983 hr = emit_get_rbase_and_offs(val + offs, &offs2);
984 if (hr != -1) {
985 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
986 switch (size) {
987 case 0: // 8
988 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
989 emith_sext(hr2, hr2, 8);
990 break;
991 case 1: // 16
992 emith_read16_r_r_offs(hr2, hr, offs2);
993 emith_sext(hr2, hr2, 16);
994 break;
995 case 2: // 32
996 emith_read_r_r_offs(hr2, hr, offs2);
997 emith_ror(hr2, hr2, 16);
998 break;
999 }
1000 rcache_free_tmp(hr);
1001 return hr2;
1002 }
1003
1004 ram_check = 0;
1005 }
1006
1007 hr = rcache_get_reg_arg(0, rs);
1008 if (offs != 0)
1009 emith_add_r_imm(hr, offs);
1010 hr = emit_memhandler_read_(size, ram_check);
1011 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1012 if (size != 2) {
1013 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1014 } else
1015 emith_move_r_r(hr2, hr);
1016 rcache_free_tmp(hr);
1017
1018 return hr2;
1019}
1020
1021static void emit_memhandler_write(int size, u32 pc, int delay)
1022{
1023 int ctxr;
1024 host_arg2reg(ctxr, 2);
1025 if (reg_map_g2h[SHR_SR] != -1)
1026 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1027
1028 switch (size) {
1029 case 0: // 8
1030 // XXX: consider inlining sh2_drc_write8
1031 if (delay) {
1032 emith_call(sh2_drc_write8_slot);
1033 } else {
1034 emit_move_r_imm32(SHR_PC, pc);
1035 rcache_clean();
1036 emith_call(sh2_drc_write8);
1037 }
1038 break;
1039 case 1: // 16
1040 if (delay) {
1041 emith_call(sh2_drc_write16_slot);
1042 } else {
1043 emit_move_r_imm32(SHR_PC, pc);
1044 rcache_clean();
1045 emith_call(sh2_drc_write16);
1046 }
1047 break;
1048 case 2: // 32
1049 emith_move_r_r(ctxr, CONTEXT_REG);
1050 emith_call(sh2_drc_write32);
1051 break;
1052 }
1053
1054 if (reg_map_g2h[SHR_SR] != -1)
1055 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1056 rcache_invalidate();
1057}
1058
1059// @(Rx,Ry)
1060static int emit_indirect_indexed_read(int rx, int ry, int size)
1061{
1062 int a0, t;
1063 a0 = rcache_get_reg_arg(0, rx);
1064 t = rcache_get_reg(ry, RC_GR_READ);
1065 emith_add_r_r(a0, t);
1066 return emit_memhandler_read(size);
1067}
1068
1069// read @Rn, @rm
1070static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1071{
1072 int tmp;
1073
1074 rcache_get_reg_arg(0, rn);
1075 tmp = emit_memhandler_read(size);
1076 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1077 rcache_free_tmp(tmp);
1078 tmp = rcache_get_reg(rn, RC_GR_RMW);
1079 emith_add_r_imm(tmp, 1 << size);
1080 rcache_unlock(tmp);
1081
1082 rcache_get_reg_arg(0, rm);
1083 *rmr = emit_memhandler_read(size);
1084 *rnr = rcache_get_tmp();
1085 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1086 tmp = rcache_get_reg(rm, RC_GR_RMW);
1087 emith_add_r_imm(tmp, 1 << size);
1088 rcache_unlock(tmp);
1089}
1090
1091static void emit_do_static_regs(int is_write, int tmpr)
1092{
1093 int i, r, count;
1094
1095 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1096 r = reg_map_g2h[i];
1097 if (r == -1)
1098 continue;
1099
1100 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1101 if (reg_map_g2h[i + 1] != r + 1)
1102 break;
1103 count++;
1104 }
1105
1106 if (count > 1) {
1107 // i, r point to last item
1108 if (is_write)
1109 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1110 else
1111 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1112 } else {
1113 if (is_write)
1114 emith_ctx_write(r, i * 4);
1115 else
1116 emith_ctx_read(r, i * 4);
1117 }
1118 }
1119}
1120
1121static void emit_block_entry(void)
1122{
1123 int arg0;
1124
1125 host_arg2reg(arg0, 0);
1126
1127#if (DRC_DEBUG & 8) || defined(PDB)
1128 int arg1, arg2;
1129 host_arg2reg(arg1, 1);
1130 host_arg2reg(arg2, 2);
1131
1132 emit_do_static_regs(1, arg2);
1133 emith_move_r_r(arg1, CONTEXT_REG);
1134 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1135 emith_call(sh2_drc_log_entry);
1136 rcache_invalidate();
1137#endif
1138 emith_tst_r_r(arg0, arg0);
1139 EMITH_SJMP_START(DCOND_EQ);
1140 emith_jump_reg_c(DCOND_NE, arg0);
1141 EMITH_SJMP_END(DCOND_EQ);
1142}
1143
1144#define DELAYED_OP \
1145 drcf.delayed_op = 2
1146
1147#define DELAY_SAVE_T(sr) { \
1148 emith_bic_r_imm(sr, T_save); \
1149 emith_tst_r_imm(sr, T); \
1150 EMITH_SJMP_START(DCOND_EQ); \
1151 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1152 EMITH_SJMP_END(DCOND_EQ); \
1153 drcf.use_saved_t = 1; \
1154}
1155
1156#define FLUSH_CYCLES(sr) \
1157 if (cycles > 0) { \
1158 emith_sub_r_imm(sr, cycles << 12); \
1159 cycles = 0; \
1160 }
1161
1162#define CHECK_UNHANDLED_BITS(mask) { \
1163 if ((op & (mask)) != 0) \
1164 goto default_; \
1165}
1166
1167#define GET_Fx() \
1168 ((op >> 4) & 0x0f)
1169
1170#define GET_Rm GET_Fx
1171
1172#define GET_Rn() \
1173 ((op >> 8) & 0x0f)
1174
1175#define CHECK_FX_LT(n) \
1176 if (GET_Fx() >= n) \
1177 goto default_
1178
1179static void *dr_get_pc_base(u32 pc, int is_slave);
1180
1181static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1182{
1183 // XXX: maybe use structs instead?
1184 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1185 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1186 int branch_target_blkid[MAX_LOCAL_BRANCHES];
1187 int branch_target_count = 0;
1188 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1189 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1190 int branch_patch_count = 0;
1191 u32 literal_addr[MAX_LITERALS];
1192 int literal_addr_count = 0;
1193 int pending_branch_cond = -1;
1194 int pending_branch_pc = 0;
1195 u8 op_flags[BLOCK_CYCLE_LIMIT];
1196 struct {
1197 u32 delayed_op:2;
1198 u32 test_irq:1;
1199 u32 use_saved_t:1; // delayed op modifies T
1200 } drcf = { 0, };
1201
1202 // PC of current, first, last, last_target_blk SH2 insn
1203 u32 pc, base_pc, end_pc, out_pc;
1204 void *block_entry;
1205 block_desc *this_block;
1206 u16 *dr_pc_base;
1207 int blkid_main = 0;
1208 int skip_op = 0;
1209 u32 tmp, tmp2;
1210 int cycles;
1211 int op;
1212 int i;
1213
1214 base_pc = sh2->pc;
1215
1216 // get base/validate PC
1217 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1218 if (dr_pc_base == (void *)-1) {
1219 printf("invalid PC, aborting: %08x\n", base_pc);
1220 // FIXME: be less destructive
1221 exit(1);
1222 }
1223
1224 tcache_ptr = tcache_ptrs[tcache_id];
1225 this_block = dr_add_block(base_pc, sh2->is_slave, &blkid_main);
1226 if (this_block == NULL)
1227 return NULL;
1228
1229 // predict tcache overflow
1230 tmp = tcache_ptr - tcache_bases[tcache_id];
1231 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1232 dbg(1, "tcache %d overflow", tcache_id);
1233 return NULL;
1234 }
1235
1236 block_entry = tcache_ptr;
1237 dbg(2, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
1238 tcache_id, blkid_main, base_pc, block_entry);
1239
1240 dr_link_blocks(tcache_ptr, base_pc, tcache_id);
1241
1242 // 1st pass: scan forward for local branches
1243 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc);
1244
1245 // collect branch_targets that don't land on delay slots
1246 for (pc = base_pc; pc <= end_pc; pc += 2) {
1247 if (!(OP_FLAGS(pc) & OF_TARGET))
1248 continue;
1249 if (OP_FLAGS(pc) & OF_DELAY_OP) {
1250 OP_FLAGS(pc) &= ~OF_TARGET;
1251 continue;
1252 }
1253 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1254 }
1255
1256 if (branch_target_count > 0) {
1257 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1258 memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count);
1259 }
1260
1261 // -------------------------------------------------
1262 // 2nd pass: actual compilation
1263 out_pc = 0;
1264 pc = base_pc;
1265 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
1266 {
1267 u32 tmp3, tmp4, sr;
1268
1269 if (drcf.delayed_op > 0)
1270 drcf.delayed_op--;
1271
1272 op = FETCH_OP(pc);
1273
1274 if ((OP_FLAGS(pc) & OF_TARGET) || pc == base_pc)
1275 {
1276 i = find_in_array(branch_target_pc, branch_target_count, pc);
1277 if (pc != base_pc)
1278 {
1279 /* make "subblock" - just a mid-block entry */
1280 block_desc *subblock;
1281
1282 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1283 FLUSH_CYCLES(sr);
1284 // decide if to flush rcache
1285 if ((op & 0xf0ff) == 0x4010 && FETCH_OP(pc + 2) == 0x8bfd) // DT; BF #-2
1286 rcache_clean();
1287 else
1288 rcache_flush();
1289 do_host_disasm(tcache_id);
1290
1291 dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
1292 tcache_id, branch_target_blkid[i], pc, tcache_ptr);
1293
1294 subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]);
1295 if (subblock == NULL)
1296 return NULL;
1297
1298 // since we made a block entry, link any other blocks that jump to current pc
1299 dr_link_blocks(tcache_ptr, pc, tcache_id);
1300 }
1301 if (i >= 0)
1302 branch_target_ptr[i] = tcache_ptr;
1303
1304 // must update PC
1305 emit_move_r_imm32(SHR_PC, pc);
1306 rcache_clean();
1307
1308 // check cycles
1309 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1310 emith_cmp_r_imm(sr, 0);
1311 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1312 do_host_disasm(tcache_id);
1313 rcache_unlock_all();
1314 }
1315
1316#if (DRC_DEBUG & 2)
1317 insns_compiled++;
1318#endif
1319#if (DRC_DEBUG & 4)
1320 DasmSH2(sh2dasm_buff, pc, op);
1321 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
1322#endif
1323#ifdef DRC_CMP
1324 //if (out_pc != 0 && out_pc != (u32)-1)
1325 // emit_move_r_imm32(SHR_PC, out_pc);
1326 //else
1327 if (!drcf.delayed_op) {
1328 emit_move_r_imm32(SHR_PC, pc);
1329 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1330 FLUSH_CYCLES(sr);
1331 // rcache_clean(); // FIXME
1332 rcache_flush();
1333 emit_do_static_regs(1, 0);
1334 emith_pass_arg_r(0, CONTEXT_REG);
1335 emith_call(do_sh2_cmp);
1336 }
1337#endif
1338
1339 pc += 2;
1340 cycles++;
1341
1342 if (skip_op > 0) {
1343 skip_op--;
1344 continue;
1345 }
1346
1347 switch ((op >> 12) & 0x0f)
1348 {
1349 /////////////////////////////////////////////
1350 case 0x00:
1351 switch (op & 0x0f)
1352 {
1353 case 0x02:
1354 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1355 switch (GET_Fx())
1356 {
1357 case 0: // STC SR,Rn 0000nnnn00000010
1358 tmp2 = SHR_SR;
1359 break;
1360 case 1: // STC GBR,Rn 0000nnnn00010010
1361 tmp2 = SHR_GBR;
1362 break;
1363 case 2: // STC VBR,Rn 0000nnnn00100010
1364 tmp2 = SHR_VBR;
1365 break;
1366 default:
1367 goto default_;
1368 }
1369 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1370 emith_move_r_r(tmp, tmp3);
1371 if (tmp2 == SHR_SR)
1372 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1373 goto end_op;
1374 case 0x03:
1375 CHECK_UNHANDLED_BITS(0xd0);
1376 // BRAF Rm 0000mmmm00100011
1377 // BSRF Rm 0000mmmm00000011
1378 DELAYED_OP;
1379 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1380 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1381 emith_move_r_r(tmp, tmp2);
1382 if (op & 0x20)
1383 emith_add_r_imm(tmp, pc + 2);
1384 else { // BSRF
1385 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1386 emith_move_r_imm(tmp3, pc + 2);
1387 emith_add_r_r(tmp, tmp3);
1388 }
1389 out_pc = (u32)-1;
1390 cycles++;
1391 goto end_op;
1392 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1393 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1394 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1395 rcache_clean();
1396 tmp = rcache_get_reg_arg(1, GET_Rm());
1397 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1398 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1399 emith_add_r_r(tmp2, tmp3);
1400 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1401 goto end_op;
1402 case 0x07:
1403 // MUL.L Rm,Rn 0000nnnnmmmm0111
1404 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1405 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1406 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1407 emith_mul(tmp3, tmp2, tmp);
1408 cycles++;
1409 goto end_op;
1410 case 0x08:
1411 CHECK_UNHANDLED_BITS(0xf00);
1412 switch (GET_Fx())
1413 {
1414 case 0: // CLRT 0000000000001000
1415 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1416 if (drcf.delayed_op)
1417 DELAY_SAVE_T(sr);
1418 emith_bic_r_imm(sr, T);
1419 break;
1420 case 1: // SETT 0000000000011000
1421 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1422 if (drcf.delayed_op)
1423 DELAY_SAVE_T(sr);
1424 emith_or_r_imm(sr, T);
1425 break;
1426 case 2: // CLRMAC 0000000000101000
1427 emit_move_r_imm32(SHR_MACL, 0);
1428 emit_move_r_imm32(SHR_MACH, 0);
1429 break;
1430 default:
1431 goto default_;
1432 }
1433 goto end_op;
1434 case 0x09:
1435 switch (GET_Fx())
1436 {
1437 case 0: // NOP 0000000000001001
1438 CHECK_UNHANDLED_BITS(0xf00);
1439 break;
1440 case 1: // DIV0U 0000000000011001
1441 CHECK_UNHANDLED_BITS(0xf00);
1442 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1443 if (drcf.delayed_op)
1444 DELAY_SAVE_T(sr);
1445 emith_bic_r_imm(sr, M|Q|T);
1446 break;
1447 case 2: // MOVT Rn 0000nnnn00101001
1448 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1449 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1450 emith_clear_msb(tmp2, sr, 31);
1451 break;
1452 default:
1453 goto default_;
1454 }
1455 goto end_op;
1456 case 0x0a:
1457 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1458 switch (GET_Fx())
1459 {
1460 case 0: // STS MACH,Rn 0000nnnn00001010
1461 tmp2 = SHR_MACH;
1462 break;
1463 case 1: // STS MACL,Rn 0000nnnn00011010
1464 tmp2 = SHR_MACL;
1465 break;
1466 case 2: // STS PR,Rn 0000nnnn00101010
1467 tmp2 = SHR_PR;
1468 break;
1469 default:
1470 goto default_;
1471 }
1472 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1473 emith_move_r_r(tmp, tmp2);
1474 goto end_op;
1475 case 0x0b:
1476 CHECK_UNHANDLED_BITS(0xf00);
1477 switch (GET_Fx())
1478 {
1479 case 0: // RTS 0000000000001011
1480 DELAYED_OP;
1481 emit_move_r_r(SHR_PC, SHR_PR);
1482 out_pc = (u32)-1;
1483 cycles++;
1484 break;
1485 case 1: // SLEEP 0000000000011011
1486 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1487 emith_clear_msb(tmp, tmp, 20); // clear cycles
1488 out_pc = out_pc - 2;
1489 cycles = 1;
1490 goto end_op;
1491 case 2: // RTE 0000000000101011
1492 DELAYED_OP;
1493 // pop PC
1494 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1495 // pop SR
1496 tmp = rcache_get_reg_arg(0, SHR_SP);
1497 emith_add_r_imm(tmp, 4);
1498 tmp = emit_memhandler_read(2);
1499 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1500 emith_write_sr(sr, tmp);
1501 rcache_free_tmp(tmp);
1502 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1503 emith_add_r_imm(tmp, 4*2);
1504 drcf.test_irq = 1;
1505 out_pc = (u32)-1;
1506 cycles += 3;
1507 break;
1508 default:
1509 goto default_;
1510 }
1511 goto end_op;
1512 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1513 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1514 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1515 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1516 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1517 if ((op & 3) != 2) {
1518 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1519 } else
1520 emith_move_r_r(tmp2, tmp);
1521 rcache_free_tmp(tmp);
1522 goto end_op;
1523 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1524 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1525 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1526 /* MS 16 MAC bits unused if saturated */
1527 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1528 emith_tst_r_imm(sr, S);
1529 EMITH_SJMP_START(DCOND_EQ);
1530 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1531 EMITH_SJMP_END(DCOND_EQ);
1532 rcache_unlock(sr);
1533 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1534 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1535 rcache_free_tmp(tmp2);
1536 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1537 emith_tst_r_imm(sr, S);
1538
1539 EMITH_JMP_START(DCOND_EQ);
1540 emith_asr(tmp, tmp4, 15);
1541 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1542 EMITH_SJMP_START(DCOND_GE);
1543 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1544 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1545 EMITH_SJMP_END(DCOND_GE);
1546 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1547 EMITH_SJMP_START(DCOND_LE);
1548 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1549 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1550 EMITH_SJMP_END(DCOND_LE);
1551 EMITH_JMP_END(DCOND_EQ);
1552
1553 rcache_free_tmp(tmp);
1554 cycles += 2;
1555 goto end_op;
1556 }
1557 goto default_;
1558
1559 /////////////////////////////////////////////
1560 case 0x01:
1561 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1562 rcache_clean();
1563 tmp = rcache_get_reg_arg(0, GET_Rn());
1564 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1565 if (op & 0x0f)
1566 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1567 emit_memhandler_write(2, pc, drcf.delayed_op);
1568 goto end_op;
1569
1570 case 0x02:
1571 switch (op & 0x0f)
1572 {
1573 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1574 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1575 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1576 rcache_clean();
1577 rcache_get_reg_arg(0, GET_Rn());
1578 rcache_get_reg_arg(1, GET_Rm());
1579 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1580 goto end_op;
1581 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1582 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1583 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1584 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1585 emith_sub_r_imm(tmp, (1 << (op & 3)));
1586 rcache_clean();
1587 rcache_get_reg_arg(0, GET_Rn());
1588 rcache_get_reg_arg(1, GET_Rm());
1589 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1590 goto end_op;
1591 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1592 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1593 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1594 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1595 if (drcf.delayed_op)
1596 DELAY_SAVE_T(sr);
1597 emith_bic_r_imm(sr, M|Q|T);
1598 emith_tst_r_imm(tmp2, (1<<31));
1599 EMITH_SJMP_START(DCOND_EQ);
1600 emith_or_r_imm_c(DCOND_NE, sr, Q);
1601 EMITH_SJMP_END(DCOND_EQ);
1602 emith_tst_r_imm(tmp3, (1<<31));
1603 EMITH_SJMP_START(DCOND_EQ);
1604 emith_or_r_imm_c(DCOND_NE, sr, M);
1605 EMITH_SJMP_END(DCOND_EQ);
1606 emith_teq_r_r(tmp2, tmp3);
1607 EMITH_SJMP_START(DCOND_PL);
1608 emith_or_r_imm_c(DCOND_MI, sr, T);
1609 EMITH_SJMP_END(DCOND_PL);
1610 goto end_op;
1611 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1612 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1613 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1614 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1615 if (drcf.delayed_op)
1616 DELAY_SAVE_T(sr);
1617 emith_bic_r_imm(sr, T);
1618 emith_tst_r_r(tmp2, tmp3);
1619 emit_or_t_if_eq(sr);
1620 goto end_op;
1621 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1622 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1623 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1624 emith_and_r_r(tmp, tmp2);
1625 goto end_op;
1626 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1627 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1628 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1629 emith_eor_r_r(tmp, tmp2);
1630 goto end_op;
1631 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1632 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1633 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1634 emith_or_r_r(tmp, tmp2);
1635 goto end_op;
1636 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1637 tmp = rcache_get_tmp();
1638 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1639 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1640 emith_eor_r_r_r(tmp, tmp2, tmp3);
1641 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1642 if (drcf.delayed_op)
1643 DELAY_SAVE_T(sr);
1644 emith_bic_r_imm(sr, T);
1645 emith_tst_r_imm(tmp, 0x000000ff);
1646 emit_or_t_if_eq(tmp);
1647 emith_tst_r_imm(tmp, 0x0000ff00);
1648 emit_or_t_if_eq(tmp);
1649 emith_tst_r_imm(tmp, 0x00ff0000);
1650 emit_or_t_if_eq(tmp);
1651 emith_tst_r_imm(tmp, 0xff000000);
1652 emit_or_t_if_eq(tmp);
1653 rcache_free_tmp(tmp);
1654 goto end_op;
1655 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1656 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1657 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1658 emith_lsr(tmp, tmp, 16);
1659 emith_or_r_r_lsl(tmp, tmp2, 16);
1660 goto end_op;
1661 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1662 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1663 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1664 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1665 if (op & 1) {
1666 emith_sext(tmp, tmp2, 16);
1667 } else
1668 emith_clear_msb(tmp, tmp2, 16);
1669 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1670 tmp2 = rcache_get_tmp();
1671 if (op & 1) {
1672 emith_sext(tmp2, tmp3, 16);
1673 } else
1674 emith_clear_msb(tmp2, tmp3, 16);
1675 emith_mul(tmp, tmp, tmp2);
1676 rcache_free_tmp(tmp2);
1677 goto end_op;
1678 }
1679 goto default_;
1680
1681 /////////////////////////////////////////////
1682 case 0x03:
1683 switch (op & 0x0f)
1684 {
1685 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1686 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1687 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1688 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1689 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1690 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1691 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1692 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1693 if (drcf.delayed_op)
1694 DELAY_SAVE_T(sr);
1695 emith_bic_r_imm(sr, T);
1696 emith_cmp_r_r(tmp2, tmp3);
1697 switch (op & 0x07)
1698 {
1699 case 0x00: // CMP/EQ
1700 emit_or_t_if_eq(sr);
1701 break;
1702 case 0x02: // CMP/HS
1703 EMITH_SJMP_START(DCOND_LO);
1704 emith_or_r_imm_c(DCOND_HS, sr, T);
1705 EMITH_SJMP_END(DCOND_LO);
1706 break;
1707 case 0x03: // CMP/GE
1708 EMITH_SJMP_START(DCOND_LT);
1709 emith_or_r_imm_c(DCOND_GE, sr, T);
1710 EMITH_SJMP_END(DCOND_LT);
1711 break;
1712 case 0x06: // CMP/HI
1713 EMITH_SJMP_START(DCOND_LS);
1714 emith_or_r_imm_c(DCOND_HI, sr, T);
1715 EMITH_SJMP_END(DCOND_LS);
1716 break;
1717 case 0x07: // CMP/GT
1718 EMITH_SJMP_START(DCOND_LE);
1719 emith_or_r_imm_c(DCOND_GT, sr, T);
1720 EMITH_SJMP_END(DCOND_LE);
1721 break;
1722 }
1723 goto end_op;
1724 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1725 // Q1 = carry(Rn = (Rn << 1) | T)
1726 // if Q ^ M
1727 // Q2 = carry(Rn += Rm)
1728 // else
1729 // Q2 = carry(Rn -= Rm)
1730 // Q = M ^ Q1 ^ Q2
1731 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1732 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1733 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1734 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1735 if (drcf.delayed_op)
1736 DELAY_SAVE_T(sr);
1737 emith_tpop_carry(sr, 0);
1738 emith_adcf_r_r(tmp2, tmp2);
1739 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1740 tmp4 = rcache_get_tmp();
1741 emith_and_r_r_imm(tmp4, sr, M);
1742 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1743 rcache_free_tmp(tmp4);
1744 // add or sub, invert T if carry to get Q1 ^ Q2
1745 // in: (Q ^ M) passed in Q, Q1 in T
1746 emith_sh2_div1_step(tmp2, tmp3, sr);
1747 emith_bic_r_imm(sr, Q);
1748 emith_tst_r_imm(sr, M);
1749 EMITH_SJMP_START(DCOND_EQ);
1750 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1751 EMITH_SJMP_END(DCOND_EQ);
1752 emith_tst_r_imm(sr, T);
1753 EMITH_SJMP_START(DCOND_EQ);
1754 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1755 EMITH_SJMP_END(DCOND_EQ);
1756 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1757 goto end_op;
1758 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1759 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1760 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1761 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1762 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1763 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1764 cycles++;
1765 goto end_op;
1766 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1767 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1768 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1769 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1770 if (op & 4) {
1771 emith_add_r_r(tmp, tmp2);
1772 } else
1773 emith_sub_r_r(tmp, tmp2);
1774 goto end_op;
1775 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1776 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1777 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1778 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1779 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1780 if (drcf.delayed_op)
1781 DELAY_SAVE_T(sr);
1782 if (op & 4) { // adc
1783 emith_tpop_carry(sr, 0);
1784 emith_adcf_r_r(tmp, tmp2);
1785 emith_tpush_carry(sr, 0);
1786 } else {
1787 emith_tpop_carry(sr, 1);
1788 emith_sbcf_r_r(tmp, tmp2);
1789 emith_tpush_carry(sr, 1);
1790 }
1791 goto end_op;
1792 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1793 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1794 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1795 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1796 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1797 if (drcf.delayed_op)
1798 DELAY_SAVE_T(sr);
1799 emith_bic_r_imm(sr, T);
1800 if (op & 4) {
1801 emith_addf_r_r(tmp, tmp2);
1802 } else
1803 emith_subf_r_r(tmp, tmp2);
1804 EMITH_SJMP_START(DCOND_VC);
1805 emith_or_r_imm_c(DCOND_VS, sr, T);
1806 EMITH_SJMP_END(DCOND_VC);
1807 goto end_op;
1808 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1809 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1810 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1811 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1812 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1813 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1814 cycles++;
1815 goto end_op;
1816 }
1817 goto default_;
1818
1819 /////////////////////////////////////////////
1820 case 0x04:
1821 switch (op & 0x0f)
1822 {
1823 case 0x00:
1824 switch (GET_Fx())
1825 {
1826 case 0: // SHLL Rn 0100nnnn00000000
1827 case 2: // SHAL Rn 0100nnnn00100000
1828 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1829 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1830 if (drcf.delayed_op)
1831 DELAY_SAVE_T(sr);
1832 emith_tpop_carry(sr, 0); // dummy
1833 emith_lslf(tmp, tmp, 1);
1834 emith_tpush_carry(sr, 0);
1835 goto end_op;
1836 case 1: // DT Rn 0100nnnn00010000
1837 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1838 if (drcf.delayed_op)
1839 DELAY_SAVE_T(sr);
1840#ifndef DRC_CMP
1841 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
1842 if (gconst_get(GET_Rn(), &tmp)) {
1843 // XXX: limit burned cycles
1844 emit_move_r_imm32(GET_Rn(), 0);
1845 emith_or_r_imm(sr, T);
1846 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
1847 skip_op = 1;
1848 }
1849 else
1850 emith_sh2_dtbf_loop();
1851 goto end_op;
1852 }
1853#endif
1854 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1855 emith_bic_r_imm(sr, T);
1856 emith_subf_r_imm(tmp, 1);
1857 emit_or_t_if_eq(sr);
1858 goto end_op;
1859 }
1860 goto default_;
1861 case 0x01:
1862 switch (GET_Fx())
1863 {
1864 case 0: // SHLR Rn 0100nnnn00000001
1865 case 2: // SHAR Rn 0100nnnn00100001
1866 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1867 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1868 if (drcf.delayed_op)
1869 DELAY_SAVE_T(sr);
1870 emith_tpop_carry(sr, 0); // dummy
1871 if (op & 0x20) {
1872 emith_asrf(tmp, tmp, 1);
1873 } else
1874 emith_lsrf(tmp, tmp, 1);
1875 emith_tpush_carry(sr, 0);
1876 goto end_op;
1877 case 1: // CMP/PZ Rn 0100nnnn00010001
1878 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1879 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1880 if (drcf.delayed_op)
1881 DELAY_SAVE_T(sr);
1882 emith_bic_r_imm(sr, T);
1883 emith_cmp_r_imm(tmp, 0);
1884 EMITH_SJMP_START(DCOND_LT);
1885 emith_or_r_imm_c(DCOND_GE, sr, T);
1886 EMITH_SJMP_END(DCOND_LT);
1887 goto end_op;
1888 }
1889 goto default_;
1890 case 0x02:
1891 case 0x03:
1892 switch (op & 0x3f)
1893 {
1894 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1895 tmp = SHR_MACH;
1896 break;
1897 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1898 tmp = SHR_MACL;
1899 break;
1900 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1901 tmp = SHR_PR;
1902 break;
1903 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1904 tmp = SHR_SR;
1905 cycles++;
1906 break;
1907 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1908 tmp = SHR_GBR;
1909 cycles++;
1910 break;
1911 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1912 tmp = SHR_VBR;
1913 cycles++;
1914 break;
1915 default:
1916 goto default_;
1917 }
1918 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1919 emith_sub_r_imm(tmp2, 4);
1920 rcache_clean();
1921 rcache_get_reg_arg(0, GET_Rn());
1922 tmp3 = rcache_get_reg_arg(1, tmp);
1923 if (tmp == SHR_SR)
1924 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1925 emit_memhandler_write(2, pc, drcf.delayed_op);
1926 goto end_op;
1927 case 0x04:
1928 case 0x05:
1929 switch (op & 0x3f)
1930 {
1931 case 0x04: // ROTL Rn 0100nnnn00000100
1932 case 0x05: // ROTR Rn 0100nnnn00000101
1933 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1934 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1935 if (drcf.delayed_op)
1936 DELAY_SAVE_T(sr);
1937 emith_tpop_carry(sr, 0); // dummy
1938 if (op & 1) {
1939 emith_rorf(tmp, tmp, 1);
1940 } else
1941 emith_rolf(tmp, tmp, 1);
1942 emith_tpush_carry(sr, 0);
1943 goto end_op;
1944 case 0x24: // ROTCL Rn 0100nnnn00100100
1945 case 0x25: // ROTCR Rn 0100nnnn00100101
1946 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1947 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1948 if (drcf.delayed_op)
1949 DELAY_SAVE_T(sr);
1950 emith_tpop_carry(sr, 0);
1951 if (op & 1) {
1952 emith_rorcf(tmp);
1953 } else
1954 emith_rolcf(tmp);
1955 emith_tpush_carry(sr, 0);
1956 goto end_op;
1957 case 0x15: // CMP/PL Rn 0100nnnn00010101
1958 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1959 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1960 if (drcf.delayed_op)
1961 DELAY_SAVE_T(sr);
1962 emith_bic_r_imm(sr, T);
1963 emith_cmp_r_imm(tmp, 0);
1964 EMITH_SJMP_START(DCOND_LE);
1965 emith_or_r_imm_c(DCOND_GT, sr, T);
1966 EMITH_SJMP_END(DCOND_LE);
1967 goto end_op;
1968 }
1969 goto default_;
1970 case 0x06:
1971 case 0x07:
1972 switch (op & 0x3f)
1973 {
1974 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
1975 tmp = SHR_MACH;
1976 break;
1977 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
1978 tmp = SHR_MACL;
1979 break;
1980 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
1981 tmp = SHR_PR;
1982 break;
1983 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
1984 tmp = SHR_SR;
1985 cycles += 2;
1986 break;
1987 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
1988 tmp = SHR_GBR;
1989 cycles += 2;
1990 break;
1991 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
1992 tmp = SHR_VBR;
1993 cycles += 2;
1994 break;
1995 default:
1996 goto default_;
1997 }
1998 rcache_get_reg_arg(0, GET_Rn());
1999 tmp2 = emit_memhandler_read(2);
2000 if (tmp == SHR_SR) {
2001 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2002 if (drcf.delayed_op)
2003 DELAY_SAVE_T(sr);
2004 emith_write_sr(sr, tmp2);
2005 drcf.test_irq = 1;
2006 } else {
2007 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2008 emith_move_r_r(tmp, tmp2);
2009 }
2010 rcache_free_tmp(tmp2);
2011 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2012 emith_add_r_imm(tmp, 4);
2013 goto end_op;
2014 case 0x08:
2015 case 0x09:
2016 switch (GET_Fx())
2017 {
2018 case 0:
2019 // SHLL2 Rn 0100nnnn00001000
2020 // SHLR2 Rn 0100nnnn00001001
2021 tmp = 2;
2022 break;
2023 case 1:
2024 // SHLL8 Rn 0100nnnn00011000
2025 // SHLR8 Rn 0100nnnn00011001
2026 tmp = 8;
2027 break;
2028 case 2:
2029 // SHLL16 Rn 0100nnnn00101000
2030 // SHLR16 Rn 0100nnnn00101001
2031 tmp = 16;
2032 break;
2033 default:
2034 goto default_;
2035 }
2036 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2037 if (op & 1) {
2038 emith_lsr(tmp2, tmp2, tmp);
2039 } else
2040 emith_lsl(tmp2, tmp2, tmp);
2041 goto end_op;
2042 case 0x0a:
2043 switch (GET_Fx())
2044 {
2045 case 0: // LDS Rm,MACH 0100mmmm00001010
2046 tmp2 = SHR_MACH;
2047 break;
2048 case 1: // LDS Rm,MACL 0100mmmm00011010
2049 tmp2 = SHR_MACL;
2050 break;
2051 case 2: // LDS Rm,PR 0100mmmm00101010
2052 tmp2 = SHR_PR;
2053 break;
2054 default:
2055 goto default_;
2056 }
2057 emit_move_r_r(tmp2, GET_Rn());
2058 goto end_op;
2059 case 0x0b:
2060 switch (GET_Fx())
2061 {
2062 case 0: // JSR @Rm 0100mmmm00001011
2063 case 2: // JMP @Rm 0100mmmm00101011
2064 DELAYED_OP;
2065 if (!(op & 0x20))
2066 emit_move_r_imm32(SHR_PR, pc + 2);
2067 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
2068 out_pc = (u32)-1;
2069 cycles++;
2070 break;
2071 case 1: // TAS.B @Rn 0100nnnn00011011
2072 // XXX: is TAS working on 32X?
2073 rcache_get_reg_arg(0, GET_Rn());
2074 tmp = emit_memhandler_read(0);
2075 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2076 if (drcf.delayed_op)
2077 DELAY_SAVE_T(sr);
2078 emith_bic_r_imm(sr, T);
2079 emith_cmp_r_imm(tmp, 0);
2080 emit_or_t_if_eq(sr);
2081 rcache_clean();
2082 emith_or_r_imm(tmp, 0x80);
2083 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2084 emith_move_r_r(tmp2, tmp);
2085 rcache_free_tmp(tmp);
2086 rcache_get_reg_arg(0, GET_Rn());
2087 emit_memhandler_write(0, pc, drcf.delayed_op);
2088 cycles += 3;
2089 break;
2090 default:
2091 goto default_;
2092 }
2093 goto end_op;
2094 case 0x0e:
2095 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2096 switch (GET_Fx())
2097 {
2098 case 0: // LDC Rm,SR 0100mmmm00001110
2099 tmp2 = SHR_SR;
2100 break;
2101 case 1: // LDC Rm,GBR 0100mmmm00011110
2102 tmp2 = SHR_GBR;
2103 break;
2104 case 2: // LDC Rm,VBR 0100mmmm00101110
2105 tmp2 = SHR_VBR;
2106 break;
2107 default:
2108 goto default_;
2109 }
2110 if (tmp2 == SHR_SR) {
2111 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2112 if (drcf.delayed_op)
2113 DELAY_SAVE_T(sr);
2114 emith_write_sr(sr, tmp);
2115 drcf.test_irq = 1;
2116 } else {
2117 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2118 emith_move_r_r(tmp2, tmp);
2119 }
2120 goto end_op;
2121 case 0x0f:
2122 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2123 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2124 emith_sext(tmp, tmp, 16);
2125 emith_sext(tmp2, tmp2, 16);
2126 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2127 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2128 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2129 rcache_free_tmp(tmp2);
2130 // XXX: MACH should be untouched when S is set?
2131 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2132 emith_tst_r_imm(sr, S);
2133 EMITH_JMP_START(DCOND_EQ);
2134
2135 emith_asr(tmp, tmp3, 31);
2136 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2137 EMITH_JMP_START(DCOND_EQ);
2138 emith_move_r_imm(tmp3, 0x80000000);
2139 emith_tst_r_r(tmp4, tmp4);
2140 EMITH_SJMP_START(DCOND_MI);
2141 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2142 EMITH_SJMP_END(DCOND_MI);
2143 EMITH_JMP_END(DCOND_EQ);
2144
2145 EMITH_JMP_END(DCOND_EQ);
2146 rcache_free_tmp(tmp);
2147 cycles += 2;
2148 goto end_op;
2149 }
2150 goto default_;
2151
2152 /////////////////////////////////////////////
2153 case 0x05:
2154 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2155 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2156 goto end_op;
2157
2158 /////////////////////////////////////////////
2159 case 0x06:
2160 switch (op & 0x0f)
2161 {
2162 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2163 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2164 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2165 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2166 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2167 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2168 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2169 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2170 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2171 emith_add_r_imm(tmp, (1 << (op & 3)));
2172 }
2173 goto end_op;
2174 case 0x03:
2175 case 0x07 ... 0x0f:
2176 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2177 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2178 switch (op & 0x0f)
2179 {
2180 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2181 emith_move_r_r(tmp2, tmp);
2182 break;
2183 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2184 emith_mvn_r_r(tmp2, tmp);
2185 break;
2186 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2187 tmp3 = tmp2;
2188 if (tmp == tmp2)
2189 tmp3 = rcache_get_tmp();
2190 tmp4 = rcache_get_tmp();
2191 emith_lsr(tmp3, tmp, 16);
2192 emith_or_r_r_lsl(tmp3, tmp, 24);
2193 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2194 emith_or_r_r_lsl(tmp3, tmp4, 8);
2195 emith_rol(tmp2, tmp3, 16);
2196 rcache_free_tmp(tmp4);
2197 if (tmp == tmp2)
2198 rcache_free_tmp(tmp3);
2199 break;
2200 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2201 emith_rol(tmp2, tmp, 16);
2202 break;
2203 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2204 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2205 if (drcf.delayed_op)
2206 DELAY_SAVE_T(sr);
2207 emith_tpop_carry(sr, 1);
2208 emith_negcf_r_r(tmp2, tmp);
2209 emith_tpush_carry(sr, 1);
2210 break;
2211 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2212 emith_neg_r_r(tmp2, tmp);
2213 break;
2214 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2215 emith_clear_msb(tmp2, tmp, 24);
2216 break;
2217 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2218 emith_clear_msb(tmp2, tmp, 16);
2219 break;
2220 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2221 emith_sext(tmp2, tmp, 8);
2222 break;
2223 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2224 emith_sext(tmp2, tmp, 16);
2225 break;
2226 }
2227 goto end_op;
2228 }
2229 goto default_;
2230
2231 /////////////////////////////////////////////
2232 case 0x07:
2233 // ADD #imm,Rn 0111nnnniiiiiiii
2234 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2235 if (op & 0x80) { // adding negative
2236 emith_sub_r_imm(tmp, -op & 0xff);
2237 } else
2238 emith_add_r_imm(tmp, op & 0xff);
2239 goto end_op;
2240
2241 /////////////////////////////////////////////
2242 case 0x08:
2243 switch (op & 0x0f00)
2244 {
2245 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2246 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2247 rcache_clean();
2248 tmp = rcache_get_reg_arg(0, GET_Rm());
2249 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2250 tmp3 = (op & 0x100) >> 8;
2251 if (op & 0x0f)
2252 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2253 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2254 goto end_op;
2255 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2256 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2257 tmp = (op & 0x100) >> 8;
2258 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2259 goto end_op;
2260 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2261 // XXX: could use cmn
2262 tmp = rcache_get_tmp();
2263 tmp2 = rcache_get_reg(0, RC_GR_READ);
2264 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2265 if (drcf.delayed_op)
2266 DELAY_SAVE_T(sr);
2267 emith_move_r_imm_s8(tmp, op & 0xff);
2268 emith_bic_r_imm(sr, T);
2269 emith_cmp_r_r(tmp2, tmp);
2270 emit_or_t_if_eq(sr);
2271 rcache_free_tmp(tmp);
2272 goto end_op;
2273 case 0x0d00: // BT/S label 10001101dddddddd
2274 case 0x0f00: // BF/S label 10001111dddddddd
2275 DELAYED_OP;
2276 // fallthrough
2277 case 0x0900: // BT label 10001001dddddddd
2278 case 0x0b00: // BF label 10001011dddddddd
2279 // will handle conditional branches later
2280 pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
2281 i = ((signed int)(op << 24) >> 23);
2282 pending_branch_pc = pc + i + 2;
2283 goto end_op;
2284 }
2285 goto default_;
2286
2287 /////////////////////////////////////////////
2288 case 0x09:
2289 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
2290 tmp = pc + (op & 0xff) * 2 + 2;
2291#if PROPAGATE_CONSTANTS
2292 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2293 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2294 gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp));
2295 }
2296 else
2297#endif
2298 {
2299 tmp2 = rcache_get_tmp_arg(0);
2300 emith_move_r_imm(tmp2, tmp);
2301 tmp2 = emit_memhandler_read(1);
2302 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2303 emith_sext(tmp3, tmp2, 16);
2304 rcache_free_tmp(tmp2);
2305 }
2306 goto end_op;
2307
2308 /////////////////////////////////////////////
2309 case 0x0a:
2310 // BRA label 1010dddddddddddd
2311 DELAYED_OP;
2312 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2313 tmp = ((signed int)(op << 20) >> 19);
2314 out_pc = pc + tmp + 2;
2315 if (tmp == (u32)-4)
2316 emith_clear_msb(sr, sr, 20); // burn cycles
2317 cycles++;
2318 break;
2319
2320 /////////////////////////////////////////////
2321 case 0x0b:
2322 // BSR label 1011dddddddddddd
2323 DELAYED_OP;
2324 emit_move_r_imm32(SHR_PR, pc + 2);
2325 tmp = ((signed int)(op << 20) >> 19);
2326 out_pc = pc + tmp + 2;
2327 cycles++;
2328 break;
2329
2330 /////////////////////////////////////////////
2331 case 0x0c:
2332 switch (op & 0x0f00)
2333 {
2334 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2335 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2336 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2337 rcache_clean();
2338 tmp = rcache_get_reg_arg(0, SHR_GBR);
2339 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2340 tmp3 = (op & 0x300) >> 8;
2341 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2342 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2343 goto end_op;
2344 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2345 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2346 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2347 tmp = (op & 0x300) >> 8;
2348 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2349 goto end_op;
2350 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2351 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2352 emith_sub_r_imm(tmp, 4*2);
2353 // push SR
2354 tmp = rcache_get_reg_arg(0, SHR_SP);
2355 emith_add_r_imm(tmp, 4);
2356 tmp = rcache_get_reg_arg(1, SHR_SR);
2357 emith_clear_msb(tmp, tmp, 22);
2358 emit_memhandler_write(2, pc, drcf.delayed_op);
2359 // push PC
2360 rcache_get_reg_arg(0, SHR_SP);
2361 tmp = rcache_get_tmp_arg(1);
2362 emith_move_r_imm(tmp, pc);
2363 emit_memhandler_write(2, pc, drcf.delayed_op);
2364 // obtain new PC
2365 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2366 out_pc = (u32)-1;
2367 cycles += 7;
2368 goto end_op;
2369 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2370 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2371 goto end_op;
2372 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2373 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2374 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2375 if (drcf.delayed_op)
2376 DELAY_SAVE_T(sr);
2377 emith_bic_r_imm(sr, T);
2378 emith_tst_r_imm(tmp, op & 0xff);
2379 emit_or_t_if_eq(sr);
2380 goto end_op;
2381 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2382 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2383 emith_and_r_imm(tmp, op & 0xff);
2384 goto end_op;
2385 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2386 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2387 emith_eor_r_imm(tmp, op & 0xff);
2388 goto end_op;
2389 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2390 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2391 emith_or_r_imm(tmp, op & 0xff);
2392 goto end_op;
2393 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2394 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2395 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2396 if (drcf.delayed_op)
2397 DELAY_SAVE_T(sr);
2398 emith_bic_r_imm(sr, T);
2399 emith_tst_r_imm(tmp, op & 0xff);
2400 emit_or_t_if_eq(sr);
2401 rcache_free_tmp(tmp);
2402 cycles += 2;
2403 goto end_op;
2404 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2405 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2406 emith_and_r_imm(tmp, op & 0xff);
2407 goto end_rmw_op;
2408 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2409 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2410 emith_eor_r_imm(tmp, op & 0xff);
2411 goto end_rmw_op;
2412 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2413 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2414 emith_or_r_imm(tmp, op & 0xff);
2415 end_rmw_op:
2416 tmp2 = rcache_get_tmp_arg(1);
2417 emith_move_r_r(tmp2, tmp);
2418 rcache_free_tmp(tmp);
2419 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2420 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2421 emith_add_r_r(tmp3, tmp4);
2422 emit_memhandler_write(0, pc, drcf.delayed_op);
2423 cycles += 2;
2424 goto end_op;
2425 }
2426 goto default_;
2427
2428 /////////////////////////////////////////////
2429 case 0x0d:
2430 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2431 tmp = (pc + (op & 0xff) * 4 + 2) & ~3;
2432#if PROPAGATE_CONSTANTS
2433 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2434 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2435 gconst_new(GET_Rn(), FETCH32(tmp));
2436 }
2437 else
2438#endif
2439 {
2440 tmp2 = rcache_get_tmp_arg(0);
2441 emith_move_r_imm(tmp2, tmp);
2442 tmp2 = emit_memhandler_read(2);
2443 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2444 emith_move_r_r(tmp3, tmp2);
2445 rcache_free_tmp(tmp2);
2446 }
2447 goto end_op;
2448
2449 /////////////////////////////////////////////
2450 case 0x0e:
2451 // MOV #imm,Rn 1110nnnniiiiiiii
2452 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2453 goto end_op;
2454
2455 default:
2456 default_:
2457 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2458 sh2->is_slave ? 's' : 'm', op, pc - 2);
2459 break;
2460 }
2461
2462end_op:
2463 rcache_unlock_all();
2464
2465 // conditional branch handling (with/without delay)
2466 if (pending_branch_cond != -1 && drcf.delayed_op != 2)
2467 {
2468 u32 target_pc = pending_branch_pc;
2469 int ctaken = drcf.delayed_op ? 1 : 2;
2470 void *target;
2471
2472 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2473 FLUSH_CYCLES(sr);
2474 if (drcf.use_saved_t)
2475 emith_tst_r_imm(sr, T_save);
2476 else
2477 emith_tst_r_imm(sr, T);
2478
2479 // handle cycles
2480 emith_sub_r_imm_c(pending_branch_cond, sr, ctaken<<12);
2481 rcache_clean();
2482
2483#if LINK_BRANCHES
2484 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
2485 // local branch
2486 // XXX: jumps back can be linked already
2487 branch_patch_pc[branch_patch_count] = target_pc;
2488 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2489 emith_jump_cond_patchable(pending_branch_cond, tcache_ptr);
2490
2491 branch_patch_count++;
2492 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2493 dbg(1, "warning: too many local branches");
2494 break;
2495 }
2496 }
2497 else
2498#endif
2499 {
2500 // can't resolve branch locally, make a block exit
2501 emit_move_r_imm32(SHR_PC, target_pc);
2502 rcache_clean();
2503
2504 target = dr_prepare_ext_branch(target_pc, sh2, tcache_id);
2505 if (target == NULL)
2506 return NULL;
2507 emith_jump_cond_patchable(pending_branch_cond, target);
2508 }
2509
2510 drcf.use_saved_t = 0;
2511 pending_branch_cond = -1;
2512 }
2513
2514 // test irq?
2515 // XXX: delay slots..
2516 if (drcf.test_irq && drcf.delayed_op != 2) {
2517 if (!drcf.delayed_op)
2518 emit_move_r_imm32(SHR_PC, pc);
2519 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2520 FLUSH_CYCLES(sr);
2521 rcache_flush();
2522 emith_call(sh2_drc_test_irq);
2523 drcf.test_irq = 0;
2524 }
2525
2526 do_host_disasm(tcache_id);
2527
2528 if (out_pc != 0 && drcf.delayed_op != 2)
2529 break;
2530 }
2531
2532 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2533 FLUSH_CYCLES(tmp);
2534 rcache_flush();
2535
2536 if (out_pc == (u32)-1) {
2537 // indirect jump -> back to dispatcher
2538 emith_jump(sh2_drc_dispatcher);
2539 } else {
2540 void *target;
2541 if (out_pc == 0)
2542 out_pc = pc;
2543 emit_move_r_imm32(SHR_PC, out_pc);
2544 rcache_flush();
2545
2546 target = dr_prepare_ext_branch(out_pc, sh2, tcache_id);
2547 if (target == NULL)
2548 return NULL;
2549 emith_jump_patchable(target);
2550 }
2551
2552 // link local branches
2553 for (i = 0; i < branch_patch_count; i++) {
2554 void *target;
2555 int t;
2556 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2557 target = branch_target_ptr[t];
2558 if (target == NULL) {
2559 // flush pc and go back to dispatcher (this should no longer happen)
2560 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2561 target = tcache_ptr;
2562 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2563 rcache_flush();
2564 emith_jump(sh2_drc_dispatcher);
2565 }
2566 emith_jump_patch(branch_patch_ptr[i], target);
2567 }
2568
2569 end_pc = pc;
2570
2571 // mark memory blocks as containing compiled code
2572 // override any overlay blocks as they become unreachable anyway
2573 if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000)
2574 {
2575 u16 *drc_ram_blk = NULL;
2576 u32 mask = 0, shift = 0;
2577
2578 if (tcache_id != 0) {
2579 // data array, BIOS
2580 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2581 shift = SH2_DRCBLK_DA_SHIFT;
2582 mask = 0xfff;
2583 }
2584 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) {
2585 // SDRAM
2586 drc_ram_blk = Pico32xMem->drcblk_ram;
2587 shift = SH2_DRCBLK_RAM_SHIFT;
2588 mask = 0x3ffff;
2589 }
2590
2591 drc_ram_blk[(base_pc >> shift) & mask] = (blkid_main << 1) | 1;
2592 for (pc = base_pc + 2; pc < end_pc; pc += 2)
2593 drc_ram_blk[(pc >> shift) & mask] = blkid_main << 1;
2594
2595 // mark subblocks
2596 for (i = 0; i < branch_target_count; i++)
2597 if (branch_target_blkid[i] != 0)
2598 drc_ram_blk[(branch_target_pc[i] >> shift) & mask] =
2599 (branch_target_blkid[i] << 1) | 1;
2600
2601 // mark literals
2602 for (i = 0; i < literal_addr_count; i++) {
2603 tmp = literal_addr[i];
2604 drc_ram_blk[(tmp >> shift) & mask] = blkid_main << 1;
2605 if (!(tmp & 3)) // assume long
2606 drc_ram_blk[((tmp + 2) >> shift) & mask] = blkid_main << 1;
2607 }
2608 }
2609
2610 tcache_ptrs[tcache_id] = tcache_ptr;
2611
2612 host_instructions_updated(block_entry, tcache_ptr);
2613
2614 do_host_disasm(tcache_id);
2615 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2616 tcache_id, block_counts[tcache_id],
2617 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2618 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
2619 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2620 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2621/*
2622 printf("~~~\n");
2623 tcache_dsm_ptrs[tcache_id] = block_entry;
2624 do_host_disasm(tcache_id);
2625 printf("~~~\n");
2626*/
2627
2628#if (DRC_DEBUG & 4)
2629 fflush(stdout);
2630#endif
2631
2632 return block_entry;
2633}
2634
2635static void sh2_generate_utils(void)
2636{
2637 int arg0, arg1, arg2, sr, tmp;
2638 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
2639
2640 sh2_drc_write32 = p32x_sh2_write32;
2641 sh2_drc_read8 = p32x_sh2_read8;
2642 sh2_drc_read16 = p32x_sh2_read16;
2643 sh2_drc_read32 = p32x_sh2_read32;
2644
2645 host_arg2reg(arg0, 0);
2646 host_arg2reg(arg1, 1);
2647 host_arg2reg(arg2, 2);
2648 emith_move_r_r(arg0, arg0); // nop
2649
2650 // sh2_drc_exit(void)
2651 sh2_drc_exit = (void *)tcache_ptr;
2652 emit_do_static_regs(1, arg2);
2653 emith_sh2_drc_exit();
2654
2655 // sh2_drc_dispatcher(void)
2656 sh2_drc_dispatcher = (void *)tcache_ptr;
2657 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2658 emith_cmp_r_imm(sr, 0);
2659 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2660 rcache_invalidate();
2661 emith_ctx_read(arg0, SHR_PC * 4);
2662 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2663 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2664 emith_call(dr_lookup_block);
2665 emit_block_entry();
2666 // lookup failed, call sh2_translate()
2667 emith_move_r_r(arg0, CONTEXT_REG);
2668 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2669 emith_call(sh2_translate);
2670 emit_block_entry();
2671 // sh2_translate() failed, flush cache and retry
2672 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2673 emith_call(flush_tcache);
2674 emith_move_r_r(arg0, CONTEXT_REG);
2675 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2676 emith_call(sh2_translate);
2677 emit_block_entry();
2678 // XXX: can't translate, fail
2679 emith_call(dr_failure);
2680
2681 // sh2_drc_test_irq(void)
2682 // assumes it's called from main function (may jump to dispatcher)
2683 sh2_drc_test_irq = (void *)tcache_ptr;
2684 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2685 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2686 emith_lsr(arg0, sr, I_SHIFT);
2687 emith_and_r_imm(arg0, 0x0f);
2688 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2689 EMITH_SJMP_START(DCOND_GT);
2690 emith_ret_c(DCOND_LE); // nope, return
2691 EMITH_SJMP_END(DCOND_GT);
2692 // adjust SP
2693 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2694 emith_sub_r_imm(tmp, 4*2);
2695 rcache_clean();
2696 // push SR
2697 tmp = rcache_get_reg_arg(0, SHR_SP);
2698 emith_add_r_imm(tmp, 4);
2699 tmp = rcache_get_reg_arg(1, SHR_SR);
2700 emith_clear_msb(tmp, tmp, 22);
2701 emith_move_r_r(arg2, CONTEXT_REG);
2702 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2703 rcache_invalidate();
2704 // push PC
2705 rcache_get_reg_arg(0, SHR_SP);
2706 emith_ctx_read(arg1, SHR_PC * 4);
2707 emith_move_r_r(arg2, CONTEXT_REG);
2708 emith_call(p32x_sh2_write32);
2709 rcache_invalidate();
2710 // update I, cycles, do callback
2711 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2712 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2713 emith_bic_r_imm(sr, I);
2714 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2715 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2716 rcache_flush();
2717 emith_move_r_r(arg0, CONTEXT_REG);
2718 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2719 // obtain new PC
2720 emith_lsl(arg0, arg0, 2);
2721 emith_ctx_read(arg1, SHR_VBR * 4);
2722 emith_add_r_r(arg0, arg1);
2723 emit_memhandler_read(2);
2724 emith_ctx_write(arg0, SHR_PC * 4);
2725#ifdef __i386__
2726 emith_add_r_imm(xSP, 4); // fix stack
2727#endif
2728 emith_jump(sh2_drc_dispatcher);
2729 rcache_invalidate();
2730
2731 // sh2_drc_entry(SH2 *sh2)
2732 sh2_drc_entry = (void *)tcache_ptr;
2733 emith_sh2_drc_entry();
2734 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2735 emit_do_static_regs(0, arg2);
2736 emith_call(sh2_drc_test_irq);
2737 emith_jump(sh2_drc_dispatcher);
2738
2739 // write-caused irq detection
2740 sh2_drc_write_end = tcache_ptr;
2741 emith_tst_r_r(arg0, arg0);
2742 EMITH_SJMP_START(DCOND_NE);
2743 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2744 EMITH_SJMP_END(DCOND_NE);
2745 emith_call(sh2_drc_test_irq);
2746 emith_jump_ctx(offsetof(SH2, drc_tmp));
2747
2748 // write-caused irq detection for writes in delay slot
2749 sh2_drc_write_slot_end = tcache_ptr;
2750 emith_tst_r_r(arg0, arg0);
2751 EMITH_SJMP_START(DCOND_NE);
2752 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2753 EMITH_SJMP_END(DCOND_NE);
2754 // just burn cycles to get back to dispatcher after branch is handled
2755 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2756 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2757 emith_clear_msb(sr, sr, 20); // clear cycles
2758 rcache_flush();
2759 emith_jump_ctx(offsetof(SH2, drc_tmp));
2760
2761 // sh2_drc_write8(u32 a, u32 d)
2762 sh2_drc_write8 = (void *)tcache_ptr;
2763 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2764 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2765 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2766
2767 // sh2_drc_write16(u32 a, u32 d)
2768 sh2_drc_write16 = (void *)tcache_ptr;
2769 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2770 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2771 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2772
2773 // sh2_drc_write8_slot(u32 a, u32 d)
2774 sh2_drc_write8_slot = (void *)tcache_ptr;
2775 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2776 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2777 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2778
2779 // sh2_drc_write16_slot(u32 a, u32 d)
2780 sh2_drc_write16_slot = (void *)tcache_ptr;
2781 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2782 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2783 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2784
2785#ifdef PDB_NET
2786 // debug
2787 #define MAKE_READ_WRAPPER(func) { \
2788 void *tmp = (void *)tcache_ptr; \
2789 emith_push_ret(); \
2790 emith_call(func); \
2791 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2792 emith_addf_r_r(arg2, arg0); \
2793 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2794 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2795 emith_adc_r_imm(arg2, 0x01000000); \
2796 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2797 emith_pop_and_ret(); \
2798 func = tmp; \
2799 }
2800 #define MAKE_WRITE_WRAPPER(func) { \
2801 void *tmp = (void *)tcache_ptr; \
2802 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2803 emith_addf_r_r(arg2, arg1); \
2804 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2805 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2806 emith_adc_r_imm(arg2, 0x01000000); \
2807 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2808 emith_move_r_r(arg2, CONTEXT_REG); \
2809 emith_jump(func); \
2810 func = tmp; \
2811 }
2812
2813 MAKE_READ_WRAPPER(sh2_drc_read8);
2814 MAKE_READ_WRAPPER(sh2_drc_read16);
2815 MAKE_READ_WRAPPER(sh2_drc_read32);
2816 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2817 MAKE_WRITE_WRAPPER(sh2_drc_write8_slot);
2818 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2819 MAKE_WRITE_WRAPPER(sh2_drc_write16_slot);
2820 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2821#if (DRC_DEBUG & 4)
2822 host_dasm_new_symbol(sh2_drc_read8);
2823 host_dasm_new_symbol(sh2_drc_read16);
2824 host_dasm_new_symbol(sh2_drc_read32);
2825 host_dasm_new_symbol(sh2_drc_write32);
2826#endif
2827#endif
2828
2829 rcache_invalidate();
2830#if (DRC_DEBUG & 4)
2831 host_dasm_new_symbol(sh2_drc_entry);
2832 host_dasm_new_symbol(sh2_drc_dispatcher);
2833 host_dasm_new_symbol(sh2_drc_exit);
2834 host_dasm_new_symbol(sh2_drc_test_irq);
2835 host_dasm_new_symbol(sh2_drc_write_end);
2836 host_dasm_new_symbol(sh2_drc_write_slot_end);
2837 host_dasm_new_symbol(sh2_drc_write8);
2838 host_dasm_new_symbol(sh2_drc_write8_slot);
2839 host_dasm_new_symbol(sh2_drc_write16);
2840 host_dasm_new_symbol(sh2_drc_write16_slot);
2841#endif
2842}
2843
2844static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id)
2845{
2846 void *tmp;
2847
2848 // XXX: kill links somehow?
2849 dbg(2, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]);
2850 if (bd->addr == 0 || bd->tcache_ptr == NULL) {
2851 dbg(1, " killing dead block!? %08x", bd->addr);
2852 return bd->tcache_ptr;
2853 }
2854
2855 // since we never reuse space of dead blocks,
2856 // insert jump to dispatcher for blocks that are linked to this point
2857 //emith_jump_at(bd->tcache_ptr, sh2_drc_dispatcher);
2858
2859 // attempt to handle self-modifying blocks by exiting at nearest known PC
2860 tmp = tcache_ptr;
2861 tcache_ptr = bd->tcache_ptr;
2862 emit_move_r_imm32(SHR_PC, bd->addr);
2863 rcache_flush();
2864 emith_jump(sh2_drc_dispatcher);
2865 tcache_ptr = tmp;
2866
2867 bd->addr = 0;
2868 return bd->tcache_ptr;
2869}
2870
2871static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2872{
2873 //block_link *bl = block_links[tcache_id];
2874 //int bl_count = block_link_counts[tcache_id];
2875 block_desc *btab = block_tables[tcache_id];
2876 u16 *p = drc_ram_blk + ((a & mask) >> shift);
2877 u16 *pmax = drc_ram_blk + (mask >> shift);
2878 void *tcache_min, *tcache_max;
2879 int zeros;
2880 u16 *pt;
2881
2882 // Figure out what the main block is, as subblocks also have the flag set.
2883 // This relies on sub having single entry. It's possible that innocent
2884 // block might be hit, but that's not such a big deal.
2885 if ((p[0] >> 1) != (p[1] >> 1)) {
2886 for (; p > drc_ram_blk; p--)
2887 if (p[-1] == 0 || (p[-1] >> 1) == (*p >> 1))
2888 break;
2889 }
2890 pt = p;
2891
2892 for (; p > drc_ram_blk; p--)
2893 if ((*p & 1))
2894 break;
2895
2896 if (!(*p & 1)) {
2897 dbg(1, "smc rm: missing block start for %08x?", a);
2898 p = pt;
2899 }
2900
2901 if (*p == 0)
2902 return;
2903
2904 tcache_min = tcache_max = sh2_smc_rm_block_entry(&btab[*p >> 1], tcache_id);
2905 *p = 0;
2906
2907 for (p++, zeros = 0; p < pmax && zeros < MAX_LITERAL_OFFSET / 2; p++) {
2908 int id = *p >> 1;
2909 if (id == 0) {
2910 // there can be holes because games sometimes keep variables
2911 // directly in literal pool and we don't inline them to avoid recompile
2912 // (Star Wars Arcade)
2913 zeros++;
2914 continue;
2915 }
2916 if (*p & 1) {
2917 if (id == (p[1] >> 1))
2918 // hit other block
2919 break;
2920 tcache_max = sh2_smc_rm_block_entry(&btab[id], tcache_id);
2921 }
2922 *p = 0;
2923 }
2924
2925 host_instructions_updated(tcache_min, (void *)((char *)tcache_max + 4*4 + 4));
2926}
2927
2928void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2929{
2930 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2931 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
2932}
2933
2934void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2935{
2936 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2937 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
2938 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
2939}
2940
2941int sh2_execute(SH2 *sh2c, int cycles)
2942{
2943 int ret_cycles;
2944
2945 sh2c->cycles_timeslice = cycles;
2946
2947 // cycles are kept in SHR_SR unused bits (upper 20)
2948 // bit11 contains T saved for delay slot
2949 // others are usual SH2 flags
2950 sh2c->sr &= 0x3f3;
2951 sh2c->sr |= cycles << 12;
2952 sh2_drc_entry(sh2c);
2953
2954 // TODO: irq cycles
2955 ret_cycles = (signed int)sh2c->sr >> 12;
2956 if (ret_cycles > 0)
2957 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
2958
2959 return sh2c->cycles_timeslice - ret_cycles;
2960}
2961
2962#if (DRC_DEBUG & 2)
2963void block_stats(void)
2964{
2965 int c, b, i, total = 0;
2966
2967 printf("block stats:\n");
2968 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2969 for (i = 0; i < block_counts[b]; i++)
2970 if (block_tables[b][i].addr != 0)
2971 total += block_tables[b][i].refcount;
2972
2973 for (c = 0; c < 10; c++) {
2974 block_desc *blk, *maxb = NULL;
2975 int max = 0;
2976 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
2977 for (i = 0; i < block_counts[b]; i++) {
2978 blk = &block_tables[b][i];
2979 if (blk->addr != 0 && blk->refcount > max) {
2980 max = blk->refcount;
2981 maxb = blk;
2982 }
2983 }
2984 }
2985 if (maxb == NULL)
2986 break;
2987 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
2988 (double)maxb->refcount / total * 100.0);
2989 maxb->refcount = 0;
2990 }
2991
2992 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2993 for (i = 0; i < block_counts[b]; i++)
2994 block_tables[b][i].refcount = 0;
2995}
2996#else
2997#define block_stats()
2998#endif
2999
3000void sh2_drc_flush_all(void)
3001{
3002 block_stats();
3003 flush_tcache(0);
3004 flush_tcache(1);
3005 flush_tcache(2);
3006}
3007
3008void sh2_drc_mem_setup(SH2 *sh2)
3009{
3010 // fill the convenience pointers
3011 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3012 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3013 sh2->p_sdram = Pico32xMem->sdram;
3014 sh2->p_rom = Pico.rom;
3015}
3016
3017int sh2_drc_init(SH2 *sh2)
3018{
3019 int i;
3020
3021 if (block_tables[0] == NULL)
3022 {
3023 for (i = 0; i < TCACHE_BUFFERS; i++) {
3024 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3025 if (block_tables[i] == NULL)
3026 goto fail;
3027 // max 2 block links (exits) per block
3028 block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0]));
3029 if (block_links[i] == NULL)
3030 goto fail;
3031 }
3032 memset(block_counts, 0, sizeof(block_counts));
3033 memset(block_link_counts, 0, sizeof(block_link_counts));
3034
3035 drc_cmn_init();
3036 tcache_ptr = tcache;
3037 sh2_generate_utils();
3038 host_instructions_updated(tcache, tcache_ptr);
3039
3040 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3041 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3042 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3043
3044 // tmp
3045 PicoOpt |= POPT_DIS_VDP_FIFO;
3046
3047#if (DRC_DEBUG & 4)
3048 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3049 tcache_dsm_ptrs[i] = tcache_bases[i];
3050 // disasm the utils
3051 tcache_dsm_ptrs[0] = tcache;
3052 do_host_disasm(0);
3053#endif
3054#if (DRC_DEBUG & 1)
3055 hash_collisions = 0;
3056#endif
3057 }
3058
3059 if (hash_table == NULL) {
3060 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
3061 if (hash_table == NULL)
3062 goto fail;
3063 }
3064
3065 return 0;
3066
3067fail:
3068 sh2_drc_finish(sh2);
3069 return -1;
3070}
3071
3072void sh2_drc_finish(SH2 *sh2)
3073{
3074 int i;
3075
3076 if (block_tables[0] != NULL) {
3077 block_stats();
3078
3079 for (i = 0; i < TCACHE_BUFFERS; i++) {
3080#if (DRC_DEBUG & 4)
3081 printf("~~~ tcache %d\n", i);
3082 tcache_dsm_ptrs[i] = tcache_bases[i];
3083 tcache_ptr = tcache_ptrs[i];
3084 do_host_disasm(i);
3085#endif
3086
3087 if (block_tables[i] != NULL)
3088 free(block_tables[i]);
3089 block_tables[i] = NULL;
3090 if (block_links[i] == NULL)
3091 free(block_links[i]);
3092 block_links[i] = NULL;
3093 }
3094
3095 drc_cmn_cleanup();
3096 }
3097
3098 if (hash_table != NULL) {
3099 free(hash_table);
3100 hash_table = NULL;
3101 }
3102}
3103
3104#endif /* DRC_SH2 */
3105
3106static void *dr_get_pc_base(u32 pc, int is_slave)
3107{
3108 void *ret = NULL;
3109 u32 mask = 0;
3110
3111 if ((pc & ~0x7ff) == 0) {
3112 // BIOS
3113 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3114 mask = 0x7ff;
3115 }
3116 else if ((pc & 0xfffff000) == 0xc0000000) {
3117 // data array
3118 ret = Pico32xMem->data_array[is_slave];
3119 mask = 0xfff;
3120 }
3121 else if ((pc & 0xc6000000) == 0x06000000) {
3122 // SDRAM
3123 ret = Pico32xMem->sdram;
3124 mask = 0x03ffff;
3125 }
3126 else if ((pc & 0xc6000000) == 0x02000000) {
3127 // ROM
3128 ret = Pico.rom;
3129 mask = 0x3fffff;
3130 }
3131
3132 if (ret == NULL)
3133 return (void *)-1; // NULL is valid value
3134
3135 return (char *)ret - (pc & ~mask);
3136}
3137
3138void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc)
3139{
3140 u16 *dr_pc_base;
3141 u32 pc, target, op;
3142 int cycles;
3143
3144 memset(op_flags, 0, BLOCK_CYCLE_LIMIT);
3145
3146 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3147
3148 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT-1; cycles++, pc += 2) {
3149 op = FETCH_OP(pc);
3150 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
3151 signed int offs = ((signed int)(op << 20) >> 19);
3152 pc += 2;
3153 OP_FLAGS(pc) |= OF_DELAY_OP;
3154 target = pc + offs + 2;
3155 if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
3156 OP_FLAGS(target) |= OF_TARGET;
3157 break;
3158 }
3159 if ((op & 0xf000) == 0) {
3160 op &= 0xff;
3161 if (op == 0x1b) // SLEEP
3162 break;
3163 // BRAF, BSRF, RTS, RTE
3164 if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) {
3165 pc += 2;
3166 OP_FLAGS(pc) |= OF_DELAY_OP;
3167 break;
3168 }
3169 continue;
3170 }
3171 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
3172 pc += 2;
3173 OP_FLAGS(pc) |= OF_DELAY_OP;
3174 break;
3175 }
3176 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
3177 signed int offs = ((signed int)(op << 24) >> 23);
3178 if (op & 0x0400)
3179 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
3180 target = pc + offs + 4;
3181 if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
3182 OP_FLAGS(target) |= OF_TARGET;
3183 }
3184 if ((op & 0xff00) == 0xc300) // TRAPA
3185 break;
3186 }
3187 *end_pc = pc;
3188}
3189
3190// vim:shiftwidth=2:ts=2:expandtab
fast MegaDrive/MegaCD/32X emulator