| | 1 | int sh2_drc_init(SH2 *sh2); |
| | 2 | void sh2_drc_finish(SH2 *sh2); |
| | 3 | void sh2_drc_wcheck_ram(u32 a, unsigned len, SH2 *sh2); |
| | 4 | void sh2_drc_wcheck_da(u32 a, unsigned len, SH2 *sh2); |
| | 5 | |
| | 6 | #ifdef DRC_SH2 |
| | 7 | void sh2_drc_mem_setup(SH2 *sh2); |
| | 8 | void sh2_drc_flush_all(void); |
| | 9 | #else |
| | 10 | #define sh2_drc_mem_setup(x) |
| | 11 | #define sh2_drc_flush_all() |
| | 12 | #define sh2_drc_frame() |
| | 13 | #endif |
| | 14 | |
| | 15 | #define BLOCK_INSN_LIMIT 1024 |
| | 16 | |
| | 17 | /* op_flags */ |
| | 18 | #define OF_DELAY_OP (1 << 0) |
| | 19 | #define OF_BTARGET (1 << 1) |
| | 20 | #define OF_LOOP (3 << 2) // NONE, IDLE, DELAY, POLL loop |
| | 21 | #define OF_B_IN_DS (1 << 4) |
| | 22 | #define OF_DELAY_INSN (1 << 5) // DT, (TODO ADD+CMP?) |
| | 23 | #define OF_POLL_INSN (1 << 6) // MOV @(...),Rn (no post increment), TST @(...) |
| | 24 | #define OF_BASIC_LOOP (1 << 7) // pinnable loop without any branches in it |
| | 25 | |
| | 26 | #define OF_IDLE_LOOP (1 << 2) |
| | 27 | #define OF_DELAY_LOOP (2 << 2) |
| | 28 | #define OF_POLL_LOOP (3 << 2) |
| | 29 | |
| | 30 | u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc, |
| | 31 | u32 *base_literals, u32 *end_literals); |
| | 32 | |
| | 33 | #if defined(DRC_SH2) && defined(__GNUC__) && !defined(__clang__) |
| | 34 | // direct access to some host CPU registers used by the DRC if gcc is used. |
| | 35 | // XXX MUST match SHR_SR definitions in cpu/drc/emit_*.c; should be moved there |
| | 36 | // XXX yuck, there's no portable way to determine register size. Use long long |
| | 37 | // if target is 64 bit and data model is ILP32 or LLP64(windows), else long |
| | 38 | #if defined(__arm__) |
| | 39 | #define DRC_SR_REG "r10" |
| | 40 | #define DRC_REG_LL 0 // 32 bit |
| | 41 | #elif defined(__aarch64__) |
| | 42 | #define DRC_SR_REG "r28" |
| | 43 | #define DRC_REG_LL (__ILP32__ || _WIN32) |
| | 44 | #elif defined(__mips__) |
| | 45 | #define DRC_SR_REG "s6" |
| | 46 | #define DRC_REG_LL (_MIPS_SZPTR > _MIPS_SZLONG) // (_MIPS_SIM == _ABIN32) |
| | 47 | #elif defined(__riscv__) || defined(__riscv) |
| | 48 | #define DRC_SR_REG "s11" |
| | 49 | #define DRC_REG_LL 0 // no ABI for (__ILP32__ && __riscv_xlen != 32) |
| | 50 | #elif defined(__powerpc__) || defined(__ppc__) || defined(__PPC__) |
| | 51 | #define DRC_SR_REG "r28" |
| | 52 | #define DRC_REG_LL 0 // no ABI for __ILP32__ |
| | 53 | //i386 only has 8 registers and reserving one of them causes too much spilling |
| | 54 | //#elif defined(__i386__) |
| | 55 | //#define DRC_SR_REG "edi" |
| | 56 | //#define DRC_REG_LL 0 // 32 bit |
| | 57 | #elif defined(__x86_64__) |
| | 58 | #define DRC_SR_REG "rbx" |
| | 59 | #define DRC_REG_LL (__ILP32__ || _WIN32) |
| | 60 | #endif |
| | 61 | #endif |
| | 62 | |
| | 63 | #ifdef DRC_SR_REG |
| | 64 | // XXX this is more clear but produces too much overhead for slow platforms |
| | 65 | extern void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2); |
| | 66 | extern void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2); |
| | 67 | |
| | 68 | // NB: sh2_sr MUST have register size if optimizing with -O3 (-fif-conversion) |
| | 69 | #if DRC_REG_LL |
| | 70 | #define DRC_DECLARE_SR register long long _sh2_sr asm(DRC_SR_REG) |
| | 71 | #else |
| | 72 | #define DRC_DECLARE_SR register long _sh2_sr asm(DRC_SR_REG) |
| | 73 | #endif |
| | 74 | // NB: save/load SR register only when DRC is executing and not in DMA access |
| | 75 | #define DRC_SAVE_SR(sh2) \ |
| | 76 | if (likely((sh2->state & (SH2_IN_DRC|SH2_STATE_SLEEP)) == SH2_IN_DRC)) \ |
| | 77 | sh2->sr = (s32)_sh2_sr |
| | 78 | // host_call(sh2_drc_save_sr, (SH2 *))(sh2) |
| | 79 | #define DRC_RESTORE_SR(sh2) \ |
| | 80 | if (likely((sh2->state & (SH2_IN_DRC|SH2_STATE_SLEEP)) == SH2_IN_DRC)) \ |
| | 81 | _sh2_sr = (s32)sh2->sr |
| | 82 | // host_call(sh2_drc_restore_sr, (SH2 *))(sh2) |
| | 83 | #else |
| | 84 | #define DRC_DECLARE_SR |
| | 85 | #define DRC_SAVE_SR(sh2) |
| | 86 | #define DRC_RESTORE_SR(sh2) |
| | 87 | #endif |
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