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android: make armeabi buildable
[picodrive.git] / cpu / sh2 / mame / sh2.c
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1/*****************************************************************************\r
2 *\r
3 * sh2.c\r
4 * Portable Hitachi SH-2 (SH7600 family) emulator\r
5 *\r
6 * Copyright Juergen Buchmueller <pullmoll@t-online.de>,\r
7 * all rights reserved.\r
8 *\r
9 * - This source code is released as freeware for non-commercial purposes.\r
10 * - You are free to use and redistribute this code in modified or\r
11 * unmodified form, provided you list me in the credits.\r
12 * - If you modify this source code, you must add a notice to each modified\r
13 * source file that it has been changed. If you're a nice person, you\r
14 * will clearly mark each change too. :)\r
15 * - If you wish to use this for commercial purposes, please contact me at\r
16 * pullmoll@t-online.de\r
17 * - The author of this copywritten work reserves the right to change the\r
18 * terms of its usage and license at any time, including retroactively\r
19 * - This entire notice must remain in the source code.\r
20 *\r
21 * This work is based on <tiraniddo@hotmail.com> C/C++ implementation of\r
22 * the SH-2 CPU core and was adapted to the MAME CPU core requirements.\r
23 * Thanks also go to Chuck Mason <chukjr@sundail.net> and Olivier Galibert\r
24 * <galibert@pobox.com> for letting me peek into their SEMU code :-)\r
25 *\r
26 *****************************************************************************/\r
27\r
28/*****************************************************************************\r
29 Changes\r
30 20130129 Angelo Salese\r
31 - added illegal opcode exception handling, side effect of some Saturn games\r
32 on loading like Feda or Falcom Classics Vol. 1\r
33 (i.e. Master CPU Incautiously transfers memory from CD to work RAM H, and\r
34 wipes out Slave CPU program code too while at it).\r
35\r
36 20051129 Mariusz Wojcieszek\r
37 - introduced memory_decrypted_read_word() for opcode fetching\r
38\r
39 20050813 Mariusz Wojcieszek\r
40 - fixed 64 bit / 32 bit division in division unit\r
41\r
42 20031015 O. Galibert\r
43 - dma fixes, thanks to sthief\r
44\r
45 20031013 O. Galibert, A. Giles\r
46 - timer fixes\r
47 - multi-cpu simplifications\r
48\r
49 20030915 O. Galibert\r
50 - fix DMA1 irq vector\r
51 - ignore writes to DRCRx\r
52 - fix cpu number issues\r
53 - fix slave/master recognition\r
54 - fix wrong-cpu-in-context problem with the timers\r
55\r
56 20021020 O. Galibert\r
57 - DMA implementation, lightly tested\r
58 - delay slot in debugger fixed\r
59 - add divide box mirrors\r
60 - Nicola-ify the indentation\r
61 - Uncrapify sh2_internal_*\r
62 - Put back nmi support that had been lost somehow\r
63\r
64 20020914 R. Belmont\r
65 - Initial SH2 internal timers implementation, based on code by O. Galibert.\r
66 Makes music work in galspanic4/s/s2, panic street, cyvern, other SKNS games.\r
67 - Fix to external division, thanks to "spice" on the E2J board.\r
68 Corrects behavior of s1945ii turret boss.\r
69\r
70 20020302 Olivier Galibert (galibert@mame.net)\r
71 - Fixed interrupt in delay slot\r
72 - Fixed rotcr\r
73 - Fixed div1\r
74 - Fixed mulu\r
75 - Fixed negc\r
76\r
77 20020301 R. Belmont\r
78 - Fixed external division\r
79\r
80 20020225 Olivier Galibert (galibert@mame.net)\r
81 - Fixed interrupt handling\r
82\r
83 20010207 Sylvain Glaize (mokona@puupuu.org)\r
84\r
85 - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)\r
86 - Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)\r
87 reason : when the two high bits of the address are set, access is\r
88 done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM\r
89 sets the stack pointer here, using these addresses as usual RAM access.\r
90\r
91 No real cache support has been added.\r
92 - Read/Write memory format correction (_bew to _bedw) (see also SH2\r
93 definition in cpuintrf.c and DasmSH2(..) in sh2dasm.c )\r
94\r
95 20010623 James Forshaw (TyRaNiD@totalise.net)\r
96\r
97 - Modified operation of sh2_exception. Done cause mame irq system is stupid, and\r
98 doesnt really seem designed for any more than 8 interrupt lines.\r
99\r
100 20010701 James Forshaw (TyRaNiD@totalise.net)\r
101\r
102 - Fixed DIV1 operation. Q bit now correctly generated\r
103\r
104 20020218 Added save states (mokona@puupuu.org)\r
105\r
106 *****************************************************************************/\r
107\r
108//#include "debugger.h"\r
109//#include "sh2.h"\r
110//#include "sh2comn.h"\r
111#define INLINE static\r
112\r
113//CPU_DISASSEMBLE( sh2 );\r
114\r
115#ifndef USE_SH2DRC\r
116\r
117/* speed up delay loops, bail out of tight loops */\r
118//#define BUSY_LOOP_HACKS 1\r
119\r
120#define VERBOSE 0\r
121\r
122#define LOG(x) do { if (VERBOSE) logerror x; } while (0)\r
123\r
124#if 0\r
125INLINE UINT8 RB(sh2_state *sh2, offs_t A)\r
126{\r
127 if (A >= 0xe0000000)\r
128 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);\r
129\r
130 if (A >= 0xc0000000)\r
131 return sh2->program->read_byte(A);\r
132\r
133 if (A >= 0x40000000)\r
134 return 0xa5;\r
135\r
136 return sh2->program->read_byte(A & AM);\r
137}\r
138\r
139INLINE UINT16 RW(sh2_state *sh2, offs_t A)\r
140{\r
141 if (A >= 0xe0000000)\r
142 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);\r
143\r
144 if (A >= 0xc0000000)\r
145 return sh2->program->read_word(A);\r
146\r
147 if (A >= 0x40000000)\r
148 return 0xa5a5;\r
149\r
150 return sh2->program->read_word(A & AM);\r
151}\r
152\r
153INLINE UINT32 RL(sh2_state *sh2, offs_t A)\r
154{\r
155 if (A >= 0xe0000000)\r
156 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);\r
157\r
158 if (A >= 0xc0000000)\r
159 return sh2->program->read_dword(A);\r
160\r
161 if (A >= 0x40000000)\r
162 return 0xa5a5a5a5;\r
163\r
164 return sh2->program->read_dword(A & AM);\r
165}\r
166\r
167INLINE void WB(sh2_state *sh2, offs_t A, UINT8 V)\r
168{\r
169 if (A >= 0xe0000000)\r
170 {\r
171 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));\r
172 return;\r
173 }\r
174\r
175 if (A >= 0xc0000000)\r
176 {\r
177 sh2->program->write_byte(A,V);\r
178 return;\r
179 }\r
180\r
181 if (A >= 0x40000000)\r
182 return;\r
183\r
184 sh2->program->write_byte(A & AM,V);\r
185}\r
186\r
187INLINE void WW(sh2_state *sh2, offs_t A, UINT16 V)\r
188{\r
189 if (A >= 0xe0000000)\r
190 {\r
191 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));\r
192 return;\r
193 }\r
194\r
195 if (A >= 0xc0000000)\r
196 {\r
197 sh2->program->write_word(A,V);\r
198 return;\r
199 }\r
200\r
201 if (A >= 0x40000000)\r
202 return;\r
203\r
204 sh2->program->write_word(A & AM,V);\r
205}\r
206\r
207INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)\r
208{\r
209 if (A >= 0xe0000000)\r
210 {\r
211 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);\r
212 return;\r
213 }\r
214\r
215 if (A >= 0xc0000000)\r
216 {\r
217 sh2->program->write_dword(A,V);\r
218 return;\r
219 }\r
220\r
221 if (A >= 0x40000000)\r
222 return;\r
223\r
224 sh2->program->write_dword(A & AM,V);\r
225}\r
226#endif\r
227\r
228/* code cycles t-bit\r
229 * 0011 nnnn mmmm 1100 1 -\r
230 * ADD Rm,Rn\r
231 */\r
232INLINE void ADD(sh2_state *sh2, UINT32 m, UINT32 n)\r
233{\r
234 sh2->r[n] += sh2->r[m];\r
235}\r
236\r
237/* code cycles t-bit\r
238 * 0111 nnnn iiii iiii 1 -\r
239 * ADD #imm,Rn\r
240 */\r
241INLINE void ADDI(sh2_state *sh2, UINT32 i, UINT32 n)\r
242{\r
243 sh2->r[n] += (INT32)(INT16)(INT8)i;\r
244}\r
245\r
246/* code cycles t-bit\r
247 * 0011 nnnn mmmm 1110 1 carry\r
248 * ADDC Rm,Rn\r
249 */\r
250INLINE void ADDC(sh2_state *sh2, UINT32 m, UINT32 n)\r
251{\r
252 UINT32 tmp0, tmp1;\r
253\r
254 tmp1 = sh2->r[n] + sh2->r[m];\r
255 tmp0 = sh2->r[n];\r
256 sh2->r[n] = tmp1 + (sh2->sr & T);\r
257 if (tmp0 > tmp1)\r
258 sh2->sr |= T;\r
259 else\r
260 sh2->sr &= ~T;\r
261 if (tmp1 > sh2->r[n])\r
262 sh2->sr |= T;\r
263}\r
264\r
265/* code cycles t-bit\r
266 * 0011 nnnn mmmm 1111 1 overflow\r
267 * ADDV Rm,Rn\r
268 */\r
269INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)\r
270{\r
271 INT32 dest, src, ans;\r
272\r
273 if ((INT32) sh2->r[n] >= 0)\r
274 dest = 0;\r
275 else\r
276 dest = 1;\r
277 if ((INT32) sh2->r[m] >= 0)\r
278 src = 0;\r
279 else\r
280 src = 1;\r
281 src += dest;\r
282 sh2->r[n] += sh2->r[m];\r
283 if ((INT32) sh2->r[n] >= 0)\r
284 ans = 0;\r
285 else\r
286 ans = 1;\r
287 ans += dest;\r
288 if (src == 0 || src == 2)\r
289 {\r
290 if (ans == 1)\r
291 sh2->sr |= T;\r
292 else\r
293 sh2->sr &= ~T;\r
294 }\r
295 else\r
296 sh2->sr &= ~T;\r
297}\r
298\r
299/* code cycles t-bit\r
300 * 0010 nnnn mmmm 1001 1 -\r
301 * AND Rm,Rn\r
302 */\r
303INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)\r
304{\r
305 sh2->r[n] &= sh2->r[m];\r
306}\r
307\r
308\r
309/* code cycles t-bit\r
310 * 1100 1001 iiii iiii 1 -\r
311 * AND #imm,R0\r
312 */\r
313INLINE void ANDI(sh2_state *sh2, UINT32 i)\r
314{\r
315 sh2->r[0] &= i;\r
316}\r
317\r
318/* code cycles t-bit\r
319 * 1100 1101 iiii iiii 1 -\r
320 * AND.B #imm,@(R0,GBR)\r
321 */\r
322INLINE void ANDM(sh2_state *sh2, UINT32 i)\r
323{\r
324 UINT32 temp;\r
325\r
326 sh2->ea = sh2->gbr + sh2->r[0];\r
327 temp = i & RB( sh2, sh2->ea );\r
328 WB( sh2, sh2->ea, temp );\r
329 sh2->icount -= 2;\r
330}\r
331\r
332/* code cycles t-bit\r
333 * 1000 1011 dddd dddd 3/1 -\r
334 * BF disp8\r
335 */\r
336INLINE void BF(sh2_state *sh2, UINT32 d)\r
337{\r
338 if ((sh2->sr & T) == 0)\r
339 {\r
340 INT32 disp = ((INT32)d << 24) >> 24;\r
341 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
342 sh2->icount -= 2;\r
343 }\r
344}\r
345\r
346/* code cycles t-bit\r
347 * 1000 1111 dddd dddd 3/1 -\r
348 * BFS disp8\r
349 */\r
350INLINE void BFS(sh2_state *sh2, UINT32 d)\r
351{\r
352 sh2->delay = sh2->pc;\r
353 sh2->pc += 2;\r
354\r
355 if ((sh2->sr & T) == 0)\r
356 {\r
357 INT32 disp = ((INT32)d << 24) >> 24;\r
358 sh2->pc = sh2->ea = sh2->pc + disp * 2;\r
359 sh2->icount--;\r
360 }\r
361}\r
362\r
363/* code cycles t-bit\r
364 * 1010 dddd dddd dddd 2 -\r
365 * BRA disp12\r
366 */\r
367INLINE void BRA(sh2_state *sh2, UINT32 d)\r
368{\r
369 INT32 disp = ((INT32)d << 20) >> 20;\r
370\r
371#if BUSY_LOOP_HACKS\r
372 if (disp == -2)\r
373 {\r
374 UINT32 next_opcode = RW( sh2, sh2->ppc & AM );\r
375 /* BRA $\r
376 * NOP\r
377 */\r
378 if (next_opcode == 0x0009)\r
379 sh2->icount %= 3; /* cycles for BRA $ and NOP taken (3) */\r
380 }\r
381#endif\r
382 sh2->delay = sh2->pc;\r
383 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
384 sh2->icount--;\r
385}\r
386\r
387/* code cycles t-bit\r
388 * 0000 mmmm 0010 0011 2 -\r
389 * BRAF Rm\r
390 */\r
391INLINE void BRAF(sh2_state *sh2, UINT32 m)\r
392{\r
393 sh2->delay = sh2->pc;\r
394 sh2->pc += sh2->r[m] + 2;\r
395 sh2->icount--;\r
396}\r
397\r
398/* code cycles t-bit\r
399 * 1011 dddd dddd dddd 2 -\r
400 * BSR disp12\r
401 */\r
402INLINE void BSR(sh2_state *sh2, UINT32 d)\r
403{\r
404 INT32 disp = ((INT32)d << 20) >> 20;\r
405\r
406 sh2->pr = sh2->pc + 2;\r
407 sh2->delay = sh2->pc;\r
408 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
409 sh2->icount--;\r
410}\r
411\r
412/* code cycles t-bit\r
413 * 0000 mmmm 0000 0011 2 -\r
414 * BSRF Rm\r
415 */\r
416INLINE void BSRF(sh2_state *sh2, UINT32 m)\r
417{\r
418 sh2->pr = sh2->pc + 2;\r
419 sh2->delay = sh2->pc;\r
420 sh2->pc += sh2->r[m] + 2;\r
421 sh2->icount--;\r
422}\r
423\r
424/* code cycles t-bit\r
425 * 1000 1001 dddd dddd 3/1 -\r
426 * BT disp8\r
427 */\r
428INLINE void BT(sh2_state *sh2, UINT32 d)\r
429{\r
430 if ((sh2->sr & T) != 0)\r
431 {\r
432 INT32 disp = ((INT32)d << 24) >> 24;\r
433 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
434 sh2->icount -= 2;\r
435 }\r
436}\r
437\r
438/* code cycles t-bit\r
439 * 1000 1101 dddd dddd 2/1 -\r
440 * BTS disp8\r
441 */\r
442INLINE void BTS(sh2_state *sh2, UINT32 d)\r
443{\r
444 sh2->delay = sh2->pc;\r
445 sh2->pc += 2;\r
446\r
447 if ((sh2->sr & T) != 0)\r
448 {\r
449 INT32 disp = ((INT32)d << 24) >> 24;\r
450 sh2->pc = sh2->ea = sh2->pc + disp * 2;\r
451 sh2->icount--;\r
452 }\r
453}\r
454\r
455/* code cycles t-bit\r
456 * 0000 0000 0010 1000 1 -\r
457 * CLRMAC\r
458 */\r
459INLINE void CLRMAC(sh2_state *sh2)\r
460{\r
461 sh2->mach = 0;\r
462 sh2->macl = 0;\r
463}\r
464\r
465/* code cycles t-bit\r
466 * 0000 0000 0000 1000 1 -\r
467 * CLRT\r
468 */\r
469INLINE void CLRT(sh2_state *sh2)\r
470{\r
471 sh2->sr &= ~T;\r
472}\r
473\r
474/* code cycles t-bit\r
475 * 0011 nnnn mmmm 0000 1 comparison result\r
476 * CMP_EQ Rm,Rn\r
477 */\r
478INLINE void CMPEQ(sh2_state *sh2, UINT32 m, UINT32 n)\r
479{\r
480 if (sh2->r[n] == sh2->r[m])\r
481 sh2->sr |= T;\r
482 else\r
483 sh2->sr &= ~T;\r
484}\r
485\r
486/* code cycles t-bit\r
487 * 0011 nnnn mmmm 0011 1 comparison result\r
488 * CMP_GE Rm,Rn\r
489 */\r
490INLINE void CMPGE(sh2_state *sh2, UINT32 m, UINT32 n)\r
491{\r
492 if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])\r
493 sh2->sr |= T;\r
494 else\r
495 sh2->sr &= ~T;\r
496}\r
497\r
498/* code cycles t-bit\r
499 * 0011 nnnn mmmm 0111 1 comparison result\r
500 * CMP_GT Rm,Rn\r
501 */\r
502INLINE void CMPGT(sh2_state *sh2, UINT32 m, UINT32 n)\r
503{\r
504 if ((INT32) sh2->r[n] > (INT32) sh2->r[m])\r
505 sh2->sr |= T;\r
506 else\r
507 sh2->sr &= ~T;\r
508}\r
509\r
510/* code cycles t-bit\r
511 * 0011 nnnn mmmm 0110 1 comparison result\r
512 * CMP_HI Rm,Rn\r
513 */\r
514INLINE void CMPHI(sh2_state *sh2, UINT32 m, UINT32 n)\r
515{\r
516 if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])\r
517 sh2->sr |= T;\r
518 else\r
519 sh2->sr &= ~T;\r
520}\r
521\r
522/* code cycles t-bit\r
523 * 0011 nnnn mmmm 0010 1 comparison result\r
524 * CMP_HS Rm,Rn\r
525 */\r
526INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)\r
527{\r
528 if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])\r
529 sh2->sr |= T;\r
530 else\r
531 sh2->sr &= ~T;\r
532}\r
533\r
534\r
535/* code cycles t-bit\r
536 * 0100 nnnn 0001 0101 1 comparison result\r
537 * CMP_PL Rn\r
538 */\r
539INLINE void CMPPL(sh2_state *sh2, UINT32 n)\r
540{\r
541 if ((INT32) sh2->r[n] > 0)\r
542 sh2->sr |= T;\r
543 else\r
544 sh2->sr &= ~T;\r
545}\r
546\r
547/* code cycles t-bit\r
548 * 0100 nnnn 0001 0001 1 comparison result\r
549 * CMP_PZ Rn\r
550 */\r
551INLINE void CMPPZ(sh2_state *sh2, UINT32 n)\r
552{\r
553 if ((INT32) sh2->r[n] >= 0)\r
554 sh2->sr |= T;\r
555 else\r
556 sh2->sr &= ~T;\r
557}\r
558\r
559/* code cycles t-bit\r
560 * 0010 nnnn mmmm 1100 1 comparison result\r
561 * CMP_STR Rm,Rn\r
562 */\r
563INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)\r
564 {\r
565 UINT32 temp;\r
566 INT32 HH, HL, LH, LL;\r
567 temp = sh2->r[n] ^ sh2->r[m];\r
568 HH = (temp >> 24) & 0xff;\r
569 HL = (temp >> 16) & 0xff;\r
570 LH = (temp >> 8) & 0xff;\r
571 LL = temp & 0xff;\r
572 if (HH && HL && LH && LL)\r
573 sh2->sr &= ~T;\r
574 else\r
575 sh2->sr |= T;\r
576 }\r
577\r
578\r
579/* code cycles t-bit\r
580 * 1000 1000 iiii iiii 1 comparison result\r
581 * CMP/EQ #imm,R0\r
582 */\r
583INLINE void CMPIM(sh2_state *sh2, UINT32 i)\r
584{\r
585 UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;\r
586\r
587 if (sh2->r[0] == imm)\r
588 sh2->sr |= T;\r
589 else\r
590 sh2->sr &= ~T;\r
591}\r
592\r
593/* code cycles t-bit\r
594 * 0010 nnnn mmmm 0111 1 calculation result\r
595 * DIV0S Rm,Rn\r
596 */\r
597INLINE void DIV0S(sh2_state *sh2, UINT32 m, UINT32 n)\r
598{\r
599 if ((sh2->r[n] & 0x80000000) == 0)\r
600 sh2->sr &= ~Q;\r
601 else\r
602 sh2->sr |= Q;\r
603 if ((sh2->r[m] & 0x80000000) == 0)\r
604 sh2->sr &= ~M;\r
605 else\r
606 sh2->sr |= M;\r
607 if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)\r
608 sh2->sr |= T;\r
609 else\r
610 sh2->sr &= ~T;\r
611}\r
612\r
613/* code cycles t-bit\r
614 * 0000 0000 0001 1001 1 0\r
615 * DIV0U\r
616 */\r
617INLINE void DIV0U(sh2_state *sh2)\r
618{\r
619 sh2->sr &= ~(M | Q | T);\r
620}\r
621\r
622/* code cycles t-bit\r
623 * 0011 nnnn mmmm 0100 1 calculation result\r
624 * DIV1 Rm,Rn\r
625 */\r
626INLINE void DIV1(sh2_state *sh2, UINT32 m, UINT32 n)\r
627{\r
628 UINT32 tmp0;\r
629 UINT32 old_q;\r
630\r
631 old_q = sh2->sr & Q;\r
632 if (0x80000000 & sh2->r[n])\r
633 sh2->sr |= Q;\r
634 else\r
635 sh2->sr &= ~Q;\r
636\r
637 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);\r
638\r
639 if (!old_q)\r
640 {\r
641 if (!(sh2->sr & M))\r
642 {\r
643 tmp0 = sh2->r[n];\r
644 sh2->r[n] -= sh2->r[m];\r
645 if(!(sh2->sr & Q))\r
646 if(sh2->r[n] > tmp0)\r
647 sh2->sr |= Q;\r
648 else\r
649 sh2->sr &= ~Q;\r
650 else\r
651 if(sh2->r[n] > tmp0)\r
652 sh2->sr &= ~Q;\r
653 else\r
654 sh2->sr |= Q;\r
655 }\r
656 else\r
657 {\r
658 tmp0 = sh2->r[n];\r
659 sh2->r[n] += sh2->r[m];\r
660 if(!(sh2->sr & Q))\r
661 {\r
662 if(sh2->r[n] < tmp0)\r
663 sh2->sr &= ~Q;\r
664 else\r
665 sh2->sr |= Q;\r
666 }\r
667 else\r
668 {\r
669 if(sh2->r[n] < tmp0)\r
670 sh2->sr |= Q;\r
671 else\r
672 sh2->sr &= ~Q;\r
673 }\r
674 }\r
675 }\r
676 else\r
677 {\r
678 if (!(sh2->sr & M))\r
679 {\r
680 tmp0 = sh2->r[n];\r
681 sh2->r[n] += sh2->r[m];\r
682 if(!(sh2->sr & Q))\r
683 if(sh2->r[n] < tmp0)\r
684 sh2->sr |= Q;\r
685 else\r
686 sh2->sr &= ~Q;\r
687 else\r
688 if(sh2->r[n] < tmp0)\r
689 sh2->sr &= ~Q;\r
690 else\r
691 sh2->sr |= Q;\r
692 }\r
693 else\r
694 {\r
695 tmp0 = sh2->r[n];\r
696 sh2->r[n] -= sh2->r[m];\r
697 if(!(sh2->sr & Q))\r
698 if(sh2->r[n] > tmp0)\r
699 sh2->sr &= ~Q;\r
700 else\r
701 sh2->sr |= Q;\r
702 else\r
703 if(sh2->r[n] > tmp0)\r
704 sh2->sr |= Q;\r
705 else\r
706 sh2->sr &= ~Q;\r
707 }\r
708 }\r
709\r
710 tmp0 = (sh2->sr & (Q | M));\r
711 if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */\r
712 sh2->sr |= T;\r
713 else\r
714 sh2->sr &= ~T;\r
715}\r
716\r
717/* DMULS.L Rm,Rn */\r
718INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)\r
719{\r
720 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
721 UINT32 temp0, temp1, temp2, temp3;\r
722 INT32 tempm, tempn, fnLmL;\r
723\r
724 tempn = (INT32) sh2->r[n];\r
725 tempm = (INT32) sh2->r[m];\r
726 if (tempn < 0)\r
727 tempn = 0 - tempn;\r
728 if (tempm < 0)\r
729 tempm = 0 - tempm;\r
730 if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)\r
731 fnLmL = -1;\r
732 else\r
733 fnLmL = 0;\r
734 temp1 = (UINT32) tempn;\r
735 temp2 = (UINT32) tempm;\r
736 RnL = temp1 & 0x0000ffff;\r
737 RnH = (temp1 >> 16) & 0x0000ffff;\r
738 RmL = temp2 & 0x0000ffff;\r
739 RmH = (temp2 >> 16) & 0x0000ffff;\r
740 temp0 = RmL * RnL;\r
741 temp1 = RmH * RnL;\r
742 temp2 = RmL * RnH;\r
743 temp3 = RmH * RnH;\r
744 Res2 = 0;\r
745 Res1 = temp1 + temp2;\r
746 if (Res1 < temp1)\r
747 Res2 += 0x00010000;\r
748 temp1 = (Res1 << 16) & 0xffff0000;\r
749 Res0 = temp0 + temp1;\r
750 if (Res0 < temp0)\r
751 Res2++;\r
752 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
753 if (fnLmL < 0)\r
754 {\r
755 Res2 = ~Res2;\r
756 if (Res0 == 0)\r
757 Res2++;\r
758 else\r
759 Res0 = (~Res0) + 1;\r
760 }\r
761 sh2->mach = Res2;\r
762 sh2->macl = Res0;\r
763 sh2->icount--;\r
764}\r
765\r
766/* DMULU.L Rm,Rn */\r
767INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)\r
768{\r
769 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
770 UINT32 temp0, temp1, temp2, temp3;\r
771\r
772 RnL = sh2->r[n] & 0x0000ffff;\r
773 RnH = (sh2->r[n] >> 16) & 0x0000ffff;\r
774 RmL = sh2->r[m] & 0x0000ffff;\r
775 RmH = (sh2->r[m] >> 16) & 0x0000ffff;\r
776 temp0 = RmL * RnL;\r
777 temp1 = RmH * RnL;\r
778 temp2 = RmL * RnH;\r
779 temp3 = RmH * RnH;\r
780 Res2 = 0;\r
781 Res1 = temp1 + temp2;\r
782 if (Res1 < temp1)\r
783 Res2 += 0x00010000;\r
784 temp1 = (Res1 << 16) & 0xffff0000;\r
785 Res0 = temp0 + temp1;\r
786 if (Res0 < temp0)\r
787 Res2++;\r
788 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
789 sh2->mach = Res2;\r
790 sh2->macl = Res0;\r
791 sh2->icount--;\r
792}\r
793\r
794/* DT Rn */\r
795INLINE void DT(sh2_state *sh2, UINT32 n)\r
796{\r
797 sh2->r[n]--;\r
798 if (sh2->r[n] == 0)\r
799 sh2->sr |= T;\r
800 else\r
801 sh2->sr &= ~T;\r
802#if BUSY_LOOP_HACKS\r
803 {\r
804 UINT32 next_opcode = RW( sh2, sh2->ppc & AM );\r
805 /* DT Rn\r
806 * BF $-2\r
807 */\r
808 if (next_opcode == 0x8bfd)\r
809 {\r
810 while (sh2->r[n] > 1 && sh2->icount > 4)\r
811 {\r
812 sh2->r[n]--;\r
813 sh2->icount -= 4; /* cycles for DT (1) and BF taken (3) */\r
814 }\r
815 }\r
816 }\r
817#endif\r
818}\r
819\r
820/* EXTS.B Rm,Rn */\r
821INLINE void EXTSB(sh2_state *sh2, UINT32 m, UINT32 n)\r
822{\r
823 sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;\r
824}\r
825\r
826/* EXTS.W Rm,Rn */\r
827INLINE void EXTSW(sh2_state *sh2, UINT32 m, UINT32 n)\r
828{\r
829 sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;\r
830}\r
831\r
832/* EXTU.B Rm,Rn */\r
833INLINE void EXTUB(sh2_state *sh2, UINT32 m, UINT32 n)\r
834{\r
835 sh2->r[n] = sh2->r[m] & 0x000000ff;\r
836}\r
837\r
838/* EXTU.W Rm,Rn */\r
839INLINE void EXTUW(sh2_state *sh2, UINT32 m, UINT32 n)\r
840{\r
841 sh2->r[n] = sh2->r[m] & 0x0000ffff;\r
842}\r
843\r
844/* ILLEGAL */\r
845INLINE void ILLEGAL(sh2_state *sh2)\r
846{\r
847 logerror("SH2: Illegal opcode at %08x\n", sh2->pc - 2);\r
848 sh2->r[15] -= 4;\r
849 WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */\r
850 sh2->r[15] -= 4;\r
851 WL( sh2, sh2->r[15], sh2->pc - 2 ); /* push PC onto stack */\r
852\r
853 /* fetch PC */\r
854 sh2->pc = RL( sh2, sh2->vbr + 4 * 4 );\r
855\r
856 /* TODO: timing is a guess */\r
857 sh2->icount -= 5;\r
858}\r
859\r
860\r
861/* JMP @Rm */\r
862INLINE void JMP(sh2_state *sh2, UINT32 m)\r
863{\r
864 sh2->delay = sh2->pc;\r
865 sh2->pc = sh2->ea = sh2->r[m];\r
866 sh2->icount--;\r
867}\r
868\r
869/* JSR @Rm */\r
870INLINE void JSR(sh2_state *sh2, UINT32 m)\r
871{\r
872 sh2->delay = sh2->pc;\r
873 sh2->pr = sh2->pc + 2;\r
874 sh2->pc = sh2->ea = sh2->r[m];\r
875 sh2->icount--;\r
876}\r
877\r
878\r
879/* LDC Rm,SR */\r
880INLINE void LDCSR(sh2_state *sh2, UINT32 m)\r
881{\r
882 sh2->sr = sh2->r[m] & FLAGS;\r
883 sh2->test_irq = 1;\r
884}\r
885\r
886/* LDC Rm,GBR */\r
887INLINE void LDCGBR(sh2_state *sh2, UINT32 m)\r
888{\r
889 sh2->gbr = sh2->r[m];\r
890}\r
891\r
892/* LDC Rm,VBR */\r
893INLINE void LDCVBR(sh2_state *sh2, UINT32 m)\r
894{\r
895 sh2->vbr = sh2->r[m];\r
896}\r
897\r
898/* LDC.L @Rm+,SR */\r
899INLINE void LDCMSR(sh2_state *sh2, UINT32 m)\r
900{\r
901 sh2->ea = sh2->r[m];\r
902 sh2->sr = RL( sh2, sh2->ea ) & FLAGS;\r
903 sh2->r[m] += 4;\r
904 sh2->icount -= 2;\r
905 sh2->test_irq = 1;\r
906}\r
907\r
908/* LDC.L @Rm+,GBR */\r
909INLINE void LDCMGBR(sh2_state *sh2, UINT32 m)\r
910{\r
911 sh2->ea = sh2->r[m];\r
912 sh2->gbr = RL( sh2, sh2->ea );\r
913 sh2->r[m] += 4;\r
914 sh2->icount -= 2;\r
915}\r
916\r
917/* LDC.L @Rm+,VBR */\r
918INLINE void LDCMVBR(sh2_state *sh2, UINT32 m)\r
919{\r
920 sh2->ea = sh2->r[m];\r
921 sh2->vbr = RL( sh2, sh2->ea );\r
922 sh2->r[m] += 4;\r
923 sh2->icount -= 2;\r
924}\r
925\r
926/* LDS Rm,MACH */\r
927INLINE void LDSMACH(sh2_state *sh2, UINT32 m)\r
928{\r
929 sh2->mach = sh2->r[m];\r
930}\r
931\r
932/* LDS Rm,MACL */\r
933INLINE void LDSMACL(sh2_state *sh2, UINT32 m)\r
934{\r
935 sh2->macl = sh2->r[m];\r
936}\r
937\r
938/* LDS Rm,PR */\r
939INLINE void LDSPR(sh2_state *sh2, UINT32 m)\r
940{\r
941 sh2->pr = sh2->r[m];\r
942}\r
943\r
944/* LDS.L @Rm+,MACH */\r
945INLINE void LDSMMACH(sh2_state *sh2, UINT32 m)\r
946{\r
947 sh2->ea = sh2->r[m];\r
948 sh2->mach = RL( sh2, sh2->ea );\r
949 sh2->r[m] += 4;\r
950}\r
951\r
952/* LDS.L @Rm+,MACL */\r
953INLINE void LDSMMACL(sh2_state *sh2, UINT32 m)\r
954{\r
955 sh2->ea = sh2->r[m];\r
956 sh2->macl = RL( sh2, sh2->ea );\r
957 sh2->r[m] += 4;\r
958}\r
959\r
960/* LDS.L @Rm+,PR */\r
961INLINE void LDSMPR(sh2_state *sh2, UINT32 m)\r
962{\r
963 sh2->ea = sh2->r[m];\r
964 sh2->pr = RL( sh2, sh2->ea );\r
965 sh2->r[m] += 4;\r
966}\r
967\r
968/* MAC.L @Rm+,@Rn+ */\r
969INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)\r
970{\r
971 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
972 UINT32 temp0, temp1, temp2, temp3;\r
973 INT32 tempm, tempn, fnLmL;\r
974\r
975 tempn = (INT32) RL( sh2, sh2->r[n] );\r
976 sh2->r[n] += 4;\r
977 tempm = (INT32) RL( sh2, sh2->r[m] );\r
978 sh2->r[m] += 4;\r
979 if ((INT32) (tempn ^ tempm) < 0)\r
980 fnLmL = -1;\r
981 else\r
982 fnLmL = 0;\r
983 if (tempn < 0)\r
984 tempn = 0 - tempn;\r
985 if (tempm < 0)\r
986 tempm = 0 - tempm;\r
987 temp1 = (UINT32) tempn;\r
988 temp2 = (UINT32) tempm;\r
989 RnL = temp1 & 0x0000ffff;\r
990 RnH = (temp1 >> 16) & 0x0000ffff;\r
991 RmL = temp2 & 0x0000ffff;\r
992 RmH = (temp2 >> 16) & 0x0000ffff;\r
993 temp0 = RmL * RnL;\r
994 temp1 = RmH * RnL;\r
995 temp2 = RmL * RnH;\r
996 temp3 = RmH * RnH;\r
997 Res2 = 0;\r
998 Res1 = temp1 + temp2;\r
999 if (Res1 < temp1)\r
1000 Res2 += 0x00010000;\r
1001 temp1 = (Res1 << 16) & 0xffff0000;\r
1002 Res0 = temp0 + temp1;\r
1003 if (Res0 < temp0)\r
1004 Res2++;\r
1005 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
1006 if (fnLmL < 0)\r
1007 {\r
1008 Res2 = ~Res2;\r
1009 if (Res0 == 0)\r
1010 Res2++;\r
1011 else\r
1012 Res0 = (~Res0) + 1;\r
1013 }\r
1014 if (sh2->sr & S)\r
1015 {\r
1016 Res0 = sh2->macl + Res0;\r
1017 if (sh2->macl > Res0)\r
1018 Res2++;\r
1019 Res2 += (sh2->mach & 0x0000ffff);\r
1020 if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))\r
1021 {\r
1022 Res2 = 0x00008000;\r
1023 Res0 = 0x00000000;\r
1024 }\r
1025 else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff))\r
1026 {\r
1027 Res2 = 0x00007fff;\r
1028 Res0 = 0xffffffff;\r
1029 }\r
1030 sh2->mach = Res2;\r
1031 sh2->macl = Res0;\r
1032 }\r
1033 else\r
1034 {\r
1035 Res0 = sh2->macl + Res0;\r
1036 if (sh2->macl > Res0)\r
1037 Res2++;\r
1038 Res2 += sh2->mach;\r
1039 sh2->mach = Res2;\r
1040 sh2->macl = Res0;\r
1041 }\r
1042 sh2->icount -= 2;\r
1043}\r
1044\r
1045/* MAC.W @Rm+,@Rn+ */\r
1046INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)\r
1047{\r
1048 INT32 tempm, tempn, dest, src, ans;\r
1049 UINT32 templ;\r
1050\r
1051 tempn = (INT32) RW( sh2, sh2->r[n] );\r
1052 sh2->r[n] += 2;\r
1053 tempm = (INT32) RW( sh2, sh2->r[m] );\r
1054 sh2->r[m] += 2;\r
1055 templ = sh2->macl;\r
1056 tempm = ((INT32) (short) tempn * (INT32) (short) tempm);\r
1057 if ((INT32) sh2->macl >= 0)\r
1058 dest = 0;\r
1059 else\r
1060 dest = 1;\r
1061 if ((INT32) tempm >= 0)\r
1062 {\r
1063 src = 0;\r
1064 tempn = 0;\r
1065 }\r
1066 else\r
1067 {\r
1068 src = 1;\r
1069 tempn = 0xffffffff;\r
1070 }\r
1071 src += dest;\r
1072 sh2->macl += tempm;\r
1073 if ((INT32) sh2->macl >= 0)\r
1074 ans = 0;\r
1075 else\r
1076 ans = 1;\r
1077 ans += dest;\r
1078 if (sh2->sr & S)\r
1079 {\r
1080 if (ans == 1)\r
1081 {\r
1082 if (src == 0)\r
1083 sh2->macl = 0x7fffffff;\r
1084 if (src == 2)\r
1085 sh2->macl = 0x80000000;\r
1086 }\r
1087 }\r
1088 else\r
1089 {\r
1090 sh2->mach += tempn;\r
1091 if (templ > sh2->macl)\r
1092 sh2->mach += 1;\r
1093 }\r
1094 sh2->icount -= 2;\r
1095}\r
1096\r
1097/* MOV Rm,Rn */\r
1098INLINE void MOV(sh2_state *sh2, UINT32 m, UINT32 n)\r
1099{\r
1100 sh2->r[n] = sh2->r[m];\r
1101}\r
1102\r
1103/* MOV.B Rm,@Rn */\r
1104INLINE void MOVBS(sh2_state *sh2, UINT32 m, UINT32 n)\r
1105{\r
1106 sh2->ea = sh2->r[n];\r
1107 WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff);\r
1108}\r
1109\r
1110/* MOV.W Rm,@Rn */\r
1111INLINE void MOVWS(sh2_state *sh2, UINT32 m, UINT32 n)\r
1112{\r
1113 sh2->ea = sh2->r[n];\r
1114 WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff);\r
1115}\r
1116\r
1117/* MOV.L Rm,@Rn */\r
1118INLINE void MOVLS(sh2_state *sh2, UINT32 m, UINT32 n)\r
1119{\r
1120 sh2->ea = sh2->r[n];\r
1121 WL( sh2, sh2->ea, sh2->r[m] );\r
1122}\r
1123\r
1124/* MOV.B @Rm,Rn */\r
1125INLINE void MOVBL(sh2_state *sh2, UINT32 m, UINT32 n)\r
1126{\r
1127 sh2->ea = sh2->r[m];\r
1128 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
1129}\r
1130\r
1131/* MOV.W @Rm,Rn */\r
1132INLINE void MOVWL(sh2_state *sh2, UINT32 m, UINT32 n)\r
1133{\r
1134 sh2->ea = sh2->r[m];\r
1135 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
1136}\r
1137\r
1138/* MOV.L @Rm,Rn */\r
1139INLINE void MOVLL(sh2_state *sh2, UINT32 m, UINT32 n)\r
1140{\r
1141 sh2->ea = sh2->r[m];\r
1142 sh2->r[n] = RL( sh2, sh2->ea );\r
1143}\r
1144\r
1145/* MOV.B Rm,@-Rn */\r
1146INLINE void MOVBM(sh2_state *sh2, UINT32 m, UINT32 n)\r
1147{\r
1148 /* SMG : bug fix, was reading sh2->r[n] */\r
1149 UINT32 data = sh2->r[m] & 0x000000ff;\r
1150\r
1151 sh2->r[n] -= 1;\r
1152 WB( sh2, sh2->r[n], data );\r
1153}\r
1154\r
1155/* MOV.W Rm,@-Rn */\r
1156INLINE void MOVWM(sh2_state *sh2, UINT32 m, UINT32 n)\r
1157{\r
1158 UINT32 data = sh2->r[m] & 0x0000ffff;\r
1159\r
1160 sh2->r[n] -= 2;\r
1161 WW( sh2, sh2->r[n], data );\r
1162}\r
1163\r
1164/* MOV.L Rm,@-Rn */\r
1165INLINE void MOVLM(sh2_state *sh2, UINT32 m, UINT32 n)\r
1166{\r
1167 UINT32 data = sh2->r[m];\r
1168\r
1169 sh2->r[n] -= 4;\r
1170 WL( sh2, sh2->r[n], data );\r
1171}\r
1172\r
1173/* MOV.B @Rm+,Rn */\r
1174INLINE void MOVBP(sh2_state *sh2, UINT32 m, UINT32 n)\r
1175{\r
1176 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->r[m] );\r
1177 if (n != m)\r
1178 sh2->r[m] += 1;\r
1179}\r
1180\r
1181/* MOV.W @Rm+,Rn */\r
1182INLINE void MOVWP(sh2_state *sh2, UINT32 m, UINT32 n)\r
1183{\r
1184 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->r[m] );\r
1185 if (n != m)\r
1186 sh2->r[m] += 2;\r
1187}\r
1188\r
1189/* MOV.L @Rm+,Rn */\r
1190INLINE void MOVLP(sh2_state *sh2, UINT32 m, UINT32 n)\r
1191{\r
1192 sh2->r[n] = RL( sh2, sh2->r[m] );\r
1193 if (n != m)\r
1194 sh2->r[m] += 4;\r
1195}\r
1196\r
1197/* MOV.B Rm,@(R0,Rn) */\r
1198INLINE void MOVBS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
1199{\r
1200 sh2->ea = sh2->r[n] + sh2->r[0];\r
1201 WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff );\r
1202}\r
1203\r
1204/* MOV.W Rm,@(R0,Rn) */\r
1205INLINE void MOVWS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
1206{\r
1207 sh2->ea = sh2->r[n] + sh2->r[0];\r
1208 WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff );\r
1209}\r
1210\r
1211/* MOV.L Rm,@(R0,Rn) */\r
1212INLINE void MOVLS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
1213{\r
1214 sh2->ea = sh2->r[n] + sh2->r[0];\r
1215 WL( sh2, sh2->ea, sh2->r[m] );\r
1216}\r
1217\r
1218/* MOV.B @(R0,Rm),Rn */\r
1219INLINE void MOVBL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
1220{\r
1221 sh2->ea = sh2->r[m] + sh2->r[0];\r
1222 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
1223}\r
1224\r
1225/* MOV.W @(R0,Rm),Rn */\r
1226INLINE void MOVWL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
1227{\r
1228 sh2->ea = sh2->r[m] + sh2->r[0];\r
1229 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
1230}\r
1231\r
1232/* MOV.L @(R0,Rm),Rn */\r
1233INLINE void MOVLL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
1234{\r
1235 sh2->ea = sh2->r[m] + sh2->r[0];\r
1236 sh2->r[n] = RL( sh2, sh2->ea );\r
1237}\r
1238\r
1239/* MOV #imm,Rn */\r
1240INLINE void MOVI(sh2_state *sh2, UINT32 i, UINT32 n)\r
1241{\r
1242 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;\r
1243}\r
1244\r
1245/* MOV.W @(disp8,PC),Rn */\r
1246INLINE void MOVWI(sh2_state *sh2, UINT32 d, UINT32 n)\r
1247{\r
1248 UINT32 disp = d & 0xff;\r
1249 sh2->ea = sh2->pc + disp * 2 + 2;\r
1250 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
1251}\r
1252\r
1253/* MOV.L @(disp8,PC),Rn */\r
1254INLINE void MOVLI(sh2_state *sh2, UINT32 d, UINT32 n)\r
1255{\r
1256 UINT32 disp = d & 0xff;\r
1257 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r
1258 sh2->r[n] = RL( sh2, sh2->ea );\r
1259}\r
1260\r
1261/* MOV.B @(disp8,GBR),R0 */\r
1262INLINE void MOVBLG(sh2_state *sh2, UINT32 d)\r
1263{\r
1264 UINT32 disp = d & 0xff;\r
1265 sh2->ea = sh2->gbr + disp;\r
1266 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
1267}\r
1268\r
1269/* MOV.W @(disp8,GBR),R0 */\r
1270INLINE void MOVWLG(sh2_state *sh2, UINT32 d)\r
1271{\r
1272 UINT32 disp = d & 0xff;\r
1273 sh2->ea = sh2->gbr + disp * 2;\r
1274 sh2->r[0] = (INT32)(INT16) RW( sh2, sh2->ea );\r
1275}\r
1276\r
1277/* MOV.L @(disp8,GBR),R0 */\r
1278INLINE void MOVLLG(sh2_state *sh2, UINT32 d)\r
1279{\r
1280 UINT32 disp = d & 0xff;\r
1281 sh2->ea = sh2->gbr + disp * 4;\r
1282 sh2->r[0] = RL( sh2, sh2->ea );\r
1283}\r
1284\r
1285/* MOV.B R0,@(disp8,GBR) */\r
1286INLINE void MOVBSG(sh2_state *sh2, UINT32 d)\r
1287{\r
1288 UINT32 disp = d & 0xff;\r
1289 sh2->ea = sh2->gbr + disp;\r
1290 WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );\r
1291}\r
1292\r
1293/* MOV.W R0,@(disp8,GBR) */\r
1294INLINE void MOVWSG(sh2_state *sh2, UINT32 d)\r
1295{\r
1296 UINT32 disp = d & 0xff;\r
1297 sh2->ea = sh2->gbr + disp * 2;\r
1298 WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );\r
1299}\r
1300\r
1301/* MOV.L R0,@(disp8,GBR) */\r
1302INLINE void MOVLSG(sh2_state *sh2, UINT32 d)\r
1303{\r
1304 UINT32 disp = d & 0xff;\r
1305 sh2->ea = sh2->gbr + disp * 4;\r
1306 WL( sh2, sh2->ea, sh2->r[0] );\r
1307}\r
1308\r
1309/* MOV.B R0,@(disp4,Rn) */\r
1310INLINE void MOVBS4(sh2_state *sh2, UINT32 d, UINT32 n)\r
1311{\r
1312 UINT32 disp = d & 0x0f;\r
1313 sh2->ea = sh2->r[n] + disp;\r
1314 WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );\r
1315}\r
1316\r
1317/* MOV.W R0,@(disp4,Rn) */\r
1318INLINE void MOVWS4(sh2_state *sh2, UINT32 d, UINT32 n)\r
1319{\r
1320 UINT32 disp = d & 0x0f;\r
1321 sh2->ea = sh2->r[n] + disp * 2;\r
1322 WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );\r
1323}\r
1324\r
1325/* MOV.L Rm,@(disp4,Rn) */\r
1326INLINE void MOVLS4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)\r
1327{\r
1328 UINT32 disp = d & 0x0f;\r
1329 sh2->ea = sh2->r[n] + disp * 4;\r
1330 WL( sh2, sh2->ea, sh2->r[m] );\r
1331}\r
1332\r
1333/* MOV.B @(disp4,Rm),R0 */\r
1334INLINE void MOVBL4(sh2_state *sh2, UINT32 m, UINT32 d)\r
1335{\r
1336 UINT32 disp = d & 0x0f;\r
1337 sh2->ea = sh2->r[m] + disp;\r
1338 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
1339}\r
1340\r
1341/* MOV.W @(disp4,Rm),R0 */\r
1342INLINE void MOVWL4(sh2_state *sh2, UINT32 m, UINT32 d)\r
1343{\r
1344 UINT32 disp = d & 0x0f;\r
1345 sh2->ea = sh2->r[m] + disp * 2;\r
1346 sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
1347}\r
1348\r
1349/* MOV.L @(disp4,Rm),Rn */\r
1350INLINE void MOVLL4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)\r
1351{\r
1352 UINT32 disp = d & 0x0f;\r
1353 sh2->ea = sh2->r[m] + disp * 4;\r
1354 sh2->r[n] = RL( sh2, sh2->ea );\r
1355}\r
1356\r
1357/* MOVA @(disp8,PC),R0 */\r
1358INLINE void MOVA(sh2_state *sh2, UINT32 d)\r
1359{\r
1360 UINT32 disp = d & 0xff;\r
1361 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r
1362 sh2->r[0] = sh2->ea;\r
1363}\r
1364\r
1365/* MOVT Rn */\r
1366INLINE void MOVT(sh2_state *sh2, UINT32 n)\r
1367{\r
1368 sh2->r[n] = sh2->sr & T;\r
1369}\r
1370\r
1371/* MUL.L Rm,Rn */\r
1372INLINE void MULL(sh2_state *sh2, UINT32 m, UINT32 n)\r
1373{\r
1374 sh2->macl = sh2->r[n] * sh2->r[m];\r
1375 sh2->icount--;\r
1376}\r
1377\r
1378/* MULS Rm,Rn */\r
1379INLINE void MULS(sh2_state *sh2, UINT32 m, UINT32 n)\r
1380{\r
1381 sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];\r
1382}\r
1383\r
1384/* MULU Rm,Rn */\r
1385INLINE void MULU(sh2_state *sh2, UINT32 m, UINT32 n)\r
1386{\r
1387 sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];\r
1388}\r
1389\r
1390/* NEG Rm,Rn */\r
1391INLINE void NEG(sh2_state *sh2, UINT32 m, UINT32 n)\r
1392{\r
1393 sh2->r[n] = 0 - sh2->r[m];\r
1394}\r
1395\r
1396/* NEGC Rm,Rn */\r
1397INLINE void NEGC(sh2_state *sh2, UINT32 m, UINT32 n)\r
1398{\r
1399 UINT32 temp;\r
1400\r
1401 temp = sh2->r[m];\r
1402 sh2->r[n] = -temp - (sh2->sr & T);\r
1403 if (temp || (sh2->sr & T))\r
1404 sh2->sr |= T;\r
1405 else\r
1406 sh2->sr &= ~T;\r
1407}\r
1408\r
1409/* NOP */\r
1410INLINE void NOP(void)\r
1411{\r
1412}\r
1413\r
1414/* NOT Rm,Rn */\r
1415INLINE void NOT(sh2_state *sh2, UINT32 m, UINT32 n)\r
1416{\r
1417 sh2->r[n] = ~sh2->r[m];\r
1418}\r
1419\r
1420/* OR Rm,Rn */\r
1421INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)\r
1422{\r
1423 sh2->r[n] |= sh2->r[m];\r
1424}\r
1425\r
1426/* OR #imm,R0 */\r
1427INLINE void ORI(sh2_state *sh2, UINT32 i)\r
1428{\r
1429 sh2->r[0] |= i;\r
1430}\r
1431\r
1432/* OR.B #imm,@(R0,GBR) */\r
1433INLINE void ORM(sh2_state *sh2, UINT32 i)\r
1434{\r
1435 UINT32 temp;\r
1436\r
1437 sh2->ea = sh2->gbr + sh2->r[0];\r
1438 temp = RB( sh2, sh2->ea );\r
1439 temp |= i;\r
1440 WB( sh2, sh2->ea, temp );\r
1441 sh2->icount -= 2;\r
1442}\r
1443\r
1444/* ROTCL Rn */\r
1445INLINE void ROTCL(sh2_state *sh2, UINT32 n)\r
1446{\r
1447 UINT32 temp;\r
1448\r
1449 temp = (sh2->r[n] >> 31) & T;\r
1450 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);\r
1451 sh2->sr = (sh2->sr & ~T) | temp;\r
1452}\r
1453\r
1454/* ROTCR Rn */\r
1455INLINE void ROTCR(sh2_state *sh2, UINT32 n)\r
1456{\r
1457 UINT32 temp;\r
1458 temp = (sh2->sr & T) << 31;\r
1459 if (sh2->r[n] & T)\r
1460 sh2->sr |= T;\r
1461 else\r
1462 sh2->sr &= ~T;\r
1463 sh2->r[n] = (sh2->r[n] >> 1) | temp;\r
1464}\r
1465\r
1466/* ROTL Rn */\r
1467INLINE void ROTL(sh2_state *sh2, UINT32 n)\r
1468{\r
1469 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
1470 sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);\r
1471}\r
1472\r
1473/* ROTR Rn */\r
1474INLINE void ROTR(sh2_state *sh2, UINT32 n)\r
1475{\r
1476 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
1477 sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);\r
1478}\r
1479\r
1480/* RTE */\r
1481INLINE void RTE(sh2_state *sh2)\r
1482{\r
1483 sh2->ea = sh2->r[15];\r
1484 sh2->delay = sh2->pc;\r
1485 sh2->pc = RL( sh2, sh2->ea );\r
1486 sh2->r[15] += 4;\r
1487 sh2->ea = sh2->r[15];\r
1488 sh2->sr = RL( sh2, sh2->ea ) & FLAGS;\r
1489 sh2->r[15] += 4;\r
1490 sh2->icount -= 3;\r
1491 sh2->test_irq = 1;\r
1492}\r
1493\r
1494/* RTS */\r
1495INLINE void RTS(sh2_state *sh2)\r
1496{\r
1497 sh2->delay = sh2->pc;\r
1498 sh2->pc = sh2->ea = sh2->pr;\r
1499 sh2->icount--;\r
1500}\r
1501\r
1502/* SETT */\r
1503INLINE void SETT(sh2_state *sh2)\r
1504{\r
1505 sh2->sr |= T;\r
1506}\r
1507\r
1508/* SHAL Rn (same as SHLL) */\r
1509INLINE void SHAL(sh2_state *sh2, UINT32 n)\r
1510{\r
1511 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
1512 sh2->r[n] <<= 1;\r
1513}\r
1514\r
1515/* SHAR Rn */\r
1516INLINE void SHAR(sh2_state *sh2, UINT32 n)\r
1517{\r
1518 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
1519 sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);\r
1520}\r
1521\r
1522/* SHLL Rn (same as SHAL) */\r
1523INLINE void SHLL(sh2_state *sh2, UINT32 n)\r
1524{\r
1525 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
1526 sh2->r[n] <<= 1;\r
1527}\r
1528\r
1529/* SHLL2 Rn */\r
1530INLINE void SHLL2(sh2_state *sh2, UINT32 n)\r
1531{\r
1532 sh2->r[n] <<= 2;\r
1533}\r
1534\r
1535/* SHLL8 Rn */\r
1536INLINE void SHLL8(sh2_state *sh2, UINT32 n)\r
1537{\r
1538 sh2->r[n] <<= 8;\r
1539}\r
1540\r
1541/* SHLL16 Rn */\r
1542INLINE void SHLL16(sh2_state *sh2, UINT32 n)\r
1543{\r
1544 sh2->r[n] <<= 16;\r
1545}\r
1546\r
1547/* SHLR Rn */\r
1548INLINE void SHLR(sh2_state *sh2, UINT32 n)\r
1549{\r
1550 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
1551 sh2->r[n] >>= 1;\r
1552}\r
1553\r
1554/* SHLR2 Rn */\r
1555INLINE void SHLR2(sh2_state *sh2, UINT32 n)\r
1556{\r
1557 sh2->r[n] >>= 2;\r
1558}\r
1559\r
1560/* SHLR8 Rn */\r
1561INLINE void SHLR8(sh2_state *sh2, UINT32 n)\r
1562{\r
1563 sh2->r[n] >>= 8;\r
1564}\r
1565\r
1566/* SHLR16 Rn */\r
1567INLINE void SHLR16(sh2_state *sh2, UINT32 n)\r
1568{\r
1569 sh2->r[n] >>= 16;\r
1570}\r
1571\r
1572/* SLEEP */\r
1573INLINE void SLEEP(sh2_state *sh2)\r
1574{\r
1575 //if(sh2->sleep_mode != 2)\r
1576 sh2->pc -= 2;\r
1577 sh2->icount -= 2;\r
1578 /* Wait_for_exception; */\r
1579 /*if(sh2->sleep_mode == 0)\r
1580 sh2->sleep_mode = 1;\r
1581 else if(sh2->sleep_mode == 2)\r
1582 sh2->sleep_mode = 0;*/\r
1583}\r
1584\r
1585/* STC SR,Rn */\r
1586INLINE void STCSR(sh2_state *sh2, UINT32 n)\r
1587{\r
1588 sh2->r[n] = sh2->sr;\r
1589}\r
1590\r
1591/* STC GBR,Rn */\r
1592INLINE void STCGBR(sh2_state *sh2, UINT32 n)\r
1593{\r
1594 sh2->r[n] = sh2->gbr;\r
1595}\r
1596\r
1597/* STC VBR,Rn */\r
1598INLINE void STCVBR(sh2_state *sh2, UINT32 n)\r
1599{\r
1600 sh2->r[n] = sh2->vbr;\r
1601}\r
1602\r
1603/* STC.L SR,@-Rn */\r
1604INLINE void STCMSR(sh2_state *sh2, UINT32 n)\r
1605{\r
1606 sh2->r[n] -= 4;\r
1607 sh2->ea = sh2->r[n];\r
1608 WL( sh2, sh2->ea, sh2->sr );\r
1609 sh2->icount--;\r
1610}\r
1611\r
1612/* STC.L GBR,@-Rn */\r
1613INLINE void STCMGBR(sh2_state *sh2, UINT32 n)\r
1614{\r
1615 sh2->r[n] -= 4;\r
1616 sh2->ea = sh2->r[n];\r
1617 WL( sh2, sh2->ea, sh2->gbr );\r
1618 sh2->icount--;\r
1619}\r
1620\r
1621/* STC.L VBR,@-Rn */\r
1622INLINE void STCMVBR(sh2_state *sh2, UINT32 n)\r
1623{\r
1624 sh2->r[n] -= 4;\r
1625 sh2->ea = sh2->r[n];\r
1626 WL( sh2, sh2->ea, sh2->vbr );\r
1627 sh2->icount--;\r
1628}\r
1629\r
1630/* STS MACH,Rn */\r
1631INLINE void STSMACH(sh2_state *sh2, UINT32 n)\r
1632{\r
1633 sh2->r[n] = sh2->mach;\r
1634}\r
1635\r
1636/* STS MACL,Rn */\r
1637INLINE void STSMACL(sh2_state *sh2, UINT32 n)\r
1638{\r
1639 sh2->r[n] = sh2->macl;\r
1640}\r
1641\r
1642/* STS PR,Rn */\r
1643INLINE void STSPR(sh2_state *sh2, UINT32 n)\r
1644{\r
1645 sh2->r[n] = sh2->pr;\r
1646}\r
1647\r
1648/* STS.L MACH,@-Rn */\r
1649INLINE void STSMMACH(sh2_state *sh2, UINT32 n)\r
1650{\r
1651 sh2->r[n] -= 4;\r
1652 sh2->ea = sh2->r[n];\r
1653 WL( sh2, sh2->ea, sh2->mach );\r
1654}\r
1655\r
1656/* STS.L MACL,@-Rn */\r
1657INLINE void STSMMACL(sh2_state *sh2, UINT32 n)\r
1658{\r
1659 sh2->r[n] -= 4;\r
1660 sh2->ea = sh2->r[n];\r
1661 WL( sh2, sh2->ea, sh2->macl );\r
1662}\r
1663\r
1664/* STS.L PR,@-Rn */\r
1665INLINE void STSMPR(sh2_state *sh2, UINT32 n)\r
1666{\r
1667 sh2->r[n] -= 4;\r
1668 sh2->ea = sh2->r[n];\r
1669 WL( sh2, sh2->ea, sh2->pr );\r
1670}\r
1671\r
1672/* SUB Rm,Rn */\r
1673INLINE void SUB(sh2_state *sh2, UINT32 m, UINT32 n)\r
1674{\r
1675 sh2->r[n] -= sh2->r[m];\r
1676}\r
1677\r
1678/* SUBC Rm,Rn */\r
1679INLINE void SUBC(sh2_state *sh2, UINT32 m, UINT32 n)\r
1680{\r
1681 UINT32 tmp0, tmp1;\r
1682\r
1683 tmp1 = sh2->r[n] - sh2->r[m];\r
1684 tmp0 = sh2->r[n];\r
1685 sh2->r[n] = tmp1 - (sh2->sr & T);\r
1686 if (tmp0 < tmp1)\r
1687 sh2->sr |= T;\r
1688 else\r
1689 sh2->sr &= ~T;\r
1690 if (tmp1 < sh2->r[n])\r
1691 sh2->sr |= T;\r
1692}\r
1693\r
1694/* SUBV Rm,Rn */\r
1695INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)\r
1696{\r
1697 INT32 dest, src, ans;\r
1698\r
1699 if ((INT32) sh2->r[n] >= 0)\r
1700 dest = 0;\r
1701 else\r
1702 dest = 1;\r
1703 if ((INT32) sh2->r[m] >= 0)\r
1704 src = 0;\r
1705 else\r
1706 src = 1;\r
1707 src += dest;\r
1708 sh2->r[n] -= sh2->r[m];\r
1709 if ((INT32) sh2->r[n] >= 0)\r
1710 ans = 0;\r
1711 else\r
1712 ans = 1;\r
1713 ans += dest;\r
1714 if (src == 1)\r
1715 {\r
1716 if (ans == 1)\r
1717 sh2->sr |= T;\r
1718 else\r
1719 sh2->sr &= ~T;\r
1720 }\r
1721 else\r
1722 sh2->sr &= ~T;\r
1723}\r
1724\r
1725/* SWAP.B Rm,Rn */\r
1726INLINE void SWAPB(sh2_state *sh2, UINT32 m, UINT32 n)\r
1727{\r
1728 UINT32 temp0, temp1;\r
1729\r
1730 temp0 = sh2->r[m] & 0xffff0000;\r
1731 temp1 = (sh2->r[m] & 0x000000ff) << 8;\r
1732 sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;\r
1733 sh2->r[n] = sh2->r[n] | temp1 | temp0;\r
1734}\r
1735\r
1736/* SWAP.W Rm,Rn */\r
1737INLINE void SWAPW(sh2_state *sh2, UINT32 m, UINT32 n)\r
1738{\r
1739 UINT32 temp;\r
1740\r
1741 temp = (sh2->r[m] >> 16) & 0x0000ffff;\r
1742 sh2->r[n] = (sh2->r[m] << 16) | temp;\r
1743}\r
1744\r
1745/* TAS.B @Rn */\r
1746INLINE void TAS(sh2_state *sh2, UINT32 n)\r
1747{\r
1748 UINT32 temp;\r
1749 sh2->ea = sh2->r[n];\r
1750 /* Bus Lock enable */\r
1751 temp = RB( sh2, sh2->ea );\r
1752 if (temp == 0)\r
1753 sh2->sr |= T;\r
1754 else\r
1755 sh2->sr &= ~T;\r
1756 temp |= 0x80;\r
1757 /* Bus Lock disable */\r
1758 WB( sh2, sh2->ea, temp );\r
1759 sh2->icount -= 3;\r
1760}\r
1761\r
1762/* TRAPA #imm */\r
1763INLINE void TRAPA(sh2_state *sh2, UINT32 i)\r
1764{\r
1765 UINT32 imm = i & 0xff;\r
1766\r
1767 sh2->ea = sh2->vbr + imm * 4;\r
1768\r
1769 sh2->r[15] -= 4;\r
1770 WL( sh2, sh2->r[15], sh2->sr );\r
1771 sh2->r[15] -= 4;\r
1772 WL( sh2, sh2->r[15], sh2->pc );\r
1773\r
1774 sh2->pc = RL( sh2, sh2->ea );\r
1775\r
1776 sh2->icount -= 7;\r
1777}\r
1778\r
1779/* TST Rm,Rn */\r
1780INLINE void TST(sh2_state *sh2, UINT32 m, UINT32 n)\r
1781{\r
1782 if ((sh2->r[n] & sh2->r[m]) == 0)\r
1783 sh2->sr |= T;\r
1784 else\r
1785 sh2->sr &= ~T;\r
1786}\r
1787\r
1788/* TST #imm,R0 */\r
1789INLINE void TSTI(sh2_state *sh2, UINT32 i)\r
1790{\r
1791 UINT32 imm = i & 0xff;\r
1792\r
1793 if ((imm & sh2->r[0]) == 0)\r
1794 sh2->sr |= T;\r
1795 else\r
1796 sh2->sr &= ~T;\r
1797}\r
1798\r
1799/* TST.B #imm,@(R0,GBR) */\r
1800INLINE void TSTM(sh2_state *sh2, UINT32 i)\r
1801{\r
1802 UINT32 imm = i & 0xff;\r
1803\r
1804 sh2->ea = sh2->gbr + sh2->r[0];\r
1805 if ((imm & RB( sh2, sh2->ea )) == 0)\r
1806 sh2->sr |= T;\r
1807 else\r
1808 sh2->sr &= ~T;\r
1809 sh2->icount -= 2;\r
1810}\r
1811\r
1812/* XOR Rm,Rn */\r
1813INLINE void XOR(sh2_state *sh2, UINT32 m, UINT32 n)\r
1814{\r
1815 sh2->r[n] ^= sh2->r[m];\r
1816}\r
1817\r
1818/* XOR #imm,R0 */\r
1819INLINE void XORI(sh2_state *sh2, UINT32 i)\r
1820{\r
1821 UINT32 imm = i & 0xff;\r
1822 sh2->r[0] ^= imm;\r
1823}\r
1824\r
1825/* XOR.B #imm,@(R0,GBR) */\r
1826INLINE void XORM(sh2_state *sh2, UINT32 i)\r
1827{\r
1828 UINT32 imm = i & 0xff;\r
1829 UINT32 temp;\r
1830\r
1831 sh2->ea = sh2->gbr + sh2->r[0];\r
1832 temp = RB( sh2, sh2->ea );\r
1833 temp ^= imm;\r
1834 WB( sh2, sh2->ea, temp );\r
1835 sh2->icount -= 2;\r
1836}\r
1837\r
1838/* XTRCT Rm,Rn */\r
1839INLINE void XTRCT(sh2_state *sh2, UINT32 m, UINT32 n)\r
1840{\r
1841 UINT32 temp;\r
1842\r
1843 temp = (sh2->r[m] << 16) & 0xffff0000;\r
1844 sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;\r
1845 sh2->r[n] |= temp;\r
1846}\r
1847\r
1848/*****************************************************************************\r
1849 * OPCODE DISPATCHERS\r
1850 *****************************************************************************/\r
1851\r
1852INLINE void op0000(sh2_state *sh2, UINT16 opcode)\r
1853{\r
1854 switch (opcode & 0x3F)\r
1855 {\r
1856 case 0x00: ILLEGAL(sh2); rlog(0); break;\r
1857 case 0x01: ILLEGAL(sh2); rlog(0); break;\r
1858 case 0x02: STCSR(sh2, Rn); rlog(LRN); break;\r
1859 case 0x03: BSRF(sh2, Rn); rlog(LRN); break;\r
1860 case 0x04: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1861 case 0x05: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1862 case 0x06: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1863 case 0x07: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1864 case 0x08: CLRT(sh2); rlog(0); break;\r
1865 case 0x09: NOP(); rlog(0); break;\r
1866 case 0x0a: STSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1867 case 0x0b: RTS(sh2); rlog(0); rlog1(SHR_PR); break;\r
1868 case 0x0c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1869 case 0x0d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1870 case 0x0e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1871 case 0x0f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1872\r
1873 case 0x10: ILLEGAL(sh2); rlog(0); break;\r
1874 case 0x11: ILLEGAL(sh2); rlog(0); break;\r
1875 case 0x12: STCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
1876 case 0x13: ILLEGAL(sh2); rlog(0); break;\r
1877 case 0x14: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1878 case 0x15: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1879 case 0x16: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1880 case 0x17: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1881 case 0x18: SETT(sh2); rlog(0); break;\r
1882 case 0x19: DIV0U(sh2); rlog(0); break;\r
1883 case 0x1a: STSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
1884 case 0x1b: SLEEP(sh2); rlog(0); break;\r
1885 case 0x1c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1886 case 0x1d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1887 case 0x1e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1888 case 0x1f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1889\r
1890 case 0x20: ILLEGAL(sh2); rlog(0); break;\r
1891 case 0x21: ILLEGAL(sh2); rlog(0); break;\r
1892 case 0x22: STCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
1893 case 0x23: BRAF(sh2, Rn); rlog(LRN); break;\r
1894 case 0x24: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1895 case 0x25: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1896 case 0x26: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1897 case 0x27: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1898 case 0x28: CLRMAC(sh2); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;\r
1899 case 0x29: MOVT(sh2, Rn); rlog(LRN); break;\r
1900 case 0x2a: STSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
1901 case 0x2b: RTE(sh2); rlog(0); break;\r
1902 case 0x2c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1903 case 0x2d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1904 case 0x2e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1905 case 0x2f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1906\r
1907 case 0x30: ILLEGAL(sh2); rlog(0); break;\r
1908 case 0x31: ILLEGAL(sh2); rlog(0); break;\r
1909 case 0x32: ILLEGAL(sh2); rlog(0); break;\r
1910 case 0x33: ILLEGAL(sh2); rlog(0); break;\r
1911 case 0x34: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1912 case 0x35: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1913 case 0x36: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1914 case 0x37: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1915 case 0x38: ILLEGAL(sh2); rlog(0); break;\r
1916 case 0x39: ILLEGAL(sh2); rlog(0); break;\r
1917 case 0x3c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1918 case 0x3d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1919 case 0x3e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1920 case 0x3f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1921 case 0x3a: ILLEGAL(sh2); rlog(0); break;\r
1922 case 0x3b: ILLEGAL(sh2); rlog(0); break;\r
1923 }\r
1924}\r
1925\r
1926INLINE void op0001(sh2_state *sh2, UINT16 opcode)\r
1927{\r
1928 MOVLS4(sh2, Rm, opcode & 0x0f, Rn);\r
1929 rlog(LRNM);\r
1930}\r
1931\r
1932INLINE void op0010(sh2_state *sh2, UINT16 opcode)\r
1933{\r
1934 switch (opcode & 15)\r
1935 {\r
1936 case 0: MOVBS(sh2, Rm, Rn); rlog(LRNM); break;\r
1937 case 1: MOVWS(sh2, Rm, Rn); rlog(LRNM); break;\r
1938 case 2: MOVLS(sh2, Rm, Rn); rlog(LRNM); break;\r
1939 case 3: ILLEGAL(sh2); rlog(0); break;\r
1940 case 4: MOVBM(sh2, Rm, Rn); rlog(LRNM); break;\r
1941 case 5: MOVWM(sh2, Rm, Rn); rlog(LRNM); break;\r
1942 case 6: MOVLM(sh2, Rm, Rn); rlog(LRNM); break;\r
1943 case 7: DIV0S(sh2, Rm, Rn); rlog(LRNM); break;\r
1944 case 8: TST(sh2, Rm, Rn); rlog(LRNM); break;\r
1945 case 9: AND(sh2, Rm, Rn); rlog(LRNM); break;\r
1946 case 10: XOR(sh2, Rm, Rn); rlog(LRNM); break;\r
1947 case 11: OR(sh2, Rm, Rn); rlog(LRNM); break;\r
1948 case 12: CMPSTR(sh2, Rm, Rn); rlog(LRNM); break;\r
1949 case 13: XTRCT(sh2, Rm, Rn); rlog(LRNM); break;\r
1950 case 14: MULU(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1951 case 15: MULS(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1952 }\r
1953}\r
1954\r
1955INLINE void op0011(sh2_state *sh2, UINT16 opcode)\r
1956{\r
1957 switch (opcode & 15)\r
1958 {\r
1959 case 0: CMPEQ(sh2, Rm, Rn); rlog(LRNM); break;\r
1960 case 1: ILLEGAL(sh2); rlog(0); break;\r
1961 case 2: CMPHS(sh2, Rm, Rn); rlog(LRNM); break;\r
1962 case 3: CMPGE(sh2, Rm, Rn); rlog(LRNM); break;\r
1963 case 4: DIV1(sh2, Rm, Rn); rlog(LRNM); break;\r
1964 case 5: DMULU(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1965 case 6: CMPHI(sh2, Rm, Rn); rlog(LRNM); break;\r
1966 case 7: CMPGT(sh2, Rm, Rn); rlog(LRNM); break;\r
1967 case 8: SUB(sh2, Rm, Rn); rlog(LRNM); break;\r
1968 case 9: ILLEGAL(sh2); rlog(0); break;\r
1969 case 10: SUBC(sh2, Rm, Rn); rlog(LRNM); break;\r
1970 case 11: SUBV(sh2, Rm, Rn); rlog(LRNM); break;\r
1971 case 12: ADD(sh2, Rm, Rn); rlog(LRNM); break;\r
1972 case 13: DMULS(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1973 case 14: ADDC(sh2, Rm, Rn); rlog(LRNM); break;\r
1974 case 15: ADDV(sh2, Rm, Rn); rlog(LRNM); break;\r
1975 }\r
1976}\r
1977\r
1978INLINE void op0100(sh2_state *sh2, UINT16 opcode)\r
1979{\r
1980 switch (opcode & 0x3F)\r
1981 {\r
1982 case 0x00: SHLL(sh2, Rn); rlog(LRN); break;\r
1983 case 0x01: SHLR(sh2, Rn); rlog(LRN); break;\r
1984 case 0x02: STSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1985 case 0x03: STCMSR(sh2, Rn); rlog(LRN); break;\r
1986 case 0x04: ROTL(sh2, Rn); rlog(LRN); break;\r
1987 case 0x05: ROTR(sh2, Rn); rlog(LRN); break;\r
1988 case 0x06: LDSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1989 case 0x07: LDCMSR(sh2, Rn); rlog(LRN); break;\r
1990 case 0x08: SHLL2(sh2, Rn); rlog(LRN); break;\r
1991 case 0x09: SHLR2(sh2, Rn); rlog(LRN); break;\r
1992 case 0x0a: LDSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1993 case 0x0b: JSR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
1994 case 0x0c: ILLEGAL(sh2); rlog(0); break;\r
1995 case 0x0d: ILLEGAL(sh2); rlog(0); break;\r
1996 case 0x0e: LDCSR(sh2, Rn); rlog(LRN); break;\r
1997 case 0x0f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1998\r
1999 case 0x10: DT(sh2, Rn); rlog(LRN); break;\r
2000 case 0x11: CMPPZ(sh2, Rn); rlog(LRN); break;\r
2001 case 0x12: STSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
2002 case 0x13: STCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
2003 case 0x14: ILLEGAL(sh2); rlog(0); break;\r
2004 case 0x15: CMPPL(sh2, Rn); rlog(LRN); break;\r
2005 case 0x16: LDSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
2006 case 0x17: LDCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
2007 case 0x18: SHLL8(sh2, Rn); rlog(LRN); break;\r
2008 case 0x19: SHLR8(sh2, Rn); rlog(LRN); break;\r
2009 case 0x1a: LDSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
2010 case 0x1b: TAS(sh2, Rn); rlog(LRN); break;\r
2011 case 0x1c: ILLEGAL(sh2); rlog(0); break;\r
2012 case 0x1d: ILLEGAL(sh2); rlog(0); break;\r
2013 case 0x1e: LDCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
2014 case 0x1f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
2015\r
2016 case 0x20: SHAL(sh2, Rn); rlog(LRN); break;\r
2017 case 0x21: SHAR(sh2, Rn); rlog(LRN); break;\r
2018 case 0x22: STSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
2019 case 0x23: STCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
2020 case 0x24: ROTCL(sh2, Rn); rlog(LRN); break;\r
2021 case 0x25: ROTCR(sh2, Rn); rlog(LRN); break;\r
2022 case 0x26: LDSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
2023 case 0x27: LDCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
2024 case 0x28: SHLL16(sh2, Rn); rlog(LRN); break;\r
2025 case 0x29: SHLR16(sh2, Rn); rlog(LRN); break;\r
2026 case 0x2a: LDSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
2027 case 0x2b: JMP(sh2, Rn); rlog(LRN); break;\r
2028 case 0x2c: ILLEGAL(sh2); rlog(0); break;\r
2029 case 0x2d: ILLEGAL(sh2); rlog(0); break;\r
2030 case 0x2e: LDCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
2031 case 0x2f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
2032\r
2033 case 0x30:\r
2034 case 0x31:\r
2035 case 0x32:\r
2036 case 0x33:\r
2037 case 0x34:\r
2038 case 0x35:\r
2039 case 0x36:\r
2040 case 0x37:\r
2041 case 0x38:\r
2042 case 0x39:\r
2043 case 0x3a:\r
2044 case 0x3b:\r
2045 case 0x3c:\r
2046 case 0x3d:\r
2047 case 0x3e: ILLEGAL(sh2); rlog(0); break;\r
2048 case 0x3f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
2049 }\r
2050}\r
2051\r
2052INLINE void op0101(sh2_state *sh2, UINT16 opcode)\r
2053{\r
2054 MOVLL4(sh2, Rm, opcode & 0x0f, Rn);\r
2055 rlog(LRNM);\r
2056}\r
2057\r
2058INLINE void op0110(sh2_state *sh2, UINT16 opcode)\r
2059{\r
2060 switch (opcode & 15)\r
2061 {\r
2062 case 0: MOVBL(sh2, Rm, Rn); break;\r
2063 case 1: MOVWL(sh2, Rm, Rn); break;\r
2064 case 2: MOVLL(sh2, Rm, Rn); break;\r
2065 case 3: MOV(sh2, Rm, Rn); break;\r
2066 case 4: MOVBP(sh2, Rm, Rn); break;\r
2067 case 5: MOVWP(sh2, Rm, Rn); break;\r
2068 case 6: MOVLP(sh2, Rm, Rn); break;\r
2069 case 7: NOT(sh2, Rm, Rn); break;\r
2070 case 8: SWAPB(sh2, Rm, Rn); break;\r
2071 case 9: SWAPW(sh2, Rm, Rn); break;\r
2072 case 10: NEGC(sh2, Rm, Rn); break;\r
2073 case 11: NEG(sh2, Rm, Rn); break;\r
2074 case 12: EXTUB(sh2, Rm, Rn); break;\r
2075 case 13: EXTUW(sh2, Rm, Rn); break;\r
2076 case 14: EXTSB(sh2, Rm, Rn); break;\r
2077 case 15: EXTSW(sh2, Rm, Rn); break;\r
2078 }\r
2079 rlog(LRNM);\r
2080}\r
2081\r
2082INLINE void op0111(sh2_state *sh2, UINT16 opcode)\r
2083{\r
2084 ADDI(sh2, opcode & 0xff, Rn);\r
2085 rlog(LRN);\r
2086}\r
2087\r
2088INLINE void op1000(sh2_state *sh2, UINT16 opcode)\r
2089{\r
2090 switch ( opcode & (15<<8) )\r
2091 {\r
2092 case 0<< 8: MOVBS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
2093 case 1<< 8: MOVWS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
2094 case 2<< 8: ILLEGAL(sh2); rlog(0); break;\r
2095 case 3<< 8: ILLEGAL(sh2); rlog(0); break;\r
2096 case 4<< 8: MOVBL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
2097 case 5<< 8: MOVWL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
2098 case 6<< 8: ILLEGAL(sh2); rlog(0); break;\r
2099 case 7<< 8: ILLEGAL(sh2); rlog(0); break;\r
2100 case 8<< 8: CMPIM(sh2, opcode & 0xff); rlog(0); rlog1(0); break;\r
2101 case 9<< 8: BT(sh2, opcode & 0xff); rlog(0); break;\r
2102 case 10<< 8: ILLEGAL(sh2); rlog(0); break;\r
2103 case 11<< 8: BF(sh2, opcode & 0xff); rlog(0); break;\r
2104 case 12<< 8: ILLEGAL(sh2); rlog(0); break;\r
2105 case 13<< 8: BTS(sh2, opcode & 0xff); rlog(0); break;\r
2106 case 14<< 8: ILLEGAL(sh2); rlog(0); break;\r
2107 case 15<< 8: BFS(sh2, opcode & 0xff); rlog(0); break;\r
2108 }\r
2109}\r
2110\r
2111\r
2112INLINE void op1001(sh2_state *sh2, UINT16 opcode)\r
2113{\r
2114 MOVWI(sh2, opcode & 0xff, Rn);\r
2115 rlog(LRN);\r
2116}\r
2117\r
2118INLINE void op1010(sh2_state *sh2, UINT16 opcode)\r
2119{\r
2120 BRA(sh2, opcode & 0xfff);\r
2121 rlog(0);\r
2122}\r
2123\r
2124INLINE void op1011(sh2_state *sh2, UINT16 opcode)\r
2125{\r
2126 BSR(sh2, opcode & 0xfff);\r
2127 rlog(0);\r
2128 rlog1(SHR_PR);\r
2129}\r
2130\r
2131INLINE void op1100(sh2_state *sh2, UINT16 opcode)\r
2132{\r
2133 switch (opcode & (15<<8))\r
2134 {\r
2135 case 0<<8: MOVBSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2136 case 1<<8: MOVWSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2137 case 2<<8: MOVLSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2138 case 3<<8: TRAPA(sh2, opcode & 0xff); rlog1(SHR_VBR); break;\r
2139 case 4<<8: MOVBLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2140 case 5<<8: MOVWLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2141 case 6<<8: MOVLLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2142 case 7<<8: MOVA(sh2, opcode & 0xff); rlog1(0); break;\r
2143 case 8<<8: TSTI(sh2, opcode & 0xff); rlog1(0); break;\r
2144 case 9<<8: ANDI(sh2, opcode & 0xff); rlog1(0); break;\r
2145 case 10<<8: XORI(sh2, opcode & 0xff); rlog1(0); break;\r
2146 case 11<<8: ORI(sh2, opcode & 0xff); rlog1(0); break;\r
2147 case 12<<8: TSTM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2148 case 13<<8: ANDM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2149 case 14<<8: XORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2150 case 15<<8: ORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2151 }\r
2152 rlog(0);\r
2153}\r
2154\r
2155INLINE void op1101(sh2_state *sh2, UINT16 opcode)\r
2156{\r
2157 MOVLI(sh2, opcode & 0xff, Rn);\r
2158 rlog(LRN);\r
2159}\r
2160\r
2161INLINE void op1110(sh2_state *sh2, UINT16 opcode)\r
2162{\r
2163 MOVI(sh2, opcode & 0xff, Rn);\r
2164 rlog(LRN);\r
2165}\r
2166\r
2167INLINE void op1111(sh2_state *sh2, UINT16 opcode)\r
2168{\r
2169 ILLEGAL(sh2);\r
2170 rlog(0);\r
2171}\r
2172\r
2173#endif\r
fast MegaDrive/MegaCD/32X emulator