[picodrive.git] / cpu / sh2 / mame / sh2pico.c

#include "../sh2.h"

// MAME types
typedef signed char  INT8;
typedef signed short INT16;
typedef signed int   INT32;
typedef unsigned int   UINT32;
typedef unsigned short UINT16;
typedef unsigned char  UINT8;

#define RB(a) p32x_sh2_read8(a,sh2->is_slave)
#define RW(a) p32x_sh2_read16(a,sh2->is_slave)
#define RL(a) p32x_sh2_read32(a,sh2->is_slave)
#define WB(a,d) p32x_sh2_write8(a,d,sh2->is_slave)
#define WW(a,d) p32x_sh2_write16(a,d,sh2->is_slave)
#define WL(a,d) p32x_sh2_write32(a,d,sh2->is_slave)

// some stuff from sh2comn.h
#define T	0x00000001
#define S	0x00000002
#define I	0x000000f0
#define Q	0x00000100
#define M	0x00000200

#define AM	0xc7ffffff

#define FLAGS	(M|Q|I|S|T)

#define Rn	((opcode>>8)&15)
#define Rm	((opcode>>4)&15)

#define sh2_icount sh2->icount

#include "sh2.c"

#ifndef DRC_TMP

void sh2_execute(SH2 *sh2_, int cycles)
{
	sh2 = sh2_;
	sh2->cycles_aim += cycles;
	sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;

	if (sh2->icount <= 0)
		return;

	do
	{
		UINT32 opcode;

		if (sh2->delay)
		{
			sh2->ppc = sh2->delay;
			opcode = RW(sh2->delay);
			sh2->pc -= 2;
		}
		else
		{
			sh2->ppc = sh2->pc;
			opcode = RW(sh2->pc);
		}

		sh2->delay = 0;
		sh2->pc += 2;

		switch (opcode & ( 15 << 12))
		{
		case  0<<12: op0000(opcode); break;
		case  1<<12: op0001(opcode); break;
		case  2<<12: op0010(opcode); break;
		case  3<<12: op0011(opcode); break;
		case  4<<12: op0100(opcode); break;
		case  5<<12: op0101(opcode); break;
		case  6<<12: op0110(opcode); break;
		case  7<<12: op0111(opcode); break;
		case  8<<12: op1000(opcode); break;
		case  9<<12: op1001(opcode); break;
		case 10<<12: op1010(opcode); break;
		case 11<<12: op1011(opcode); break;
		case 12<<12: op1100(opcode); break;
		case 13<<12: op1101(opcode); break;
		case 14<<12: op1110(opcode); break;
		default: op1111(opcode); break;
		}

		if (sh2->test_irq && !sh2->delay)
		{
			if (sh2->pending_irl > sh2->pending_int_irq)
				sh2_irl_irq(sh2, sh2->pending_irl);
			else
				sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
			sh2->test_irq = 0;
		}
		sh2->icount--;
	}
	while (sh2->icount > 0 || sh2->delay);	/* can't interrupt before delay */

	sh2->cycles_done += cycles - sh2->icount;
}

#else // DRC_TMP

// tmp
void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2_, int opcode)
{
	sh2 = sh2_;
	sh2->pc += 2;

	switch (opcode & ( 15 << 12))
	{
		case  0<<12: op0000(opcode); break;
		case  1<<12: op0001(opcode); break;
		case  2<<12: op0010(opcode); break;
		case  3<<12: op0011(opcode); break;
		case  4<<12: op0100(opcode); break;
		case  5<<12: op0101(opcode); break;
		case  6<<12: op0110(opcode); break;
		case  7<<12: op0111(opcode); break;
		case  8<<12: op1000(opcode); break;
		case  9<<12: op1001(opcode); break;
		case 10<<12: op1010(opcode); break;
		case 11<<12: op1011(opcode); break;
		case 12<<12: op1100(opcode); break;
		case 13<<12: op1101(opcode); break;
		case 14<<12: op1110(opcode); break;
		default: op1111(opcode); break;
	}
}

#endif
Commit	Line	Data
	1	#include "../sh2.h"
	2
	3	// MAME types
	4	typedef signed char INT8;
	5	typedef signed short INT16;
	6	typedef signed int INT32;
	7	typedef unsigned int UINT32;
	8	typedef unsigned short UINT16;
	9	typedef unsigned char UINT8;
	10
	11	#define RB(a) p32x_sh2_read8(a,sh2->is_slave)
	12	#define RW(a) p32x_sh2_read16(a,sh2->is_slave)
	13	#define RL(a) p32x_sh2_read32(a,sh2->is_slave)
	14	#define WB(a,d) p32x_sh2_write8(a,d,sh2->is_slave)
	15	#define WW(a,d) p32x_sh2_write16(a,d,sh2->is_slave)
	16	#define WL(a,d) p32x_sh2_write32(a,d,sh2->is_slave)
	17
	18	// some stuff from sh2comn.h
	19	#define T 0x00000001
	20	#define S 0x00000002
	21	#define I 0x000000f0
	22	#define Q 0x00000100
	23	#define M 0x00000200
	24
	25	#define AM 0xc7ffffff
	26
	27	#define FLAGS (M\|Q\|I\|S\|T)
	28
	29	#define Rn ((opcode>>8)&15)
	30	#define Rm ((opcode>>4)&15)
	31
	32	#define sh2_icount sh2->icount
	33
	34	#include "sh2.c"
	35
	36	#ifndef DRC_TMP
	37
	38	void sh2_execute(SH2 *sh2_, int cycles)
	39	{
	40	sh2 = sh2_;
	41	sh2->cycles_aim += cycles;
	42	sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
	43
	44	if (sh2->icount <= 0)
	45	return;
	46
	47	do
	48	{
	49	UINT32 opcode;
	50
	51	if (sh2->delay)
	52	{
	53	sh2->ppc = sh2->delay;
	54	opcode = RW(sh2->delay);
	55	sh2->pc -= 2;
	56	}
	57	else
	58	{
	59	sh2->ppc = sh2->pc;
	60	opcode = RW(sh2->pc);
	61	}
	62
	63	sh2->delay = 0;
	64	sh2->pc += 2;
	65
	66	switch (opcode & ( 15 << 12))
	67	{
	68	case 0<<12: op0000(opcode); break;
	69	case 1<<12: op0001(opcode); break;
	70	case 2<<12: op0010(opcode); break;
	71	case 3<<12: op0011(opcode); break;
	72	case 4<<12: op0100(opcode); break;
	73	case 5<<12: op0101(opcode); break;
	74	case 6<<12: op0110(opcode); break;
	75	case 7<<12: op0111(opcode); break;
	76	case 8<<12: op1000(opcode); break;
	77	case 9<<12: op1001(opcode); break;
	78	case 10<<12: op1010(opcode); break;
	79	case 11<<12: op1011(opcode); break;
	80	case 12<<12: op1100(opcode); break;
	81	case 13<<12: op1101(opcode); break;
	82	case 14<<12: op1110(opcode); break;
	83	default: op1111(opcode); break;
	84	}
	85
	86	if (sh2->test_irq && !sh2->delay)
	87	{
	88	if (sh2->pending_irl > sh2->pending_int_irq)
	89	sh2_irl_irq(sh2, sh2->pending_irl);
	90	else
	91	sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
	92	sh2->test_irq = 0;
	93	}
	94	sh2->icount--;
	95	}
	96	while (sh2->icount > 0 \|\| sh2->delay); /* can't interrupt before delay */
	97
	98	sh2->cycles_done += cycles - sh2->icount;
	99	}
	100
	101	#else // DRC_TMP
	102
	103	// tmp
	104	void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2_, int opcode)
	105	{
	106	sh2 = sh2_;
	107	sh2->pc += 2;
	108
	109	switch (opcode & ( 15 << 12))
	110	{
	111	case 0<<12: op0000(opcode); break;
	112	case 1<<12: op0001(opcode); break;
	113	case 2<<12: op0010(opcode); break;
	114	case 3<<12: op0011(opcode); break;
	115	case 4<<12: op0100(opcode); break;
	116	case 5<<12: op0101(opcode); break;
	117	case 6<<12: op0110(opcode); break;
	118	case 7<<12: op0111(opcode); break;
	119	case 8<<12: op1000(opcode); break;
	120	case 9<<12: op1001(opcode); break;
	121	case 10<<12: op1010(opcode); break;
	122	case 11<<12: op1011(opcode); break;
	123	case 12<<12: op1100(opcode); break;
	124	case 13<<12: op1101(opcode); break;
	125	case 14<<12: op1110(opcode); break;
	126	default: op1111(opcode); break;
	127	}
	128	}
	129
	130	#endif
	131