| 1 | #ifndef __SH2_H__\r |
| 2 | #define __SH2_H__\r |
| 3 | \r |
| 4 | #if !defined(REGPARM) && defined(__i386__) \r |
| 5 | #define REGPARM(x) __attribute__((regparm(x)))\r |
| 6 | #else\r |
| 7 | #define REGPARM(x)\r |
| 8 | #endif\r |
| 9 | \r |
| 10 | // registers - matches structure order\r |
| 11 | typedef enum {\r |
| 12 | SHR_R0 = 0, SHR_SP = 15,\r |
| 13 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r |
| 14 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r |
| 15 | } sh2_reg_e;\r |
| 16 | \r |
| 17 | typedef struct SH2_\r |
| 18 | {\r |
| 19 | unsigned int r[16]; // 00\r |
| 20 | unsigned int pc; // 40\r |
| 21 | unsigned int ppc;\r |
| 22 | unsigned int pr;\r |
| 23 | unsigned int sr;\r |
| 24 | unsigned int gbr, vbr; // 50\r |
| 25 | unsigned int mach, macl; // 58\r |
| 26 | \r |
| 27 | // common\r |
| 28 | const void *read8_map; // 60\r |
| 29 | const void *read16_map;\r |
| 30 | const void **write8_tab;\r |
| 31 | const void **write16_tab;\r |
| 32 | \r |
| 33 | // drc stuff\r |
| 34 | int drc_tmp; // 70\r |
| 35 | int irq_cycles;\r |
| 36 | void *p_bios; // convenience pointers\r |
| 37 | void *p_da;\r |
| 38 | void *p_sdram; // 80\r |
| 39 | void *p_rom;\r |
| 40 | unsigned int pdb_io_csum[2];\r |
| 41 | \r |
| 42 | // interpreter stuff\r |
| 43 | int icount; // cycles left in current timeslice\r |
| 44 | unsigned int ea;\r |
| 45 | unsigned int delay;\r |
| 46 | unsigned int test_irq;\r |
| 47 | \r |
| 48 | int pending_level; // MAX(pending_irl, pending_int_irq)\r |
| 49 | int pending_irl;\r |
| 50 | int pending_int_irq; // internal irq\r |
| 51 | int pending_int_vector;\r |
| 52 | int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r |
| 53 | int is_slave;\r |
| 54 | \r |
| 55 | unsigned int cycles_aim; // subtract sh2_icount to get global counter\r |
| 56 | unsigned int cycles_done;\r |
| 57 | } SH2;\r |
| 58 | \r |
| 59 | extern SH2 *sh2; // active sh2. XXX: consider removing\r |
| 60 | \r |
| 61 | int sh2_init(SH2 *sh2, int is_slave);\r |
| 62 | void sh2_finish(SH2 *sh2);\r |
| 63 | void sh2_reset(SH2 *sh2);\r |
| 64 | void sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r |
| 65 | void sh2_internal_irq(SH2 *sh2, int level, int vector);\r |
| 66 | void sh2_do_irq(SH2 *sh2, int level, int vector);\r |
| 67 | void sh2_pack(const SH2 *sh2, unsigned char *buff);\r |
| 68 | void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r |
| 69 | \r |
| 70 | void sh2_execute(SH2 *sh2, int cycles);\r |
| 71 | \r |
| 72 | // regs, pending_int*, cycles, reserved\r |
| 73 | #define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r |
| 74 | \r |
| 75 | // pico memhandlers\r |
| 76 | // XXX: move somewhere else\r |
| 77 | unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r |
| 78 | unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r |
| 79 | unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r |
| 80 | int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r |
| 81 | int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r |
| 82 | int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r |
| 83 | \r |
| 84 | #endif /* __SH2_H__ */\r |