| 1 | #ifndef __SH2_H__\r |
| 2 | #define __SH2_H__\r |
| 3 | \r |
| 4 | #include "../../pico/pico_port.h"\r |
| 5 | \r |
| 6 | // registers - matches structure order\r |
| 7 | typedef enum {\r |
| 8 | SHR_R0 = 0, SHR_SP = 15,\r |
| 9 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r |
| 10 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r |
| 11 | } sh2_reg_e;\r |
| 12 | \r |
| 13 | typedef struct SH2_\r |
| 14 | {\r |
| 15 | unsigned int r[16]; // 00\r |
| 16 | unsigned int pc; // 40\r |
| 17 | unsigned int ppc;\r |
| 18 | unsigned int pr;\r |
| 19 | unsigned int sr;\r |
| 20 | unsigned int gbr, vbr; // 50\r |
| 21 | unsigned int mach, macl; // 58\r |
| 22 | \r |
| 23 | // common\r |
| 24 | const void *read8_map; // 60\r |
| 25 | const void *read16_map;\r |
| 26 | const void **write8_tab;\r |
| 27 | const void **write16_tab;\r |
| 28 | \r |
| 29 | // drc stuff\r |
| 30 | int drc_tmp; // 70\r |
| 31 | int irq_cycles;\r |
| 32 | void *p_bios; // convenience pointers\r |
| 33 | void *p_da;\r |
| 34 | void *p_sdram; // 80\r |
| 35 | void *p_rom;\r |
| 36 | unsigned int pdb_io_csum[2];\r |
| 37 | \r |
| 38 | #define SH2_STATE_RUN (1 << 0) // to prevent recursion\r |
| 39 | #define SH2_STATE_SLEEP (1 << 1)\r |
| 40 | #define SH2_STATE_CPOLL (1 << 2) // polling comm regs\r |
| 41 | #define SH2_STATE_VPOLL (1 << 3) // polling VDP\r |
| 42 | unsigned int state;\r |
| 43 | unsigned int poll_addr;\r |
| 44 | int poll_cycles;\r |
| 45 | int poll_cnt;\r |
| 46 | \r |
| 47 | // interpreter stuff\r |
| 48 | int icount; // cycles left in current timeslice\r |
| 49 | unsigned int ea;\r |
| 50 | unsigned int delay;\r |
| 51 | unsigned int test_irq;\r |
| 52 | \r |
| 53 | int pending_level; // MAX(pending_irl, pending_int_irq)\r |
| 54 | int pending_irl;\r |
| 55 | int pending_int_irq; // internal irq\r |
| 56 | int pending_int_vector;\r |
| 57 | int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r |
| 58 | int is_slave;\r |
| 59 | \r |
| 60 | unsigned int cycles_timeslice;\r |
| 61 | \r |
| 62 | struct SH2_ *other_sh2;\r |
| 63 | \r |
| 64 | // we use 68k reference cycles for easier sync\r |
| 65 | unsigned int m68krcycles_done;\r |
| 66 | unsigned int mult_m68k_to_sh2;\r |
| 67 | unsigned int mult_sh2_to_m68k;\r |
| 68 | \r |
| 69 | unsigned char data_array[0x1000]; // cache (can be used as RAM)\r |
| 70 | unsigned int peri_regs[0x200/4]; // periphereal regs\r |
| 71 | } SH2;\r |
| 72 | \r |
| 73 | #define CYCLE_MULT_SHIFT 10\r |
| 74 | #define C_M68K_TO_SH2(xsh2, c) \\r |
| 75 | ((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r |
| 76 | #define C_SH2_TO_M68K(xsh2, c) \\r |
| 77 | ((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r |
| 78 | \r |
| 79 | int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r |
| 80 | void sh2_finish(SH2 *sh2);\r |
| 81 | void sh2_reset(SH2 *sh2);\r |
| 82 | int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r |
| 83 | void sh2_internal_irq(SH2 *sh2, int level, int vector);\r |
| 84 | void sh2_do_irq(SH2 *sh2, int level, int vector);\r |
| 85 | void sh2_pack(const SH2 *sh2, unsigned char *buff);\r |
| 86 | void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r |
| 87 | \r |
| 88 | int sh2_execute_drc(SH2 *sh2c, int cycles);\r |
| 89 | int sh2_execute_interpreter(SH2 *sh2c, int cycles);\r |
| 90 | \r |
| 91 | static __inline int sh2_execute(SH2 *sh2, int cycles, int use_drc)\r |
| 92 | {\r |
| 93 | int ret;\r |
| 94 | \r |
| 95 | sh2->cycles_timeslice = cycles;\r |
| 96 | #ifdef DRC_SH2\r |
| 97 | if (use_drc)\r |
| 98 | ret = sh2_execute_drc(sh2, cycles);\r |
| 99 | else\r |
| 100 | #endif\r |
| 101 | ret = sh2_execute_interpreter(sh2, cycles);\r |
| 102 | \r |
| 103 | return sh2->cycles_timeslice - ret;\r |
| 104 | }\r |
| 105 | \r |
| 106 | // regs, pending_int*, cycles, reserved\r |
| 107 | #define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r |
| 108 | \r |
| 109 | // pico memhandlers\r |
| 110 | // XXX: move somewhere else\r |
| 111 | unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r |
| 112 | unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r |
| 113 | unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r |
| 114 | void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r |
| 115 | void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r |
| 116 | void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r |
| 117 | \r |
| 118 | // debug\r |
| 119 | #ifdef DRC_CMP\r |
| 120 | void do_sh2_trace(SH2 *current, int cycles);\r |
| 121 | void do_sh2_cmp(SH2 *current);\r |
| 122 | #endif\r |
| 123 | \r |
| 124 | #endif /* __SH2_H__ */\r |