[picodrive.git] / cpu / sh2 / sh2.h

#ifndef __SH2_H__\r
#define __SH2_H__\r
\r
typedef struct\r
{\r
	unsigned int	r[16];		// 00\r
	unsigned int	pc;		// 40\r
	unsigned int	ppc;\r
	unsigned int	pr;\r
	unsigned int	sr;\r
	unsigned int	gbr, vbr;	// 50\r
	unsigned int	mach, macl;	// 58\r
\r
	// interpreter stuff\r
	int		icount;		// 60 cycles left in current timeslice\r
	unsigned int	ea;\r
	unsigned int	delay;\r
	unsigned int	test_irq;\r
\r
	// common\r
	const void	*read8_map;	// 70\r
	const void	*read16_map;\r
	const void	**write8_tab;\r
	const void	**write16_tab;\r
\r
	// drc stuff\r
	//void	**pc_hashtab;		// 80\r
\r
	int	pending_level;		// MAX(pending_irl, pending_int_irq)\r
	int	pending_irl;\r
	int	pending_int_irq;	// internal irq\r
	int	pending_int_vector;\r
	void	(*irq_callback)(int id, int level);\r
	int	is_slave;\r
\r
	unsigned int	cycles_aim;	// subtract sh2_icount to get global counter\r
	unsigned int	cycles_done;\r
} SH2;\r
\r
extern SH2 *sh2; // active sh2\r
\r
int  sh2_init(SH2 *sh2, int is_slave);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
void sh2_irl_irq(SH2 *sh2, int level);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
\r
void sh2_execute(SH2 *sh2, int cycles);\r
\r
// pico memhandlers\r
// XXX: move somewhere else\r
unsigned int p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
void p32x_sh2_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
void p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
void p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
#endif /* __SH2_H__ */\r
Commit	Line	Data
	1	#ifndef __SH2_H__\r
	2	#define __SH2_H__\r
	3	\r
	4	typedef struct\r
	5	{\r
	6	unsigned int r[16]; // 00\r
	7	unsigned int pc; // 40\r
	8	unsigned int ppc;\r
	9	unsigned int pr;\r
	10	unsigned int sr;\r
	11	unsigned int gbr, vbr; // 50\r
	12	unsigned int mach, macl; // 58\r
	13	\r
	14	// interpreter stuff\r
	15	int icount; // 60 cycles left in current timeslice\r
	16	unsigned int ea;\r
	17	unsigned int delay;\r
	18	unsigned int test_irq;\r
	19	\r
	20	// common\r
	21	const void *read8_map; // 70\r
	22	const void *read16_map;\r
	23	const void **write8_tab;\r
	24	const void **write16_tab;\r
	25	\r
	26	// drc stuff\r
	27	//void **pc_hashtab; // 80\r
	28	\r
	29	int pending_level; // MAX(pending_irl, pending_int_irq)\r
	30	int pending_irl;\r
	31	int pending_int_irq; // internal irq\r
	32	int pending_int_vector;\r
	33	void (*irq_callback)(int id, int level);\r
	34	int is_slave;\r
	35	\r
	36	unsigned int cycles_aim; // subtract sh2_icount to get global counter\r
	37	unsigned int cycles_done;\r
	38	} SH2;\r
	39	\r
	40	extern SH2 *sh2; // active sh2\r
	41	\r
	42	int sh2_init(SH2 *sh2, int is_slave);\r
	43	void sh2_finish(SH2 *sh2);\r
	44	void sh2_reset(SH2 *sh2);\r
	45	void sh2_irl_irq(SH2 *sh2, int level);\r
	46	void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
	47	void sh2_do_irq(SH2 *sh2, int level, int vector);\r
	48	\r
	49	void sh2_execute(SH2 *sh2, int cycles);\r
	50	\r
	51	// pico memhandlers\r
	52	// XXX: move somewhere else\r
	53	unsigned int p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
	54	unsigned int p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
	55	unsigned int p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
	56	void p32x_sh2_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
	57	void p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
	58	void p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
	59	\r
	60	#endif /* __SH2_H__ */\r