| | 1 | #ifndef __SH2_H__\r |
| | 2 | #define __SH2_H__\r |
| | 3 | \r |
| | 4 | #include <pico/pico_types.h>\r |
| | 5 | #include <pico/pico_port.h>\r |
| | 6 | \r |
| | 7 | // registers - matches structure order\r |
| | 8 | typedef enum {\r |
| | 9 | SHR_R0 = 0, SHR_SP = 15,\r |
| | 10 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r |
| | 11 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r |
| | 12 | SH2_REGS, // register set size\r |
| | 13 | SHR_T = 29, SHR_MEM = 30, SHR_TMP = 31, // drc specific pseudo regs\r |
| | 14 | } sh2_reg_e;\r |
| | 15 | #define SHR_R(n) (SHR_R0+(n))\r |
| | 16 | \r |
| | 17 | typedef struct SH2_\r |
| | 18 | {\r |
| | 19 | // registers. this MUST correlate with enum sh2_reg_e.\r |
| | 20 | uint32_t r[16] ALIGNED(32);\r |
| | 21 | uint32_t pc; // 40\r |
| | 22 | uint32_t ppc;\r |
| | 23 | uint32_t pr;\r |
| | 24 | uint32_t sr;\r |
| | 25 | uint32_t gbr, vbr; // 50\r |
| | 26 | uint32_t mach, macl; // 58\r |
| | 27 | \r |
| | 28 | // common\r |
| | 29 | const void *read8_map;\r |
| | 30 | const void *read16_map;\r |
| | 31 | const void *read32_map;\r |
| | 32 | const void **write8_tab;\r |
| | 33 | const void **write16_tab;\r |
| | 34 | const void **write32_tab;\r |
| | 35 | \r |
| | 36 | // drc stuff\r |
| | 37 | int drc_tmp;\r |
| | 38 | int irq_cycles;\r |
| | 39 | void *p_bios; // convenience pointers\r |
| | 40 | void *p_da;\r |
| | 41 | void *p_sdram;\r |
| | 42 | void *p_rom;\r |
| | 43 | void *p_dram;\r |
| | 44 | void *p_drcblk_da;\r |
| | 45 | void *p_drcblk_ram;\r |
| | 46 | unsigned int pdb_io_csum[2];\r |
| | 47 | \r |
| | 48 | #define SH2_STATE_RUN (1 << 0) // to prevent recursion\r |
| | 49 | #define SH2_STATE_SLEEP (1 << 1) // temporarily stopped (DMA, IO, ...)\r |
| | 50 | #define SH2_STATE_CPOLL (1 << 2) // polling comm regs\r |
| | 51 | #define SH2_STATE_VPOLL (1 << 3) // polling VDP\r |
| | 52 | #define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM\r |
| | 53 | #define SH2_TIMER_RUN (1 << 6) // SOC WDT timer is running\r |
| | 54 | #define SH2_IN_DRC (1 << 7) // DRC in use\r |
| | 55 | unsigned int state;\r |
| | 56 | uint32_t poll_addr;\r |
| | 57 | unsigned int poll_cycles;\r |
| | 58 | int poll_cnt;\r |
| | 59 | // NB MUST be a bit unused in SH2 SR, see also cpu/sh2/compiler.c!\r |
| | 60 | #define SH2_NO_POLLING (1 << 10) // poll detection control\r |
| | 61 | int no_polling;\r |
| | 62 | \r |
| | 63 | // DRC branch cache. size must be 2^n and <=128\r |
| | 64 | int rts_cache_idx;\r |
| | 65 | struct { uint32_t pc; void *code; } rts_cache[16];\r |
| | 66 | struct { uint32_t pc; void *code; } branch_cache[128];\r |
| | 67 | \r |
| | 68 | // interpreter stuff\r |
| | 69 | int icount; // cycles left in current timeslice\r |
| | 70 | unsigned int ea;\r |
| | 71 | unsigned int delay;\r |
| | 72 | unsigned int test_irq;\r |
| | 73 | \r |
| | 74 | int pending_level; // MAX(pending_irl, pending_int_irq)\r |
| | 75 | int pending_irl;\r |
| | 76 | int pending_int_irq; // internal irq\r |
| | 77 | int pending_int_vector;\r |
| | 78 | int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r |
| | 79 | int is_slave;\r |
| | 80 | \r |
| | 81 | unsigned int cycles_timeslice;\r |
| | 82 | \r |
| | 83 | struct SH2_ *other_sh2;\r |
| | 84 | int (*run)(struct SH2_ *, int);\r |
| | 85 | \r |
| | 86 | // we use 68k reference cycles for easier sync\r |
| | 87 | unsigned int m68krcycles_done;\r |
| | 88 | unsigned int mult_m68k_to_sh2;\r |
| | 89 | unsigned int mult_sh2_to_m68k;\r |
| | 90 | \r |
| | 91 | uint8_t data_array[0x1000]; // cache (can be used as RAM)\r |
| | 92 | uint32_t peri_regs[0x200/4]; // peripheral regs\r |
| | 93 | } SH2;\r |
| | 94 | \r |
| | 95 | #define CYCLE_MULT_SHIFT 10\r |
| | 96 | #define C_M68K_TO_SH2(xsh2, c) \\r |
| | 97 | (int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r |
| | 98 | #define C_SH2_TO_M68K(xsh2, c) \\r |
| | 99 | (int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r |
| | 100 | \r |
| | 101 | int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r |
| | 102 | void sh2_finish(SH2 *sh2);\r |
| | 103 | void sh2_reset(SH2 *sh2);\r |
| | 104 | int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r |
| | 105 | void sh2_internal_irq(SH2 *sh2, int level, int vector);\r |
| | 106 | void sh2_do_irq(SH2 *sh2, int level, int vector);\r |
| | 107 | void sh2_pack(const SH2 *sh2, unsigned char *buff);\r |
| | 108 | void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r |
| | 109 | \r |
| | 110 | int sh2_execute_drc(SH2 *sh2c, int cycles);\r |
| | 111 | int sh2_execute_interpreter(SH2 *sh2c, int cycles);\r |
| | 112 | \r |
| | 113 | static __inline void sh2_execute_prepare(SH2 *sh2, int use_drc)\r |
| | 114 | {\r |
| | 115 | #ifdef DRC_SH2\r |
| | 116 | sh2->run = use_drc ? sh2_execute_drc : sh2_execute_interpreter;\r |
| | 117 | #else\r |
| | 118 | sh2->run = sh2_execute_interpreter;\r |
| | 119 | #endif\r |
| | 120 | }\r |
| | 121 | \r |
| | 122 | static __inline int sh2_execute(SH2 *sh2, int cycles)\r |
| | 123 | {\r |
| | 124 | int ret;\r |
| | 125 | \r |
| | 126 | sh2->cycles_timeslice = cycles;\r |
| | 127 | ret = sh2->run(sh2, cycles);\r |
| | 128 | \r |
| | 129 | return sh2->cycles_timeslice - ret;\r |
| | 130 | }\r |
| | 131 | \r |
| | 132 | // regs, pending_int*, cycles, reserved\r |
| | 133 | #define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r |
| | 134 | \r |
| | 135 | // pico memhandlers\r |
| | 136 | // XXX: move somewhere else\r |
| | 137 | u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2);\r |
| | 138 | u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2);\r |
| | 139 | u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2);\r |
| | 140 | void REGPARM(3) p32x_sh2_write8 (u32 a, u32 d, SH2 *sh2);\r |
| | 141 | void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2);\r |
| | 142 | void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2);\r |
| | 143 | \r |
| | 144 | // debug\r |
| | 145 | #ifdef DRC_CMP\r |
| | 146 | void do_sh2_trace(SH2 *current, int cycles);\r |
| | 147 | void REGPARM(1) do_sh2_cmp(SH2 *current);\r |
| | 148 | #endif\r |
| | 149 | \r |
| | 150 | #endif /* __SH2_H__ */\r |
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