lightrec: Add mirror to parallel port
[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c
... / ...
CommitLineData
1#include <lightrec.h>
2#include <errno.h>
3#include <stdbool.h>
4#include <stdio.h>
5#include <unistd.h>
6#include <signal.h>
7#include <assert.h>
8
9#if P_HAVE_MMAP
10#include <sys/mman.h>
11#endif
12
13#include "../cdrom.h"
14#include "../gpu.h"
15#include "../gte.h"
16#include "../mdec.h"
17#include "../psxdma.h"
18#include "../psxhw.h"
19#include "../psxmem.h"
20#include "../r3000a.h"
21#include "../psxinterpreter.h"
22#include "../new_dynarec/events.h"
23
24#include "../frontend/main.h"
25
26#include "mem.h"
27#include "plugin.h"
28
29#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
30#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
31#endif
32
33#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
34
35#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
36# define LE32TOH(x) __builtin_bswap32(x)
37# define HTOLE32(x) __builtin_bswap32(x)
38# define LE16TOH(x) __builtin_bswap16(x)
39# define HTOLE16(x) __builtin_bswap16(x)
40#else
41# define LE32TOH(x) (x)
42# define HTOLE32(x) (x)
43# define LE16TOH(x) (x)
44# define HTOLE16(x) (x)
45#endif
46
47#ifdef __GNUC__
48# define likely(x) __builtin_expect(!!(x),1)
49# define unlikely(x) __builtin_expect(!!(x),0)
50#else
51# define likely(x) (x)
52# define unlikely(x) (x)
53#endif
54
55psxRegisters psxRegs;
56Rcnt rcnts[4];
57
58void* code_buffer;
59
60static struct lightrec_state *lightrec_state;
61
62static char *name = "retroarch.exe";
63
64static bool use_lightrec_interpreter;
65static bool use_pcsx_interpreter;
66static bool block_stepping;
67static u32 cycle_mult_to_pcsx; // 22.10 fractional
68static u32 cycle_mult_from_pcsx;
69
70enum my_cp2_opcodes {
71 OP_CP2_RTPS = 0x01,
72 OP_CP2_NCLIP = 0x06,
73 OP_CP2_OP = 0x0c,
74 OP_CP2_DPCS = 0x10,
75 OP_CP2_INTPL = 0x11,
76 OP_CP2_MVMVA = 0x12,
77 OP_CP2_NCDS = 0x13,
78 OP_CP2_CDP = 0x14,
79 OP_CP2_NCDT = 0x16,
80 OP_CP2_NCCS = 0x1b,
81 OP_CP2_CC = 0x1c,
82 OP_CP2_NCS = 0x1e,
83 OP_CP2_NCT = 0x20,
84 OP_CP2_SQR = 0x28,
85 OP_CP2_DCPL = 0x29,
86 OP_CP2_DPCT = 0x2a,
87 OP_CP2_AVSZ3 = 0x2d,
88 OP_CP2_AVSZ4 = 0x2e,
89 OP_CP2_RTPT = 0x30,
90 OP_CP2_GPF = 0x3d,
91 OP_CP2_GPL = 0x3e,
92 OP_CP2_NCCT = 0x3f,
93};
94
95static void (*cp2_ops[])(struct psxCP2Regs *) = {
96 [OP_CP2_RTPS] = gteRTPS,
97 [OP_CP2_RTPS] = gteRTPS,
98 [OP_CP2_NCLIP] = gteNCLIP,
99 [OP_CP2_OP] = gteOP,
100 [OP_CP2_DPCS] = gteDPCS,
101 [OP_CP2_INTPL] = gteINTPL,
102 [OP_CP2_MVMVA] = gteMVMVA,
103 [OP_CP2_NCDS] = gteNCDS,
104 [OP_CP2_CDP] = gteCDP,
105 [OP_CP2_NCDT] = gteNCDT,
106 [OP_CP2_NCCS] = gteNCCS,
107 [OP_CP2_CC] = gteCC,
108 [OP_CP2_NCS] = gteNCS,
109 [OP_CP2_NCT] = gteNCT,
110 [OP_CP2_SQR] = gteSQR,
111 [OP_CP2_DCPL] = gteDCPL,
112 [OP_CP2_DPCT] = gteDPCT,
113 [OP_CP2_AVSZ3] = gteAVSZ3,
114 [OP_CP2_AVSZ4] = gteAVSZ4,
115 [OP_CP2_RTPT] = gteRTPT,
116 [OP_CP2_GPF] = gteGPF,
117 [OP_CP2_GPL] = gteGPL,
118 [OP_CP2_NCCT] = gteNCCT,
119};
120
121static char cache_buf[64 * 1024];
122
123static void cop2_op(struct lightrec_state *state, u32 func)
124{
125 struct lightrec_registers *regs = lightrec_get_registers(state);
126
127 psxRegs.code = func;
128
129 if (unlikely(!cp2_ops[func & 0x3f])) {
130 fprintf(stderr, "Invalid CP2 function %u\n", func);
131 } else {
132 /* This works because regs->cp2c comes right after regs->cp2d,
133 * so it can be cast to a pcsxCP2Regs pointer. */
134 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
135 }
136}
137
138static bool has_interrupt(void)
139{
140 struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
141
142 return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
143 (regs->cp0[12] & 0x401) == 0x401) ||
144 (regs->cp0[12] & regs->cp0[13] & 0x0300);
145}
146
147static u32 cycles_pcsx_to_lightrec(u32 c)
148{
149 assert((u64)c * cycle_mult_from_pcsx <= (u32)-1);
150 return c * cycle_mult_from_pcsx >> 10;
151}
152
153static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
154{
155 psxRegs.cycle += lightrec_current_cycle_count(state) * cycle_mult_to_pcsx >> 10;
156 lightrec_reset_cycle_count(state, 0);
157}
158
159static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
160{
161 s32 cycles_left = next_interupt - psxRegs.cycle;
162
163 if (block_stepping || cycles_left <= 0 || has_interrupt())
164 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
165 else {
166 lightrec_set_target_cycle_count(state,
167 cycles_pcsx_to_lightrec(cycles_left));
168 }
169}
170
171static void hw_write_byte(struct lightrec_state *state,
172 u32 op, void *host, u32 mem, u8 val)
173{
174 lightrec_tansition_to_pcsx(state);
175
176 psxHwWrite8(mem, val);
177
178 lightrec_tansition_from_pcsx(state);
179}
180
181static void hw_write_half(struct lightrec_state *state,
182 u32 op, void *host, u32 mem, u16 val)
183{
184 lightrec_tansition_to_pcsx(state);
185
186 psxHwWrite16(mem, val);
187
188 lightrec_tansition_from_pcsx(state);
189}
190
191static void hw_write_word(struct lightrec_state *state,
192 u32 op, void *host, u32 mem, u32 val)
193{
194 lightrec_tansition_to_pcsx(state);
195
196 psxHwWrite32(mem, val);
197
198 lightrec_tansition_from_pcsx(state);
199}
200
201static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
202{
203 u8 val;
204
205 lightrec_tansition_to_pcsx(state);
206
207 val = psxHwRead8(mem);
208
209 lightrec_tansition_from_pcsx(state);
210
211 return val;
212}
213
214static u16 hw_read_half(struct lightrec_state *state,
215 u32 op, void *host, u32 mem)
216{
217 u16 val;
218
219 lightrec_tansition_to_pcsx(state);
220
221 val = psxHwRead16(mem);
222
223 lightrec_tansition_from_pcsx(state);
224
225 return val;
226}
227
228static u32 hw_read_word(struct lightrec_state *state,
229 u32 op, void *host, u32 mem)
230{
231 u32 val;
232
233 lightrec_tansition_to_pcsx(state);
234
235 val = psxHwRead32(mem);
236
237 lightrec_tansition_from_pcsx(state);
238
239 return val;
240}
241
242static struct lightrec_mem_map_ops hw_regs_ops = {
243 .sb = hw_write_byte,
244 .sh = hw_write_half,
245 .sw = hw_write_word,
246 .lb = hw_read_byte,
247 .lh = hw_read_half,
248 .lw = hw_read_word,
249};
250
251static u32 cache_ctrl;
252
253static void cache_ctrl_write_word(struct lightrec_state *state,
254 u32 op, void *host, u32 mem, u32 val)
255{
256 cache_ctrl = val;
257}
258
259static u32 cache_ctrl_read_word(struct lightrec_state *state,
260 u32 op, void *host, u32 mem)
261{
262 return cache_ctrl;
263}
264
265static struct lightrec_mem_map_ops cache_ctrl_ops = {
266 .sw = cache_ctrl_write_word,
267 .lw = cache_ctrl_read_word,
268};
269
270static struct lightrec_mem_map lightrec_map[] = {
271 [PSX_MAP_KERNEL_USER_RAM] = {
272 /* Kernel and user memory */
273 .pc = 0x00000000,
274 .length = 0x200000,
275 },
276 [PSX_MAP_BIOS] = {
277 /* BIOS */
278 .pc = 0x1fc00000,
279 .length = 0x80000,
280 },
281 [PSX_MAP_SCRATCH_PAD] = {
282 /* Scratch pad */
283 .pc = 0x1f800000,
284 .length = 0x400,
285 },
286 [PSX_MAP_PARALLEL_PORT] = {
287 /* Parallel port */
288 .pc = 0x1f000000,
289 .length = 0x10000,
290 },
291 [PSX_MAP_HW_REGISTERS] = {
292 /* Hardware registers */
293 .pc = 0x1f801000,
294 .length = 0x8000,
295 .ops = &hw_regs_ops,
296 },
297 [PSX_MAP_CACHE_CONTROL] = {
298 /* Cache control */
299 .pc = 0x5ffe0130,
300 .length = 4,
301 .ops = &cache_ctrl_ops,
302 },
303
304 /* Mirrors of the kernel/user memory */
305 [PSX_MAP_MIRROR1] = {
306 .pc = 0x00200000,
307 .length = 0x200000,
308 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
309 },
310 [PSX_MAP_MIRROR2] = {
311 .pc = 0x00400000,
312 .length = 0x200000,
313 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
314 },
315 [PSX_MAP_MIRROR3] = {
316 .pc = 0x00600000,
317 .length = 0x200000,
318 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
319 },
320
321 /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
322 [PSX_MAP_PPORT_MIRROR] = {
323 .pc = 0x1fa00000,
324 .length = 0x10000,
325 .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
326 },
327
328 /* Code buffer */
329 [PSX_MAP_CODE_BUFFER] = {
330 .length = CODE_BUFFER_SIZE,
331 },
332};
333
334static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
335{
336 if (enable)
337 memcpy(psxM, cache_buf, sizeof(cache_buf));
338 else
339 memcpy(cache_buf, psxM, sizeof(cache_buf));
340}
341
342static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
343{
344 switch (size) {
345 case 8:
346 switch (kaddr) {
347 case 0x1f801040:
348 case 0x1f801050:
349 case 0x1f801800:
350 case 0x1f801801:
351 case 0x1f801802:
352 case 0x1f801803:
353 return false;
354 default:
355 return true;
356 }
357 case 16:
358 switch (kaddr) {
359 case 0x1f801040:
360 case 0x1f801044:
361 case 0x1f801048:
362 case 0x1f80104a:
363 case 0x1f80104e:
364 case 0x1f801050:
365 case 0x1f801054:
366 case 0x1f80105a:
367 case 0x1f80105e:
368 case 0x1f801100:
369 case 0x1f801104:
370 case 0x1f801108:
371 case 0x1f801110:
372 case 0x1f801114:
373 case 0x1f801118:
374 case 0x1f801120:
375 case 0x1f801124:
376 case 0x1f801128:
377 return false;
378 case 0x1f801070:
379 case 0x1f801074:
380 return !is_write;
381 default:
382 return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
383 }
384 default:
385 switch (kaddr) {
386 case 0x1f801040:
387 case 0x1f801050:
388 case 0x1f801100:
389 case 0x1f801104:
390 case 0x1f801108:
391 case 0x1f801110:
392 case 0x1f801114:
393 case 0x1f801118:
394 case 0x1f801120:
395 case 0x1f801124:
396 case 0x1f801128:
397 case 0x1f801810:
398 case 0x1f801814:
399 case 0x1f801820:
400 case 0x1f801824:
401 return false;
402 case 0x1f801070:
403 case 0x1f801074:
404 case 0x1f801088:
405 case 0x1f801098:
406 case 0x1f8010a8:
407 case 0x1f8010b8:
408 case 0x1f8010c8:
409 case 0x1f8010e8:
410 case 0x1f8010f4:
411 return !is_write;
412 default:
413 return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
414 }
415 }
416}
417
418#if defined(HW_DOL) || defined(HW_RVL)
419static void lightrec_code_inv(void *ptr, uint32_t len)
420{
421 extern void DCFlushRange(void *ptr, u32 len);
422 extern void ICInvalidateRange(void *ptr, u32 len);
423
424 DCFlushRange(ptr, len);
425 ICInvalidateRange(ptr, len);
426}
427#elif defined(HW_WUP)
428static void lightrec_code_inv(void *ptr, uint32_t len)
429{
430 wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
431}
432#endif
433
434static const struct lightrec_ops lightrec_ops = {
435 .cop2_op = cop2_op,
436 .enable_ram = lightrec_enable_ram,
437 .hw_direct = lightrec_can_hw_direct,
438#if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
439 .code_inv = lightrec_code_inv,
440#endif
441};
442
443static int lightrec_plugin_init(void)
444{
445 lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
446 lightrec_map[PSX_MAP_BIOS].address = psxR;
447 lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
448 lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
449 lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
450
451 if (!LIGHTREC_CUSTOM_MAP) {
452#if P_HAVE_MMAP
453 code_buffer = mmap(0, CODE_BUFFER_SIZE,
454 PROT_EXEC | PROT_READ | PROT_WRITE,
455 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
456 if (code_buffer == MAP_FAILED)
457 return -ENOMEM;
458#else
459 code_buffer = malloc(CODE_BUFFER_SIZE);
460 if (!code_buffer)
461 return -ENOMEM;
462#endif
463 }
464
465 if (LIGHTREC_CUSTOM_MAP) {
466 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
467 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
468 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
469 }
470
471 lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
472
473 use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
474
475 lightrec_state = lightrec_init(name,
476 lightrec_map, ARRAY_SIZE(lightrec_map),
477 &lightrec_ops);
478
479 // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
480 // (uintptr_t) psxM,
481 // (uintptr_t) psxP,
482 // (uintptr_t) psxR,
483 // (uintptr_t) psxH);
484
485#ifndef _WIN32
486 signal(SIGPIPE, exit);
487#endif
488 return 0;
489}
490
491static void lightrec_plugin_execute_internal(bool block_only)
492{
493 struct lightrec_registers *regs;
494 u32 flags, cycles_pcsx;
495
496 regs = lightrec_get_registers(lightrec_state);
497 gen_interupt((psxCP0Regs *)regs->cp0);
498 cycles_pcsx = next_interupt - psxRegs.cycle;
499 assert((s32)cycles_pcsx > 0);
500
501 // step during early boot so that 0x80030000 fastboot hack works
502 block_stepping = block_only;
503 if (block_only)
504 cycles_pcsx = 0;
505
506 if (use_pcsx_interpreter) {
507 intExecuteBlock(0);
508 } else {
509 u32 cycles_lightrec = cycles_pcsx_to_lightrec(cycles_pcsx);
510 if (unlikely(use_lightrec_interpreter)) {
511 psxRegs.pc = lightrec_run_interpreter(lightrec_state,
512 psxRegs.pc,
513 cycles_lightrec);
514 } else {
515 psxRegs.pc = lightrec_execute(lightrec_state,
516 psxRegs.pc, cycles_lightrec);
517 }
518
519 lightrec_tansition_to_pcsx(lightrec_state);
520
521 flags = lightrec_exit_flags(lightrec_state);
522
523 if (flags & LIGHTREC_EXIT_SEGFAULT) {
524 fprintf(stderr, "Exiting at cycle 0x%08x\n",
525 psxRegs.cycle);
526 exit(1);
527 }
528
529 if (flags & LIGHTREC_EXIT_SYSCALL)
530 psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
531 }
532
533 if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
534 /* Handle software interrupts */
535 regs->cp0[13] &= ~0x7c;
536 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
537 }
538}
539
540static void lightrec_plugin_execute(void)
541{
542 extern int stop;
543
544 while (!stop)
545 lightrec_plugin_execute_internal(false);
546}
547
548static void lightrec_plugin_execute_block(enum blockExecCaller caller)
549{
550 lightrec_plugin_execute_internal(true);
551}
552
553static void lightrec_plugin_clear(u32 addr, u32 size)
554{
555 if (addr == 0 && size == UINT32_MAX)
556 lightrec_invalidate_all(lightrec_state);
557 else
558 /* size * 4: PCSX uses DMA units */
559 lightrec_invalidate(lightrec_state, addr, size * 4);
560}
561
562static void lightrec_plugin_sync_regs_to_pcsx(void);
563static void lightrec_plugin_sync_regs_from_pcsx(void);
564
565static void lightrec_plugin_notify(enum R3000Anote note, void *data)
566{
567 switch (note)
568 {
569 case R3000ACPU_NOTIFY_CACHE_ISOLATED:
570 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
571 /* not used, lightrec calls lightrec_enable_ram() instead */
572 break;
573 case R3000ACPU_NOTIFY_BEFORE_SAVE:
574 lightrec_plugin_sync_regs_to_pcsx();
575 break;
576 case R3000ACPU_NOTIFY_AFTER_LOAD:
577 lightrec_plugin_sync_regs_from_pcsx();
578 break;
579 }
580}
581
582static void lightrec_plugin_apply_config()
583{
584 u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
585 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
586 assert(cycle_mult);
587 cycle_mult_to_pcsx = (cycle_mult * 1024 + 199) / 200;
588 cycle_mult_from_pcsx = (200 * 1024 + cycle_mult/2) / cycle_mult;
589}
590
591static void lightrec_plugin_shutdown(void)
592{
593 lightrec_destroy(lightrec_state);
594
595 if (!LIGHTREC_CUSTOM_MAP) {
596#if P_HAVE_MMAP
597 munmap(code_buffer, CODE_BUFFER_SIZE);
598#else
599 free(code_buffer);
600#endif
601 }
602}
603
604static void lightrec_plugin_reset(void)
605{
606 struct lightrec_registers *regs;
607
608 regs = lightrec_get_registers(lightrec_state);
609
610 /* Invalidate all blocks */
611 lightrec_invalidate_all(lightrec_state);
612
613 /* Reset registers */
614 memset(regs, 0, sizeof(*regs));
615
616 regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
617 regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
618}
619
620static void lightrec_plugin_sync_regs_from_pcsx(void)
621{
622 struct lightrec_registers *regs;
623
624 regs = lightrec_get_registers(lightrec_state);
625 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
626 memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
627 memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
628
629 lightrec_invalidate_all(lightrec_state);
630}
631
632static void lightrec_plugin_sync_regs_to_pcsx(void)
633{
634 struct lightrec_registers *regs;
635
636 regs = lightrec_get_registers(lightrec_state);
637 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
638 memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
639 memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
640}
641
642R3000Acpu psxRec =
643{
644 lightrec_plugin_init,
645 lightrec_plugin_reset,
646 lightrec_plugin_execute,
647 lightrec_plugin_execute_block,
648 lightrec_plugin_clear,
649 lightrec_plugin_notify,
650 lightrec_plugin_apply_config,
651 lightrec_plugin_shutdown,
652};