attempt to fix build
[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c
... / ...
CommitLineData
1#include <lightrec.h>
2#include <stdbool.h>
3#include <stdio.h>
4#include <unistd.h>
5#include <signal.h>
6
7#include "../cdrom.h"
8#include "../gpu.h"
9#include "../gte.h"
10#include "../mdec.h"
11#include "../psxdma.h"
12#include "../psxhw.h"
13#include "../psxmem.h"
14#include "../r3000a.h"
15#include "../psxinterpreter.h"
16#include "../new_dynarec/events.h"
17
18#include "../frontend/main.h"
19
20#include "mem.h"
21#include "plugin.h"
22
23#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
24#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
25#endif
26
27#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
28
29#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
30# define LE32TOH(x) __builtin_bswap32(x)
31# define HTOLE32(x) __builtin_bswap32(x)
32# define LE16TOH(x) __builtin_bswap16(x)
33# define HTOLE16(x) __builtin_bswap16(x)
34#else
35# define LE32TOH(x) (x)
36# define HTOLE32(x) (x)
37# define LE16TOH(x) (x)
38# define HTOLE16(x) (x)
39#endif
40
41#ifdef __GNUC__
42# define likely(x) __builtin_expect(!!(x),1)
43# define unlikely(x) __builtin_expect(!!(x),0)
44#else
45# define likely(x) (x)
46# define unlikely(x) (x)
47#endif
48
49psxRegisters psxRegs;
50Rcnt rcnts[4];
51
52static struct lightrec_state *lightrec_state;
53
54static char *name = "retroarch.exe";
55
56static bool use_lightrec_interpreter;
57static bool use_pcsx_interpreter;
58static bool block_stepping;
59
60enum my_cp2_opcodes {
61 OP_CP2_RTPS = 0x01,
62 OP_CP2_NCLIP = 0x06,
63 OP_CP2_OP = 0x0c,
64 OP_CP2_DPCS = 0x10,
65 OP_CP2_INTPL = 0x11,
66 OP_CP2_MVMVA = 0x12,
67 OP_CP2_NCDS = 0x13,
68 OP_CP2_CDP = 0x14,
69 OP_CP2_NCDT = 0x16,
70 OP_CP2_NCCS = 0x1b,
71 OP_CP2_CC = 0x1c,
72 OP_CP2_NCS = 0x1e,
73 OP_CP2_NCT = 0x20,
74 OP_CP2_SQR = 0x28,
75 OP_CP2_DCPL = 0x29,
76 OP_CP2_DPCT = 0x2a,
77 OP_CP2_AVSZ3 = 0x2d,
78 OP_CP2_AVSZ4 = 0x2e,
79 OP_CP2_RTPT = 0x30,
80 OP_CP2_GPF = 0x3d,
81 OP_CP2_GPL = 0x3e,
82 OP_CP2_NCCT = 0x3f,
83};
84
85static void (*cp2_ops[])(struct psxCP2Regs *) = {
86 [OP_CP2_RTPS] = gteRTPS,
87 [OP_CP2_RTPS] = gteRTPS,
88 [OP_CP2_NCLIP] = gteNCLIP,
89 [OP_CP2_OP] = gteOP,
90 [OP_CP2_DPCS] = gteDPCS,
91 [OP_CP2_INTPL] = gteINTPL,
92 [OP_CP2_MVMVA] = gteMVMVA,
93 [OP_CP2_NCDS] = gteNCDS,
94 [OP_CP2_CDP] = gteCDP,
95 [OP_CP2_NCDT] = gteNCDT,
96 [OP_CP2_NCCS] = gteNCCS,
97 [OP_CP2_CC] = gteCC,
98 [OP_CP2_NCS] = gteNCS,
99 [OP_CP2_NCT] = gteNCT,
100 [OP_CP2_SQR] = gteSQR,
101 [OP_CP2_DCPL] = gteDCPL,
102 [OP_CP2_DPCT] = gteDPCT,
103 [OP_CP2_AVSZ3] = gteAVSZ3,
104 [OP_CP2_AVSZ4] = gteAVSZ4,
105 [OP_CP2_RTPT] = gteRTPT,
106 [OP_CP2_GPF] = gteGPF,
107 [OP_CP2_GPL] = gteGPL,
108 [OP_CP2_NCCT] = gteNCCT,
109};
110
111static char cache_buf[64 * 1024];
112
113static void cop2_op(struct lightrec_state *state, u32 func)
114{
115 struct lightrec_registers *regs = lightrec_get_registers(state);
116
117 psxRegs.code = func;
118
119 if (unlikely(!cp2_ops[func & 0x3f])) {
120 fprintf(stderr, "Invalid CP2 function %u\n", func);
121 } else {
122 /* This works because regs->cp2c comes right after regs->cp2d,
123 * so it can be cast to a pcsxCP2Regs pointer. */
124 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
125 }
126}
127
128static bool has_interrupt(void)
129{
130 struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
131
132 return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
133 (regs->cp0[12] & 0x401) == 0x401) ||
134 (regs->cp0[12] & regs->cp0[13] & 0x0300);
135}
136
137static void lightrec_restore_state(struct lightrec_state *state)
138{
139 lightrec_reset_cycle_count(state, psxRegs.cycle);
140
141 if (block_stepping || has_interrupt())
142 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
143 else
144 lightrec_set_target_cycle_count(state, next_interupt);
145}
146
147static void hw_write_byte(struct lightrec_state *state,
148 u32 op, void *host, u32 mem, u8 val)
149{
150 psxRegs.cycle = lightrec_current_cycle_count(state);
151
152 psxHwWrite8(mem, val);
153
154 lightrec_restore_state(state);
155}
156
157static void hw_write_half(struct lightrec_state *state,
158 u32 op, void *host, u32 mem, u16 val)
159{
160 psxRegs.cycle = lightrec_current_cycle_count(state);
161
162 psxHwWrite16(mem, val);
163
164 lightrec_restore_state(state);
165}
166
167static void hw_write_word(struct lightrec_state *state,
168 u32 op, void *host, u32 mem, u32 val)
169{
170 psxRegs.cycle = lightrec_current_cycle_count(state);
171
172 psxHwWrite32(mem, val);
173
174 lightrec_restore_state(state);
175}
176
177static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
178{
179 u8 val;
180
181 psxRegs.cycle = lightrec_current_cycle_count(state);
182
183 val = psxHwRead8(mem);
184
185 lightrec_restore_state(state);
186
187 return val;
188}
189
190static u16 hw_read_half(struct lightrec_state *state,
191 u32 op, void *host, u32 mem)
192{
193 u16 val;
194
195 psxRegs.cycle = lightrec_current_cycle_count(state);
196
197 val = psxHwRead16(mem);
198
199 lightrec_restore_state(state);
200
201 return val;
202}
203
204static u32 hw_read_word(struct lightrec_state *state,
205 u32 op, void *host, u32 mem)
206{
207 u32 val;
208
209 psxRegs.cycle = lightrec_current_cycle_count(state);
210
211 val = psxHwRead32(mem);
212
213 lightrec_restore_state(state);
214
215 return val;
216}
217
218static struct lightrec_mem_map_ops hw_regs_ops = {
219 .sb = hw_write_byte,
220 .sh = hw_write_half,
221 .sw = hw_write_word,
222 .lb = hw_read_byte,
223 .lh = hw_read_half,
224 .lw = hw_read_word,
225};
226
227static u32 cache_ctrl;
228
229static void cache_ctrl_write_word(struct lightrec_state *state,
230 u32 op, void *host, u32 mem, u32 val)
231{
232 cache_ctrl = val;
233}
234
235static u32 cache_ctrl_read_word(struct lightrec_state *state,
236 u32 op, void *host, u32 mem)
237{
238 return cache_ctrl;
239}
240
241static struct lightrec_mem_map_ops cache_ctrl_ops = {
242 .sw = cache_ctrl_write_word,
243 .lw = cache_ctrl_read_word,
244};
245
246static struct lightrec_mem_map lightrec_map[] = {
247 [PSX_MAP_KERNEL_USER_RAM] = {
248 /* Kernel and user memory */
249 .pc = 0x00000000,
250 .length = 0x200000,
251 },
252 [PSX_MAP_BIOS] = {
253 /* BIOS */
254 .pc = 0x1fc00000,
255 .length = 0x80000,
256 },
257 [PSX_MAP_SCRATCH_PAD] = {
258 /* Scratch pad */
259 .pc = 0x1f800000,
260 .length = 0x400,
261 },
262 [PSX_MAP_PARALLEL_PORT] = {
263 /* Parallel port */
264 .pc = 0x1f000000,
265 .length = 0x10000,
266 },
267 [PSX_MAP_HW_REGISTERS] = {
268 /* Hardware registers */
269 .pc = 0x1f801000,
270 .length = 0x2000,
271 .ops = &hw_regs_ops,
272 },
273 [PSX_MAP_CACHE_CONTROL] = {
274 /* Cache control */
275 .pc = 0x5ffe0130,
276 .length = 4,
277 .ops = &cache_ctrl_ops,
278 },
279
280 /* Mirrors of the kernel/user memory */
281 [PSX_MAP_MIRROR1] = {
282 .pc = 0x00200000,
283 .length = 0x200000,
284 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
285 },
286 [PSX_MAP_MIRROR2] = {
287 .pc = 0x00400000,
288 .length = 0x200000,
289 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
290 },
291 [PSX_MAP_MIRROR3] = {
292 .pc = 0x00600000,
293 .length = 0x200000,
294 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
295 },
296 [PSX_MAP_CODE_BUFFER] = {
297 .length = CODE_BUFFER_SIZE,
298 },
299};
300
301static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
302{
303 if (enable)
304 memcpy(psxM, cache_buf, sizeof(cache_buf));
305 else
306 memcpy(cache_buf, psxM, sizeof(cache_buf));
307}
308
309static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
310{
311 switch (size) {
312 case 8:
313 switch (kaddr) {
314 case 0x1f801040:
315 case 0x1f801050:
316 case 0x1f801800:
317 case 0x1f801801:
318 case 0x1f801802:
319 case 0x1f801803:
320 return false;
321 default:
322 return true;
323 }
324 case 16:
325 switch (kaddr) {
326 case 0x1f801040:
327 case 0x1f801044:
328 case 0x1f801048:
329 case 0x1f80104a:
330 case 0x1f80104e:
331 case 0x1f801050:
332 case 0x1f801054:
333 case 0x1f80105a:
334 case 0x1f80105e:
335 case 0x1f801100:
336 case 0x1f801104:
337 case 0x1f801108:
338 case 0x1f801110:
339 case 0x1f801114:
340 case 0x1f801118:
341 case 0x1f801120:
342 case 0x1f801124:
343 case 0x1f801128:
344 return false;
345 case 0x1f801070:
346 case 0x1f801074:
347 return !is_write;
348 default:
349 return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
350 }
351 default:
352 switch (kaddr) {
353 case 0x1f801040:
354 case 0x1f801050:
355 case 0x1f801100:
356 case 0x1f801104:
357 case 0x1f801108:
358 case 0x1f801110:
359 case 0x1f801114:
360 case 0x1f801118:
361 case 0x1f801120:
362 case 0x1f801124:
363 case 0x1f801128:
364 case 0x1f801810:
365 case 0x1f801814:
366 case 0x1f801820:
367 case 0x1f801824:
368 return false;
369 case 0x1f801070:
370 case 0x1f801074:
371 case 0x1f801088:
372 case 0x1f801098:
373 case 0x1f8010a8:
374 case 0x1f8010b8:
375 case 0x1f8010c8:
376 case 0x1f8010e8:
377 case 0x1f8010f4:
378 return !is_write;
379 default:
380 return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
381 }
382 }
383}
384
385static const struct lightrec_ops lightrec_ops = {
386 .cop2_op = cop2_op,
387 .enable_ram = lightrec_enable_ram,
388 .hw_direct = lightrec_can_hw_direct,
389};
390
391static int lightrec_plugin_init(void)
392{
393 lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
394 lightrec_map[PSX_MAP_BIOS].address = psxR;
395 lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
396 lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
397 lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
398
399 if (LIGHTREC_CUSTOM_MAP) {
400 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
401 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
402 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
403 lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
404 }
405
406 use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
407
408 lightrec_state = lightrec_init(name,
409 lightrec_map, ARRAY_SIZE(lightrec_map),
410 &lightrec_ops);
411
412 // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
413 // (uintptr_t) psxM,
414 // (uintptr_t) psxP,
415 // (uintptr_t) psxR,
416 // (uintptr_t) psxH);
417
418#ifndef _WIN32
419 signal(SIGPIPE, exit);
420#endif
421 return 0;
422}
423
424static void lightrec_plugin_execute_internal(bool block_only)
425{
426 struct lightrec_registers *regs;
427 u32 flags;
428
429 regs = lightrec_get_registers(lightrec_state);
430 gen_interupt((psxCP0Regs *)regs->cp0);
431
432 // step during early boot so that 0x80030000 fastboot hack works
433 block_stepping = block_only;
434 if (block_only)
435 next_interupt = psxRegs.cycle;
436
437 if (use_pcsx_interpreter) {
438 intExecuteBlock(0);
439 } else {
440 lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
441
442 if (unlikely(use_lightrec_interpreter)) {
443 psxRegs.pc = lightrec_run_interpreter(lightrec_state,
444 psxRegs.pc,
445 next_interupt);
446 } else {
447 psxRegs.pc = lightrec_execute(lightrec_state,
448 psxRegs.pc, next_interupt);
449 }
450
451 psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
452
453 flags = lightrec_exit_flags(lightrec_state);
454
455 if (flags & LIGHTREC_EXIT_SEGFAULT) {
456 fprintf(stderr, "Exiting at cycle 0x%08x\n",
457 psxRegs.cycle);
458 exit(1);
459 }
460
461 if (flags & LIGHTREC_EXIT_SYSCALL)
462 psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
463 }
464
465 if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
466 /* Handle software interrupts */
467 regs->cp0[13] &= ~0x7c;
468 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
469 }
470}
471
472static void lightrec_plugin_execute(void)
473{
474 extern int stop;
475
476 while (!stop)
477 lightrec_plugin_execute_internal(false);
478}
479
480static void lightrec_plugin_execute_block(enum blockExecCaller caller)
481{
482 lightrec_plugin_execute_internal(true);
483}
484
485static void lightrec_plugin_clear(u32 addr, u32 size)
486{
487 if (addr == 0 && size == UINT32_MAX)
488 lightrec_invalidate_all(lightrec_state);
489 else
490 /* size * 4: PCSX uses DMA units */
491 lightrec_invalidate(lightrec_state, addr, size * 4);
492}
493
494static void lightrec_plugin_sync_regs_to_pcsx(void);
495static void lightrec_plugin_sync_regs_from_pcsx(void);
496
497static void lightrec_plugin_notify(enum R3000Anote note, void *data)
498{
499 switch (note)
500 {
501 case R3000ACPU_NOTIFY_CACHE_ISOLATED:
502 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
503 /* not used, lightrec calls lightrec_enable_ram() instead */
504 break;
505 case R3000ACPU_NOTIFY_BEFORE_SAVE:
506 lightrec_plugin_sync_regs_to_pcsx();
507 break;
508 case R3000ACPU_NOTIFY_AFTER_LOAD:
509 lightrec_plugin_sync_regs_from_pcsx();
510 break;
511 }
512}
513
514static void lightrec_plugin_apply_config()
515{
516}
517
518static void lightrec_plugin_shutdown(void)
519{
520 lightrec_destroy(lightrec_state);
521}
522
523static void lightrec_plugin_reset(void)
524{
525 struct lightrec_registers *regs;
526
527 regs = lightrec_get_registers(lightrec_state);
528
529 /* Invalidate all blocks */
530 lightrec_invalidate_all(lightrec_state);
531
532 /* Reset registers */
533 memset(regs, 0, sizeof(*regs));
534
535 regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
536 regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
537}
538
539static void lightrec_plugin_sync_regs_from_pcsx(void)
540{
541 struct lightrec_registers *regs;
542
543 regs = lightrec_get_registers(lightrec_state);
544 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
545 memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
546 memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
547
548 lightrec_invalidate_all(lightrec_state);
549}
550
551static void lightrec_plugin_sync_regs_to_pcsx(void)
552{
553 struct lightrec_registers *regs;
554
555 regs = lightrec_get_registers(lightrec_state);
556 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
557 memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
558 memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
559}
560
561R3000Acpu psxRec =
562{
563 lightrec_plugin_init,
564 lightrec_plugin_reset,
565 lightrec_plugin_execute,
566 lightrec_plugin_execute_block,
567 lightrec_plugin_clear,
568 lightrec_plugin_notify,
569 lightrec_plugin_apply_config,
570 lightrec_plugin_shutdown,
571};