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spu: try to improve timing
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24#include <errno.h>
25#include <sys/mman.h>
26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef HAVE_LIBNX
33#include <switch.h>
34static Jit g_jit;
35#endif
36
37#include "new_dynarec_config.h"
38#include "../psxhle.h"
39#include "../psxinterpreter.h"
40#include "../psxcounters.h"
41#include "../gte.h"
42#include "emu_if.h" // emulator interface
43#include "linkage_offsets.h"
44#include "compiler_features.h"
45#include "arm_features.h"
46
47#ifndef ARRAY_SIZE
48#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
49#endif
50#ifndef min
51#define min(a, b) ((b) < (a) ? (b) : (a))
52#endif
53#ifndef max
54#define max(a, b) ((b) > (a) ? (b) : (a))
55#endif
56
57//#define DISASM
58//#define ASSEM_PRINT
59//#define REGMAP_PRINT // with DISASM only
60//#define INV_DEBUG_W
61//#define STAT_PRINT
62
63#ifdef ASSEM_PRINT
64#define assem_debug printf
65#else
66#define assem_debug(...)
67#endif
68//#define inv_debug printf
69#define inv_debug(...)
70
71#ifdef __i386__
72#include "assem_x86.h"
73#endif
74#ifdef __x86_64__
75#include "assem_x64.h"
76#endif
77#ifdef __arm__
78#include "assem_arm.h"
79#endif
80#ifdef __aarch64__
81#include "assem_arm64.h"
82#endif
83
84#define RAM_SIZE 0x200000
85#define MAXBLOCK 2048
86#define MAX_OUTPUT_BLOCK_SIZE 262144
87#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
88#define PAGE_COUNT 1024
89
90#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
91#define INVALIDATE_USE_COND_CALL
92#endif
93
94#ifdef VITA
95// apparently Vita has a 16MB limit, so either we cut tc in half,
96// or use this hack (it's a hack because tc size was designed to be power-of-2)
97#define TC_REDUCE_BYTES 4096
98#else
99#define TC_REDUCE_BYTES 0
100#endif
101
102struct ndrc_tramp
103{
104 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
105 const void *f[2048 / sizeof(void *)];
106};
107
108struct ndrc_mem
109{
110 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
111 struct ndrc_tramp tramp;
112};
113
114#ifdef BASE_ADDR_DYNAMIC
115static struct ndrc_mem *ndrc;
116#else
117static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
118static struct ndrc_mem *ndrc = &ndrc_;
119#endif
120#ifdef TC_WRITE_OFFSET
121# ifdef __GLIBC__
122# include <sys/types.h>
123# include <sys/stat.h>
124# include <fcntl.h>
125# include <unistd.h>
126# endif
127static long ndrc_write_ofs;
128#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
129#else
130#define NDRC_WRITE_OFFSET(x) (x)
131#endif
132
133// stubs
134enum stub_type {
135 CC_STUB = 1,
136 //FP_STUB = 2,
137 LOADB_STUB = 3,
138 LOADH_STUB = 4,
139 LOADW_STUB = 5,
140 //LOADD_STUB = 6,
141 LOADBU_STUB = 7,
142 LOADHU_STUB = 8,
143 STOREB_STUB = 9,
144 STOREH_STUB = 10,
145 STOREW_STUB = 11,
146 //STORED_STUB = 12,
147 STORELR_STUB = 13,
148 INVCODE_STUB = 14,
149 OVERFLOW_STUB = 15,
150 ALIGNMENT_STUB = 16,
151};
152
153// regmap_pre[i] - regs before [i] insn starts; dirty things here that
154// don't match .regmap will be written back
155// [i].regmap_entry - regs that must be set up if someone jumps here
156// [i].regmap - regs [i] insn will read/(over)write
157// branch_regs[i].* - same as above but for branches, takes delay slot into account
158struct regstat
159{
160 signed char regmap_entry[HOST_REGS];
161 signed char regmap[HOST_REGS];
162 u_int wasdirty;
163 u_int dirty;
164 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
165 u_int isconst; // ... but isconst is false when r2 is known (hr)
166 u_int loadedconst; // host regs that have constants loaded
167 u_int noevict; // can't evict this hr (alloced by current op)
168 //u_int waswritten; // MIPS regs that were used as store base before
169 uint64_t u;
170};
171
172struct ht_entry
173{
174 u_int vaddr[2];
175 void *tcaddr[2];
176};
177
178struct code_stub
179{
180 enum stub_type type;
181 void *addr;
182 void *retaddr;
183 u_int a;
184 uintptr_t b;
185 uintptr_t c;
186 u_int d;
187 u_int e;
188};
189
190struct link_entry
191{
192 void *addr;
193 u_int target;
194 u_int internal;
195};
196
197struct block_info
198{
199 struct block_info *next;
200 const void *source;
201 const void *copy;
202 u_int start; // vaddr of the block start
203 u_int len; // of the whole block source
204 u_int tc_offs;
205 //u_int tc_len;
206 u_int reg_sv_flags;
207 u_char is_dirty;
208 u_char inv_near_misses;
209 u_short jump_in_cnt;
210 struct {
211 u_int vaddr;
212 void *addr;
213 } jump_in[0];
214};
215
216struct jump_info
217{
218 int alloc;
219 int count;
220 struct {
221 u_int target_vaddr;
222 void *stub;
223 } e[0];
224};
225
226static struct decoded_insn
227{
228 u_char itype;
229 u_char opcode; // bits 31-26
230 u_char opcode2; // (depends on opcode)
231 u_char rs1;
232 u_char rs2;
233 u_char rt1;
234 u_char rt2;
235 u_char use_lt1:1;
236 u_char bt:1;
237 u_char ooo:1;
238 u_char is_ds:1;
239 u_char is_jump:1;
240 u_char is_ujump:1;
241 u_char is_load:1;
242 u_char is_store:1;
243 u_char is_delay_load:1; // is_load + MFC/CFC
244 u_char is_exception:1; // unconditional, also interp. fallback
245 u_char may_except:1; // might generate an exception
246 u_char ls_type:2; // load/store type (ls_width_type)
247} dops[MAXBLOCK];
248
249enum ls_width_type {
250 LS_8 = 0, LS_16, LS_32, LS_LR
251};
252
253static struct compile_info
254{
255 int imm;
256 u_int ba;
257 int ccadj;
258 signed char min_free_regs;
259 signed char addr;
260 signed char reserved[2];
261} cinfo[MAXBLOCK];
262
263 static u_char *out;
264 static char invalid_code[0x100000];
265 static struct ht_entry hash_table[65536];
266 static struct block_info *blocks[PAGE_COUNT];
267 static struct jump_info *jumps[PAGE_COUNT];
268 static u_int start;
269 static u_int *source;
270 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
271 static uint64_t gte_rt[MAXBLOCK];
272 static uint64_t gte_unneeded[MAXBLOCK];
273 static u_int smrv[32]; // speculated MIPS register values
274 static u_int smrv_strong; // mask or regs that are likely to have correct values
275 static u_int smrv_weak; // same, but somewhat less likely
276 static u_int smrv_strong_next; // same, but after current insn executes
277 static u_int smrv_weak_next;
278 static uint64_t unneeded_reg[MAXBLOCK];
279 static uint64_t branch_unneeded_reg[MAXBLOCK];
280 // see 'struct regstat' for a description
281 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
282 // contains 'real' consts at [i] insn, but may differ from what's actually
283 // loaded in host reg as 'final' value is always loaded, see get_final_value()
284 static uint32_t current_constmap[HOST_REGS];
285 static uint32_t constmap[MAXBLOCK][HOST_REGS];
286 static struct regstat regs[MAXBLOCK];
287 static struct regstat branch_regs[MAXBLOCK];
288 static int slen;
289 static void *instr_addr[MAXBLOCK];
290 static struct link_entry link_addr[MAXBLOCK];
291 static int linkcount;
292 static struct code_stub stubs[MAXBLOCK*3];
293 static int stubcount;
294 static u_int literals[1024][2];
295 static int literalcount;
296 static int is_delayslot;
297 static char shadow[1048576] __attribute__((aligned(16)));
298 static void *copy;
299 static u_int expirep;
300 static u_int stop_after_jal;
301 static u_int f1_hack;
302#ifdef STAT_PRINT
303 static int stat_bc_direct;
304 static int stat_bc_pre;
305 static int stat_bc_restore;
306 static int stat_ht_lookups;
307 static int stat_jump_in_lookups;
308 static int stat_restore_tries;
309 static int stat_restore_compares;
310 static int stat_inv_addr_calls;
311 static int stat_inv_hits;
312 static int stat_blocks;
313 static int stat_links;
314 #define stat_inc(s) s++
315 #define stat_dec(s) s--
316 #define stat_clear(s) s = 0
317#else
318 #define stat_inc(s)
319 #define stat_dec(s)
320 #define stat_clear(s)
321#endif
322
323 int new_dynarec_hacks;
324 int new_dynarec_hacks_pergame;
325 int new_dynarec_hacks_old;
326 int new_dynarec_did_compile;
327
328 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
329
330 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
331 extern int last_count; // last absolute target, often = next_interupt
332 extern int pcaddr;
333 extern int pending_exception;
334 extern int branch_target;
335 extern uintptr_t ram_offset;
336 extern uintptr_t mini_ht[32][2];
337
338 /* registers that may be allocated */
339 /* 1-31 gpr */
340#define LOREG 32 // lo
341#define HIREG 33 // hi
342//#define FSREG 34 // FPU status (FCSR)
343//#define CSREG 35 // Coprocessor status
344#define CCREG 36 // Cycle count
345#define INVCP 37 // Pointer to invalid_code
346//#define MMREG 38 // Pointer to memory_map
347#define ROREG 39 // ram offset (if psxM != 0x80000000)
348#define TEMPREG 40
349#define FTEMP 40 // Load/store temporary register (was fpu)
350#define PTEMP 41 // Prefetch temporary register
351//#define TLREG 42 // TLB mapping offset
352#define RHASH 43 // Return address hash
353#define RHTBL 44 // Return address hash table address
354#define RTEMP 45 // JR/JALR address register
355#define MAXREG 45
356#define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
357//#define AGEN2 47 // Address generation temporary register
358
359 /* instruction types */
360#define NOP 0 // No operation
361#define LOAD 1 // Load
362#define STORE 2 // Store
363#define LOADLR 3 // Unaligned load
364#define STORELR 4 // Unaligned store
365#define MOV 5 // Move (hi/lo only)
366#define ALU 6 // Arithmetic/logic
367#define MULTDIV 7 // Multiply/divide
368#define SHIFT 8 // Shift by register
369#define SHIFTIMM 9// Shift by immediate
370#define IMM16 10 // 16-bit immediate
371#define RJUMP 11 // Unconditional jump to register
372#define UJUMP 12 // Unconditional jump
373#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
374#define SJUMP 14 // Conditional branch (regimm format)
375#define COP0 15 // Coprocessor 0
376#define RFE 16
377#define SYSCALL 22// SYSCALL,BREAK
378#define OTHER 23 // Other/unknown - do nothing
379#define HLECALL 26// PCSX fake opcodes for HLE
380#define COP2 27 // Coprocessor 2 move
381#define C2LS 28 // Coprocessor 2 load/store
382#define C2OP 29 // Coprocessor 2 operation
383#define INTCALL 30// Call interpreter to handle rare corner cases
384
385 /* branch codes */
386#define TAKEN 1
387#define NOTTAKEN 2
388
389#define DJT_1 (void *)1l // no function, just a label in assem_debug log
390#define DJT_2 (void *)2l
391
392// asm linkage
393void dyna_linker();
394void cc_interrupt();
395void jump_syscall (u_int u0, u_int u1, u_int pc);
396void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
397void jump_break (u_int u0, u_int u1, u_int pc);
398void jump_break_ds(u_int u0, u_int u1, u_int pc);
399void jump_overflow (u_int u0, u_int u1, u_int pc);
400void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
401void jump_addrerror (u_int cause, u_int addr, u_int pc);
402void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
403void jump_to_new_pc();
404void call_gteStall();
405void new_dyna_leave();
406
407void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
408void *ndrc_get_addr_ht(u_int vaddr);
409void ndrc_add_jump_out(u_int vaddr, void *src);
410void ndrc_write_invalidate_one(u_int addr);
411static void ndrc_write_invalidate_many(u_int addr, u_int end);
412
413static int new_recompile_block(u_int addr);
414static void invalidate_block(struct block_info *block);
415static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
416
417// Needed by assembler
418static void wb_register(signed char r, const signed char regmap[], u_int dirty);
419static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
420static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
421static void load_all_regs(const signed char i_regmap[]);
422static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
423static void load_regs_entry(int t);
424static void load_all_consts(const signed char regmap[], u_int dirty, int i);
425static u_int get_host_reglist(const signed char *regmap);
426
427static int get_final_value(int hr, int i, u_int *value);
428static void add_stub(enum stub_type type, void *addr, void *retaddr,
429 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
430static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
431 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
432static void add_to_linker(void *addr, u_int target, int ext);
433static void *get_direct_memhandler(void *table, u_int addr,
434 enum stub_type type, uintptr_t *addr_host);
435static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
436static void pass_args(int a0, int a1);
437static void emit_far_jump(const void *f);
438static void emit_far_call(const void *f);
439
440#ifdef VITA
441#include <psp2/kernel/sysmem.h>
442static int sceBlock;
443// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
444extern int getVMBlock();
445int _newlib_vm_size_user = sizeof(*ndrc);
446#endif
447
448static void mprotect_w_x(void *start, void *end, int is_x)
449{
450#ifdef NO_WRITE_EXEC
451 #if defined(VITA)
452 // *Open* enables write on all memory that was
453 // allocated by sceKernelAllocMemBlockForVM()?
454 if (is_x)
455 sceKernelCloseVMDomain();
456 else
457 sceKernelOpenVMDomain();
458 #elif defined(HAVE_LIBNX)
459 Result rc;
460 // check to avoid the full flush in jitTransitionToExecutable()
461 if (g_jit.type != JitType_CodeMemory) {
462 if (is_x)
463 rc = jitTransitionToExecutable(&g_jit);
464 else
465 rc = jitTransitionToWritable(&g_jit);
466 if (R_FAILED(rc))
467 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
468 }
469 #elif defined(TC_WRITE_OFFSET)
470 // separated rx and rw areas are always available
471 #else
472 u_long mstart = (u_long)start & ~4095ul;
473 u_long mend = (u_long)end;
474 if (mprotect((void *)mstart, mend - mstart,
475 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
476 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
477 #endif
478#endif
479}
480
481static void start_tcache_write(void *start, void *end)
482{
483 mprotect_w_x(start, end, 0);
484}
485
486static void end_tcache_write(void *start, void *end)
487{
488#if defined(__arm__) || defined(__aarch64__)
489 size_t len = (char *)end - (char *)start;
490 #if defined(__BLACKBERRY_QNX__)
491 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
492 #elif defined(__MACH__)
493 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
494 #elif defined(VITA)
495 sceKernelSyncVMDomain(sceBlock, start, len);
496 #elif defined(_3DS)
497 ctr_flush_invalidate_cache();
498 #elif defined(HAVE_LIBNX)
499 if (g_jit.type == JitType_CodeMemory) {
500 armDCacheClean(start, len);
501 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
502 // as of v4.2.1 libnx lacks isb
503 __asm__ volatile("isb" ::: "memory");
504 }
505 #elif defined(__aarch64__)
506 // as of 2021, __clear_cache() is still broken on arm64
507 // so here is a custom one :(
508 clear_cache_arm64(start, end);
509 #else
510 __clear_cache(start, end);
511 #endif
512 (void)len;
513#endif
514
515 mprotect_w_x(start, end, 1);
516}
517
518static void *start_block(void)
519{
520 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
521 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
522 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
523 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
524 return out;
525}
526
527static void end_block(void *start)
528{
529 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
530}
531
532#ifdef NDRC_CACHE_FLUSH_ALL
533
534static int needs_clear_cache;
535
536static void mark_clear_cache(void *target)
537{
538 if (!needs_clear_cache) {
539 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
540 needs_clear_cache = 1;
541 }
542}
543
544static void do_clear_cache(void)
545{
546 if (needs_clear_cache) {
547 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
548 needs_clear_cache = 0;
549 }
550}
551
552#else
553
554// also takes care of w^x mappings when patching code
555static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
556
557static void mark_clear_cache(void *target)
558{
559 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
560 u_int mask = 1u << ((offset >> 12) & 31);
561 if (!(needs_clear_cache[offset >> 17] & mask)) {
562 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
563 start_tcache_write(start, start + 4095);
564 needs_clear_cache[offset >> 17] |= mask;
565 }
566}
567
568// Clearing the cache is rather slow on ARM Linux, so mark the areas
569// that need to be cleared, and then only clear these areas once.
570static void do_clear_cache(void)
571{
572 int i, j;
573 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
574 {
575 u_int bitmap = needs_clear_cache[i];
576 if (!bitmap)
577 continue;
578 for (j = 0; j < 32; j++)
579 {
580 u_char *start, *end;
581 if (!(bitmap & (1u << j)))
582 continue;
583
584 start = ndrc->translation_cache + i*131072 + j*4096;
585 end = start + 4095;
586 for (j++; j < 32; j++) {
587 if (!(bitmap & (1u << j)))
588 break;
589 end += 4096;
590 }
591 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
592 }
593 needs_clear_cache[i] = 0;
594 }
595}
596
597#endif // NDRC_CACHE_FLUSH_ALL
598
599#define NO_CYCLE_PENALTY_THR 12
600
601int cycle_multiplier_old;
602static int cycle_multiplier_active;
603
604static int CLOCK_ADJUST(int x)
605{
606 int m = cycle_multiplier_active;
607 int s = (x >> 31) | 1;
608 return (x * m + s * 50) / 100;
609}
610
611static int ds_writes_rjump_rs(int i)
612{
613 return dops[i].rs1 != 0
614 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
615 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
616}
617
618// psx addr mirror masking (for invalidation)
619static u_int pmmask(u_int vaddr)
620{
621 vaddr &= ~0xe0000000;
622 if (vaddr < 0x01000000)
623 vaddr &= ~0x00e00000; // RAM mirrors
624 return vaddr;
625}
626
627static u_int get_page(u_int vaddr)
628{
629 u_int page = pmmask(vaddr) >> 12;
630 if (page >= PAGE_COUNT / 2)
631 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
632 return page;
633}
634
635// get a page for looking for a block that has vaddr
636// (needed because the block may start in previous page)
637static u_int get_page_prev(u_int vaddr)
638{
639 assert(MAXBLOCK <= (1 << 12));
640 u_int page = get_page(vaddr);
641 if (page & 511)
642 page--;
643 return page;
644}
645
646static struct ht_entry *hash_table_get(u_int vaddr)
647{
648 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
649}
650
651static void hash_table_add(u_int vaddr, void *tcaddr)
652{
653 struct ht_entry *ht_bin = hash_table_get(vaddr);
654 assert(tcaddr);
655 ht_bin->vaddr[1] = ht_bin->vaddr[0];
656 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
657 ht_bin->vaddr[0] = vaddr;
658 ht_bin->tcaddr[0] = tcaddr;
659}
660
661static void hash_table_remove(int vaddr)
662{
663 //printf("remove hash: %x\n",vaddr);
664 struct ht_entry *ht_bin = hash_table_get(vaddr);
665 if (ht_bin->vaddr[1] == vaddr) {
666 ht_bin->vaddr[1] = -1;
667 ht_bin->tcaddr[1] = NULL;
668 }
669 if (ht_bin->vaddr[0] == vaddr) {
670 ht_bin->vaddr[0] = ht_bin->vaddr[1];
671 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
672 ht_bin->vaddr[1] = -1;
673 ht_bin->tcaddr[1] = NULL;
674 }
675}
676
677static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
678{
679 u_int vaddr_m = vaddr & 0x1fffffff;
680 u_int i, j;
681 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
682 // ram mirrors, but should not hurt bios
683 for (j = 0; j < 0x800000; j += 0x200000) {
684 invalid_code[(i|j) >> 12] =
685 invalid_code[(i|j|0x80000000u) >> 12] =
686 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
687 }
688 }
689 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
690 inv_code_start = inv_code_end = ~0;
691}
692
693static int doesnt_expire_soon(u_char *tcaddr)
694{
695 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
696 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
697}
698
699static unused void check_for_block_changes(u_int start, u_int end)
700{
701 u_int start_page = get_page_prev(start);
702 u_int end_page = get_page(end - 1);
703 u_int page;
704
705 for (page = start_page; page <= end_page; page++) {
706 struct block_info *block;
707 for (block = blocks[page]; block != NULL; block = block->next) {
708 if (block->is_dirty)
709 continue;
710 if (memcmp(block->source, block->copy, block->len)) {
711 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
712 block->start, block->start + block->len,
713 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
714 fflush(stdout);
715 abort();
716 }
717 }
718 }
719}
720
721static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
722{
723 void *found_clean = NULL;
724 u_int i, page;
725
726 stat_inc(stat_restore_tries);
727 for (page = start_page; page <= end_page; page++) {
728 struct block_info *block;
729 for (block = blocks[page]; block != NULL; block = block->next) {
730 if (vaddr < block->start)
731 break;
732 if (!block->is_dirty || vaddr >= block->start + block->len)
733 continue;
734 for (i = 0; i < block->jump_in_cnt; i++)
735 if (block->jump_in[i].vaddr == vaddr)
736 break;
737 if (i == block->jump_in_cnt)
738 continue;
739 assert(block->source && block->copy);
740 stat_inc(stat_restore_compares);
741 if (memcmp(block->source, block->copy, block->len))
742 continue;
743
744 block->is_dirty = block->inv_near_misses = 0;
745 found_clean = block->jump_in[i].addr;
746 hash_table_add(vaddr, found_clean);
747 mark_invalid_code(block->start, block->len, 0);
748 stat_inc(stat_bc_restore);
749 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
750 return found_clean;
751 }
752 }
753 return NULL;
754}
755
756// this doesn't normally happen
757static noinline u_int generate_exception(u_int pc)
758{
759 //if (execBreakCheck(&psxRegs, pc))
760 // return psxRegs.pc;
761
762 // generate an address or bus error
763 psxRegs.CP0.n.Cause &= 0x300;
764 psxRegs.CP0.n.EPC = pc;
765 if (pc & 3) {
766 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
767 psxRegs.CP0.n.BadVAddr = pc;
768#ifdef DRC_DBG
769 last_count -= 2;
770#endif
771 } else
772 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
773 return (psxRegs.pc = 0x80000080);
774}
775
776// Get address from virtual address
777// This is called from the recompiled JR/JALR instructions
778static void noinline *get_addr(u_int vaddr, int can_compile)
779{
780 u_int start_page = get_page_prev(vaddr);
781 u_int i, page, end_page = get_page(vaddr);
782 void *found_clean = NULL;
783
784 stat_inc(stat_jump_in_lookups);
785 for (page = start_page; page <= end_page; page++) {
786 const struct block_info *block;
787 for (block = blocks[page]; block != NULL; block = block->next) {
788 if (vaddr < block->start)
789 break;
790 if (block->is_dirty || vaddr >= block->start + block->len)
791 continue;
792 for (i = 0; i < block->jump_in_cnt; i++)
793 if (block->jump_in[i].vaddr == vaddr)
794 break;
795 if (i == block->jump_in_cnt)
796 continue;
797 found_clean = block->jump_in[i].addr;
798 hash_table_add(vaddr, found_clean);
799 return found_clean;
800 }
801 }
802 found_clean = try_restore_block(vaddr, start_page, end_page);
803 if (found_clean)
804 return found_clean;
805
806 if (!can_compile)
807 return NULL;
808
809 int r = new_recompile_block(vaddr);
810 if (likely(r == 0))
811 return ndrc_get_addr_ht(vaddr);
812
813 return ndrc_get_addr_ht(generate_exception(vaddr));
814}
815
816// Look up address in hash table first
817void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
818{
819 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
820 const struct ht_entry *ht_bin = hash_table_get(vaddr);
821 u_int vaddr_a = vaddr & ~3;
822 stat_inc(stat_ht_lookups);
823 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
824 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
825 return get_addr(vaddr, can_compile);
826}
827
828void *ndrc_get_addr_ht(u_int vaddr)
829{
830 return ndrc_get_addr_ht_param(vaddr, 1);
831}
832
833static void clear_all_regs(signed char regmap[])
834{
835 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
836}
837
838// get_reg: get allocated host reg from mips reg
839// returns -1 if no such mips reg was allocated
840#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
841
842extern signed char get_reg(const signed char regmap[], signed char r);
843
844#else
845
846static signed char get_reg(const signed char regmap[], signed char r)
847{
848 int hr;
849 for (hr = 0; hr < HOST_REGS; hr++) {
850 if (hr == EXCLUDE_REG)
851 continue;
852 if (regmap[hr] == r)
853 return hr;
854 }
855 return -1;
856}
857
858#endif
859
860// get reg suitable for writing
861static signed char get_reg_w(const signed char regmap[], signed char r)
862{
863 return r == 0 ? -1 : get_reg(regmap, r);
864}
865
866// get reg as mask bit (1 << hr)
867static u_int get_regm(const signed char regmap[], signed char r)
868{
869 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
870}
871
872static signed char get_reg_temp(const signed char regmap[])
873{
874 int hr;
875 for (hr = 0; hr < HOST_REGS; hr++) {
876 if (hr == EXCLUDE_REG)
877 continue;
878 if (regmap[hr] == (signed char)-1)
879 return hr;
880 }
881 return -1;
882}
883
884// Find a register that is available for two consecutive cycles
885static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
886{
887 int hr;
888 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
889 return -1;
890}
891
892// reverse reg map: mips -> host
893#define RRMAP_SIZE 64
894static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
895 u_int *regs_can_change)
896{
897 u_int r, hr, hr_can_change = 0;
898 memset(rrmap, -1, RRMAP_SIZE);
899 for (hr = 0; hr < HOST_REGS; )
900 {
901 r = regmap[hr];
902 rrmap[r & (RRMAP_SIZE - 1)] = hr;
903 // only add mips $1-$31+$lo, others shifted out
904 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
905 hr++;
906 if (hr == EXCLUDE_REG)
907 hr++;
908 }
909 hr_can_change |= 1u << (rrmap[33] & 31);
910 hr_can_change |= 1u << (rrmap[CCREG] & 31);
911 hr_can_change &= ~(1u << 31);
912 *regs_can_change = hr_can_change;
913}
914
915// same as get_reg, but takes rrmap
916static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
917{
918 assert(0 <= r && r < RRMAP_SIZE);
919 return rrmap[r];
920}
921
922static int count_free_regs(const signed char regmap[])
923{
924 int count=0;
925 int hr;
926 for(hr=0;hr<HOST_REGS;hr++)
927 {
928 if(hr!=EXCLUDE_REG) {
929 if(regmap[hr]<0) count++;
930 }
931 }
932 return count;
933}
934
935static void dirty_reg(struct regstat *cur, signed char reg)
936{
937 int hr;
938 if (!reg) return;
939 hr = get_reg(cur->regmap, reg);
940 if (hr >= 0)
941 cur->dirty |= 1<<hr;
942}
943
944static void set_const(struct regstat *cur, signed char reg, uint32_t value)
945{
946 int hr;
947 if (!reg) return;
948 hr = get_reg(cur->regmap, reg);
949 if (hr >= 0) {
950 cur->isconst |= 1<<hr;
951 current_constmap[hr] = value;
952 }
953}
954
955static void clear_const(struct regstat *cur, signed char reg)
956{
957 int hr;
958 if (!reg) return;
959 hr = get_reg(cur->regmap, reg);
960 if (hr >= 0)
961 cur->isconst &= ~(1<<hr);
962}
963
964static int is_const(const struct regstat *cur, signed char reg)
965{
966 int hr;
967 if (reg < 0) return 0;
968 if (!reg) return 1;
969 hr = get_reg(cur->regmap, reg);
970 if (hr >= 0)
971 return (cur->isconst>>hr)&1;
972 return 0;
973}
974
975static uint32_t get_const(const struct regstat *cur, signed char reg)
976{
977 int hr;
978 if (!reg) return 0;
979 hr = get_reg(cur->regmap, reg);
980 if (hr >= 0)
981 return current_constmap[hr];
982
983 SysPrintf("Unknown constant in r%d\n", reg);
984 abort();
985}
986
987// Least soon needed registers
988// Look at the next ten instructions and see which registers
989// will be used. Try not to reallocate these.
990static void lsn(u_char hsn[], int i)
991{
992 int j;
993 int b=-1;
994 for(j=0;j<9;j++)
995 {
996 if(i+j>=slen) {
997 j=slen-i-1;
998 break;
999 }
1000 if (dops[i+j].is_ujump)
1001 {
1002 // Don't go past an unconditonal jump
1003 j++;
1004 break;
1005 }
1006 }
1007 for(;j>=0;j--)
1008 {
1009 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1010 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1011 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1012 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1013 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
1014 // Stores can allocate zero
1015 hsn[dops[i+j].rs1]=j;
1016 hsn[dops[i+j].rs2]=j;
1017 }
1018 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1019 hsn[ROREG] = j;
1020 // On some architectures stores need invc_ptr
1021 #if defined(HOST_IMM8)
1022 if (dops[i+j].is_store)
1023 hsn[INVCP] = j;
1024 #endif
1025 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1026 {
1027 hsn[CCREG]=j;
1028 b=j;
1029 }
1030 }
1031 if(b>=0)
1032 {
1033 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
1034 {
1035 // Follow first branch
1036 int t=(cinfo[i+b].ba-start)>>2;
1037 j=7-b;if(t+j>=slen) j=slen-t-1;
1038 for(;j>=0;j--)
1039 {
1040 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1041 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1042 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1043 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
1044 }
1045 }
1046 // TODO: preferred register based on backward branch
1047 }
1048 // Delay slot should preferably not overwrite branch conditions or cycle count
1049 if (i > 0 && dops[i-1].is_jump) {
1050 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1051 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
1052 hsn[CCREG]=1;
1053 // ...or hash tables
1054 hsn[RHASH]=1;
1055 hsn[RHTBL]=1;
1056 }
1057 // Coprocessor load/store needs FTEMP, even if not declared
1058 if(dops[i].itype==C2LS) {
1059 hsn[FTEMP]=0;
1060 }
1061 // Load/store L/R also uses FTEMP as a temporary register
1062 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
1063 hsn[FTEMP]=0;
1064 }
1065 // Don't remove the miniht registers
1066 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
1067 {
1068 hsn[RHASH]=0;
1069 hsn[RHTBL]=0;
1070 }
1071}
1072
1073// We only want to allocate registers if we're going to use them again soon
1074static int needed_again(int r, int i)
1075{
1076 int j;
1077 int b=-1;
1078 int rn=10;
1079
1080 if (i > 0 && dops[i-1].is_ujump)
1081 {
1082 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
1083 return 0; // Don't need any registers if exiting the block
1084 }
1085 for(j=0;j<9;j++)
1086 {
1087 if(i+j>=slen) {
1088 j=slen-i-1;
1089 break;
1090 }
1091 if (dops[i+j].is_ujump)
1092 {
1093 // Don't go past an unconditonal jump
1094 j++;
1095 break;
1096 }
1097 if (dops[i+j].is_exception)
1098 {
1099 break;
1100 }
1101 }
1102 for(;j>=1;j--)
1103 {
1104 if(dops[i+j].rs1==r) rn=j;
1105 if(dops[i+j].rs2==r) rn=j;
1106 if((unneeded_reg[i+j]>>r)&1) rn=10;
1107 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1108 {
1109 b=j;
1110 }
1111 }
1112 if(rn<10) return 1;
1113 (void)b;
1114 return 0;
1115}
1116
1117// Try to match register allocations at the end of a loop with those
1118// at the beginning
1119static int loop_reg(int i, int r, int hr)
1120{
1121 int j,k;
1122 for(j=0;j<9;j++)
1123 {
1124 if(i+j>=slen) {
1125 j=slen-i-1;
1126 break;
1127 }
1128 if (dops[i+j].is_ujump)
1129 {
1130 // Don't go past an unconditonal jump
1131 j++;
1132 break;
1133 }
1134 }
1135 k=0;
1136 if(i>0){
1137 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1138 k--;
1139 }
1140 for(;k<j;k++)
1141 {
1142 assert(r < 64);
1143 if((unneeded_reg[i+k]>>r)&1) return hr;
1144 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1145 {
1146 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
1147 {
1148 int t=(cinfo[i+k].ba-start)>>2;
1149 int reg=get_reg(regs[t].regmap_entry,r);
1150 if(reg>=0) return reg;
1151 //reg=get_reg(regs[t+1].regmap_entry,r);
1152 //if(reg>=0) return reg;
1153 }
1154 }
1155 }
1156 return hr;
1157}
1158
1159
1160// Allocate every register, preserving source/target regs
1161static void alloc_all(struct regstat *cur,int i)
1162{
1163 int hr;
1164
1165 for(hr=0;hr<HOST_REGS;hr++) {
1166 if(hr!=EXCLUDE_REG) {
1167 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1168 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1169 {
1170 cur->regmap[hr]=-1;
1171 cur->dirty&=~(1<<hr);
1172 }
1173 // Don't need zeros
1174 if(cur->regmap[hr]==0)
1175 {
1176 cur->regmap[hr]=-1;
1177 cur->dirty&=~(1<<hr);
1178 }
1179 }
1180 }
1181}
1182
1183#ifndef NDEBUG
1184static int host_tempreg_in_use;
1185
1186static void host_tempreg_acquire(void)
1187{
1188 assert(!host_tempreg_in_use);
1189 host_tempreg_in_use = 1;
1190}
1191
1192static void host_tempreg_release(void)
1193{
1194 host_tempreg_in_use = 0;
1195}
1196#else
1197static void host_tempreg_acquire(void) {}
1198static void host_tempreg_release(void) {}
1199#endif
1200
1201#ifdef ASSEM_PRINT
1202extern void gen_interupt();
1203extern void do_insn_cmp();
1204#define FUNCNAME(f) { f, " " #f }
1205static const struct {
1206 void *addr;
1207 const char *name;
1208} function_names[] = {
1209 FUNCNAME(cc_interrupt),
1210 FUNCNAME(gen_interupt),
1211 FUNCNAME(ndrc_get_addr_ht),
1212 FUNCNAME(jump_handler_read8),
1213 FUNCNAME(jump_handler_read16),
1214 FUNCNAME(jump_handler_read32),
1215 FUNCNAME(jump_handler_write8),
1216 FUNCNAME(jump_handler_write16),
1217 FUNCNAME(jump_handler_write32),
1218 FUNCNAME(ndrc_write_invalidate_one),
1219 FUNCNAME(ndrc_write_invalidate_many),
1220 FUNCNAME(jump_to_new_pc),
1221 FUNCNAME(jump_break),
1222 FUNCNAME(jump_break_ds),
1223 FUNCNAME(jump_syscall),
1224 FUNCNAME(jump_syscall_ds),
1225 FUNCNAME(jump_overflow),
1226 FUNCNAME(jump_overflow_ds),
1227 FUNCNAME(jump_addrerror),
1228 FUNCNAME(jump_addrerror_ds),
1229 FUNCNAME(call_gteStall),
1230 FUNCNAME(new_dyna_leave),
1231 FUNCNAME(pcsx_mtc0),
1232 FUNCNAME(pcsx_mtc0_ds),
1233 FUNCNAME(execI),
1234#ifdef __aarch64__
1235 FUNCNAME(do_memhandler_pre),
1236 FUNCNAME(do_memhandler_post),
1237#endif
1238#ifdef DRC_DBG
1239# ifdef __aarch64__
1240 FUNCNAME(do_insn_cmp_arm64),
1241# else
1242 FUNCNAME(do_insn_cmp),
1243# endif
1244#endif
1245};
1246
1247static const char *func_name(const void *a)
1248{
1249 int i;
1250 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1251 if (function_names[i].addr == a)
1252 return function_names[i].name;
1253 return "";
1254}
1255
1256static const char *fpofs_name(u_int ofs)
1257{
1258 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1259 static char buf[64];
1260 switch (ofs) {
1261 #define ofscase(x) case LO_##x: return " ; " #x
1262 ofscase(next_interupt);
1263 ofscase(cycle_count);
1264 ofscase(last_count);
1265 ofscase(pending_exception);
1266 ofscase(stop);
1267 ofscase(address);
1268 ofscase(lo);
1269 ofscase(hi);
1270 ofscase(PC);
1271 ofscase(cycle);
1272 ofscase(mem_rtab);
1273 ofscase(mem_wtab);
1274 ofscase(psxH_ptr);
1275 ofscase(invc_ptr);
1276 ofscase(ram_offset);
1277 #undef ofscase
1278 }
1279 buf[0] = 0;
1280 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1281 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1282 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1283 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1284 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1285 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1286 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1287 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1288 return buf;
1289}
1290#else
1291#define func_name(x) ""
1292#define fpofs_name(x) ""
1293#endif
1294
1295#ifdef __i386__
1296#include "assem_x86.c"
1297#endif
1298#ifdef __x86_64__
1299#include "assem_x64.c"
1300#endif
1301#ifdef __arm__
1302#include "assem_arm.c"
1303#endif
1304#ifdef __aarch64__
1305#include "assem_arm64.c"
1306#endif
1307
1308static void *get_trampoline(const void *f)
1309{
1310 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
1311 size_t i;
1312
1313 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1314 if (tramp->f[i] == f || tramp->f[i] == NULL)
1315 break;
1316 }
1317 if (i == ARRAY_SIZE(tramp->f)) {
1318 SysPrintf("trampoline table is full, last func %p\n", f);
1319 abort();
1320 }
1321 if (tramp->f[i] == NULL) {
1322 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1323 tramp->f[i] = f;
1324 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1325#ifdef HAVE_LIBNX
1326 // invalidate the RX mirror (unsure if necessary, but just in case...)
1327 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1328#endif
1329 }
1330 return &ndrc->tramp.ops[i];
1331}
1332
1333static void emit_far_jump(const void *f)
1334{
1335 if (can_jump_or_call(f)) {
1336 emit_jmp(f);
1337 return;
1338 }
1339
1340 f = get_trampoline(f);
1341 emit_jmp(f);
1342}
1343
1344static void emit_far_call(const void *f)
1345{
1346 if (can_jump_or_call(f)) {
1347 emit_call(f);
1348 return;
1349 }
1350
1351 f = get_trampoline(f);
1352 emit_call(f);
1353}
1354
1355// Check if an address is already compiled
1356// but don't return addresses which are about to expire from the cache
1357static void *check_addr(u_int vaddr)
1358{
1359 struct ht_entry *ht_bin = hash_table_get(vaddr);
1360 size_t i;
1361 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1362 if (ht_bin->vaddr[i] == vaddr)
1363 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1364 return ht_bin->tcaddr[i];
1365 }
1366
1367 // refactor to get_addr_nocompile?
1368 u_int start_page = get_page_prev(vaddr);
1369 u_int page, end_page = get_page(vaddr);
1370
1371 stat_inc(stat_jump_in_lookups);
1372 for (page = start_page; page <= end_page; page++) {
1373 const struct block_info *block;
1374 for (block = blocks[page]; block != NULL; block = block->next) {
1375 if (vaddr < block->start)
1376 break;
1377 if (block->is_dirty || vaddr >= block->start + block->len)
1378 continue;
1379 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1380 continue;
1381 for (i = 0; i < block->jump_in_cnt; i++)
1382 if (block->jump_in[i].vaddr == vaddr)
1383 break;
1384 if (i == block->jump_in_cnt)
1385 continue;
1386
1387 // Update existing entry with current address
1388 void *addr = block->jump_in[i].addr;
1389 if (ht_bin->vaddr[0] == vaddr) {
1390 ht_bin->tcaddr[0] = addr;
1391 return addr;
1392 }
1393 if (ht_bin->vaddr[1] == vaddr) {
1394 ht_bin->tcaddr[1] = addr;
1395 return addr;
1396 }
1397 // Insert into hash table with low priority.
1398 // Don't evict existing entries, as they are probably
1399 // addresses that are being accessed frequently.
1400 if (ht_bin->vaddr[0] == -1) {
1401 ht_bin->vaddr[0] = vaddr;
1402 ht_bin->tcaddr[0] = addr;
1403 }
1404 else if (ht_bin->vaddr[1] == -1) {
1405 ht_bin->vaddr[1] = vaddr;
1406 ht_bin->tcaddr[1] = addr;
1407 }
1408 return addr;
1409 }
1410 }
1411 return NULL;
1412}
1413
1414static void blocks_clear(struct block_info **head)
1415{
1416 struct block_info *cur, *next;
1417
1418 if ((cur = *head)) {
1419 *head = NULL;
1420 while (cur) {
1421 next = cur->next;
1422 free(cur);
1423 cur = next;
1424 }
1425 }
1426}
1427
1428static int blocks_remove_matching_addrs(struct block_info **head,
1429 u_int base_offs, int shift)
1430{
1431 struct block_info *next;
1432 int hit = 0;
1433 while (*head) {
1434 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1435 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
1436 invalidate_block(*head);
1437 next = (*head)->next;
1438 free(*head);
1439 *head = next;
1440 stat_dec(stat_blocks);
1441 hit = 1;
1442 }
1443 else
1444 {
1445 head = &((*head)->next);
1446 }
1447 }
1448 return hit;
1449}
1450
1451// This is called when we write to a compiled block (see do_invstub)
1452static void unlink_jumps_vaddr_range(u_int start, u_int end)
1453{
1454 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1455 int i;
1456
1457 for (page = start_page; page <= end_page; page++) {
1458 struct jump_info *ji = jumps[page];
1459 if (ji == NULL)
1460 continue;
1461 for (i = 0; i < ji->count; ) {
1462 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1463 i++;
1464 continue;
1465 }
1466
1467 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1468 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1469 void *host_addr = find_extjump_insn(ji->e[i].stub);
1470 mark_clear_cache(host_addr);
1471 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1472
1473 stat_dec(stat_links);
1474 ji->count--;
1475 if (i < ji->count) {
1476 ji->e[i] = ji->e[ji->count];
1477 continue;
1478 }
1479 i++;
1480 }
1481 }
1482}
1483
1484static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1485{
1486 int i;
1487 if (ji == NULL)
1488 return;
1489 for (i = 0; i < ji->count; ) {
1490 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1491 if (((tc_offs ^ base_offs) >> shift) != 0) {
1492 i++;
1493 continue;
1494 }
1495
1496 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
1497 stat_dec(stat_links);
1498 ji->count--;
1499 if (i < ji->count) {
1500 ji->e[i] = ji->e[ji->count];
1501 continue;
1502 }
1503 i++;
1504 }
1505}
1506
1507static void invalidate_block(struct block_info *block)
1508{
1509 u_int i;
1510
1511 block->is_dirty = 1;
1512 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1513 for (i = 0; i < block->jump_in_cnt; i++)
1514 hash_table_remove(block->jump_in[i].vaddr);
1515}
1516
1517static int invalidate_range(u_int start, u_int end,
1518 u32 *inv_start_ret, u32 *inv_end_ret)
1519{
1520 struct block_info *last_block = NULL;
1521 u_int start_page = get_page_prev(start);
1522 u_int end_page = get_page(end - 1);
1523 u_int start_m = pmmask(start);
1524 u_int end_m = pmmask(end - 1);
1525 u_int inv_start, inv_end;
1526 u_int blk_start_m, blk_end_m;
1527 u_int page;
1528 int hit = 0;
1529
1530 // additional area without code (to supplement invalid_code[]), [start, end)
1531 // avoids excessive ndrc_write_invalidate*() calls
1532 inv_start = start_m & ~0xfff;
1533 inv_end = end_m | 0xfff;
1534
1535 for (page = start_page; page <= end_page; page++) {
1536 struct block_info *block;
1537 for (block = blocks[page]; block != NULL; block = block->next) {
1538 if (block->is_dirty)
1539 continue;
1540 last_block = block;
1541 blk_end_m = pmmask(block->start + block->len);
1542 if (blk_end_m <= start_m) {
1543 inv_start = max(inv_start, blk_end_m);
1544 continue;
1545 }
1546 blk_start_m = pmmask(block->start);
1547 if (end_m <= blk_start_m) {
1548 inv_end = min(inv_end, blk_start_m - 1);
1549 continue;
1550 }
1551 if (!block->source) // "hack" block - leave it alone
1552 continue;
1553
1554 hit++;
1555 invalidate_block(block);
1556 stat_inc(stat_inv_hits);
1557 }
1558 }
1559
1560 if (!hit && last_block && last_block->source) {
1561 // could be some leftover unused block, uselessly trapping writes
1562 last_block->inv_near_misses++;
1563 if (last_block->inv_near_misses > 128) {
1564 invalidate_block(last_block);
1565 stat_inc(stat_inv_hits);
1566 hit++;
1567 }
1568 }
1569 if (hit) {
1570 do_clear_cache();
1571#ifdef USE_MINI_HT
1572 memset(mini_ht, -1, sizeof(mini_ht));
1573#endif
1574 }
1575
1576 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1577 // the whole page is empty now
1578 mark_invalid_code(start, 1, 1);
1579
1580 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1581 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1582 return hit;
1583}
1584
1585void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1586{
1587 invalidate_range(start, end, NULL, NULL);
1588}
1589
1590static void ndrc_write_invalidate_many(u_int start, u_int end)
1591{
1592 // this check is done by the caller
1593 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1594 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1595#ifdef INV_DEBUG_W
1596 int invc = invalid_code[start >> 12];
1597 u_int len = end - start;
1598 if (ret)
1599 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
1600 else
1601 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1602 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1603 check_for_block_changes(start, end);
1604#endif
1605 stat_inc(stat_inv_addr_calls);
1606 (void)ret;
1607}
1608
1609void ndrc_write_invalidate_one(u_int addr)
1610{
1611 ndrc_write_invalidate_many(addr, addr + 4);
1612}
1613
1614// This is called when loading a save state.
1615// Anything could have changed, so invalidate everything.
1616void new_dynarec_invalidate_all_pages(void)
1617{
1618 struct block_info *block;
1619 u_int page;
1620 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1621 for (block = blocks[page]; block != NULL; block = block->next) {
1622 if (block->is_dirty)
1623 continue;
1624 if (!block->source) // hack block?
1625 continue;
1626 invalidate_block(block);
1627 }
1628 }
1629
1630 #ifdef USE_MINI_HT
1631 memset(mini_ht, -1, sizeof(mini_ht));
1632 #endif
1633 do_clear_cache();
1634}
1635
1636// Add an entry to jump_out after making a link
1637// src should point to code by emit_extjump()
1638void ndrc_add_jump_out(u_int vaddr, void *src)
1639{
1640 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1641 u_int page = get_page(vaddr);
1642 struct jump_info *ji;
1643
1644 stat_inc(stat_links);
1645 check_extjump2(src);
1646 ji = jumps[page];
1647 if (ji == NULL) {
1648 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1649 ji->alloc = 16;
1650 ji->count = 0;
1651 }
1652 else if (ji->count >= ji->alloc) {
1653 ji->alloc += 16;
1654 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1655 }
1656 jumps[page] = ji;
1657 ji->e[ji->count].target_vaddr = vaddr;
1658 ji->e[ji->count].stub = src;
1659 ji->count++;
1660}
1661
1662/* Register allocation */
1663
1664static void alloc_set(struct regstat *cur, int reg, int hr)
1665{
1666 cur->regmap[hr] = reg;
1667 cur->dirty &= ~(1u << hr);
1668 cur->isconst &= ~(1u << hr);
1669 cur->noevict |= 1u << hr;
1670}
1671
1672static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1673{
1674 u_char hsn[MAXREG+1];
1675 int j, r, hr;
1676 memset(hsn, 10, sizeof(hsn));
1677 lsn(hsn, i);
1678 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1679 if(i>0) {
1680 // Don't evict the cycle count at entry points, otherwise the entry
1681 // stub will have to write it.
1682 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1683 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1684 for(j=10;j>=3;j--)
1685 {
1686 // Alloc preferred register if available
1687 if (!((cur->noevict >> preferred_hr) & 1)
1688 && hsn[cur->regmap[preferred_hr]] == j)
1689 {
1690 alloc_set(cur, reg, preferred_hr);
1691 return;
1692 }
1693 for(r=1;r<=MAXREG;r++)
1694 {
1695 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1696 for(hr=0;hr<HOST_REGS;hr++) {
1697 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1698 continue;
1699 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1700 if(cur->regmap[hr]==r) {
1701 alloc_set(cur, reg, hr);
1702 return;
1703 }
1704 }
1705 }
1706 }
1707 }
1708 }
1709 }
1710 for(j=10;j>=0;j--)
1711 {
1712 for(r=1;r<=MAXREG;r++)
1713 {
1714 if(hsn[r]==j) {
1715 for(hr=0;hr<HOST_REGS;hr++) {
1716 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1717 continue;
1718 if(cur->regmap[hr]==r) {
1719 alloc_set(cur, reg, hr);
1720 return;
1721 }
1722 }
1723 }
1724 }
1725 }
1726 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1727 abort();
1728}
1729
1730// Note: registers are allocated clean (unmodified state)
1731// if you intend to modify the register, you must call dirty_reg().
1732static void alloc_reg(struct regstat *cur,int i,signed char reg)
1733{
1734 int r,hr;
1735 int preferred_reg = PREFERRED_REG_FIRST
1736 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1737 if (reg == CCREG) preferred_reg = HOST_CCREG;
1738 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1739 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1740 assert(reg >= 0);
1741
1742 // Don't allocate unused registers
1743 if((cur->u>>reg)&1) return;
1744
1745 // see if it's already allocated
1746 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1747 cur->noevict |= 1u << hr;
1748 return;
1749 }
1750
1751 // Keep the same mapping if the register was already allocated in a loop
1752 preferred_reg = loop_reg(i,reg,preferred_reg);
1753
1754 // Try to allocate the preferred register
1755 if (cur->regmap[preferred_reg] == -1) {
1756 alloc_set(cur, reg, preferred_reg);
1757 return;
1758 }
1759 r=cur->regmap[preferred_reg];
1760 assert(r < 64);
1761 if((cur->u>>r)&1) {
1762 alloc_set(cur, reg, preferred_reg);
1763 return;
1764 }
1765
1766 // Clear any unneeded registers
1767 // We try to keep the mapping consistent, if possible, because it
1768 // makes branches easier (especially loops). So we try to allocate
1769 // first (see above) before removing old mappings. If this is not
1770 // possible then go ahead and clear out the registers that are no
1771 // longer needed.
1772 for(hr=0;hr<HOST_REGS;hr++)
1773 {
1774 r=cur->regmap[hr];
1775 if(r>=0) {
1776 assert(r < 64);
1777 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1778 }
1779 }
1780
1781 // Try to allocate any available register, but prefer
1782 // registers that have not been used recently.
1783 if (i > 0) {
1784 for (hr = PREFERRED_REG_FIRST; ; ) {
1785 if (cur->regmap[hr] < 0) {
1786 int oldreg = regs[i-1].regmap[hr];
1787 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1788 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1789 {
1790 alloc_set(cur, reg, hr);
1791 return;
1792 }
1793 }
1794 hr++;
1795 if (hr == EXCLUDE_REG)
1796 hr++;
1797 if (hr == HOST_REGS)
1798 hr = 0;
1799 if (hr == PREFERRED_REG_FIRST)
1800 break;
1801 }
1802 }
1803
1804 // Try to allocate any available register
1805 for (hr = PREFERRED_REG_FIRST; ; ) {
1806 if (cur->regmap[hr] < 0) {
1807 alloc_set(cur, reg, hr);
1808 return;
1809 }
1810 hr++;
1811 if (hr == EXCLUDE_REG)
1812 hr++;
1813 if (hr == HOST_REGS)
1814 hr = 0;
1815 if (hr == PREFERRED_REG_FIRST)
1816 break;
1817 }
1818
1819 // Ok, now we have to evict someone
1820 // Pick a register we hopefully won't need soon
1821 evict_alloc_reg(cur, i, reg, preferred_reg);
1822}
1823
1824// Allocate a temporary register. This is done without regard to
1825// dirty status or whether the register we request is on the unneeded list
1826// Note: This will only allocate one register, even if called multiple times
1827static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1828{
1829 int r,hr;
1830
1831 // see if it's already allocated
1832 for (hr = 0; hr < HOST_REGS; hr++)
1833 {
1834 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1835 cur->noevict |= 1u << hr;
1836 return;
1837 }
1838 }
1839
1840 // Try to allocate any available register
1841 for(hr=HOST_REGS-1;hr>=0;hr--) {
1842 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1843 alloc_set(cur, reg, hr);
1844 return;
1845 }
1846 }
1847
1848 // Find an unneeded register
1849 for(hr=HOST_REGS-1;hr>=0;hr--)
1850 {
1851 r=cur->regmap[hr];
1852 if(r>=0) {
1853 assert(r < 64);
1854 if((cur->u>>r)&1) {
1855 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1856 alloc_set(cur, reg, hr);
1857 return;
1858 }
1859 }
1860 }
1861 }
1862
1863 // Ok, now we have to evict someone
1864 // Pick a register we hopefully won't need soon
1865 evict_alloc_reg(cur, i, reg, 0);
1866}
1867
1868static void mov_alloc(struct regstat *current,int i)
1869{
1870 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1871 alloc_cc(current,i); // for stalls
1872 dirty_reg(current,CCREG);
1873 }
1874
1875 // Note: Don't need to actually alloc the source registers
1876 //alloc_reg(current,i,dops[i].rs1);
1877 alloc_reg(current,i,dops[i].rt1);
1878
1879 clear_const(current,dops[i].rs1);
1880 clear_const(current,dops[i].rt1);
1881 dirty_reg(current,dops[i].rt1);
1882}
1883
1884static void shiftimm_alloc(struct regstat *current,int i)
1885{
1886 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1887 {
1888 if(dops[i].rt1) {
1889 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1890 else dops[i].use_lt1=!!dops[i].rs1;
1891 alloc_reg(current,i,dops[i].rt1);
1892 dirty_reg(current,dops[i].rt1);
1893 if(is_const(current,dops[i].rs1)) {
1894 int v=get_const(current,dops[i].rs1);
1895 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1896 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1897 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
1898 }
1899 else clear_const(current,dops[i].rt1);
1900 }
1901 }
1902 else
1903 {
1904 clear_const(current,dops[i].rs1);
1905 clear_const(current,dops[i].rt1);
1906 }
1907
1908 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1909 {
1910 assert(0);
1911 }
1912 if(dops[i].opcode2==0x3c) // DSLL32
1913 {
1914 assert(0);
1915 }
1916 if(dops[i].opcode2==0x3e) // DSRL32
1917 {
1918 assert(0);
1919 }
1920 if(dops[i].opcode2==0x3f) // DSRA32
1921 {
1922 assert(0);
1923 }
1924}
1925
1926static void shift_alloc(struct regstat *current,int i)
1927{
1928 if(dops[i].rt1) {
1929 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1930 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1931 alloc_reg(current,i,dops[i].rt1);
1932 if(dops[i].rt1==dops[i].rs2) {
1933 alloc_reg_temp(current,i,-1);
1934 cinfo[i].min_free_regs=1;
1935 }
1936 clear_const(current,dops[i].rs1);
1937 clear_const(current,dops[i].rs2);
1938 clear_const(current,dops[i].rt1);
1939 dirty_reg(current,dops[i].rt1);
1940 }
1941}
1942
1943static void alu_alloc(struct regstat *current,int i)
1944{
1945 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1946 if(dops[i].rt1) {
1947 if(dops[i].rs1&&dops[i].rs2) {
1948 alloc_reg(current,i,dops[i].rs1);
1949 alloc_reg(current,i,dops[i].rs2);
1950 }
1951 else {
1952 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1953 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1954 }
1955 alloc_reg(current,i,dops[i].rt1);
1956 }
1957 if (dops[i].may_except) {
1958 alloc_cc_optional(current, i); // for exceptions
1959 alloc_reg_temp(current, i, -1);
1960 cinfo[i].min_free_regs = 1;
1961 }
1962 }
1963 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1964 if(dops[i].rt1) {
1965 alloc_reg(current,i,dops[i].rs1);
1966 alloc_reg(current,i,dops[i].rs2);
1967 alloc_reg(current,i,dops[i].rt1);
1968 }
1969 }
1970 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1971 if(dops[i].rt1) {
1972 if(dops[i].rs1&&dops[i].rs2) {
1973 alloc_reg(current,i,dops[i].rs1);
1974 alloc_reg(current,i,dops[i].rs2);
1975 }
1976 else
1977 {
1978 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1979 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1980 }
1981 alloc_reg(current,i,dops[i].rt1);
1982 }
1983 }
1984 clear_const(current,dops[i].rs1);
1985 clear_const(current,dops[i].rs2);
1986 clear_const(current,dops[i].rt1);
1987 dirty_reg(current,dops[i].rt1);
1988}
1989
1990static void imm16_alloc(struct regstat *current,int i)
1991{
1992 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1993 else dops[i].use_lt1=!!dops[i].rs1;
1994 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1995 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1996 clear_const(current,dops[i].rs1);
1997 clear_const(current,dops[i].rt1);
1998 }
1999 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2000 if(is_const(current,dops[i].rs1)) {
2001 int v=get_const(current,dops[i].rs1);
2002 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2003 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2004 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
2005 }
2006 else clear_const(current,dops[i].rt1);
2007 }
2008 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2009 if(is_const(current,dops[i].rs1)) {
2010 int v=get_const(current,dops[i].rs1);
2011 set_const(current,dops[i].rt1,v+cinfo[i].imm);
2012 }
2013 else clear_const(current,dops[i].rt1);
2014 if (dops[i].may_except) {
2015 alloc_cc_optional(current, i); // for exceptions
2016 alloc_reg_temp(current, i, -1);
2017 cinfo[i].min_free_regs = 1;
2018 }
2019 }
2020 else {
2021 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
2022 }
2023 dirty_reg(current,dops[i].rt1);
2024}
2025
2026static void load_alloc(struct regstat *current,int i)
2027{
2028 int need_temp = 0;
2029 clear_const(current,dops[i].rt1);
2030 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2031 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
2032 if (needed_again(dops[i].rs1, i))
2033 alloc_reg(current, i, dops[i].rs1);
2034 if (ram_offset)
2035 alloc_reg(current, i, ROREG);
2036 if (dops[i].may_except) {
2037 alloc_cc_optional(current, i); // for exceptions
2038 need_temp = 1;
2039 }
2040 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2041 alloc_reg(current,i,dops[i].rt1);
2042 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
2043 dirty_reg(current,dops[i].rt1);
2044 // LWL/LWR need a temporary register for the old value
2045 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2046 {
2047 alloc_reg(current,i,FTEMP);
2048 need_temp = 1;
2049 }
2050 }
2051 else
2052 {
2053 // Load to r0 or unneeded register (dummy load)
2054 // but we still need a register to calculate the address
2055 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2056 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2057 need_temp = 1;
2058 }
2059 if (need_temp) {
2060 alloc_reg_temp(current, i, -1);
2061 cinfo[i].min_free_regs = 1;
2062 }
2063}
2064
2065// this may eat up to 7 registers
2066static void store_alloc(struct regstat *current, int i)
2067{
2068 clear_const(current,dops[i].rs2);
2069 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2070 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2071 alloc_reg(current,i,dops[i].rs2);
2072 if (ram_offset)
2073 alloc_reg(current, i, ROREG);
2074 #if defined(HOST_IMM8)
2075 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2076 alloc_reg(current, i, INVCP);
2077 #endif
2078 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
2079 alloc_reg(current,i,FTEMP);
2080 }
2081 if (dops[i].may_except)
2082 alloc_cc_optional(current, i); // for exceptions
2083 // We need a temporary register for address generation
2084 alloc_reg_temp(current,i,-1);
2085 cinfo[i].min_free_regs=1;
2086}
2087
2088static void c2ls_alloc(struct regstat *current, int i)
2089{
2090 clear_const(current,dops[i].rt1);
2091 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2092 alloc_reg(current,i,FTEMP);
2093 if (ram_offset)
2094 alloc_reg(current, i, ROREG);
2095 #if defined(HOST_IMM8)
2096 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2097 if (dops[i].opcode == 0x3a) // SWC2
2098 alloc_reg(current,i,INVCP);
2099 #endif
2100 if (dops[i].may_except)
2101 alloc_cc_optional(current, i); // for exceptions
2102 // We need a temporary register for address generation
2103 alloc_reg_temp(current,i,-1);
2104 cinfo[i].min_free_regs=1;
2105}
2106
2107#ifndef multdiv_alloc
2108static void multdiv_alloc(struct regstat *current,int i)
2109{
2110 // case 0x18: MULT
2111 // case 0x19: MULTU
2112 // case 0x1A: DIV
2113 // case 0x1B: DIVU
2114 clear_const(current,dops[i].rs1);
2115 clear_const(current,dops[i].rs2);
2116 alloc_cc(current,i); // for stalls
2117 dirty_reg(current,CCREG);
2118 current->u &= ~(1ull << HIREG);
2119 current->u &= ~(1ull << LOREG);
2120 alloc_reg(current, i, HIREG);
2121 alloc_reg(current, i, LOREG);
2122 dirty_reg(current, HIREG);
2123 dirty_reg(current, LOREG);
2124 if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
2125 {
2126 alloc_reg(current, i, dops[i].rs1);
2127 alloc_reg(current, i, dops[i].rs2);
2128 }
2129 // else multiply by zero is zero
2130}
2131#endif
2132
2133static void cop0_alloc(struct regstat *current,int i)
2134{
2135 if(dops[i].opcode2==0) // MFC0
2136 {
2137 if(dops[i].rt1) {
2138 clear_const(current,dops[i].rt1);
2139 alloc_reg(current,i,dops[i].rt1);
2140 dirty_reg(current,dops[i].rt1);
2141 }
2142 }
2143 else if(dops[i].opcode2==4) // MTC0
2144 {
2145 if (((source[i]>>11)&0x1e) == 12) {
2146 alloc_cc(current, i);
2147 dirty_reg(current, CCREG);
2148 }
2149 if(dops[i].rs1){
2150 clear_const(current,dops[i].rs1);
2151 alloc_reg(current,i,dops[i].rs1);
2152 alloc_all(current,i);
2153 }
2154 else {
2155 alloc_all(current,i); // FIXME: Keep r0
2156 current->u&=~1LL;
2157 alloc_reg(current,i,0);
2158 }
2159 cinfo[i].min_free_regs = HOST_REGS;
2160 }
2161}
2162
2163static void rfe_alloc(struct regstat *current, int i)
2164{
2165 alloc_all(current, i);
2166 cinfo[i].min_free_regs = HOST_REGS;
2167}
2168
2169static void cop2_alloc(struct regstat *current,int i)
2170{
2171 if (dops[i].opcode2 < 3) // MFC2/CFC2
2172 {
2173 alloc_cc(current,i); // for stalls
2174 dirty_reg(current,CCREG);
2175 if(dops[i].rt1){
2176 clear_const(current,dops[i].rt1);
2177 alloc_reg(current,i,dops[i].rt1);
2178 dirty_reg(current,dops[i].rt1);
2179 }
2180 }
2181 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2182 {
2183 if(dops[i].rs1){
2184 clear_const(current,dops[i].rs1);
2185 alloc_reg(current,i,dops[i].rs1);
2186 }
2187 else {
2188 current->u&=~1LL;
2189 alloc_reg(current,i,0);
2190 }
2191 }
2192 alloc_reg_temp(current,i,-1);
2193 cinfo[i].min_free_regs=1;
2194}
2195
2196static void c2op_alloc(struct regstat *current,int i)
2197{
2198 alloc_cc(current,i); // for stalls
2199 dirty_reg(current,CCREG);
2200 alloc_reg_temp(current,i,-1);
2201}
2202
2203static void syscall_alloc(struct regstat *current,int i)
2204{
2205 alloc_cc(current,i);
2206 dirty_reg(current,CCREG);
2207 alloc_all(current,i);
2208 cinfo[i].min_free_regs=HOST_REGS;
2209 current->isconst=0;
2210}
2211
2212static void delayslot_alloc(struct regstat *current,int i)
2213{
2214 switch(dops[i].itype) {
2215 case UJUMP:
2216 case CJUMP:
2217 case SJUMP:
2218 case RJUMP:
2219 case SYSCALL:
2220 case HLECALL:
2221 case IMM16:
2222 imm16_alloc(current,i);
2223 break;
2224 case LOAD:
2225 case LOADLR:
2226 load_alloc(current,i);
2227 break;
2228 case STORE:
2229 case STORELR:
2230 store_alloc(current,i);
2231 break;
2232 case ALU:
2233 alu_alloc(current,i);
2234 break;
2235 case SHIFT:
2236 shift_alloc(current,i);
2237 break;
2238 case MULTDIV:
2239 multdiv_alloc(current,i);
2240 break;
2241 case SHIFTIMM:
2242 shiftimm_alloc(current,i);
2243 break;
2244 case MOV:
2245 mov_alloc(current,i);
2246 break;
2247 case COP0:
2248 cop0_alloc(current,i);
2249 break;
2250 case RFE:
2251 rfe_alloc(current,i);
2252 break;
2253 case COP2:
2254 cop2_alloc(current,i);
2255 break;
2256 case C2LS:
2257 c2ls_alloc(current,i);
2258 break;
2259 case C2OP:
2260 c2op_alloc(current,i);
2261 break;
2262 }
2263}
2264
2265static void add_stub(enum stub_type type, void *addr, void *retaddr,
2266 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2267{
2268 assert(stubcount < ARRAY_SIZE(stubs));
2269 stubs[stubcount].type = type;
2270 stubs[stubcount].addr = addr;
2271 stubs[stubcount].retaddr = retaddr;
2272 stubs[stubcount].a = a;
2273 stubs[stubcount].b = b;
2274 stubs[stubcount].c = c;
2275 stubs[stubcount].d = d;
2276 stubs[stubcount].e = e;
2277 stubcount++;
2278}
2279
2280static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2281 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2282{
2283 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2284}
2285
2286// Write out a single register
2287static void wb_register(signed char r, const signed char regmap[], u_int dirty)
2288{
2289 int hr;
2290 for(hr=0;hr<HOST_REGS;hr++) {
2291 if(hr!=EXCLUDE_REG) {
2292 if(regmap[hr]==r) {
2293 if((dirty>>hr)&1) {
2294 assert(regmap[hr]<64);
2295 emit_storereg(r,hr);
2296 }
2297 break;
2298 }
2299 }
2300 }
2301}
2302
2303static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2304{
2305 //if(dirty_pre==dirty) return;
2306 int hr, r;
2307 for (hr = 0; hr < HOST_REGS; hr++) {
2308 r = pre[hr];
2309 if (r < 1 || r > 33 || ((u >> r) & 1))
2310 continue;
2311 if (((dirty_pre & ~dirty) >> hr) & 1)
2312 emit_storereg(r, hr);
2313 }
2314}
2315
2316// trashes r2
2317static void pass_args(int a0, int a1)
2318{
2319 if(a0==1&&a1==0) {
2320 // must swap
2321 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2322 }
2323 else if(a0!=0&&a1==0) {
2324 emit_mov(a1,1);
2325 if (a0>=0) emit_mov(a0,0);
2326 }
2327 else {
2328 if(a0>=0&&a0!=0) emit_mov(a0,0);
2329 if(a1>=0&&a1!=1) emit_mov(a1,1);
2330 }
2331}
2332
2333static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
2334{
2335 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2336 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2337 if (dops[i].rt1 || do_oflow) {
2338 int do_exception_check = 0;
2339 signed char s1, s2, t, tmp;
2340 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2341 tmp = get_reg_temp(i_regs->regmap);
2342 if (do_oflow)
2343 assert(tmp >= 0);
2344 if (t < 0 && do_oflow)
2345 t = tmp;
2346 if (t >= 0) {
2347 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2348 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2349 if (dops[i].rs1 && dops[i].rs2) {
2350 assert(s1>=0);
2351 assert(s2>=0);
2352 if (dops[i].opcode2 & 2) {
2353 if (do_oflow) {
2354 emit_subs(s1, s2, tmp);
2355 do_exception_check = 1;
2356 }
2357 else
2358 emit_sub(s1,s2,t);
2359 }
2360 else {
2361 if (do_oflow) {
2362 emit_adds(s1, s2, tmp);
2363 do_exception_check = 1;
2364 }
2365 else
2366 emit_add(s1,s2,t);
2367 }
2368 }
2369 else if(dops[i].rs1) {
2370 if(s1>=0) emit_mov(s1,t);
2371 else emit_loadreg(dops[i].rs1,t);
2372 }
2373 else if(dops[i].rs2) {
2374 if (s2 < 0) {
2375 emit_loadreg(dops[i].rs2, t);
2376 s2 = t;
2377 }
2378 if (dops[i].opcode2 & 2) {
2379 if (do_oflow) {
2380 emit_negs(s2, tmp);
2381 do_exception_check = 1;
2382 }
2383 else
2384 emit_neg(s2, t);
2385 }
2386 else if (s2 != t)
2387 emit_mov(s2, t);
2388 }
2389 else
2390 emit_zeroreg(t);
2391 }
2392 if (do_exception_check) {
2393 void *jaddr = out;
2394 emit_jo(0);
2395 if (t >= 0 && tmp != t)
2396 emit_mov(tmp, t);
2397 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2398 }
2399 }
2400 }
2401 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2402 if(dops[i].rt1) {
2403 signed char s1l,s2l,t;
2404 {
2405 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2406 //assert(t>=0);
2407 if(t>=0) {
2408 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2409 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2410 if(dops[i].rs2==0) // rx<r0
2411 {
2412 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2413 assert(s1l>=0);
2414 emit_shrimm(s1l,31,t);
2415 }
2416 else // SLTU (unsigned can not be less than zero, 0<0)
2417 emit_zeroreg(t);
2418 }
2419 else if(dops[i].rs1==0) // r0<rx
2420 {
2421 assert(s2l>=0);
2422 if(dops[i].opcode2==0x2a) // SLT
2423 emit_set_gz32(s2l,t);
2424 else // SLTU (set if not zero)
2425 emit_set_nz32(s2l,t);
2426 }
2427 else{
2428 assert(s1l>=0);assert(s2l>=0);
2429 if(dops[i].opcode2==0x2a) // SLT
2430 emit_set_if_less32(s1l,s2l,t);
2431 else // SLTU
2432 emit_set_if_carry32(s1l,s2l,t);
2433 }
2434 }
2435 }
2436 }
2437 }
2438 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2439 if(dops[i].rt1) {
2440 signed char s1l,s2l,tl;
2441 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2442 {
2443 if(tl>=0) {
2444 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2445 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2446 if(dops[i].rs1&&dops[i].rs2) {
2447 assert(s1l>=0);
2448 assert(s2l>=0);
2449 if(dops[i].opcode2==0x24) { // AND
2450 emit_and(s1l,s2l,tl);
2451 } else
2452 if(dops[i].opcode2==0x25) { // OR
2453 emit_or(s1l,s2l,tl);
2454 } else
2455 if(dops[i].opcode2==0x26) { // XOR
2456 emit_xor(s1l,s2l,tl);
2457 } else
2458 if(dops[i].opcode2==0x27) { // NOR
2459 emit_or(s1l,s2l,tl);
2460 emit_not(tl,tl);
2461 }
2462 }
2463 else
2464 {
2465 if(dops[i].opcode2==0x24) { // AND
2466 emit_zeroreg(tl);
2467 } else
2468 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2469 if(dops[i].rs1){
2470 if(s1l>=0) emit_mov(s1l,tl);
2471 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2472 }
2473 else
2474 if(dops[i].rs2){
2475 if(s2l>=0) emit_mov(s2l,tl);
2476 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2477 }
2478 else emit_zeroreg(tl);
2479 } else
2480 if(dops[i].opcode2==0x27) { // NOR
2481 if(dops[i].rs1){
2482 if(s1l>=0) emit_not(s1l,tl);
2483 else {
2484 emit_loadreg(dops[i].rs1,tl);
2485 emit_not(tl,tl);
2486 }
2487 }
2488 else
2489 if(dops[i].rs2){
2490 if(s2l>=0) emit_not(s2l,tl);
2491 else {
2492 emit_loadreg(dops[i].rs2,tl);
2493 emit_not(tl,tl);
2494 }
2495 }
2496 else emit_movimm(-1,tl);
2497 }
2498 }
2499 }
2500 }
2501 }
2502 }
2503}
2504
2505static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
2506{
2507 if (dops[i].opcode==0x0f) { // LUI
2508 if(dops[i].rt1) {
2509 signed char t;
2510 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2511 //assert(t>=0);
2512 if(t>=0) {
2513 if(!((i_regs->isconst>>t)&1))
2514 emit_movimm(cinfo[i].imm<<16,t);
2515 }
2516 }
2517 }
2518 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2519 int is_addi = dops[i].may_except;
2520 if (dops[i].rt1 || is_addi) {
2521 signed char s, t, tmp;
2522 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2523 s=get_reg(i_regs->regmap,dops[i].rs1);
2524 if(dops[i].rs1) {
2525 tmp = get_reg_temp(i_regs->regmap);
2526 if (is_addi) {
2527 assert(tmp >= 0);
2528 if (t < 0) t = tmp;
2529 }
2530 if(t>=0) {
2531 if(!((i_regs->isconst>>t)&1)) {
2532 int sum, do_exception_check = 0;
2533 if (s < 0) {
2534 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2535 if (is_addi) {
2536 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
2537 do_exception_check = 1;
2538 }
2539 else
2540 emit_addimm(t, cinfo[i].imm, t);
2541 } else {
2542 if (!((i_regs->wasconst >> s) & 1)) {
2543 if (is_addi) {
2544 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
2545 do_exception_check = 1;
2546 }
2547 else
2548 emit_addimm(s, cinfo[i].imm, t);
2549 }
2550 else {
2551 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
2552 if (is_addi && oflow)
2553 do_exception_check = 2;
2554 else
2555 emit_movimm(sum, t);
2556 }
2557 }
2558 if (do_exception_check) {
2559 void *jaddr = out;
2560 if (do_exception_check == 2)
2561 emit_jmp(0);
2562 else {
2563 emit_jo(0);
2564 if (tmp != t)
2565 emit_mov(tmp, t);
2566 }
2567 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2568 }
2569 }
2570 }
2571 } else {
2572 if(t>=0) {
2573 if(!((i_regs->isconst>>t)&1))
2574 emit_movimm(cinfo[i].imm,t);
2575 }
2576 }
2577 }
2578 }
2579 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2580 if(dops[i].rt1) {
2581 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2582 signed char sl,t;
2583 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2584 sl=get_reg(i_regs->regmap,dops[i].rs1);
2585 //assert(t>=0);
2586 if(t>=0) {
2587 if(dops[i].rs1>0) {
2588 if(dops[i].opcode==0x0a) { // SLTI
2589 if(sl<0) {
2590 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2591 emit_slti32(t,cinfo[i].imm,t);
2592 }else{
2593 emit_slti32(sl,cinfo[i].imm,t);
2594 }
2595 }
2596 else { // SLTIU
2597 if(sl<0) {
2598 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2599 emit_sltiu32(t,cinfo[i].imm,t);
2600 }else{
2601 emit_sltiu32(sl,cinfo[i].imm,t);
2602 }
2603 }
2604 }else{
2605 // SLTI(U) with r0 is just stupid,
2606 // nonetheless examples can be found
2607 if(dops[i].opcode==0x0a) // SLTI
2608 if(0<cinfo[i].imm) emit_movimm(1,t);
2609 else emit_zeroreg(t);
2610 else // SLTIU
2611 {
2612 if(cinfo[i].imm) emit_movimm(1,t);
2613 else emit_zeroreg(t);
2614 }
2615 }
2616 }
2617 }
2618 }
2619 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2620 if(dops[i].rt1) {
2621 signed char sl,tl;
2622 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2623 sl=get_reg(i_regs->regmap,dops[i].rs1);
2624 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2625 if(dops[i].opcode==0x0c) //ANDI
2626 {
2627 if(dops[i].rs1) {
2628 if(sl<0) {
2629 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2630 emit_andimm(tl,cinfo[i].imm,tl);
2631 }else{
2632 if(!((i_regs->wasconst>>sl)&1))
2633 emit_andimm(sl,cinfo[i].imm,tl);
2634 else
2635 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
2636 }
2637 }
2638 else
2639 emit_zeroreg(tl);
2640 }
2641 else
2642 {
2643 if(dops[i].rs1) {
2644 if(sl<0) {
2645 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2646 }
2647 if(dops[i].opcode==0x0d) { // ORI
2648 if(sl<0) {
2649 emit_orimm(tl,cinfo[i].imm,tl);
2650 }else{
2651 if(!((i_regs->wasconst>>sl)&1))
2652 emit_orimm(sl,cinfo[i].imm,tl);
2653 else
2654 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
2655 }
2656 }
2657 if(dops[i].opcode==0x0e) { // XORI
2658 if(sl<0) {
2659 emit_xorimm(tl,cinfo[i].imm,tl);
2660 }else{
2661 if(!((i_regs->wasconst>>sl)&1))
2662 emit_xorimm(sl,cinfo[i].imm,tl);
2663 else
2664 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
2665 }
2666 }
2667 }
2668 else {
2669 emit_movimm(cinfo[i].imm,tl);
2670 }
2671 }
2672 }
2673 }
2674 }
2675}
2676
2677static void shiftimm_assemble(int i, const struct regstat *i_regs)
2678{
2679 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2680 {
2681 if(dops[i].rt1) {
2682 signed char s,t;
2683 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2684 s=get_reg(i_regs->regmap,dops[i].rs1);
2685 //assert(t>=0);
2686 if(t>=0&&!((i_regs->isconst>>t)&1)){
2687 if(dops[i].rs1==0)
2688 {
2689 emit_zeroreg(t);
2690 }
2691 else
2692 {
2693 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2694 if(cinfo[i].imm) {
2695 if(dops[i].opcode2==0) // SLL
2696 {
2697 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
2698 }
2699 if(dops[i].opcode2==2) // SRL
2700 {
2701 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
2702 }
2703 if(dops[i].opcode2==3) // SRA
2704 {
2705 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
2706 }
2707 }else{
2708 // Shift by zero
2709 if(s>=0 && s!=t) emit_mov(s,t);
2710 }
2711 }
2712 }
2713 //emit_storereg(dops[i].rt1,t); //DEBUG
2714 }
2715 }
2716 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2717 {
2718 assert(0);
2719 }
2720 if(dops[i].opcode2==0x3c) // DSLL32
2721 {
2722 assert(0);
2723 }
2724 if(dops[i].opcode2==0x3e) // DSRL32
2725 {
2726 assert(0);
2727 }
2728 if(dops[i].opcode2==0x3f) // DSRA32
2729 {
2730 assert(0);
2731 }
2732}
2733
2734#ifndef shift_assemble
2735static void shift_assemble(int i, const struct regstat *i_regs)
2736{
2737 signed char s,t,shift;
2738 if (dops[i].rt1 == 0)
2739 return;
2740 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2741 t = get_reg(i_regs->regmap, dops[i].rt1);
2742 s = get_reg(i_regs->regmap, dops[i].rs1);
2743 shift = get_reg(i_regs->regmap, dops[i].rs2);
2744 if (t < 0)
2745 return;
2746
2747 if(dops[i].rs1==0)
2748 emit_zeroreg(t);
2749 else if(dops[i].rs2==0) {
2750 assert(s>=0);
2751 if(s!=t) emit_mov(s,t);
2752 }
2753 else {
2754 host_tempreg_acquire();
2755 emit_andimm(shift,31,HOST_TEMPREG);
2756 switch(dops[i].opcode2) {
2757 case 4: // SLLV
2758 emit_shl(s,HOST_TEMPREG,t);
2759 break;
2760 case 6: // SRLV
2761 emit_shr(s,HOST_TEMPREG,t);
2762 break;
2763 case 7: // SRAV
2764 emit_sar(s,HOST_TEMPREG,t);
2765 break;
2766 default:
2767 assert(0);
2768 }
2769 host_tempreg_release();
2770 }
2771}
2772
2773#endif
2774
2775enum {
2776 MTYPE_8000 = 0,
2777 MTYPE_8020,
2778 MTYPE_0000,
2779 MTYPE_A000,
2780 MTYPE_1F80,
2781};
2782
2783static int get_ptr_mem_type(u_int a)
2784{
2785 if(a < 0x00200000) {
2786 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2787 // return wrong, must use memhandler for BIOS self-test to pass
2788 // 007 does similar stuff from a00 mirror, weird stuff
2789 return MTYPE_8000;
2790 return MTYPE_0000;
2791 }
2792 if(0x1f800000 <= a && a < 0x1f801000)
2793 return MTYPE_1F80;
2794 if(0x80200000 <= a && a < 0x80800000)
2795 return MTYPE_8020;
2796 if(0xa0000000 <= a && a < 0xa0200000)
2797 return MTYPE_A000;
2798 return MTYPE_8000;
2799}
2800
2801static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2802{
2803 int r = get_reg(i_regs->regmap, ROREG);
2804 if (r < 0 && host_tempreg_free) {
2805 host_tempreg_acquire();
2806 emit_loadreg(ROREG, r = HOST_TEMPREG);
2807 }
2808 if (r < 0)
2809 abort();
2810 return r;
2811}
2812
2813static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2814 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
2815{
2816 void *jaddr = NULL;
2817 int type = 0;
2818 int mr = dops[i].rs1;
2819 assert(addr >= 0);
2820 *offset_reg = -1;
2821 if(((smrv_strong|smrv_weak)>>mr)&1) {
2822 type=get_ptr_mem_type(smrv[mr]);
2823 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2824 }
2825 else {
2826 // use the mirror we are running on
2827 type=get_ptr_mem_type(start);
2828 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2829 }
2830
2831 if (dops[i].may_except) {
2832 // alignment check
2833 u_int op = dops[i].opcode;
2834 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
2835 void *jaddr2;
2836 emit_testimm(addr, mask);
2837 jaddr2 = out;
2838 emit_jne(0);
2839 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
2840 }
2841
2842 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2843 host_tempreg_acquire();
2844 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2845 addr=*addr_reg_override=HOST_TEMPREG;
2846 type=0;
2847 }
2848 else if(type==MTYPE_0000) { // RAM 0 mirror
2849 host_tempreg_acquire();
2850 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2851 addr=*addr_reg_override=HOST_TEMPREG;
2852 type=0;
2853 }
2854 else if(type==MTYPE_A000) { // RAM A mirror
2855 host_tempreg_acquire();
2856 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2857 addr=*addr_reg_override=HOST_TEMPREG;
2858 type=0;
2859 }
2860 else if(type==MTYPE_1F80) { // scratchpad
2861 if (psxH == (void *)0x1f800000) {
2862 host_tempreg_acquire();
2863 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2864 emit_cmpimm(HOST_TEMPREG,0x1000);
2865 host_tempreg_release();
2866 jaddr=out;
2867 emit_jc(0);
2868 }
2869 else {
2870 // do the usual RAM check, jump will go to the right handler
2871 type=0;
2872 }
2873 }
2874
2875 if (type == 0) // need ram check
2876 {
2877 emit_cmpimm(addr,RAM_SIZE);
2878 jaddr = out;
2879 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2880 // Hint to branch predictor that the branch is unlikely to be taken
2881 if (dops[i].rs1 >= 28)
2882 emit_jno_unlikely(0);
2883 else
2884 #endif
2885 emit_jno(0);
2886 if (ram_offset != 0)
2887 *offset_reg = get_ro_reg(i_regs, 0);
2888 }
2889
2890 return jaddr;
2891}
2892
2893// return memhandler, or get directly accessable address and return 0
2894static void *get_direct_memhandler(void *table, u_int addr,
2895 enum stub_type type, uintptr_t *addr_host)
2896{
2897 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2898 uintptr_t l1, l2 = 0;
2899 l1 = ((uintptr_t *)table)[addr>>12];
2900 if (!(l1 & msb)) {
2901 uintptr_t v = l1 << 1;
2902 *addr_host = v + addr;
2903 return NULL;
2904 }
2905 else {
2906 l1 <<= 1;
2907 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2908 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2909 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2910 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2911 else
2912 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2913 if (!(l2 & msb)) {
2914 uintptr_t v = l2 << 1;
2915 *addr_host = v + (addr&0xfff);
2916 return NULL;
2917 }
2918 return (void *)(l2 << 1);
2919 }
2920}
2921
2922static u_int get_host_reglist(const signed char *regmap)
2923{
2924 u_int reglist = 0, hr;
2925 for (hr = 0; hr < HOST_REGS; hr++) {
2926 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2927 reglist |= 1 << hr;
2928 }
2929 return reglist;
2930}
2931
2932static u_int reglist_exclude(u_int reglist, int r1, int r2)
2933{
2934 if (r1 >= 0)
2935 reglist &= ~(1u << r1);
2936 if (r2 >= 0)
2937 reglist &= ~(1u << r2);
2938 return reglist;
2939}
2940
2941// find a temp caller-saved register not in reglist (so assumed to be free)
2942static int reglist_find_free(u_int reglist)
2943{
2944 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2945 if (free_regs == 0)
2946 return -1;
2947 return __builtin_ctz(free_regs);
2948}
2949
2950static void do_load_word(int a, int rt, int offset_reg)
2951{
2952 if (offset_reg >= 0)
2953 emit_ldr_dualindexed(offset_reg, a, rt);
2954 else
2955 emit_readword_indexed(0, a, rt);
2956}
2957
2958static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2959{
2960 if (offset_reg < 0) {
2961 emit_writeword_indexed(rt, ofs, a);
2962 return;
2963 }
2964 if (ofs != 0)
2965 emit_addimm(a, ofs, a);
2966 emit_str_dualindexed(offset_reg, a, rt);
2967 if (ofs != 0 && preseve_a)
2968 emit_addimm(a, -ofs, a);
2969}
2970
2971static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2972{
2973 if (offset_reg < 0) {
2974 emit_writehword_indexed(rt, ofs, a);
2975 return;
2976 }
2977 if (ofs != 0)
2978 emit_addimm(a, ofs, a);
2979 emit_strh_dualindexed(offset_reg, a, rt);
2980 if (ofs != 0 && preseve_a)
2981 emit_addimm(a, -ofs, a);
2982}
2983
2984static void do_store_byte(int a, int rt, int offset_reg)
2985{
2986 if (offset_reg >= 0)
2987 emit_strb_dualindexed(offset_reg, a, rt);
2988 else
2989 emit_writebyte_indexed(rt, 0, a);
2990}
2991
2992static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2993{
2994 int addr = cinfo[i].addr;
2995 int s,tl;
2996 int offset;
2997 void *jaddr=0;
2998 int memtarget=0,c=0;
2999 int offset_reg = -1;
3000 int fastio_reg_override = -1;
3001 u_int reglist=get_host_reglist(i_regs->regmap);
3002 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3003 s=get_reg(i_regs->regmap,dops[i].rs1);
3004 offset=cinfo[i].imm;
3005 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3006 if(s>=0) {
3007 c=(i_regs->wasconst>>s)&1;
3008 if (c) {
3009 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3010 }
3011 }
3012 //printf("load_assemble: c=%d\n",c);
3013 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3014 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
3015 // could be FIFO, must perform the read
3016 // ||dummy read
3017 assem_debug("(forced read)\n");
3018 tl = get_reg_temp(i_regs->regmap); // may be == addr
3019 assert(tl>=0);
3020 }
3021 assert(addr >= 0);
3022 if(tl>=0) {
3023 //printf("load_assemble: c=%d\n",c);
3024 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3025 reglist&=~(1<<tl);
3026 if(!c) {
3027 #ifdef R29_HACK
3028 // Strmnnrmn's speed hack
3029 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3030 #endif
3031 {
3032 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3033 &offset_reg, &fastio_reg_override, ccadj_);
3034 }
3035 }
3036 else if (ram_offset && memtarget) {
3037 offset_reg = get_ro_reg(i_regs, 0);
3038 }
3039 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
3040 switch (dops[i].opcode) {
3041 case 0x20: // LB
3042 if(!c||memtarget) {
3043 if(!dummy) {
3044 int a = addr;
3045 if (fastio_reg_override >= 0)
3046 a = fastio_reg_override;
3047
3048 if (offset_reg >= 0)
3049 emit_ldrsb_dualindexed(offset_reg, a, tl);
3050 else
3051 emit_movsbl_indexed(0, a, tl);
3052 }
3053 if(jaddr)
3054 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3055 }
3056 else
3057 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3058 break;
3059 case 0x21: // LH
3060 if(!c||memtarget) {
3061 if(!dummy) {
3062 int a = addr;
3063 if (fastio_reg_override >= 0)
3064 a = fastio_reg_override;
3065 if (offset_reg >= 0)
3066 emit_ldrsh_dualindexed(offset_reg, a, tl);
3067 else
3068 emit_movswl_indexed(0, a, tl);
3069 }
3070 if(jaddr)
3071 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3072 }
3073 else
3074 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3075 break;
3076 case 0x23: // LW
3077 if(!c||memtarget) {
3078 if(!dummy) {
3079 int a = addr;
3080 if (fastio_reg_override >= 0)
3081 a = fastio_reg_override;
3082 do_load_word(a, tl, offset_reg);
3083 }
3084 if(jaddr)
3085 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3086 }
3087 else
3088 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3089 break;
3090 case 0x24: // LBU
3091 if(!c||memtarget) {
3092 if(!dummy) {
3093 int a = addr;
3094 if (fastio_reg_override >= 0)
3095 a = fastio_reg_override;
3096
3097 if (offset_reg >= 0)
3098 emit_ldrb_dualindexed(offset_reg, a, tl);
3099 else
3100 emit_movzbl_indexed(0, a, tl);
3101 }
3102 if(jaddr)
3103 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3104 }
3105 else
3106 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3107 break;
3108 case 0x25: // LHU
3109 if(!c||memtarget) {
3110 if(!dummy) {
3111 int a = addr;
3112 if (fastio_reg_override >= 0)
3113 a = fastio_reg_override;
3114 if (offset_reg >= 0)
3115 emit_ldrh_dualindexed(offset_reg, a, tl);
3116 else
3117 emit_movzwl_indexed(0, a, tl);
3118 }
3119 if(jaddr)
3120 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3121 }
3122 else
3123 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3124 break;
3125 default:
3126 assert(0);
3127 }
3128 } // tl >= 0
3129 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3130 host_tempreg_release();
3131}
3132
3133#ifndef loadlr_assemble
3134static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3135{
3136 int addr = cinfo[i].addr;
3137 int s,tl,temp,temp2;
3138 int offset;
3139 void *jaddr=0;
3140 int memtarget=0,c=0;
3141 int offset_reg = -1;
3142 int fastio_reg_override = -1;
3143 u_int reglist=get_host_reglist(i_regs->regmap);
3144 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3145 s=get_reg(i_regs->regmap,dops[i].rs1);
3146 temp=get_reg_temp(i_regs->regmap);
3147 temp2=get_reg(i_regs->regmap,FTEMP);
3148 offset=cinfo[i].imm;
3149 reglist|=1<<temp;
3150 assert(addr >= 0);
3151 if(s>=0) {
3152 c=(i_regs->wasconst>>s)&1;
3153 if(c) {
3154 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3155 }
3156 }
3157 if(!c) {
3158 emit_shlimm(addr,3,temp);
3159 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3160 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3161 }else{
3162 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3163 }
3164 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3165 &offset_reg, &fastio_reg_override, ccadj_);
3166 }
3167 else {
3168 if (ram_offset && memtarget) {
3169 offset_reg = get_ro_reg(i_regs, 0);
3170 }
3171 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3172 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3173 }else{
3174 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3175 }
3176 }
3177 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3178 if(!c||memtarget) {
3179 int a = temp2;
3180 if (fastio_reg_override >= 0)
3181 a = fastio_reg_override;
3182 do_load_word(a, temp2, offset_reg);
3183 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3184 host_tempreg_release();
3185 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3186 }
3187 else
3188 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3189 if(dops[i].rt1) {
3190 assert(tl>=0);
3191 emit_andimm(temp,24,temp);
3192 if (dops[i].opcode==0x22) // LWL
3193 emit_xorimm(temp,24,temp);
3194 host_tempreg_acquire();
3195 emit_movimm(-1,HOST_TEMPREG);
3196 if (dops[i].opcode==0x26) {
3197 emit_shr(temp2,temp,temp2);
3198 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3199 }else{
3200 emit_shl(temp2,temp,temp2);
3201 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3202 }
3203 host_tempreg_release();
3204 emit_or(temp2,tl,tl);
3205 }
3206 //emit_storereg(dops[i].rt1,tl); // DEBUG
3207 }
3208 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3209 assert(0);
3210 }
3211}
3212#endif
3213
3214static void do_invstub(int n)
3215{
3216 literal_pool(20);
3217 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
3218 u_int reglist = stubs[n].a;
3219 u_int addrr = stubs[n].b;
3220 int ofs_start = stubs[n].c;
3221 int ofs_end = stubs[n].d;
3222 int len = ofs_end - ofs_start;
3223 u_int rightr = 0;
3224
3225 set_jump_target(stubs[n].addr, out);
3226 save_regs(reglist);
3227 if (addrr != 0 || ofs_start != 0)
3228 emit_addimm(addrr, ofs_start, 0);
3229 emit_readword(&inv_code_start, 2);
3230 emit_readword(&inv_code_end, 3);
3231 if (len != 0)
3232 emit_addimm(0, len + 4, (rightr = 1));
3233 emit_cmp(0, 2);
3234 emit_cmpcs(3, rightr);
3235 void *jaddr = out;
3236 emit_jc(0);
3237 void *func = (len != 0)
3238 ? (void *)ndrc_write_invalidate_many
3239 : (void *)ndrc_write_invalidate_one;
3240 emit_far_call(func);
3241 set_jump_target(jaddr, out);
3242 restore_regs(reglist);
3243 emit_jmp(stubs[n].retaddr);
3244}
3245
3246static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3247{
3248 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3249 return;
3250 // this can't be used any more since we started to check exact
3251 // block boundaries in invalidate_range()
3252 //if (i_regs->waswritten & (1<<dops[i].rs1))
3253 // return;
3254 // (naively) assume nobody will run code from stack
3255 if (dops[i].rs1 == 29)
3256 return;
3257
3258 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
3259 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
3260 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
3261 return;
3262 for (j = i - 1; j >= 0; j--) {
3263 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
3264 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
3265 break;
3266 count++;
3267 if (imm_min > cinfo[j].imm)
3268 imm_min = cinfo[j].imm;
3269 if (imm_max < cinfo[j].imm)
3270 imm_max = cinfo[j].imm;
3271 }
3272#if defined(HOST_IMM8)
3273 int ir = get_reg(i_regs->regmap, INVCP);
3274 assert(ir >= 0);
3275 host_tempreg_acquire();
3276 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3277#else
3278 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3279 #error not handled
3280#endif
3281#ifdef INVALIDATE_USE_COND_CALL
3282 if (count == 1) {
3283 emit_cmpimm(HOST_TEMPREG, 1);
3284 emit_callne(invalidate_addr_reg[addr]);
3285 host_tempreg_release();
3286 return;
3287 }
3288#endif
3289 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3290 host_tempreg_release();
3291 imm_min -= cinfo[i].imm;
3292 imm_max -= cinfo[i].imm;
3293 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
3294 addr, imm_min, imm_max, i);
3295}
3296
3297// determines if code overwrite checking is needed only
3298// (also true non-existent 0x20000000 mirror that shouldn't matter)
3299#define is_ram_addr(a) !((a) & 0x5f800000)
3300
3301static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3302{
3303 int s,tl;
3304 int addr = cinfo[i].addr;
3305 int offset;
3306 void *jaddr=0;
3307 enum stub_type type=0;
3308 int memtarget=0,c=0;
3309 int offset_reg = -1;
3310 int fastio_reg_override = -1;
3311 u_int addr_const = ~0;
3312 u_int reglist=get_host_reglist(i_regs->regmap);
3313 tl=get_reg(i_regs->regmap,dops[i].rs2);
3314 s=get_reg(i_regs->regmap,dops[i].rs1);
3315 offset=cinfo[i].imm;
3316 if(s>=0) {
3317 c=(i_regs->wasconst>>s)&1;
3318 if (c) {
3319 addr_const = constmap[i][s] + offset;
3320 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3321 }
3322 }
3323 assert(tl>=0);
3324 assert(addr >= 0);
3325 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3326 reglist |= 1u << addr;
3327 if (!c) {
3328 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3329 &offset_reg, &fastio_reg_override, ccadj_);
3330 }
3331 else if (ram_offset && memtarget) {
3332 offset_reg = get_ro_reg(i_regs, 0);
3333 }
3334
3335 switch (dops[i].opcode) {
3336 case 0x28: // SB
3337 if(!c||memtarget) {
3338 int a = addr;
3339 if (fastio_reg_override >= 0)
3340 a = fastio_reg_override;
3341 do_store_byte(a, tl, offset_reg);
3342 }
3343 type = STOREB_STUB;
3344 break;
3345 case 0x29: // SH
3346 if(!c||memtarget) {
3347 int a = addr;
3348 if (fastio_reg_override >= 0)
3349 a = fastio_reg_override;
3350 do_store_hword(a, 0, tl, offset_reg, 1);
3351 }
3352 type = STOREH_STUB;
3353 break;
3354 case 0x2B: // SW
3355 if(!c||memtarget) {
3356 int a = addr;
3357 if (fastio_reg_override >= 0)
3358 a = fastio_reg_override;
3359 do_store_word(a, 0, tl, offset_reg, 1);
3360 }
3361 type = STOREW_STUB;
3362 break;
3363 default:
3364 assert(0);
3365 }
3366 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3367 host_tempreg_release();
3368 if (jaddr) {
3369 // PCSX store handlers don't check invcode again
3370 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3371 }
3372 if (!c || is_ram_addr(addr_const))
3373 do_store_smc_check(i, i_regs, reglist, addr);
3374 if (c && !memtarget)
3375 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
3376 // basic current block modification detection..
3377 // not looking back as that should be in mips cache already
3378 // (see Spyro2 title->attract mode)
3379 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3380 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
3381 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3382 if(i_regs->regmap==regs[i].regmap) {
3383 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3384 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3385 emit_movimm(start+i*4+4,0);
3386 emit_writeword(0,&pcaddr);
3387 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3388 emit_far_call(ndrc_get_addr_ht);
3389 emit_jmpreg(0);
3390 }
3391 }
3392}
3393
3394static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3395{
3396 int addr = cinfo[i].addr;
3397 int s,tl;
3398 int offset;
3399 void *jaddr=0;
3400 void *case1, *case23, *case3;
3401 void *done0, *done1, *done2;
3402 int memtarget=0,c=0;
3403 int offset_reg = -1;
3404 u_int addr_const = ~0;
3405 u_int reglist = get_host_reglist(i_regs->regmap);
3406 tl=get_reg(i_regs->regmap,dops[i].rs2);
3407 s=get_reg(i_regs->regmap,dops[i].rs1);
3408 offset=cinfo[i].imm;
3409 if(s>=0) {
3410 c = (i_regs->isconst >> s) & 1;
3411 if (c) {
3412 addr_const = constmap[i][s] + offset;
3413 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3414 }
3415 }
3416 assert(tl>=0);
3417 assert(addr >= 0);
3418 reglist |= 1u << addr;
3419 if(!c) {
3420 emit_cmpimm(addr, RAM_SIZE);
3421 jaddr=out;
3422 emit_jno(0);
3423 }
3424 else
3425 {
3426 if(!memtarget||!dops[i].rs1) {
3427 jaddr=out;
3428 emit_jmp(0);
3429 }
3430 }
3431 if (ram_offset)
3432 offset_reg = get_ro_reg(i_regs, 0);
3433
3434 emit_testimm(addr,2);
3435 case23=out;
3436 emit_jne(0);
3437 emit_testimm(addr,1);
3438 case1=out;
3439 emit_jne(0);
3440 // 0
3441 if (dops[i].opcode == 0x2A) { // SWL
3442 // Write msb into least significant byte
3443 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3444 do_store_byte(addr, tl, offset_reg);
3445 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3446 }
3447 else if (dops[i].opcode == 0x2E) { // SWR
3448 // Write entire word
3449 do_store_word(addr, 0, tl, offset_reg, 1);
3450 }
3451 done0 = out;
3452 emit_jmp(0);
3453 // 1
3454 set_jump_target(case1, out);
3455 if (dops[i].opcode == 0x2A) { // SWL
3456 // Write two msb into two least significant bytes
3457 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3458 do_store_hword(addr, -1, tl, offset_reg, 1);
3459 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3460 }
3461 else if (dops[i].opcode == 0x2E) { // SWR
3462 // Write 3 lsb into three most significant bytes
3463 do_store_byte(addr, tl, offset_reg);
3464 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3465 do_store_hword(addr, 1, tl, offset_reg, 1);
3466 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3467 }
3468 done1=out;
3469 emit_jmp(0);
3470 // 2,3
3471 set_jump_target(case23, out);
3472 emit_testimm(addr,1);
3473 case3 = out;
3474 emit_jne(0);
3475 // 2
3476 if (dops[i].opcode==0x2A) { // SWL
3477 // Write 3 msb into three least significant bytes
3478 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3479 do_store_hword(addr, -2, tl, offset_reg, 1);
3480 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3481 do_store_byte(addr, tl, offset_reg);
3482 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3483 }
3484 else if (dops[i].opcode == 0x2E) { // SWR
3485 // Write two lsb into two most significant bytes
3486 do_store_hword(addr, 0, tl, offset_reg, 1);
3487 }
3488 done2 = out;
3489 emit_jmp(0);
3490 // 3
3491 set_jump_target(case3, out);
3492 if (dops[i].opcode == 0x2A) { // SWL
3493 do_store_word(addr, -3, tl, offset_reg, 1);
3494 }
3495 else if (dops[i].opcode == 0x2E) { // SWR
3496 do_store_byte(addr, tl, offset_reg);
3497 }
3498 set_jump_target(done0, out);
3499 set_jump_target(done1, out);
3500 set_jump_target(done2, out);
3501 if (offset_reg == HOST_TEMPREG)
3502 host_tempreg_release();
3503 if (!c || !memtarget)
3504 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3505 if (!c || is_ram_addr(addr_const))
3506 do_store_smc_check(i, i_regs, reglist, addr);
3507}
3508
3509static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3510{
3511 if(dops[i].opcode2==0) // MFC0
3512 {
3513 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
3514 u_int copr=(source[i]>>11)&0x1f;
3515 if(t>=0&&dops[i].rt1!=0) {
3516 emit_readword(&reg_cop0[copr],t);
3517 }
3518 }
3519 else if(dops[i].opcode2==4) // MTC0
3520 {
3521 int s = get_reg(i_regs->regmap, dops[i].rs1);
3522 int cc = get_reg(i_regs->regmap, CCREG);
3523 char copr=(source[i]>>11)&0x1f;
3524 assert(s>=0);
3525 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3526 if (copr == 12 || copr == 13) {
3527 emit_readword(&last_count,HOST_TEMPREG);
3528 if (cc != HOST_CCREG)
3529 emit_loadreg(CCREG, HOST_CCREG);
3530 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3531 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3532 emit_writeword(HOST_CCREG, &psxRegs.cycle);
3533 if (is_delayslot) {
3534 // burn cycles to cause cc_interrupt, which will
3535 // reschedule next_interupt. Relies on CCREG from above.
3536 assem_debug("MTC0 DS %d\n", copr);
3537 emit_writeword(HOST_CCREG,&last_count);
3538 emit_movimm(0,HOST_CCREG);
3539 emit_storereg(CCREG,HOST_CCREG);
3540 emit_loadreg(dops[i].rs1,1);
3541 emit_movimm(copr,0);
3542 emit_far_call(pcsx_mtc0_ds);
3543 emit_loadreg(dops[i].rs1,s);
3544 return;
3545 }
3546 emit_movimm(start+i*4+4,HOST_TEMPREG);
3547 emit_writeword(HOST_TEMPREG,&pcaddr);
3548 emit_movimm(0,HOST_TEMPREG);
3549 emit_writeword(HOST_TEMPREG,&pending_exception);
3550 }
3551 if( s != 1)
3552 emit_mov(s, 1);
3553 emit_movimm(copr, 0);
3554 emit_far_call(pcsx_mtc0);
3555 if (copr == 12 || copr == 13) {
3556 emit_readword(&psxRegs.cycle,HOST_CCREG);
3557 emit_readword(&last_count,HOST_TEMPREG);
3558 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3559 //emit_writeword(HOST_TEMPREG,&last_count);
3560 assert(!is_delayslot);
3561 emit_readword(&pending_exception,HOST_TEMPREG);
3562 emit_test(HOST_TEMPREG,HOST_TEMPREG);
3563 void *jaddr = out;
3564 emit_jeq(0);
3565 emit_readword(&pcaddr, 0);
3566 emit_far_call(ndrc_get_addr_ht);
3567 emit_jmpreg(0);
3568 set_jump_target(jaddr, out);
3569 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3570 if (cc != HOST_CCREG)
3571 emit_storereg(CCREG, HOST_CCREG);
3572 }
3573 emit_loadreg(dops[i].rs1,s);
3574 }
3575}
3576
3577static void rfe_assemble(int i, const struct regstat *i_regs)
3578{
3579 emit_readword(&psxRegs.CP0.n.SR, 0);
3580 emit_andimm(0, 0x3c, 1);
3581 emit_andimm(0, ~0xf, 0);
3582 emit_orrshr_imm(1, 2, 0);
3583 emit_writeword(0, &psxRegs.CP0.n.SR);
3584}
3585
3586static int cop2_is_stalling_op(int i, int *cycles)
3587{
3588 if (dops[i].opcode == 0x3a) { // SWC2
3589 *cycles = 0;
3590 return 1;
3591 }
3592 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3593 *cycles = 0;
3594 return 1;
3595 }
3596 if (dops[i].itype == C2OP) {
3597 *cycles = gte_cycletab[source[i] & 0x3f];
3598 return 1;
3599 }
3600 // ... what about MTC2/CTC2/LWC2?
3601 return 0;
3602}
3603
3604#if 0
3605static void log_gte_stall(int stall, u_int cycle)
3606{
3607 if ((u_int)stall <= 44)
3608 printf("x stall %2d %u\n", stall, cycle + last_count);
3609}
3610
3611static void emit_log_gte_stall(int i, int stall, u_int reglist)
3612{
3613 save_regs(reglist);
3614 if (stall > 0)
3615 emit_movimm(stall, 0);
3616 else
3617 emit_mov(HOST_TEMPREG, 0);
3618 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3619 emit_far_call(log_gte_stall);
3620 restore_regs(reglist);
3621}
3622#endif
3623
3624static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3625{
3626 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3627 int rtmp = reglist_find_free(reglist);
3628
3629 if (HACK_ENABLED(NDHACK_NO_STALLS))
3630 return;
3631 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3632 // happens occasionally... cc evicted? Don't bother then
3633 //printf("no cc %08x\n", start + i*4);
3634 return;
3635 }
3636 if (!dops[i].bt) {
3637 for (j = i - 1; j >= 0; j--) {
3638 //if (dops[j].is_ds) break;
3639 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3640 break;
3641 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
3642 break;
3643 }
3644 j = max(j, 0);
3645 }
3646 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
3647 if (other_gte_op_cycles >= 0)
3648 stall = other_gte_op_cycles - cycles_passed;
3649 else if (cycles_passed >= 44)
3650 stall = 0; // can't stall
3651 if (stall == -MAXBLOCK && rtmp >= 0) {
3652 // unknown stall, do the expensive runtime check
3653 assem_debug("; cop2_do_stall_check\n");
3654#if 0 // too slow
3655 save_regs(reglist);
3656 emit_movimm(gte_cycletab[op], 0);
3657 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3658 emit_far_call(call_gteStall);
3659 restore_regs(reglist);
3660#else
3661 host_tempreg_acquire();
3662 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3663 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3664 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3665 emit_cmpimm(HOST_TEMPREG, 44);
3666 emit_cmovb_reg(rtmp, HOST_CCREG);
3667 //emit_log_gte_stall(i, 0, reglist);
3668 host_tempreg_release();
3669#endif
3670 }
3671 else if (stall > 0) {
3672 //emit_log_gte_stall(i, stall, reglist);
3673 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3674 }
3675
3676 // save gteBusyCycle, if needed
3677 if (gte_cycletab[op] == 0)
3678 return;
3679 other_gte_op_cycles = -1;
3680 for (j = i + 1; j < slen; j++) {
3681 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3682 break;
3683 if (dops[j].is_jump) {
3684 // check ds
3685 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3686 j++;
3687 break;
3688 }
3689 }
3690 if (other_gte_op_cycles >= 0)
3691 // will handle stall when assembling that op
3692 return;
3693 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
3694 if (cycles_passed >= 44)
3695 return;
3696 assem_debug("; save gteBusyCycle\n");
3697 host_tempreg_acquire();
3698#if 0
3699 emit_readword(&last_count, HOST_TEMPREG);
3700 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3701 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
3702 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3703 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3704#else
3705 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
3706 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3707#endif
3708 host_tempreg_release();
3709}
3710
3711static int is_mflohi(int i)
3712{
3713 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3714}
3715
3716static int check_multdiv(int i, int *cycles)
3717{
3718 if (dops[i].itype != MULTDIV)
3719 return 0;
3720 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3721 *cycles = 11; // approx from 7 11 14
3722 else
3723 *cycles = 37;
3724 return 1;
3725}
3726
3727static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3728{
3729 int j, found = 0, c = 0;
3730 if (HACK_ENABLED(NDHACK_NO_STALLS))
3731 return;
3732 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3733 // happens occasionally... cc evicted? Don't bother then
3734 return;
3735 }
3736 for (j = i + 1; j < slen; j++) {
3737 if (dops[j].bt)
3738 break;
3739 if ((found = is_mflohi(j)))
3740 break;
3741 if (dops[j].is_jump) {
3742 // check ds
3743 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3744 j++;
3745 break;
3746 }
3747 }
3748 if (found)
3749 // handle all in multdiv_do_stall()
3750 return;
3751 check_multdiv(i, &c);
3752 assert(c > 0);
3753 assem_debug("; muldiv prepare stall %d\n", c);
3754 host_tempreg_acquire();
3755 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3756 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3757 host_tempreg_release();
3758}
3759
3760static void multdiv_do_stall(int i, const struct regstat *i_regs)
3761{
3762 int j, known_cycles = 0;
3763 u_int reglist = get_host_reglist(i_regs->regmap);
3764 int rtmp = get_reg_temp(i_regs->regmap);
3765 if (rtmp < 0)
3766 rtmp = reglist_find_free(reglist);
3767 if (HACK_ENABLED(NDHACK_NO_STALLS))
3768 return;
3769 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3770 // happens occasionally... cc evicted? Don't bother then
3771 //printf("no cc/rtmp %08x\n", start + i*4);
3772 return;
3773 }
3774 if (!dops[i].bt) {
3775 for (j = i - 1; j >= 0; j--) {
3776 if (dops[j].is_ds) break;
3777 if (check_multdiv(j, &known_cycles))
3778 break;
3779 if (is_mflohi(j))
3780 // already handled by this op
3781 return;
3782 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
3783 break;
3784 }
3785 j = max(j, 0);
3786 }
3787 if (known_cycles > 0) {
3788 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
3789 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3790 if (known_cycles > 0)
3791 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3792 return;
3793 }
3794 assem_debug("; muldiv stall unresolved\n");
3795 host_tempreg_acquire();
3796 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3797 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3798 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3799 emit_cmpimm(HOST_TEMPREG, 37);
3800 emit_cmovb_reg(rtmp, HOST_CCREG);
3801 //emit_log_gte_stall(i, 0, reglist);
3802 host_tempreg_release();
3803}
3804
3805static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3806{
3807 switch (copr) {
3808 case 1:
3809 case 3:
3810 case 5:
3811 case 8:
3812 case 9:
3813 case 10:
3814 case 11:
3815 emit_readword(&reg_cop2d[copr],tl);
3816 emit_signextend16(tl,tl);
3817 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3818 break;
3819 case 7:
3820 case 16:
3821 case 17:
3822 case 18:
3823 case 19:
3824 emit_readword(&reg_cop2d[copr],tl);
3825 emit_andimm(tl,0xffff,tl);
3826 emit_writeword(tl,&reg_cop2d[copr]);
3827 break;
3828 case 15:
3829 emit_readword(&reg_cop2d[14],tl); // SXY2
3830 emit_writeword(tl,&reg_cop2d[copr]);
3831 break;
3832 case 28:
3833 case 29:
3834 c2op_mfc2_29_assemble(tl,temp);
3835 break;
3836 default:
3837 emit_readword(&reg_cop2d[copr],tl);
3838 break;
3839 }
3840}
3841
3842static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3843{
3844 switch (copr) {
3845 case 15:
3846 emit_readword(&reg_cop2d[13],temp); // SXY1
3847 emit_writeword(sl,&reg_cop2d[copr]);
3848 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3849 emit_readword(&reg_cop2d[14],temp); // SXY2
3850 emit_writeword(sl,&reg_cop2d[14]);
3851 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3852 break;
3853 case 28:
3854 emit_andimm(sl,0x001f,temp);
3855 emit_shlimm(temp,7,temp);
3856 emit_writeword(temp,&reg_cop2d[9]);
3857 emit_andimm(sl,0x03e0,temp);
3858 emit_shlimm(temp,2,temp);
3859 emit_writeword(temp,&reg_cop2d[10]);
3860 emit_andimm(sl,0x7c00,temp);
3861 emit_shrimm(temp,3,temp);
3862 emit_writeword(temp,&reg_cop2d[11]);
3863 emit_writeword(sl,&reg_cop2d[28]);
3864 break;
3865 case 30:
3866 emit_xorsar_imm(sl,sl,31,temp);
3867#if defined(HAVE_ARMV5) || defined(__aarch64__)
3868 emit_clz(temp,temp);
3869#else
3870 emit_movs(temp,HOST_TEMPREG);
3871 emit_movimm(0,temp);
3872 emit_jeq((int)out+4*4);
3873 emit_addpl_imm(temp,1,temp);
3874 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3875 emit_jns((int)out-2*4);
3876#endif
3877 emit_writeword(sl,&reg_cop2d[30]);
3878 emit_writeword(temp,&reg_cop2d[31]);
3879 break;
3880 case 31:
3881 break;
3882 default:
3883 emit_writeword(sl,&reg_cop2d[copr]);
3884 break;
3885 }
3886}
3887
3888static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3889{
3890 int s,tl;
3891 int ar;
3892 int offset;
3893 int memtarget=0,c=0;
3894 void *jaddr2=NULL;
3895 enum stub_type type;
3896 int offset_reg = -1;
3897 int fastio_reg_override = -1;
3898 u_int addr_const = ~0;
3899 u_int reglist=get_host_reglist(i_regs->regmap);
3900 u_int copr=(source[i]>>16)&0x1f;
3901 s=get_reg(i_regs->regmap,dops[i].rs1);
3902 tl=get_reg(i_regs->regmap,FTEMP);
3903 offset=cinfo[i].imm;
3904 assert(tl>=0);
3905
3906 if(i_regs->regmap[HOST_CCREG]==CCREG)
3907 reglist&=~(1<<HOST_CCREG);
3908
3909 // get the address
3910 ar = cinfo[i].addr;
3911 assert(ar >= 0);
3912 if (dops[i].opcode==0x3a) { // SWC2
3913 reglist |= 1<<ar;
3914 }
3915 if (s >= 0) {
3916 c = (i_regs->isconst >> s) & 1;
3917 if (c) {
3918 addr_const = constmap[i][s] + offset;
3919 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3920 }
3921 }
3922
3923 cop2_do_stall_check(0, i, i_regs, reglist);
3924
3925 if (dops[i].opcode==0x3a) { // SWC2
3926 cop2_get_dreg(copr,tl,-1);
3927 type=STOREW_STUB;
3928 }
3929 else
3930 type=LOADW_STUB;
3931
3932 if(c&&!memtarget) {
3933 jaddr2=out;
3934 emit_jmp(0); // inline_readstub/inline_writestub?
3935 }
3936 else {
3937 if(!c) {
3938 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3939 &offset_reg, &fastio_reg_override, ccadj_);
3940 }
3941 else if (ram_offset && memtarget) {
3942 offset_reg = get_ro_reg(i_regs, 0);
3943 }
3944 switch (dops[i].opcode) {
3945 case 0x32: { // LWC2
3946 int a = ar;
3947 if (fastio_reg_override >= 0)
3948 a = fastio_reg_override;
3949 do_load_word(a, tl, offset_reg);
3950 break;
3951 }
3952 case 0x3a: { // SWC2
3953 #ifdef DESTRUCTIVE_SHIFT
3954 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3955 #endif
3956 int a = ar;
3957 if (fastio_reg_override >= 0)
3958 a = fastio_reg_override;
3959 do_store_word(a, 0, tl, offset_reg, 1);
3960 break;
3961 }
3962 default:
3963 assert(0);
3964 }
3965 }
3966 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3967 host_tempreg_release();
3968 if(jaddr2)
3969 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3970 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
3971 do_store_smc_check(i, i_regs, reglist, ar);
3972 if (dops[i].opcode == 0x32) { // LWC2
3973 host_tempreg_acquire();
3974 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3975 host_tempreg_release();
3976 }
3977}
3978
3979static void cop2_assemble(int i, const struct regstat *i_regs)
3980{
3981 u_int copr = (source[i]>>11) & 0x1f;
3982 signed char temp = get_reg_temp(i_regs->regmap);
3983
3984 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3985 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3986 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3987 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3988 reglist = reglist_exclude(reglist, tl, -1);
3989 }
3990 cop2_do_stall_check(0, i, i_regs, reglist);
3991 }
3992 if (dops[i].opcode2==0) { // MFC2
3993 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3994 if(tl>=0&&dops[i].rt1!=0)
3995 cop2_get_dreg(copr,tl,temp);
3996 }
3997 else if (dops[i].opcode2==4) { // MTC2
3998 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3999 cop2_put_dreg(copr,sl,temp);
4000 }
4001 else if (dops[i].opcode2==2) // CFC2
4002 {
4003 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4004 if(tl>=0&&dops[i].rt1!=0)
4005 emit_readword(&reg_cop2c[copr],tl);
4006 }
4007 else if (dops[i].opcode2==6) // CTC2
4008 {
4009 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4010 switch(copr) {
4011 case 4:
4012 case 12:
4013 case 20:
4014 case 26:
4015 case 27:
4016 case 29:
4017 case 30:
4018 emit_signextend16(sl,temp);
4019 break;
4020 case 31:
4021 c2op_ctc2_31_assemble(sl,temp);
4022 break;
4023 default:
4024 temp=sl;
4025 break;
4026 }
4027 emit_writeword(temp,&reg_cop2c[copr]);
4028 assert(sl>=0);
4029 }
4030}
4031
4032static void do_unalignedwritestub(int n)
4033{
4034 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4035 literal_pool(256);
4036 set_jump_target(stubs[n].addr, out);
4037
4038 int i=stubs[n].a;
4039 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4040 int addr=stubs[n].b;
4041 u_int reglist=stubs[n].e;
4042 signed char *i_regmap=i_regs->regmap;
4043 int temp2=get_reg(i_regmap,FTEMP);
4044 int rt;
4045 rt=get_reg(i_regmap,dops[i].rs2);
4046 assert(rt>=0);
4047 assert(addr>=0);
4048 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
4049 reglist|=(1<<addr);
4050 reglist&=~(1<<temp2);
4051
4052 // don't bother with it and call write handler
4053 save_regs(reglist);
4054 pass_args(addr,rt);
4055 int cc=get_reg(i_regmap,CCREG);
4056 if(cc<0)
4057 emit_loadreg(CCREG,2);
4058 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
4059 emit_movimm(start + i*4,3);
4060 emit_writeword(3,&psxRegs.pc);
4061 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
4062 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
4063 if(cc<0)
4064 emit_storereg(CCREG,2);
4065 restore_regs(reglist);
4066 emit_jmp(stubs[n].retaddr); // return address
4067}
4068
4069static void do_overflowstub(int n)
4070{
4071 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4072 literal_pool(24);
4073 int i = stubs[n].a;
4074 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4075 int ccadj = stubs[n].d;
4076 set_jump_target(stubs[n].addr, out);
4077 wb_dirtys(regs[i].regmap, regs[i].dirty);
4078 exception_assemble(i, i_regs, ccadj);
4079}
4080
4081static void do_alignmentstub(int n)
4082{
4083 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4084 literal_pool(24);
4085 int i = stubs[n].a;
4086 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4087 int ccadj = stubs[n].d;
4088 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4089 int cause = (dops[i].opcode & 3) << 28;
4090 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4091 set_jump_target(stubs[n].addr, out);
4092 wb_dirtys(regs[i].regmap, regs[i].dirty);
4093 if (stubs[n].b != 1)
4094 emit_mov(stubs[n].b, 1); // faulting address
4095 emit_movimm(cause, 0);
4096 exception_assemble(i, i_regs, ccadj);
4097}
4098
4099#ifndef multdiv_assemble
4100void multdiv_assemble(int i,struct regstat *i_regs)
4101{
4102 printf("Need multdiv_assemble for this architecture.\n");
4103 abort();
4104}
4105#endif
4106
4107static void mov_assemble(int i, const struct regstat *i_regs)
4108{
4109 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4110 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4111 if(dops[i].rt1) {
4112 signed char sl,tl;
4113 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4114 //assert(tl>=0);
4115 if(tl>=0) {
4116 sl=get_reg(i_regs->regmap,dops[i].rs1);
4117 if(sl>=0) emit_mov(sl,tl);
4118 else emit_loadreg(dops[i].rs1,tl);
4119 }
4120 }
4121 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
4122 multdiv_do_stall(i, i_regs);
4123}
4124
4125// call interpreter, exception handler, things that change pc/regs/cycles ...
4126static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
4127{
4128 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4129 assert(ccreg==HOST_CCREG);
4130 assert(!is_delayslot);
4131 (void)ccreg;
4132
4133 emit_movimm(pc,3); // Get PC
4134 emit_readword(&last_count,2);
4135 emit_writeword(3,&psxRegs.pc);
4136 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4137 emit_add(2,HOST_CCREG,2);
4138 emit_writeword(2,&psxRegs.cycle);
4139 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
4140 emit_far_call(func);
4141 emit_far_jump(jump_to_new_pc);
4142}
4143
4144static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
4145{
4146 // 'break' tends to be littered around to catch things like
4147 // division by 0 and is almost never executed, so don't emit much code here
4148 void *func;
4149 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4150 func = is_delayslot ? jump_overflow_ds : jump_overflow;
4151 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4152 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
4153 else if (dops[i].opcode2 == 0x0C)
4154 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4155 else
4156 func = is_delayslot ? jump_break_ds : jump_break;
4157 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4158 emit_loadreg(CCREG, HOST_CCREG);
4159 emit_movimm(start + i*4, 2); // pc
4160 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4161 emit_far_jump(func);
4162}
4163
4164static void hlecall_bad()
4165{
4166 assert(0);
4167}
4168
4169static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4170{
4171 void *hlefunc = hlecall_bad;
4172 uint32_t hleCode = source[i] & 0x03ffffff;
4173 if (hleCode < ARRAY_SIZE(psxHLEt))
4174 hlefunc = psxHLEt[hleCode];
4175
4176 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4177}
4178
4179static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4180{
4181 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4182}
4183
4184static void speculate_mov(int rs,int rt)
4185{
4186 if(rt!=0) {
4187 smrv_strong_next|=1<<rt;
4188 smrv[rt]=smrv[rs];
4189 }
4190}
4191
4192static void speculate_mov_weak(int rs,int rt)
4193{
4194 if(rt!=0) {
4195 smrv_weak_next|=1<<rt;
4196 smrv[rt]=smrv[rs];
4197 }
4198}
4199
4200static void speculate_register_values(int i)
4201{
4202 if(i==0) {
4203 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4204 // gp,sp are likely to stay the same throughout the block
4205 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4206 smrv_weak_next=~smrv_strong_next;
4207 //printf(" llr %08x\n", smrv[4]);
4208 }
4209 smrv_strong=smrv_strong_next;
4210 smrv_weak=smrv_weak_next;
4211 switch(dops[i].itype) {
4212 case ALU:
4213 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4214 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4215 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4216 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4217 else {
4218 smrv_strong_next&=~(1<<dops[i].rt1);
4219 smrv_weak_next&=~(1<<dops[i].rt1);
4220 }
4221 break;
4222 case SHIFTIMM:
4223 smrv_strong_next&=~(1<<dops[i].rt1);
4224 smrv_weak_next&=~(1<<dops[i].rt1);
4225 // fallthrough
4226 case IMM16:
4227 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4228 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4229 u_int value;
4230 if(hr>=0) {
4231 if(get_final_value(hr,i,&value))
4232 smrv[dops[i].rt1]=value;
4233 else smrv[dops[i].rt1]=constmap[i][hr];
4234 smrv_strong_next|=1<<dops[i].rt1;
4235 }
4236 }
4237 else {
4238 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4239 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4240 }
4241 break;
4242 case LOAD:
4243 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4244 // special case for BIOS
4245 smrv[dops[i].rt1]=0xa0000000;
4246 smrv_strong_next|=1<<dops[i].rt1;
4247 break;
4248 }
4249 // fallthrough
4250 case SHIFT:
4251 case LOADLR:
4252 case MOV:
4253 smrv_strong_next&=~(1<<dops[i].rt1);
4254 smrv_weak_next&=~(1<<dops[i].rt1);
4255 break;
4256 case COP0:
4257 case COP2:
4258 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4259 smrv_strong_next&=~(1<<dops[i].rt1);
4260 smrv_weak_next&=~(1<<dops[i].rt1);
4261 }
4262 break;
4263 case C2LS:
4264 if (dops[i].opcode==0x32) { // LWC2
4265 smrv_strong_next&=~(1<<dops[i].rt1);
4266 smrv_weak_next&=~(1<<dops[i].rt1);
4267 }
4268 break;
4269 }
4270#if 0
4271 int r=4;
4272 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4273 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4274#endif
4275}
4276
4277static void ujump_assemble(int i, const struct regstat *i_regs);
4278static void rjump_assemble(int i, const struct regstat *i_regs);
4279static void cjump_assemble(int i, const struct regstat *i_regs);
4280static void sjump_assemble(int i, const struct regstat *i_regs);
4281
4282static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4283{
4284 int ds = 0;
4285 switch (dops[i].itype) {
4286 case ALU:
4287 alu_assemble(i, i_regs, ccadj_);
4288 break;
4289 case IMM16:
4290 imm16_assemble(i, i_regs, ccadj_);
4291 break;
4292 case SHIFT:
4293 shift_assemble(i, i_regs);
4294 break;
4295 case SHIFTIMM:
4296 shiftimm_assemble(i, i_regs);
4297 break;
4298 case LOAD:
4299 load_assemble(i, i_regs, ccadj_);
4300 break;
4301 case LOADLR:
4302 loadlr_assemble(i, i_regs, ccadj_);
4303 break;
4304 case STORE:
4305 store_assemble(i, i_regs, ccadj_);
4306 break;
4307 case STORELR:
4308 storelr_assemble(i, i_regs, ccadj_);
4309 break;
4310 case COP0:
4311 cop0_assemble(i, i_regs, ccadj_);
4312 break;
4313 case RFE:
4314 rfe_assemble(i, i_regs);
4315 break;
4316 case COP2:
4317 cop2_assemble(i, i_regs);
4318 break;
4319 case C2LS:
4320 c2ls_assemble(i, i_regs, ccadj_);
4321 break;
4322 case C2OP:
4323 c2op_assemble(i, i_regs);
4324 break;
4325 case MULTDIV:
4326 multdiv_assemble(i, i_regs);
4327 multdiv_prepare_stall(i, i_regs, ccadj_);
4328 break;
4329 case MOV:
4330 mov_assemble(i, i_regs);
4331 break;
4332 case SYSCALL:
4333 exception_assemble(i, i_regs, ccadj_);
4334 break;
4335 case HLECALL:
4336 hlecall_assemble(i, i_regs, ccadj_);
4337 break;
4338 case INTCALL:
4339 intcall_assemble(i, i_regs, ccadj_);
4340 break;
4341 case UJUMP:
4342 ujump_assemble(i, i_regs);
4343 ds = 1;
4344 break;
4345 case RJUMP:
4346 rjump_assemble(i, i_regs);
4347 ds = 1;
4348 break;
4349 case CJUMP:
4350 cjump_assemble(i, i_regs);
4351 ds = 1;
4352 break;
4353 case SJUMP:
4354 sjump_assemble(i, i_regs);
4355 ds = 1;
4356 break;
4357 case NOP:
4358 case OTHER:
4359 // not handled, just skip
4360 break;
4361 default:
4362 assert(0);
4363 }
4364 return ds;
4365}
4366
4367static void ds_assemble(int i, const struct regstat *i_regs)
4368{
4369 speculate_register_values(i);
4370 is_delayslot = 1;
4371 switch (dops[i].itype) {
4372 case SYSCALL:
4373 case HLECALL:
4374 case INTCALL:
4375 case UJUMP:
4376 case RJUMP:
4377 case CJUMP:
4378 case SJUMP:
4379 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4380 break;
4381 default:
4382 assemble(i, i_regs, cinfo[i].ccadj);
4383 }
4384 is_delayslot = 0;
4385}
4386
4387// Is the branch target a valid internal jump?
4388static int internal_branch(int addr)
4389{
4390 if(addr&1) return 0; // Indirect (register) jump
4391 if(addr>=start && addr<start+slen*4-4)
4392 {
4393 return 1;
4394 }
4395 return 0;
4396}
4397
4398static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4399{
4400 int hr;
4401 for(hr=0;hr<HOST_REGS;hr++) {
4402 if(hr!=EXCLUDE_REG) {
4403 if(pre[hr]!=entry[hr]) {
4404 if(pre[hr]>=0) {
4405 if((dirty>>hr)&1) {
4406 if(get_reg(entry,pre[hr])<0) {
4407 assert(pre[hr]<64);
4408 if(!((u>>pre[hr])&1))
4409 emit_storereg(pre[hr],hr);
4410 }
4411 }
4412 }
4413 }
4414 }
4415 }
4416 // Move from one register to another (no writeback)
4417 for(hr=0;hr<HOST_REGS;hr++) {
4418 if(hr!=EXCLUDE_REG) {
4419 if(pre[hr]!=entry[hr]) {
4420 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4421 int nr;
4422 if((nr=get_reg(entry,pre[hr]))>=0) {
4423 emit_mov(hr,nr);
4424 }
4425 }
4426 }
4427 }
4428 }
4429}
4430
4431// Load the specified registers
4432// This only loads the registers given as arguments because
4433// we don't want to load things that will be overwritten
4434static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4435{
4436 int hr = get_reg(regmap, rs);
4437 if (hr >= 0 && entry[hr] != regmap[hr])
4438 emit_loadreg(regmap[hr], hr);
4439}
4440
4441static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4442{
4443 load_reg(entry, regmap, rs1);
4444 if (rs1 != rs2)
4445 load_reg(entry, regmap, rs2);
4446}
4447
4448// Load registers prior to the start of a loop
4449// so that they are not loaded within the loop
4450static void loop_preload(signed char pre[],signed char entry[])
4451{
4452 int hr;
4453 for (hr = 0; hr < HOST_REGS; hr++) {
4454 int r = entry[hr];
4455 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4456 assem_debug("loop preload:\n");
4457 if (r < TEMPREG)
4458 emit_loadreg(r, hr);
4459 }
4460 }
4461}
4462
4463// Generate address for load/store instruction
4464// goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4465// AGEN is assigned by pass5b_preallocate2
4466static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4467{
4468 if (dops[i].is_load || dops[i].is_store) {
4469 int ra = -1;
4470 int agr = AGEN1 + (i&1);
4471 if(dops[i].itype==LOAD) {
4472 if (!dops[i].may_except)
4473 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4474 if (ra < 0)
4475 ra = get_reg_temp(i_regs->regmap);
4476 }
4477 if(dops[i].itype==LOADLR) {
4478 ra=get_reg(i_regs->regmap,FTEMP);
4479 }
4480 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4481 ra=get_reg(i_regs->regmap,agr);
4482 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4483 }
4484 if(dops[i].itype==C2LS) {
4485 if (dops[i].opcode == 0x32) // LWC2
4486 ra=get_reg(i_regs->regmap,FTEMP);
4487 else { // SWC2
4488 ra=get_reg(i_regs->regmap,agr);
4489 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4490 }
4491 }
4492 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4493 //if(ra>=0)
4494 {
4495 int offset = cinfo[i].imm;
4496 int add_offset = offset != 0;
4497 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
4498 if(dops[i].rs1==0) {
4499 // Using r0 as a base address
4500 assert(ra >= 0);
4501 if(!entry||entry[ra]!=agr) {
4502 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4503 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4504 }else{
4505 emit_movimm(offset,ra);
4506 }
4507 } // else did it in the previous cycle
4508 cinfo[i].addr = ra;
4509 add_offset = 0;
4510 }
4511 else if (rs < 0) {
4512 assert(ra >= 0);
4513 if (!entry || entry[ra] != dops[i].rs1)
4514 emit_loadreg(dops[i].rs1, ra);
4515 cinfo[i].addr = ra;
4516 //if(!entry||entry[ra]!=dops[i].rs1)
4517 // printf("poor load scheduling!\n");
4518 }
4519 else if(c) {
4520 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4521 assert(ra >= 0);
4522 if(!entry||entry[ra]!=agr) {
4523 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4524 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4525 }else{
4526 emit_movimm(constmap[i][rs]+offset,ra);
4527 regs[i].loadedconst|=1<<ra;
4528 }
4529 } // else did it in the previous cycle
4530 cinfo[i].addr = ra;
4531 }
4532 else // else load_consts already did it
4533 cinfo[i].addr = rs;
4534 add_offset = 0;
4535 }
4536 else
4537 cinfo[i].addr = rs;
4538 if (add_offset) {
4539 assert(ra >= 0);
4540 if(rs>=0) {
4541 emit_addimm(rs,offset,ra);
4542 }else{
4543 emit_addimm(ra,offset,ra);
4544 }
4545 cinfo[i].addr = ra;
4546 }
4547 }
4548 assert(cinfo[i].addr >= 0);
4549 }
4550 // Preload constants for next instruction
4551 if (dops[i+1].is_load || dops[i+1].is_store) {
4552 int agr,ra;
4553 // Actual address
4554 agr=AGEN1+((i+1)&1);
4555 ra=get_reg(i_regs->regmap,agr);
4556 if(ra>=0) {
4557 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4558 int offset=cinfo[i+1].imm;
4559 int c=(regs[i+1].wasconst>>rs)&1;
4560 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4561 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4562 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4563 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4564 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4565 }else{
4566 emit_movimm(constmap[i+1][rs]+offset,ra);
4567 regs[i+1].loadedconst|=1<<ra;
4568 }
4569 }
4570 else if(dops[i+1].rs1==0) {
4571 // Using r0 as a base address
4572 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4573 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4574 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4575 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4576 }else{
4577 emit_movimm(offset,ra);
4578 }
4579 }
4580 }
4581 }
4582}
4583
4584static int get_final_value(int hr, int i, u_int *value)
4585{
4586 int reg=regs[i].regmap[hr];
4587 while(i<slen-1) {
4588 if(regs[i+1].regmap[hr]!=reg) break;
4589 if(!((regs[i+1].isconst>>hr)&1)) break;
4590 if(dops[i+1].bt) break;
4591 i++;
4592 }
4593 if(i<slen-1) {
4594 if (dops[i].is_jump) {
4595 *value=constmap[i][hr];
4596 return 1;
4597 }
4598 if(!dops[i+1].bt) {
4599 if (dops[i+1].is_jump) {
4600 // Load in delay slot, out-of-order execution
4601 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4602 {
4603 // Precompute load address
4604 *value=constmap[i][hr]+cinfo[i+2].imm;
4605 return 1;
4606 }
4607 }
4608 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4609 {
4610 // Precompute load address
4611 *value=constmap[i][hr]+cinfo[i+1].imm;
4612 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
4613 return 1;
4614 }
4615 }
4616 }
4617 *value=constmap[i][hr];
4618 //printf("c=%lx\n",(long)constmap[i][hr]);
4619 if(i==slen-1) return 1;
4620 assert(reg < 64);
4621 return !((unneeded_reg[i+1]>>reg)&1);
4622}
4623
4624// Load registers with known constants
4625static void load_consts(signed char pre[],signed char regmap[],int i)
4626{
4627 int hr,hr2;
4628 // propagate loaded constant flags
4629 if(i==0||dops[i].bt)
4630 regs[i].loadedconst=0;
4631 else {
4632 for (hr = 0; hr < HOST_REGS; hr++) {
4633 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4634 continue;
4635 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4636 && regmap[hr] == regs[i-1].regmap[hr])
4637 {
4638 regs[i].loadedconst |= 1u << hr;
4639 }
4640 }
4641 }
4642 // Load 32-bit regs
4643 for(hr=0;hr<HOST_REGS;hr++) {
4644 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4645 //if(entry[hr]!=regmap[hr]) {
4646 if(!((regs[i].loadedconst>>hr)&1)) {
4647 assert(regmap[hr]<64);
4648 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4649 u_int value, similar=0;
4650 if(get_final_value(hr,i,&value)) {
4651 // see if some other register has similar value
4652 for(hr2=0;hr2<HOST_REGS;hr2++) {
4653 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4654 if(is_similar_value(value,constmap[i][hr2])) {
4655 similar=1;
4656 break;
4657 }
4658 }
4659 }
4660 if(similar) {
4661 u_int value2;
4662 if(get_final_value(hr2,i,&value2)) // is this needed?
4663 emit_movimm_from(value2,hr2,value,hr);
4664 else
4665 emit_movimm(value,hr);
4666 }
4667 else if(value==0) {
4668 emit_zeroreg(hr);
4669 }
4670 else {
4671 emit_movimm(value,hr);
4672 }
4673 }
4674 regs[i].loadedconst|=1<<hr;
4675 }
4676 }
4677 }
4678 }
4679}
4680
4681static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4682{
4683 int hr;
4684 // Load 32-bit regs
4685 for(hr=0;hr<HOST_REGS;hr++) {
4686 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4687 assert(regmap[hr] < 64);
4688 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4689 int value=constmap[i][hr];
4690 if(value==0) {
4691 emit_zeroreg(hr);
4692 }
4693 else {
4694 emit_movimm(value,hr);
4695 }
4696 }
4697 }
4698 }
4699}
4700
4701// Write out all dirty registers (except cycle count)
4702#ifndef wb_dirtys
4703static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
4704{
4705 int hr;
4706 for(hr=0;hr<HOST_REGS;hr++) {
4707 if(hr!=EXCLUDE_REG) {
4708 if(i_regmap[hr]>0) {
4709 if(i_regmap[hr]!=CCREG) {
4710 if((i_dirty>>hr)&1) {
4711 assert(i_regmap[hr]<64);
4712 emit_storereg(i_regmap[hr],hr);
4713 }
4714 }
4715 }
4716 }
4717 }
4718}
4719#endif
4720
4721// Write out dirty registers that we need to reload (pair with load_needed_regs)
4722// This writes the registers not written by store_regs_bt
4723static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
4724{
4725 int hr;
4726 int t=(addr-start)>>2;
4727 for(hr=0;hr<HOST_REGS;hr++) {
4728 if(hr!=EXCLUDE_REG) {
4729 if(i_regmap[hr]>0) {
4730 if(i_regmap[hr]!=CCREG) {
4731 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4732 if((i_dirty>>hr)&1) {
4733 assert(i_regmap[hr]<64);
4734 emit_storereg(i_regmap[hr],hr);
4735 }
4736 }
4737 }
4738 }
4739 }
4740 }
4741}
4742
4743// Load all registers (except cycle count)
4744#ifndef load_all_regs
4745static void load_all_regs(const signed char i_regmap[])
4746{
4747 int hr;
4748 for(hr=0;hr<HOST_REGS;hr++) {
4749 if(hr!=EXCLUDE_REG) {
4750 if(i_regmap[hr]==0) {
4751 emit_zeroreg(hr);
4752 }
4753 else
4754 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4755 {
4756 emit_loadreg(i_regmap[hr],hr);
4757 }
4758 }
4759 }
4760}
4761#endif
4762
4763// Load all current registers also needed by next instruction
4764static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4765{
4766 signed char regmap_sel[HOST_REGS];
4767 int hr;
4768 for (hr = 0; hr < HOST_REGS; hr++) {
4769 regmap_sel[hr] = -1;
4770 if (hr != EXCLUDE_REG)
4771 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4772 regmap_sel[hr] = i_regmap[hr];
4773 }
4774 load_all_regs(regmap_sel);
4775}
4776
4777// Load all regs, storing cycle count if necessary
4778static void load_regs_entry(int t)
4779{
4780 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4781 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
4782 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4783 emit_storereg(CCREG,HOST_CCREG);
4784 }
4785 load_all_regs(regs[t].regmap_entry);
4786}
4787
4788// Store dirty registers prior to branch
4789static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4790{
4791 if(internal_branch(addr))
4792 {
4793 int t=(addr-start)>>2;
4794 int hr;
4795 for(hr=0;hr<HOST_REGS;hr++) {
4796 if(hr!=EXCLUDE_REG) {
4797 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4798 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4799 if((i_dirty>>hr)&1) {
4800 assert(i_regmap[hr]<64);
4801 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4802 emit_storereg(i_regmap[hr],hr);
4803 }
4804 }
4805 }
4806 }
4807 }
4808 }
4809 else
4810 {
4811 // Branch out of this block, write out all dirty regs
4812 wb_dirtys(i_regmap,i_dirty);
4813 }
4814}
4815
4816// Load all needed registers for branch target
4817static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4818{
4819 //if(addr>=start && addr<(start+slen*4))
4820 if(internal_branch(addr))
4821 {
4822 int t=(addr-start)>>2;
4823 int hr;
4824 // Store the cycle count before loading something else
4825 if(i_regmap[HOST_CCREG]!=CCREG) {
4826 assert(i_regmap[HOST_CCREG]==-1);
4827 }
4828 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4829 emit_storereg(CCREG,HOST_CCREG);
4830 }
4831 // Load 32-bit regs
4832 for(hr=0;hr<HOST_REGS;hr++) {
4833 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4834 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4835 if(regs[t].regmap_entry[hr]==0) {
4836 emit_zeroreg(hr);
4837 }
4838 else if(regs[t].regmap_entry[hr]!=CCREG)
4839 {
4840 emit_loadreg(regs[t].regmap_entry[hr],hr);
4841 }
4842 }
4843 }
4844 }
4845 }
4846}
4847
4848static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4849{
4850 if(addr>=start && addr<start+slen*4-4)
4851 {
4852 int t=(addr-start)>>2;
4853 int hr;
4854 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4855 for(hr=0;hr<HOST_REGS;hr++)
4856 {
4857 if(hr!=EXCLUDE_REG)
4858 {
4859 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4860 {
4861 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4862 {
4863 return 0;
4864 }
4865 else
4866 if((i_dirty>>hr)&1)
4867 {
4868 if(i_regmap[hr]<TEMPREG)
4869 {
4870 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4871 return 0;
4872 }
4873 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4874 {
4875 assert(0);
4876 }
4877 }
4878 }
4879 else // Same register but is it 32-bit or dirty?
4880 if(i_regmap[hr]>=0)
4881 {
4882 if(!((regs[t].dirty>>hr)&1))
4883 {
4884 if((i_dirty>>hr)&1)
4885 {
4886 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4887 {
4888 //printf("%x: dirty no match\n",addr);
4889 return 0;
4890 }
4891 }
4892 }
4893 }
4894 }
4895 }
4896 // Delay slots are not valid branch targets
4897 //if(t>0&&(dops[t-1].is_jump) return 0;
4898 // Delay slots require additional processing, so do not match
4899 if(dops[t].is_ds) return 0;
4900 }
4901 else
4902 {
4903 int hr;
4904 for(hr=0;hr<HOST_REGS;hr++)
4905 {
4906 if(hr!=EXCLUDE_REG)
4907 {
4908 if(i_regmap[hr]>=0)
4909 {
4910 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4911 {
4912 if((i_dirty>>hr)&1)
4913 {
4914 return 0;
4915 }
4916 }
4917 }
4918 }
4919 }
4920 }
4921 return 1;
4922}
4923
4924#ifdef DRC_DBG
4925static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4926{
4927 extern void do_insn_cmp();
4928 //extern int cycle;
4929 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4930 reglist |= get_host_reglist(regs[i].regmap_entry);
4931 reglist &= DRC_DBG_REGMASK;
4932
4933 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4934 save_regs(reglist);
4935 // write out changed consts to match the interpreter
4936 if (i > 0 && !dops[i].bt) {
4937 for (hr = 0; hr < HOST_REGS; hr++) {
4938 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4939 if (hr == EXCLUDE_REG || reg <= 0)
4940 continue;
4941 if (!((regs[i-1].isconst >> hr) & 1))
4942 continue;
4943 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4944 continue;
4945 emit_movimm(constmap[i-1][hr],0);
4946 emit_storereg(reg, 0);
4947 }
4948 }
4949 if (dops[i].opcode == 0x0f) { // LUI
4950 emit_movimm(cinfo[i].imm << 16, 0);
4951 emit_storereg(dops[i].rt1, 0);
4952 }
4953 emit_movimm(start+i*4,0);
4954 emit_writeword(0,&pcaddr);
4955 int cc = get_reg(regs[i].regmap_entry, CCREG);
4956 if (cc < 0)
4957 emit_loadreg(CCREG, cc = 0);
4958 emit_addimm(cc, ccadj_, 0);
4959 emit_writeword(0, &psxRegs.cycle);
4960 emit_far_call(do_insn_cmp);
4961 //emit_readword(&cycle,0);
4962 //emit_addimm(0,2,0);
4963 //emit_writeword(0,&cycle);
4964 (void)get_reg2;
4965 restore_regs(reglist);
4966 assem_debug("\\\\do_insn_cmp\n");
4967}
4968static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs)
4969{
4970 // write-out non-consts, consts are likely different because of get_final_value()
4971 if (i_regs->dirty & ~i_regs->loadedconst) {
4972 assem_debug("/ drc_dbg_wb\n");
4973 wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst);
4974 assem_debug("\\ drc_dbg_wb\n");
4975 }
4976}
4977#else
4978#define drc_dbg_emit_do_cmp(x,y)
4979#define drc_dbg_emit_wb_dirtys(x,y)
4980#endif
4981
4982// Used when a branch jumps into the delay slot of another branch
4983static void ds_assemble_entry(int i)
4984{
4985 int t = (cinfo[i].ba - start) >> 2;
4986 int ccadj_ = -CLOCK_ADJUST(1);
4987 if (!instr_addr[t])
4988 instr_addr[t] = out;
4989 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
4990 assem_debug("<->\n");
4991 drc_dbg_emit_do_cmp(t, ccadj_);
4992 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4993 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4994 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4995 address_generation(t,&regs[t],regs[t].regmap_entry);
4996 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4997 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
4998 if (dops[t].is_store)
4999 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
5000 is_delayslot=0;
5001 switch (dops[t].itype) {
5002 case SYSCALL:
5003 case HLECALL:
5004 case INTCALL:
5005 case UJUMP:
5006 case RJUMP:
5007 case CJUMP:
5008 case SJUMP:
5009 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5010 break;
5011 default:
5012 assemble(t, &regs[t], ccadj_);
5013 }
5014 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5015 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5016 if(internal_branch(cinfo[i].ba+4))
5017 assem_debug("branch: internal\n");
5018 else
5019 assem_debug("branch: external\n");
5020 assert(internal_branch(cinfo[i].ba+4));
5021 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
5022 emit_jmp(0);
5023}
5024
5025// Load 2 immediates optimizing for small code size
5026static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5027{
5028 emit_movimm(imm1,rt1);
5029 emit_movimm_from(imm1,rt1,imm2,rt2);
5030}
5031
5032static void do_cc(int i, const signed char i_regmap[], int *adj,
5033 int addr, int taken, int invert)
5034{
5035 int count, count_plus2;
5036 void *jaddr;
5037 void *idle=NULL;
5038 int t=0;
5039 if(dops[i].itype==RJUMP)
5040 {
5041 *adj=0;
5042 }
5043 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5044 if(internal_branch(cinfo[i].ba))
5045 {
5046 t=(cinfo[i].ba-start)>>2;
5047 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
5048 else *adj=cinfo[t].ccadj;
5049 }
5050 else
5051 {
5052 *adj=0;
5053 }
5054 count = cinfo[i].ccadj;
5055 count_plus2 = count + CLOCK_ADJUST(2);
5056 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
5057 // Idle loop
5058 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5059 idle=out;
5060 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5061 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5062 jaddr=out;
5063 emit_jmp(0);
5064 }
5065 else if(*adj==0||invert) {
5066 int cycles = count_plus2;
5067 // faster loop HACK
5068#if 0
5069 if (t&&*adj) {
5070 int rel=t-i;
5071 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5072 cycles=*adj+count+2-*adj;
5073 }
5074#endif
5075 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5076 jaddr = out;
5077 emit_jns(0);
5078 }
5079 else
5080 {
5081 emit_cmpimm(HOST_CCREG, -count_plus2);
5082 jaddr = out;
5083 emit_jns(0);
5084 }
5085 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
5086}
5087
5088static void do_ccstub(int n)
5089{
5090 literal_pool(256);
5091 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
5092 set_jump_target(stubs[n].addr, out);
5093 int i=stubs[n].b;
5094 if (stubs[n].d != TAKEN) {
5095 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
5096 }
5097 else {
5098 if(internal_branch(cinfo[i].ba))
5099 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5100 }
5101 if(stubs[n].c!=-1)
5102 {
5103 // Save PC as return address
5104 emit_movimm(stubs[n].c,0);
5105 emit_writeword(0,&pcaddr);
5106 }
5107 else
5108 {
5109 // Return address depends on which way the branch goes
5110 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
5111 {
5112 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5113 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5114 if(dops[i].rs1==0)
5115 {
5116 s1l=s2l;
5117 s2l=-1;
5118 }
5119 else if(dops[i].rs2==0)
5120 {
5121 s2l=-1;
5122 }
5123 assert(s1l>=0);
5124 #ifdef DESTRUCTIVE_WRITEBACK
5125 if(dops[i].rs1) {
5126 if((branch_regs[i].dirty>>s1l)&&1)
5127 emit_loadreg(dops[i].rs1,s1l);
5128 }
5129 else {
5130 if((branch_regs[i].dirty>>s1l)&1)
5131 emit_loadreg(dops[i].rs2,s1l);
5132 }
5133 if(s2l>=0)
5134 if((branch_regs[i].dirty>>s2l)&1)
5135 emit_loadreg(dops[i].rs2,s2l);
5136 #endif
5137 int hr=0;
5138 int addr=-1,alt=-1,ntaddr=-1;
5139 while(hr<HOST_REGS)
5140 {
5141 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5142 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5143 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5144 {
5145 addr=hr++;break;
5146 }
5147 hr++;
5148 }
5149 while(hr<HOST_REGS)
5150 {
5151 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5152 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5153 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5154 {
5155 alt=hr++;break;
5156 }
5157 hr++;
5158 }
5159 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
5160 {
5161 while(hr<HOST_REGS)
5162 {
5163 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5164 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5165 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5166 {
5167 ntaddr=hr;break;
5168 }
5169 hr++;
5170 }
5171 assert(hr<HOST_REGS);
5172 }
5173 if (dops[i].opcode == 4) // BEQ
5174 {
5175 #ifdef HAVE_CMOV_IMM
5176 if(s2l>=0) emit_cmp(s1l,s2l);
5177 else emit_test(s1l,s1l);
5178 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
5179 #else
5180 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
5181 if(s2l>=0) emit_cmp(s1l,s2l);
5182 else emit_test(s1l,s1l);
5183 emit_cmovne_reg(alt,addr);
5184 #endif
5185 }
5186 else if (dops[i].opcode == 5) // BNE
5187 {
5188 #ifdef HAVE_CMOV_IMM
5189 if(s2l>=0) emit_cmp(s1l,s2l);
5190 else emit_test(s1l,s1l);
5191 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
5192 #else
5193 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
5194 if(s2l>=0) emit_cmp(s1l,s2l);
5195 else emit_test(s1l,s1l);
5196 emit_cmovne_reg(alt,addr);
5197 #endif
5198 }
5199 else if (dops[i].opcode == 6) // BLEZ
5200 {
5201 //emit_movimm(cinfo[i].ba,alt);
5202 //emit_movimm(start+i*4+8,addr);
5203 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
5204 emit_cmpimm(s1l,1);
5205 emit_cmovl_reg(alt,addr);
5206 }
5207 else if (dops[i].opcode == 7) // BGTZ
5208 {
5209 //emit_movimm(cinfo[i].ba,addr);
5210 //emit_movimm(start+i*4+8,ntaddr);
5211 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
5212 emit_cmpimm(s1l,1);
5213 emit_cmovl_reg(ntaddr,addr);
5214 }
5215 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
5216 {
5217 //emit_movimm(cinfo[i].ba,alt);
5218 //emit_movimm(start+i*4+8,addr);
5219 if (dops[i].rs1) {
5220 emit_mov2imm_compact(cinfo[i].ba,
5221 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5222 (dops[i].opcode2 & 1) ? alt : addr);
5223 emit_test(s1l,s1l);
5224 emit_cmovs_reg(alt,addr);
5225 }
5226 else
5227 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
5228 }
5229 emit_writeword(addr, &pcaddr);
5230 }
5231 else
5232 if(dops[i].itype==RJUMP)
5233 {
5234 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5235 if (ds_writes_rjump_rs(i)) {
5236 r=get_reg(branch_regs[i].regmap,RTEMP);
5237 }
5238 emit_writeword(r,&pcaddr);
5239 }
5240 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5241 }
5242 // Update cycle count
5243 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5244 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5245 emit_far_call(cc_interrupt);
5246 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5247 if(stubs[n].d==TAKEN) {
5248 if(internal_branch(cinfo[i].ba))
5249 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
5250 else if(dops[i].itype==RJUMP) {
5251 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5252 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5253 else
5254 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5255 }
5256 }else if(stubs[n].d==NOTTAKEN) {
5257 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5258 else load_all_regs(branch_regs[i].regmap);
5259 }else{
5260 load_all_regs(branch_regs[i].regmap);
5261 }
5262 if (stubs[n].retaddr)
5263 emit_jmp(stubs[n].retaddr);
5264 else
5265 do_jump_vaddr(stubs[n].e);
5266}
5267
5268static void add_to_linker(void *addr, u_int target, int is_internal)
5269{
5270 assert(linkcount < ARRAY_SIZE(link_addr));
5271 link_addr[linkcount].addr = addr;
5272 link_addr[linkcount].target = target;
5273 link_addr[linkcount].internal = is_internal;
5274 linkcount++;
5275}
5276
5277static void ujump_assemble_write_ra(int i)
5278{
5279 int rt;
5280 unsigned int return_address;
5281 rt=get_reg(branch_regs[i].regmap,31);
5282 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5283 //assert(rt>=0);
5284 return_address=start+i*4+8;
5285 if(rt>=0) {
5286 #ifdef USE_MINI_HT
5287 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5288 int temp=-1; // note: must be ds-safe
5289 #ifdef HOST_TEMPREG
5290 temp=HOST_TEMPREG;
5291 #endif
5292 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5293 else emit_movimm(return_address,rt);
5294 }
5295 else
5296 #endif
5297 {
5298 #ifdef REG_PREFETCH
5299 if(temp>=0)
5300 {
5301 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5302 }
5303 #endif
5304 if (!((regs[i].loadedconst >> rt) & 1))
5305 emit_movimm(return_address, rt); // PC into link register
5306 #ifdef IMM_PREFETCH
5307 emit_prefetch(hash_table_get(return_address));
5308 #endif
5309 }
5310 }
5311}
5312
5313static void ujump_assemble(int i, const struct regstat *i_regs)
5314{
5315 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5316 address_generation(i+1,i_regs,regs[i].regmap_entry);
5317 #ifdef REG_PREFETCH
5318 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5319 if(dops[i].rt1==31&&temp>=0)
5320 {
5321 signed char *i_regmap=i_regs->regmap;
5322 int return_address=start+i*4+8;
5323 if(get_reg(branch_regs[i].regmap,31)>0)
5324 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5325 }
5326 #endif
5327 if (dops[i].rt1 == 31)
5328 ujump_assemble_write_ra(i); // writeback ra for DS
5329 ds_assemble(i+1,i_regs);
5330 uint64_t bc_unneeded=branch_regs[i].u;
5331 bc_unneeded|=1|(1LL<<dops[i].rt1);
5332 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5333 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5334 int cc,adj;
5335 cc=get_reg(branch_regs[i].regmap,CCREG);
5336 assert(cc==HOST_CCREG);
5337 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5338 #ifdef REG_PREFETCH
5339 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5340 #endif
5341 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5342 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5343 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5344 if(internal_branch(cinfo[i].ba))
5345 assem_debug("branch: internal\n");
5346 else
5347 assem_debug("branch: external\n");
5348 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
5349 ds_assemble_entry(i);
5350 }
5351 else {
5352 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
5353 emit_jmp(0);
5354 }
5355}
5356
5357static void rjump_assemble_write_ra(int i)
5358{
5359 int rt,return_address;
5360 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
5361 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5362 assert(rt>=0);
5363 return_address=start+i*4+8;
5364 #ifdef REG_PREFETCH
5365 if(temp>=0)
5366 {
5367 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5368 }
5369 #endif
5370 if (!((regs[i].loadedconst >> rt) & 1))
5371 emit_movimm(return_address, rt); // PC into link register
5372 #ifdef IMM_PREFETCH
5373 emit_prefetch(hash_table_get(return_address));
5374 #endif
5375}
5376
5377static void rjump_assemble(int i, const struct regstat *i_regs)
5378{
5379 int temp;
5380 int rs,cc;
5381 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5382 assert(rs>=0);
5383 if (ds_writes_rjump_rs(i)) {
5384 // Delay slot abuse, make a copy of the branch address register
5385 temp=get_reg(branch_regs[i].regmap,RTEMP);
5386 assert(temp>=0);
5387 assert(regs[i].regmap[temp]==RTEMP);
5388 emit_mov(rs,temp);
5389 rs=temp;
5390 }
5391 address_generation(i+1,i_regs,regs[i].regmap_entry);
5392 #ifdef REG_PREFETCH
5393 if(dops[i].rt1==31)
5394 {
5395 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5396 signed char *i_regmap=i_regs->regmap;
5397 int return_address=start+i*4+8;
5398 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5399 }
5400 }
5401 #endif
5402 #ifdef USE_MINI_HT
5403 if(dops[i].rs1==31) {
5404 int rh=get_reg(regs[i].regmap,RHASH);
5405 if(rh>=0) do_preload_rhash(rh);
5406 }
5407 #endif
5408 if (dops[i].rt1 != 0)
5409 rjump_assemble_write_ra(i);
5410 ds_assemble(i+1,i_regs);
5411 uint64_t bc_unneeded=branch_regs[i].u;
5412 bc_unneeded|=1|(1LL<<dops[i].rt1);
5413 bc_unneeded&=~(1LL<<dops[i].rs1);
5414 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5415 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5416 cc=get_reg(branch_regs[i].regmap,CCREG);
5417 assert(cc==HOST_CCREG);
5418 (void)cc;
5419 #ifdef USE_MINI_HT
5420 int rh=get_reg(branch_regs[i].regmap,RHASH);
5421 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5422 if(dops[i].rs1==31) {
5423 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5424 do_preload_rhtbl(ht);
5425 do_rhash(rs,rh);
5426 }
5427 #endif
5428 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5429 #ifdef DESTRUCTIVE_WRITEBACK
5430 if((branch_regs[i].dirty>>rs)&1) {
5431 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5432 emit_loadreg(dops[i].rs1,rs);
5433 }
5434 }
5435 #endif
5436 #ifdef REG_PREFETCH
5437 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5438 #endif
5439 #ifdef USE_MINI_HT
5440 if(dops[i].rs1==31) {
5441 do_miniht_load(ht,rh);
5442 }
5443 #endif
5444 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5445 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
5446 //assert(adj==0);
5447 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5448 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5449 if (dops[i+1].itype == RFE)
5450 // special case for RFE
5451 emit_jmp(0);
5452 else
5453 emit_jns(0);
5454 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5455 #ifdef USE_MINI_HT
5456 if(dops[i].rs1==31) {
5457 do_miniht_jump(rs,rh,ht);
5458 }
5459 else
5460 #endif
5461 {
5462 do_jump_vaddr(rs);
5463 }
5464 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5465 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5466 #endif
5467}
5468
5469static void cjump_assemble(int i, const struct regstat *i_regs)
5470{
5471 const signed char *i_regmap = i_regs->regmap;
5472 int cc;
5473 int match;
5474 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5475 assem_debug("match=%d\n",match);
5476 int s1l,s2l;
5477 int unconditional=0,nop=0;
5478 int invert=0;
5479 int internal=internal_branch(cinfo[i].ba);
5480 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5481 if(!match) invert=1;
5482 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5483 if(i>(cinfo[i].ba-start)>>2) invert=1;
5484 #endif
5485 #ifdef __aarch64__
5486 invert=1; // because of near cond. branches
5487 #endif
5488
5489 if(dops[i].ooo) {
5490 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5491 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5492 }
5493 else {
5494 s1l=get_reg(i_regmap,dops[i].rs1);
5495 s2l=get_reg(i_regmap,dops[i].rs2);
5496 }
5497 if(dops[i].rs1==0&&dops[i].rs2==0)
5498 {
5499 if(dops[i].opcode&1) nop=1;
5500 else unconditional=1;
5501 //assert(dops[i].opcode!=5);
5502 //assert(dops[i].opcode!=7);
5503 //assert(dops[i].opcode!=0x15);
5504 //assert(dops[i].opcode!=0x17);
5505 }
5506 else if(dops[i].rs1==0)
5507 {
5508 s1l=s2l;
5509 s2l=-1;
5510 }
5511 else if(dops[i].rs2==0)
5512 {
5513 s2l=-1;
5514 }
5515
5516 if(dops[i].ooo) {
5517 // Out of order execution (delay slot first)
5518 //printf("OOOE\n");
5519 address_generation(i+1,i_regs,regs[i].regmap_entry);
5520 ds_assemble(i+1,i_regs);
5521 int adj;
5522 uint64_t bc_unneeded=branch_regs[i].u;
5523 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5524 bc_unneeded|=1;
5525 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5526 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5527 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5528 cc=get_reg(branch_regs[i].regmap,CCREG);
5529 assert(cc==HOST_CCREG);
5530 if(unconditional)
5531 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5532 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5533 //assem_debug("cycle count (adj)\n");
5534 if(unconditional) {
5535 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5536 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5537 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5538 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5539 if(internal)
5540 assem_debug("branch: internal\n");
5541 else
5542 assem_debug("branch: external\n");
5543 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
5544 ds_assemble_entry(i);
5545 }
5546 else {
5547 add_to_linker(out,cinfo[i].ba,internal);
5548 emit_jmp(0);
5549 }
5550 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5551 if(((u_int)out)&7) emit_addnop(0);
5552 #endif
5553 }
5554 }
5555 else if(nop) {
5556 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5557 void *jaddr=out;
5558 emit_jns(0);
5559 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5560 }
5561 else {
5562 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5563 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5564 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5565
5566 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5567 assert(s1l>=0);
5568 if(dops[i].opcode==4) // BEQ
5569 {
5570 if(s2l>=0) emit_cmp(s1l,s2l);
5571 else emit_test(s1l,s1l);
5572 if(invert){
5573 nottaken=out;
5574 emit_jne(DJT_1);
5575 }else{
5576 add_to_linker(out,cinfo[i].ba,internal);
5577 emit_jeq(0);
5578 }
5579 }
5580 if(dops[i].opcode==5) // BNE
5581 {
5582 if(s2l>=0) emit_cmp(s1l,s2l);
5583 else emit_test(s1l,s1l);
5584 if(invert){
5585 nottaken=out;
5586 emit_jeq(DJT_1);
5587 }else{
5588 add_to_linker(out,cinfo[i].ba,internal);
5589 emit_jne(0);
5590 }
5591 }
5592 if(dops[i].opcode==6) // BLEZ
5593 {
5594 emit_cmpimm(s1l,1);
5595 if(invert){
5596 nottaken=out;
5597 emit_jge(DJT_1);
5598 }else{
5599 add_to_linker(out,cinfo[i].ba,internal);
5600 emit_jl(0);
5601 }
5602 }
5603 if(dops[i].opcode==7) // BGTZ
5604 {
5605 emit_cmpimm(s1l,1);
5606 if(invert){
5607 nottaken=out;
5608 emit_jl(DJT_1);
5609 }else{
5610 add_to_linker(out,cinfo[i].ba,internal);
5611 emit_jge(0);
5612 }
5613 }
5614 if(invert) {
5615 if(taken) set_jump_target(taken, out);
5616 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5617 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
5618 if(adj) {
5619 emit_addimm(cc,-adj,cc);
5620 add_to_linker(out,cinfo[i].ba,internal);
5621 }else{
5622 emit_addnop(13);
5623 add_to_linker(out,cinfo[i].ba,internal*2);
5624 }
5625 emit_jmp(0);
5626 }else
5627 #endif
5628 {
5629 if(adj) emit_addimm(cc,-adj,cc);
5630 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5631 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5632 if(internal)
5633 assem_debug("branch: internal\n");
5634 else
5635 assem_debug("branch: external\n");
5636 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5637 ds_assemble_entry(i);
5638 }
5639 else {
5640 add_to_linker(out,cinfo[i].ba,internal);
5641 emit_jmp(0);
5642 }
5643 }
5644 set_jump_target(nottaken, out);
5645 }
5646
5647 if(nottaken1) set_jump_target(nottaken1, out);
5648 if(adj) {
5649 if(!invert) emit_addimm(cc,adj,cc);
5650 }
5651 } // (!unconditional)
5652 } // if(ooo)
5653 else
5654 {
5655 // In-order execution (branch first)
5656 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5657 if(!unconditional&&!nop) {
5658 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5659 assert(s1l>=0);
5660 if((dops[i].opcode&0x2f)==4) // BEQ
5661 {
5662 if(s2l>=0) emit_cmp(s1l,s2l);
5663 else emit_test(s1l,s1l);
5664 nottaken=out;
5665 emit_jne(DJT_2);
5666 }
5667 if((dops[i].opcode&0x2f)==5) // BNE
5668 {
5669 if(s2l>=0) emit_cmp(s1l,s2l);
5670 else emit_test(s1l,s1l);
5671 nottaken=out;
5672 emit_jeq(DJT_2);
5673 }
5674 if((dops[i].opcode&0x2f)==6) // BLEZ
5675 {
5676 emit_cmpimm(s1l,1);
5677 nottaken=out;
5678 emit_jge(DJT_2);
5679 }
5680 if((dops[i].opcode&0x2f)==7) // BGTZ
5681 {
5682 emit_cmpimm(s1l,1);
5683 nottaken=out;
5684 emit_jl(DJT_2);
5685 }
5686 } // if(!unconditional)
5687 int adj;
5688 uint64_t ds_unneeded=branch_regs[i].u;
5689 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5690 ds_unneeded|=1;
5691 // branch taken
5692 if(!nop) {
5693 if(taken) set_jump_target(taken, out);
5694 assem_debug("1:\n");
5695 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5696 // load regs
5697 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5698 address_generation(i+1,&branch_regs[i],0);
5699 if (ram_offset)
5700 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5701 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5702 ds_assemble(i+1,&branch_regs[i]);
5703 drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]);
5704 cc=get_reg(branch_regs[i].regmap,CCREG);
5705 if(cc==-1) {
5706 emit_loadreg(CCREG,cc=HOST_CCREG);
5707 // CHECK: Is the following instruction (fall thru) allocated ok?
5708 }
5709 assert(cc==HOST_CCREG);
5710 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5711 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5712 assem_debug("cycle count (adj)\n");
5713 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5714 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5715 if(internal)
5716 assem_debug("branch: internal\n");
5717 else
5718 assem_debug("branch: external\n");
5719 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5720 ds_assemble_entry(i);
5721 }
5722 else {
5723 add_to_linker(out,cinfo[i].ba,internal);
5724 emit_jmp(0);
5725 }
5726 }
5727 // branch not taken
5728 if(!unconditional) {
5729 if(nottaken1) set_jump_target(nottaken1, out);
5730 set_jump_target(nottaken, out);
5731 assem_debug("2:\n");
5732 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5733 // load regs
5734 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5735 address_generation(i+1,&branch_regs[i],0);
5736 if (ram_offset)
5737 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5738 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5739 ds_assemble(i+1,&branch_regs[i]);
5740 cc=get_reg(branch_regs[i].regmap,CCREG);
5741 if (cc == -1) {
5742 // Cycle count isn't in a register, temporarily load it then write it out
5743 emit_loadreg(CCREG,HOST_CCREG);
5744 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5745 void *jaddr=out;
5746 emit_jns(0);
5747 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5748 emit_storereg(CCREG,HOST_CCREG);
5749 }
5750 else{
5751 cc=get_reg(i_regmap,CCREG);
5752 assert(cc==HOST_CCREG);
5753 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5754 void *jaddr=out;
5755 emit_jns(0);
5756 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5757 }
5758 }
5759 }
5760}
5761
5762static void sjump_assemble(int i, const struct regstat *i_regs)
5763{
5764 const signed char *i_regmap = i_regs->regmap;
5765 int cc;
5766 int match;
5767 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5768 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5769 int s1l;
5770 int unconditional=0,nevertaken=0;
5771 int invert=0;
5772 int internal=internal_branch(cinfo[i].ba);
5773 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5774 if(!match) invert=1;
5775 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5776 if(i>(cinfo[i].ba-start)>>2) invert=1;
5777 #endif
5778 #ifdef __aarch64__
5779 invert=1; // because of near cond. branches
5780 #endif
5781
5782 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5783 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5784
5785 if(dops[i].ooo) {
5786 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5787 }
5788 else {
5789 s1l=get_reg(i_regmap,dops[i].rs1);
5790 }
5791 if(dops[i].rs1==0)
5792 {
5793 if(dops[i].opcode2&1) unconditional=1;
5794 else nevertaken=1;
5795 // These are never taken (r0 is never less than zero)
5796 //assert(dops[i].opcode2!=0);
5797 //assert(dops[i].opcode2!=2);
5798 //assert(dops[i].opcode2!=0x10);
5799 //assert(dops[i].opcode2!=0x12);
5800 }
5801
5802 if(dops[i].ooo) {
5803 // Out of order execution (delay slot first)
5804 //printf("OOOE\n");
5805 address_generation(i+1,i_regs,regs[i].regmap_entry);
5806 ds_assemble(i+1,i_regs);
5807 int adj;
5808 uint64_t bc_unneeded=branch_regs[i].u;
5809 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5810 bc_unneeded|=1;
5811 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5812 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5813 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5814 if(dops[i].rt1==31) {
5815 int rt,return_address;
5816 rt=get_reg(branch_regs[i].regmap,31);
5817 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5818 if(rt>=0) {
5819 // Save the PC even if the branch is not taken
5820 return_address=start+i*4+8;
5821 emit_movimm(return_address,rt); // PC into link register
5822 #ifdef IMM_PREFETCH
5823 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5824 #endif
5825 }
5826 }
5827 cc=get_reg(branch_regs[i].regmap,CCREG);
5828 assert(cc==HOST_CCREG);
5829 if(unconditional)
5830 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5831 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5832 assem_debug("cycle count (adj)\n");
5833 if(unconditional) {
5834 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5835 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5836 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5837 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5838 if(internal)
5839 assem_debug("branch: internal\n");
5840 else
5841 assem_debug("branch: external\n");
5842 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5843 ds_assemble_entry(i);
5844 }
5845 else {
5846 add_to_linker(out,cinfo[i].ba,internal);
5847 emit_jmp(0);
5848 }
5849 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5850 if(((u_int)out)&7) emit_addnop(0);
5851 #endif
5852 }
5853 }
5854 else if(nevertaken) {
5855 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5856 void *jaddr=out;
5857 emit_jns(0);
5858 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5859 }
5860 else {
5861 void *nottaken = NULL;
5862 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5863 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5864 {
5865 assert(s1l>=0);
5866 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
5867 {
5868 emit_test(s1l,s1l);
5869 if(invert){
5870 nottaken=out;
5871 emit_jns(DJT_1);
5872 }else{
5873 add_to_linker(out,cinfo[i].ba,internal);
5874 emit_js(0);
5875 }
5876 }
5877 else // BGEZ/BGEZAL
5878 {
5879 emit_test(s1l,s1l);
5880 if(invert){
5881 nottaken=out;
5882 emit_js(DJT_1);
5883 }else{
5884 add_to_linker(out,cinfo[i].ba,internal);
5885 emit_jns(0);
5886 }
5887 }
5888 }
5889
5890 if(invert) {
5891 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5892 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
5893 if(adj) {
5894 emit_addimm(cc,-adj,cc);
5895 add_to_linker(out,cinfo[i].ba,internal);
5896 }else{
5897 emit_addnop(13);
5898 add_to_linker(out,cinfo[i].ba,internal*2);
5899 }
5900 emit_jmp(0);
5901 }else
5902 #endif
5903 {
5904 if(adj) emit_addimm(cc,-adj,cc);
5905 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5906 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5907 if(internal)
5908 assem_debug("branch: internal\n");
5909 else
5910 assem_debug("branch: external\n");
5911 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5912 ds_assemble_entry(i);
5913 }
5914 else {
5915 add_to_linker(out,cinfo[i].ba,internal);
5916 emit_jmp(0);
5917 }
5918 }
5919 set_jump_target(nottaken, out);
5920 }
5921
5922 if(adj) {
5923 if(!invert) emit_addimm(cc,adj,cc);
5924 }
5925 } // (!unconditional)
5926 } // if(ooo)
5927 else
5928 {
5929 // In-order execution (branch first)
5930 //printf("IOE\n");
5931 void *nottaken = NULL;
5932 if (!unconditional && !nevertaken) {
5933 assert(s1l >= 0);
5934 emit_test(s1l, s1l);
5935 }
5936 if (dops[i].rt1 == 31) {
5937 int rt, return_address;
5938 rt = get_reg(branch_regs[i].regmap,31);
5939 if(rt >= 0) {
5940 // Save the PC even if the branch is not taken
5941 return_address = start + i*4+8;
5942 emit_movimm(return_address, rt); // PC into link register
5943 #ifdef IMM_PREFETCH
5944 emit_prefetch(hash_table_get(return_address));
5945 #endif
5946 }
5947 }
5948 if (!unconditional && !nevertaken) {
5949 nottaken = out;
5950 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5951 emit_jns(DJT_1);
5952 else // BGEZ/BGEZAL
5953 emit_js(DJT_1);
5954 }
5955 int adj;
5956 uint64_t ds_unneeded=branch_regs[i].u;
5957 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5958 ds_unneeded|=1;
5959 // branch taken
5960 if(!nevertaken) {
5961 //assem_debug("1:\n");
5962 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5963 // load regs
5964 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5965 address_generation(i+1,&branch_regs[i],0);
5966 if (ram_offset)
5967 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5968 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5969 ds_assemble(i+1,&branch_regs[i]);
5970 cc=get_reg(branch_regs[i].regmap,CCREG);
5971 if(cc==-1) {
5972 emit_loadreg(CCREG,cc=HOST_CCREG);
5973 // CHECK: Is the following instruction (fall thru) allocated ok?
5974 }
5975 assert(cc==HOST_CCREG);
5976 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5977 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5978 assem_debug("cycle count (adj)\n");
5979 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5980 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5981 if(internal)
5982 assem_debug("branch: internal\n");
5983 else
5984 assem_debug("branch: external\n");
5985 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5986 ds_assemble_entry(i);
5987 }
5988 else {
5989 add_to_linker(out,cinfo[i].ba,internal);
5990 emit_jmp(0);
5991 }
5992 }
5993 // branch not taken
5994 if(!unconditional) {
5995 if (!nevertaken) {
5996 assert(nottaken);
5997 set_jump_target(nottaken, out);
5998 }
5999 assem_debug("1:\n");
6000 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6001 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6002 address_generation(i+1,&branch_regs[i],0);
6003 if (ram_offset)
6004 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
6005 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
6006 ds_assemble(i+1,&branch_regs[i]);
6007 cc=get_reg(branch_regs[i].regmap,CCREG);
6008 if (cc == -1) {
6009 // Cycle count isn't in a register, temporarily load it then write it out
6010 emit_loadreg(CCREG,HOST_CCREG);
6011 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
6012 void *jaddr=out;
6013 emit_jns(0);
6014 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6015 emit_storereg(CCREG,HOST_CCREG);
6016 }
6017 else{
6018 cc=get_reg(i_regmap,CCREG);
6019 assert(cc==HOST_CCREG);
6020 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
6021 void *jaddr=out;
6022 emit_jns(0);
6023 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6024 }
6025 }
6026 }
6027}
6028
6029static void check_regmap(signed char *regmap)
6030{
6031#ifndef NDEBUG
6032 int i,j;
6033 for (i = 0; i < HOST_REGS; i++) {
6034 if (regmap[i] < 0)
6035 continue;
6036 for (j = i + 1; j < HOST_REGS; j++)
6037 assert(regmap[i] != regmap[j]);
6038 }
6039#endif
6040}
6041
6042#ifdef DISASM
6043#include <inttypes.h>
6044static char insn[MAXBLOCK][10];
6045
6046#define set_mnemonic(i_, n_) \
6047 strcpy(insn[i_], n_)
6048
6049void print_regmap(const char *name, const signed char *regmap)
6050{
6051 char buf[5];
6052 int i, l;
6053 fputs(name, stdout);
6054 for (i = 0; i < HOST_REGS; i++) {
6055 l = 0;
6056 if (regmap[i] >= 0)
6057 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6058 for (; l < 3; l++)
6059 buf[l] = ' ';
6060 buf[l] = 0;
6061 printf(" r%d=%s", i, buf);
6062 }
6063 fputs("\n", stdout);
6064}
6065
6066 /* disassembly */
6067void disassemble_inst(int i)
6068{
6069 if (dops[i].bt) printf("*"); else printf(" ");
6070 switch(dops[i].itype) {
6071 case UJUMP:
6072 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
6073 case CJUMP:
6074 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
6075 case SJUMP:
6076 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6077 case RJUMP:
6078 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
6079 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6080 else
6081 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6082 break;
6083 case IMM16:
6084 if(dops[i].opcode==0xf) //LUI
6085 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
6086 else
6087 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6088 break;
6089 case LOAD:
6090 case LOADLR:
6091 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6092 break;
6093 case STORE:
6094 case STORELR:
6095 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
6096 break;
6097 case ALU:
6098 case SHIFT:
6099 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6100 break;
6101 case MULTDIV:
6102 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6103 break;
6104 case SHIFTIMM:
6105 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6106 break;
6107 case MOV:
6108 if((dops[i].opcode2&0x1d)==0x10)
6109 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6110 else if((dops[i].opcode2&0x1d)==0x11)
6111 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6112 else
6113 printf (" %x: %s\n",start+i*4,insn[i]);
6114 break;
6115 case COP0:
6116 if(dops[i].opcode2==0)
6117 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6118 else if(dops[i].opcode2==4)
6119 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6120 else printf (" %x: %s\n",start+i*4,insn[i]);
6121 break;
6122 case COP2:
6123 if(dops[i].opcode2<3)
6124 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6125 else if(dops[i].opcode2>3)
6126 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6127 else printf (" %x: %s\n",start+i*4,insn[i]);
6128 break;
6129 case C2LS:
6130 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
6131 break;
6132 case INTCALL:
6133 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6134 break;
6135 default:
6136 //printf (" %s %8x\n",insn[i],source[i]);
6137 printf (" %x: %s\n",start+i*4,insn[i]);
6138 }
6139 #ifndef REGMAP_PRINT
6140 return;
6141 #endif
6142 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
6143 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6144 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
6145 print_regmap("pre: ", regmap_pre[i]);
6146 print_regmap("entry: ", regs[i].regmap_entry);
6147 print_regmap("map: ", regs[i].regmap);
6148 if (dops[i].is_jump) {
6149 print_regmap("bentry:", branch_regs[i].regmap_entry);
6150 print_regmap("bmap: ", branch_regs[i].regmap);
6151 }
6152}
6153#else
6154#define set_mnemonic(i_, n_)
6155static void disassemble_inst(int i) {}
6156#endif // DISASM
6157
6158#define DRC_TEST_VAL 0x74657374
6159
6160static noinline void new_dynarec_test(void)
6161{
6162 int (*testfunc)(void);
6163 void *beginning;
6164 int ret[2];
6165 size_t i;
6166
6167 // check structure linkage
6168 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6169 {
6170 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6171 }
6172
6173 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6174 new_dynarec_test, out);
6175 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
6176
6177 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6178 out = ndrc->translation_cache;
6179 beginning = start_block();
6180 emit_movimm(DRC_TEST_VAL + i, 0); // test
6181 emit_ret();
6182 literal_pool(0);
6183 end_block(beginning);
6184 testfunc = beginning;
6185 ret[i] = testfunc();
6186 }
6187
6188 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6189 SysPrintf("test passed.\n");
6190 else
6191 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6192 out = ndrc->translation_cache;
6193}
6194
6195static int get_cycle_multiplier(void)
6196{
6197 return Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
6198 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
6199}
6200
6201// clear the state completely, instead of just marking
6202// things invalid like invalidate_all_pages() does
6203void new_dynarec_clear_full(void)
6204{
6205 int n;
6206 out = ndrc->translation_cache;
6207 memset(invalid_code,1,sizeof(invalid_code));
6208 memset(hash_table,0xff,sizeof(hash_table));
6209 memset(mini_ht,-1,sizeof(mini_ht));
6210 memset(shadow,0,sizeof(shadow));
6211 copy=shadow;
6212 expirep = EXPIRITY_OFFSET;
6213 pending_exception=0;
6214 literalcount=0;
6215 stop_after_jal=0;
6216 inv_code_start=inv_code_end=~0;
6217 hack_addr=0;
6218 f1_hack=0;
6219 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6220 blocks_clear(&blocks[n]);
6221 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6222 free(jumps[n]);
6223 jumps[n] = NULL;
6224 }
6225 stat_clear(stat_blocks);
6226 stat_clear(stat_links);
6227
6228 if (cycle_multiplier_old != Config.cycle_multiplier
6229 || new_dynarec_hacks_old != new_dynarec_hacks)
6230 {
6231 SysPrintf("ndrc config: mul=%d, ha=%x, pex=%d\n",
6232 get_cycle_multiplier(), new_dynarec_hacks, Config.PreciseExceptions);
6233 }
6234 cycle_multiplier_old = Config.cycle_multiplier;
6235 new_dynarec_hacks_old = new_dynarec_hacks;
6236}
6237
6238void new_dynarec_init(void)
6239{
6240 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6241
6242#ifdef _3DS
6243 check_rosalina();
6244#endif
6245#ifdef BASE_ADDR_DYNAMIC
6246 #ifdef VITA
6247 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6248 if (sceBlock <= 0)
6249 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6250 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6251 if (ret < 0)
6252 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6253 sceKernelOpenVMDomain();
6254 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6255 #elif defined(_MSC_VER)
6256 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6257 PAGE_EXECUTE_READWRITE);
6258 #elif defined(HAVE_LIBNX)
6259 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6260 if (R_FAILED(rc))
6261 SysPrintf("jitCreate failed: %08x\n", rc);
6262 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
6263 jitTransitionToWritable(&g_jit);
6264 ndrc = g_jit.rx_addr;
6265 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
6266 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
6267 #else
6268 uintptr_t desired_addr = 0;
6269 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6270 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6271 int fd = -1;
6272 #ifdef __ELF__
6273 extern char _end;
6274 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6275 #endif
6276 #ifdef TC_WRITE_OFFSET
6277 // mostly for testing
6278 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6279 ftruncate(fd, sizeof(*ndrc));
6280 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6281 (flags = MAP_SHARED), fd, 0);
6282 assert(mw != MAP_FAILED);
6283 prot = PROT_READ | PROT_EXEC;
6284 #endif
6285 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
6286 if (ndrc == MAP_FAILED) {
6287 SysPrintf("mmap() failed: %s\n", strerror(errno));
6288 abort();
6289 }
6290 #ifdef TC_WRITE_OFFSET
6291 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6292 #endif
6293 #endif
6294#else
6295 #ifndef NO_WRITE_EXEC
6296 // not all systems allow execute in data segment by default
6297 // size must be 4K aligned for 3DS?
6298 if (mprotect(ndrc, sizeof(*ndrc),
6299 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6300 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6301 #endif
6302#endif
6303 out = ndrc->translation_cache;
6304 new_dynarec_clear_full();
6305#ifdef HOST_IMM8
6306 // Copy this into local area so we don't have to put it in every literal pool
6307 invc_ptr=invalid_code;
6308#endif
6309 arch_init();
6310 new_dynarec_test();
6311 ram_offset = (uintptr_t)psxM - 0x80000000;
6312 if (ram_offset!=0)
6313 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6314 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6315 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6316}
6317
6318void new_dynarec_cleanup(void)
6319{
6320 int n;
6321#ifdef BASE_ADDR_DYNAMIC
6322 #ifdef VITA
6323 // sceBlock is managed by retroarch's bootstrap code
6324 //sceKernelFreeMemBlock(sceBlock);
6325 //sceBlock = -1;
6326 #elif defined(HAVE_LIBNX)
6327 jitClose(&g_jit);
6328 ndrc = NULL;
6329 #else
6330 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6331 SysPrintf("munmap() failed\n");
6332 ndrc = NULL;
6333 #endif
6334#endif
6335 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6336 blocks_clear(&blocks[n]);
6337 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6338 free(jumps[n]);
6339 jumps[n] = NULL;
6340 }
6341 stat_clear(stat_blocks);
6342 stat_clear(stat_links);
6343 new_dynarec_print_stats();
6344}
6345
6346static u_int *get_source_start(u_int addr, u_int *limit)
6347{
6348 if (addr < 0x00800000
6349 || (0x80000000 <= addr && addr < 0x80800000)
6350 || (0xa0000000 <= addr && addr < 0xa0800000))
6351 {
6352 // used for BIOS calls mostly?
6353 *limit = (addr & 0xa0600000) + 0x00200000;
6354 return (u_int *)(psxM + (addr & 0x1fffff));
6355 }
6356 else if (
6357 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6358 (0xbfc00000 <= addr && addr < 0xbfc80000))
6359 {
6360 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6361 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
6362 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6363 cycle_multiplier_active = 200;
6364
6365 *limit = (addr & 0xfff00000) | 0x80000;
6366 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6367 }
6368 return NULL;
6369}
6370
6371static u_int scan_for_ret(u_int addr)
6372{
6373 u_int limit = 0;
6374 u_int *mem;
6375
6376 mem = get_source_start(addr, &limit);
6377 if (mem == NULL)
6378 return addr;
6379
6380 if (limit > addr + 0x1000)
6381 limit = addr + 0x1000;
6382 for (; addr < limit; addr += 4, mem++) {
6383 if (*mem == 0x03e00008) // jr $ra
6384 return addr + 8;
6385 }
6386 return addr;
6387}
6388
6389struct savestate_block {
6390 uint32_t addr;
6391 uint32_t regflags;
6392};
6393
6394static int addr_cmp(const void *p1_, const void *p2_)
6395{
6396 const struct savestate_block *p1 = p1_, *p2 = p2_;
6397 return p1->addr - p2->addr;
6398}
6399
6400int new_dynarec_save_blocks(void *save, int size)
6401{
6402 struct savestate_block *sblocks = save;
6403 int maxcount = size / sizeof(sblocks[0]);
6404 struct savestate_block tmp_blocks[1024];
6405 struct block_info *block;
6406 int p, s, d, o, bcnt;
6407 u_int addr;
6408
6409 o = 0;
6410 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6411 bcnt = 0;
6412 for (block = blocks[p]; block != NULL; block = block->next) {
6413 if (block->is_dirty)
6414 continue;
6415 tmp_blocks[bcnt].addr = block->start;
6416 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6417 bcnt++;
6418 }
6419 if (bcnt < 1)
6420 continue;
6421 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6422
6423 addr = tmp_blocks[0].addr;
6424 for (s = d = 0; s < bcnt; s++) {
6425 if (tmp_blocks[s].addr < addr)
6426 continue;
6427 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6428 tmp_blocks[d++] = tmp_blocks[s];
6429 addr = scan_for_ret(tmp_blocks[s].addr);
6430 }
6431
6432 if (o + d > maxcount)
6433 d = maxcount - o;
6434 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6435 o += d;
6436 }
6437
6438 return o * sizeof(sblocks[0]);
6439}
6440
6441void new_dynarec_load_blocks(const void *save, int size)
6442{
6443 const struct savestate_block *sblocks = save;
6444 int count = size / sizeof(sblocks[0]);
6445 struct block_info *block;
6446 u_int regs_save[32];
6447 u_int page;
6448 uint32_t f;
6449 int i, b;
6450
6451 // restore clean blocks, if any
6452 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6453 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6454 if (!block->is_dirty)
6455 continue;
6456 assert(block->source && block->copy);
6457 if (memcmp(block->source, block->copy, block->len))
6458 continue;
6459
6460 // see try_restore_block
6461 block->is_dirty = 0;
6462 mark_invalid_code(block->start, block->len, 0);
6463 i++;
6464 }
6465 }
6466 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6467
6468 // change GPRs for speculation to at least partially work..
6469 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6470 for (i = 1; i < 32; i++)
6471 psxRegs.GPR.r[i] = 0x80000000;
6472
6473 for (b = 0; b < count; b++) {
6474 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6475 if (f & 1)
6476 psxRegs.GPR.r[i] = 0x1f800000;
6477 }
6478
6479 ndrc_get_addr_ht(sblocks[b].addr);
6480
6481 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6482 if (f & 1)
6483 psxRegs.GPR.r[i] = 0x80000000;
6484 }
6485 }
6486
6487 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6488}
6489
6490void new_dynarec_print_stats(void)
6491{
6492#ifdef STAT_PRINT
6493 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6494 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6495 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6496 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6497 out - ndrc->translation_cache, stat_blocks, stat_links);
6498 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6499 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6500 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6501#endif
6502}
6503
6504static void force_intcall(int i)
6505{
6506 memset(&dops[i], 0, sizeof(dops[i]));
6507 dops[i].itype = INTCALL;
6508 dops[i].rs1 = CCREG;
6509 dops[i].is_exception = 1;
6510 cinfo[i].ba = -1;
6511}
6512
6513static int apply_hacks(void)
6514{
6515 int i;
6516 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6517 return 0;
6518 /* special hack(s) */
6519 for (i = 0; i < slen - 4; i++)
6520 {
6521 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6522 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6523 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6524 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
6525 {
6526 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6527 dops[i + 3].itype = NOP;
6528 }
6529 }
6530 i = slen;
6531 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6532 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6533 && dops[i-7].itype == STORE)
6534 {
6535 i = i-8;
6536 if (dops[i].itype == IMM16)
6537 i--;
6538 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6539 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6540 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6541 {
6542 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6543 f1_hack = 1;
6544 return 1;
6545 }
6546 }
6547 if (Config.HLE)
6548 {
6549 if (start <= psxRegs.biosBranchCheck && psxRegs.biosBranchCheck < start + i*4)
6550 {
6551 i = (psxRegs.biosBranchCheck - start) / 4u + 23;
6552 if (dops[i].is_jump && !dops[i+1].bt)
6553 {
6554 force_intcall(i);
6555 dops[i+1].is_ds = 0;
6556 }
6557 }
6558 }
6559 return 0;
6560}
6561
6562static int is_ld_use_hazard(const struct decoded_insn *op_ld,
6563 const struct decoded_insn *op)
6564{
6565 if (op_ld->rt1 == 0 || (op_ld->rt1 != op->rs1 && op_ld->rt1 != op->rs2))
6566 return 0;
6567 if (op_ld->itype == LOADLR && op->itype == LOADLR)
6568 return op_ld->rt1 == op_ld->rs1;
6569 return op->itype != CJUMP && op->itype != SJUMP;
6570}
6571
6572static void disassemble_one(int i, u_int src)
6573{
6574 unsigned int type, op, op2, op3;
6575 enum ls_width_type ls_type = LS_32;
6576 memset(&dops[i], 0, sizeof(dops[i]));
6577 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6578 cinfo[i].ba = -1;
6579 cinfo[i].addr = -1;
6580 dops[i].opcode = op = src >> 26;
6581 op2 = 0;
6582 type = INTCALL;
6583 set_mnemonic(i, "???");
6584 switch(op)
6585 {
6586 case 0x00: set_mnemonic(i, "special");
6587 op2 = src & 0x3f;
6588 switch(op2)
6589 {
6590 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6591 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6592 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6593 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6594 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6595 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6596 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6597 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6598 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6599 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6600 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6601 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6602 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6603 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6604 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6605 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6606 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6607 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6608 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6609 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6610 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6611 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6612 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6613 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6614 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6615 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6616 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6617 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6618 }
6619 break;
6620 case 0x01: set_mnemonic(i, "regimm");
6621 type = SJUMP;
6622 op2 = (src >> 16) & 0x1f;
6623 switch(op2)
6624 {
6625 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6626 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6627 default:
6628 if (op2 & 1)
6629 set_mnemonic(i, "BGEZ");
6630 else
6631 set_mnemonic(i, "BLTZ");
6632 }
6633 break;
6634 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6635 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6636 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6637 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6638 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6639 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6640 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6641 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6642 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6643 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6644 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6645 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6646 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6647 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6648 case 0x10: set_mnemonic(i, "COP0");
6649 op2 = (src >> 21) & 0x1f;
6650 if (op2 & 0x10) {
6651 op3 = src & 0x1f;
6652 switch (op3)
6653 {
6654 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6655 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6656 default: type = OTHER; break;
6657 }
6658 break;
6659 }
6660 switch(op2)
6661 {
6662 u32 rd;
6663 case 0x00:
6664 set_mnemonic(i, "MFC0");
6665 rd = (src >> 11) & 0x1F;
6666 if (!(0x00000417u & (1u << rd)))
6667 type = COP0;
6668 break;
6669 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6670 case 0x02:
6671 case 0x06: type = INTCALL; break;
6672 default: type = OTHER; break;
6673 }
6674 break;
6675 case 0x11: set_mnemonic(i, "COP1");
6676 op2 = (src >> 21) & 0x1f;
6677 break;
6678 case 0x12: set_mnemonic(i, "COP2");
6679 op2 = (src >> 21) & 0x1f;
6680 if (op2 & 0x10) {
6681 type = OTHER;
6682 if (gte_handlers[src & 0x3f] != NULL) {
6683#ifdef DISASM
6684 if (gte_regnames[src & 0x3f] != NULL)
6685 strcpy(insn[i], gte_regnames[src & 0x3f]);
6686 else
6687 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
6688#endif
6689 type = C2OP;
6690 }
6691 }
6692 else switch(op2)
6693 {
6694 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6695 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6696 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6697 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6698 }
6699 break;
6700 case 0x13: set_mnemonic(i, "COP3");
6701 op2 = (src >> 21) & 0x1f;
6702 break;
6703 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6704 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6705 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6706 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6707 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6708 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6709 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6710 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6711 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6712 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6713 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6714 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6715 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6716 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
6717 case 0x3B:
6718 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
6719 set_mnemonic(i, "HLECALL");
6720 type = HLECALL;
6721 }
6722 break;
6723 default:
6724 break;
6725 }
6726 if (type == INTCALL)
6727 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
6728 dops[i].itype = type;
6729 dops[i].opcode2 = op2;
6730 dops[i].ls_type = ls_type;
6731 /* Get registers/immediates */
6732 dops[i].use_lt1=0;
6733 gte_rs[i]=gte_rt[i]=0;
6734 dops[i].rs1 = 0;
6735 dops[i].rs2 = 0;
6736 dops[i].rt1 = 0;
6737 dops[i].rt2 = 0;
6738 switch(type) {
6739 case LOAD:
6740 dops[i].rs1 = (src >> 21) & 0x1f;
6741 dops[i].rt1 = (src >> 16) & 0x1f;
6742 cinfo[i].imm = (short)src;
6743 break;
6744 case STORE:
6745 case STORELR:
6746 dops[i].rs1 = (src >> 21) & 0x1f;
6747 dops[i].rs2 = (src >> 16) & 0x1f;
6748 cinfo[i].imm = (short)src;
6749 break;
6750 case LOADLR:
6751 // LWL/LWR only load part of the register,
6752 // therefore the target register must be treated as a source too
6753 dops[i].rs1 = (src >> 21) & 0x1f;
6754 dops[i].rs2 = (src >> 16) & 0x1f;
6755 dops[i].rt1 = (src >> 16) & 0x1f;
6756 cinfo[i].imm = (short)src;
6757 break;
6758 case IMM16:
6759 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6760 else dops[i].rs1 = (src >> 21) & 0x1f;
6761 dops[i].rs2 = 0;
6762 dops[i].rt1 = (src >> 16) & 0x1f;
6763 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6764 cinfo[i].imm = (unsigned short)src;
6765 }else{
6766 cinfo[i].imm = (short)src;
6767 }
6768 break;
6769 case UJUMP:
6770 // The JAL instruction writes to r31.
6771 if (op&1) {
6772 dops[i].rt1=31;
6773 }
6774 dops[i].rs2=CCREG;
6775 break;
6776 case RJUMP:
6777 dops[i].rs1 = (src >> 21) & 0x1f;
6778 // The JALR instruction writes to rd.
6779 if (op2&1) {
6780 dops[i].rt1 = (src >> 11) & 0x1f;
6781 }
6782 dops[i].rs2=CCREG;
6783 break;
6784 case CJUMP:
6785 dops[i].rs1 = (src >> 21) & 0x1f;
6786 dops[i].rs2 = (src >> 16) & 0x1f;
6787 if(op&2) { // BGTZ/BLEZ
6788 dops[i].rs2=0;
6789 }
6790 break;
6791 case SJUMP:
6792 dops[i].rs1 = (src >> 21) & 0x1f;
6793 dops[i].rs2 = CCREG;
6794 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6795 dops[i].rt1 = 31;
6796 // NOTE: If the branch is not taken, r31 is still overwritten
6797 }
6798 break;
6799 case ALU:
6800 dops[i].rs1=(src>>21)&0x1f; // source
6801 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6802 dops[i].rt1=(src>>11)&0x1f; // destination
6803 break;
6804 case MULTDIV:
6805 dops[i].rs1=(src>>21)&0x1f; // source
6806 dops[i].rs2=(src>>16)&0x1f; // divisor
6807 dops[i].rt1=HIREG;
6808 dops[i].rt2=LOREG;
6809 break;
6810 case MOV:
6811 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6812 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6813 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6814 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6815 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6816 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
6817 break;
6818 case SHIFT:
6819 dops[i].rs1=(src>>16)&0x1f; // target of shift
6820 dops[i].rs2=(src>>21)&0x1f; // shift amount
6821 dops[i].rt1=(src>>11)&0x1f; // destination
6822 break;
6823 case SHIFTIMM:
6824 dops[i].rs1=(src>>16)&0x1f;
6825 dops[i].rs2=0;
6826 dops[i].rt1=(src>>11)&0x1f;
6827 cinfo[i].imm=(src>>6)&0x1f;
6828 break;
6829 case COP0:
6830 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6831 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6832 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
6833 break;
6834 case COP2:
6835 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6836 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6837 int gr=(src>>11)&0x1F;
6838 switch(op2)
6839 {
6840 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6841 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6842 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6843 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6844 }
6845 break;
6846 case C2LS:
6847 dops[i].rs1=(src>>21)&0x1F;
6848 cinfo[i].imm=(short)src;
6849 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6850 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
6851 break;
6852 case C2OP:
6853 gte_rs[i]=gte_reg_reads[src&0x3f];
6854 gte_rt[i]=gte_reg_writes[src&0x3f];
6855 gte_rt[i]|=1ll<<63; // every op changes flags
6856 if((src&0x3f)==GTE_MVMVA) {
6857 int v = (src >> 15) & 3;
6858 gte_rs[i]&=~0xe3fll;
6859 if(v==3) gte_rs[i]|=0xe00ll;
6860 else gte_rs[i]|=3ll<<(v*2);
6861 }
6862 break;
6863 case SYSCALL:
6864 case HLECALL:
6865 case INTCALL:
6866 dops[i].rs1=CCREG;
6867 break;
6868 default:
6869 break;
6870 }
6871}
6872
6873static noinline void pass1_disassemble(u_int pagelimit)
6874{
6875 int i, j, done = 0, ni_count = 0;
6876 int ds_next = 0;
6877
6878 for (i = 0; !done; i++)
6879 {
6880 int force_j_to_interpreter = 0;
6881 unsigned int type, op, op2;
6882
6883 disassemble_one(i, source[i]);
6884 dops[i].is_ds = ds_next; ds_next = 0;
6885 type = dops[i].itype;
6886 op = dops[i].opcode;
6887 op2 = dops[i].opcode2;
6888
6889 /* Calculate branch target addresses */
6890 if(type==UJUMP)
6891 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6892 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6893 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6894 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6895 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6896 else if(type==CJUMP||type==SJUMP)
6897 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6898
6899 /* simplify always (not)taken branches */
6900 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6901 dops[i].rs1 = dops[i].rs2 = 0;
6902 if (!(op & 1)) {
6903 dops[i].itype = type = UJUMP;
6904 dops[i].rs2 = CCREG;
6905 }
6906 }
6907 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6908 dops[i].itype = type = UJUMP;
6909
6910 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6911 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6912 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
6913 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
6914 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6915 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6916 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
6917 ds_next = dops[i].is_jump;
6918
6919 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6920 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6921 dops[i].may_except = 1;
6922 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6923 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6924 dops[i].may_except = 1;
6925
6926 /* rare messy cases to just pass over to the interpreter */
6927 if (i > 0 && dops[i-1].is_jump) {
6928 j = i - 1;
6929 // branch in delay slot?
6930 if (dops[i].is_jump) {
6931 // don't handle first branch and call interpreter if it's hit
6932 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
6933 force_j_to_interpreter = 1;
6934 }
6935 // load delay detection through a branch
6936 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
6937 const struct decoded_insn *dop = NULL;
6938 int t = -1;
6939 if (cinfo[i-1].ba != -1) {
6940 t = (cinfo[i-1].ba - start) / 4;
6941 if (t < 0 || t > i) {
6942 u_int limit = 0;
6943 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6944 if (mem != NULL) {
6945 disassemble_one(MAXBLOCK - 1, mem[0]);
6946 dop = &dops[MAXBLOCK - 1];
6947 }
6948 }
6949 else
6950 dop = &dops[t];
6951 }
6952 if ((dop && is_ld_use_hazard(&dops[i], dop))
6953 || (!dop && Config.PreciseExceptions)) {
6954 // jump target wants DS result - potential load delay effect
6955 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
6956 force_j_to_interpreter = 1;
6957 if (0 <= t && t < i)
6958 dops[t + 1].bt = 1; // expected return from interpreter
6959 }
6960 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6961 !(i>=3&&dops[i-3].is_jump)) {
6962 // v0 overwrite like this is a sign of trouble, bail out
6963 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6964 force_j_to_interpreter = 1;
6965 }
6966 }
6967 }
6968 else if (i > 0 && dops[i-1].is_delay_load
6969 && is_ld_use_hazard(&dops[i-1], &dops[i])
6970 && (i < 2 || !dops[i-2].is_ujump)) {
6971 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6972 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
6973 if (dops[j-1].rt1 != dops[i-1].rt1)
6974 break;
6975 force_j_to_interpreter = 1;
6976 }
6977 if (force_j_to_interpreter) {
6978 force_intcall(j);
6979 done = 2;
6980 i = j; // don't compile the problematic branch/load/etc
6981 }
6982 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
6983 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
6984 i--;
6985 force_intcall(i);
6986 done = 2;
6987 }
6988 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
6989 dops[i].bt = 1;
6990 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
6991 dops[i].bt = 1;
6992
6993 /* Is this the end of the block? */
6994 if (i > 0 && dops[i-1].is_ujump) {
6995 if (dops[i-1].rt1 == 0) { // not jal
6996 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
6997 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6998 // scan for a branch back to i+1
6999 for (j = t; j < t + 64; j++) {
7000 int tmpop = source[j] >> 26;
7001 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
7002 int t2 = j + 1 + (int)(signed short)source[j];
7003 if (t2 == i + 1) {
7004 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
7005 found_bbranch = 1;
7006 break;
7007 }
7008 }
7009 }
7010 }
7011 if (!found_bbranch)
7012 done = 2;
7013 }
7014 else {
7015 if(stop_after_jal) done=1;
7016 // Stop on BREAK
7017 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7018 }
7019 // Don't recompile stuff that's already compiled
7020 if(check_addr(start+i*4+4)) done=1;
7021 // Don't get too close to the limit
7022 if (i > MAXBLOCK - 64)
7023 done = 1;
7024 }
7025 if (dops[i].itype == HLECALL)
7026 done = 1;
7027 else if (dops[i].itype == INTCALL)
7028 done = 2;
7029 else if (dops[i].is_exception)
7030 done = stop_after_jal ? 1 : 2;
7031 if (done == 2) {
7032 // Does the block continue due to a branch?
7033 for(j=i-1;j>=0;j--)
7034 {
7035 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7036 if(cinfo[j].ba==start+i*4+4) done=j=0;
7037 if(cinfo[j].ba==start+i*4+8) done=j=0;
7038 }
7039 }
7040 //assert(i<MAXBLOCK-1);
7041 if(start+i*4==pagelimit-4) done=1;
7042 assert(start+i*4<pagelimit);
7043 if (i == MAXBLOCK - 2)
7044 done = 1;
7045 // Stop if we're compiling junk
7046 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
7047 done=stop_after_jal=1;
7048 SysPrintf("Disabled speculative precompilation\n");
7049 }
7050 }
7051 while (i > 0 && dops[i-1].is_jump)
7052 i--;
7053 assert(i > 0);
7054 assert(!dops[i-1].is_jump);
7055 slen = i;
7056}
7057
7058// Basic liveness analysis for MIPS registers
7059static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7060{
7061 int i;
7062 uint64_t u,gte_u,b,gte_b;
7063 uint64_t temp_u,temp_gte_u=0;
7064 uint64_t gte_u_unknown=0;
7065 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7066 gte_u_unknown=~0ll;
7067 if(iend==slen-1) {
7068 u=1;
7069 gte_u=gte_u_unknown;
7070 }else{
7071 //u=unneeded_reg[iend+1];
7072 u=1;
7073 gte_u=gte_unneeded[iend+1];
7074 }
7075
7076 for (i=iend;i>=istart;i--)
7077 {
7078 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7079 if(dops[i].is_jump)
7080 {
7081 // If subroutine call, flag return address as a possible branch target
7082 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7083
7084 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7085 {
7086 // Branch out of this block, flush all regs
7087 u=1;
7088 gte_u=gte_u_unknown;
7089 branch_unneeded_reg[i]=u;
7090 // Merge in delay slot
7091 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7092 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7093 u|=1;
7094 gte_u|=gte_rt[i+1];
7095 gte_u&=~gte_rs[i+1];
7096 }
7097 else
7098 {
7099 // Internal branch, flag target
7100 dops[(cinfo[i].ba-start)>>2].bt=1;
7101 if(cinfo[i].ba<=start+i*4) {
7102 // Backward branch
7103 if(dops[i].is_ujump)
7104 {
7105 // Unconditional branch
7106 temp_u=1;
7107 temp_gte_u=0;
7108 } else {
7109 // Conditional branch (not taken case)
7110 temp_u=unneeded_reg[i+2];
7111 temp_gte_u&=gte_unneeded[i+2];
7112 }
7113 // Merge in delay slot
7114 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7115 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7116 temp_u|=1;
7117 temp_gte_u|=gte_rt[i+1];
7118 temp_gte_u&=~gte_rs[i+1];
7119 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7120 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7121 temp_u|=1;
7122 temp_gte_u|=gte_rt[i];
7123 temp_gte_u&=~gte_rs[i];
7124 unneeded_reg[i]=temp_u;
7125 gte_unneeded[i]=temp_gte_u;
7126 // Only go three levels deep. This recursion can take an
7127 // excessive amount of time if there are a lot of nested loops.
7128 if(r<2) {
7129 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
7130 }else{
7131 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7132 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
7133 }
7134 } /*else*/ if(1) {
7135 if (dops[i].is_ujump)
7136 {
7137 // Unconditional branch
7138 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7139 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
7140 branch_unneeded_reg[i]=u;
7141 // Merge in delay slot
7142 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7143 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7144 u|=1;
7145 gte_u|=gte_rt[i+1];
7146 gte_u&=~gte_rs[i+1];
7147 } else {
7148 // Conditional branch
7149 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7150 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
7151 branch_unneeded_reg[i]=b;
7152 // Branch delay slot
7153 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7154 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7155 b|=1;
7156 gte_b|=gte_rt[i+1];
7157 gte_b&=~gte_rs[i+1];
7158 u&=b;
7159 gte_u&=gte_b;
7160 if(i<slen-1) {
7161 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7162 } else {
7163 branch_unneeded_reg[i]=1;
7164 }
7165 }
7166 }
7167 }
7168 }
7169 //u=1; // DEBUG
7170 // Written registers are unneeded
7171 u|=1LL<<dops[i].rt1;
7172 u|=1LL<<dops[i].rt2;
7173 gte_u|=gte_rt[i];
7174 // Accessed registers are needed
7175 u&=~(1LL<<dops[i].rs1);
7176 u&=~(1LL<<dops[i].rs2);
7177 gte_u&=~gte_rs[i];
7178 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7179 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7180 if (dops[i].may_except || dops[i].itype == RFE)
7181 {
7182 // SYSCALL instruction, etc or conditional exception
7183 u=1;
7184 }
7185 // Source-target dependencies
7186 // R0 is always unneeded
7187 u|=1;
7188 // Save it
7189 unneeded_reg[i]=u;
7190 gte_unneeded[i]=gte_u;
7191 /*
7192 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7193 printf("U:");
7194 int r;
7195 for(r=1;r<=CCREG;r++) {
7196 if((unneeded_reg[i]>>r)&1) {
7197 if(r==HIREG) printf(" HI");
7198 else if(r==LOREG) printf(" LO");
7199 else printf(" r%d",r);
7200 }
7201 }
7202 printf("\n");
7203 */
7204 }
7205}
7206
7207static noinline void pass2a_unneeded_other(void)
7208{
7209 int i, j;
7210 for (i = 0; i < slen; i++)
7211 {
7212 // remove redundant alignment checks
7213 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7214 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7215 {
7216 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7217 int mask = ls_type == LS_32 ? 3 : 1;
7218 lsb &= mask;
7219 for (j = i + 1; j < slen; j++) {
7220 if (dops[j].bt || dops[j].is_jump)
7221 break;
7222 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7223 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7224 dops[j].may_except = 0;
7225 if (dops[j].rt1 == base)
7226 break;
7227 }
7228 }
7229 }
7230}
7231
7232static noinline void pass3_register_alloc(u_int addr)
7233{
7234 struct regstat current; // Current register allocations/status
7235 clear_all_regs(current.regmap_entry);
7236 clear_all_regs(current.regmap);
7237 current.wasdirty = current.dirty = 0;
7238 current.u = unneeded_reg[0];
7239 alloc_reg(&current, 0, CCREG);
7240 dirty_reg(&current, CCREG);
7241 current.wasconst = 0;
7242 current.isconst = 0;
7243 current.loadedconst = 0;
7244 current.noevict = 0;
7245 //current.waswritten = 0;
7246 int ds=0;
7247 int cc=0;
7248 int hr;
7249 int i, j;
7250
7251 if (addr & 1) {
7252 // First instruction is delay slot
7253 cc=-1;
7254 dops[1].bt=1;
7255 ds=1;
7256 unneeded_reg[0]=1;
7257 }
7258
7259 for(i=0;i<slen;i++)
7260 {
7261 if(dops[i].bt)
7262 {
7263 for(hr=0;hr<HOST_REGS;hr++)
7264 {
7265 // Is this really necessary?
7266 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7267 }
7268 current.isconst=0;
7269 //current.waswritten=0;
7270 }
7271
7272 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7273 regs[i].wasconst=current.isconst;
7274 regs[i].wasdirty=current.dirty;
7275 regs[i].dirty=0;
7276 regs[i].u=0;
7277 regs[i].isconst=0;
7278 regs[i].loadedconst=0;
7279 if (!dops[i].is_jump) {
7280 if(i+1<slen) {
7281 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7282 current.u|=1;
7283 } else {
7284 current.u=1;
7285 }
7286 } else {
7287 if(i+1<slen) {
7288 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7289 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7290 current.u|=1;
7291 } else {
7292 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7293 abort();
7294 }
7295 }
7296 assert(dops[i].is_ds == ds);
7297 if(ds) {
7298 ds=0; // Skip delay slot, already allocated as part of branch
7299 // ...but we need to alloc it in case something jumps here
7300 if(i+1<slen) {
7301 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7302 }else{
7303 current.u=branch_unneeded_reg[i-1];
7304 }
7305 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7306 current.u|=1;
7307 struct regstat temp;
7308 memcpy(&temp,&current,sizeof(current));
7309 temp.wasdirty=temp.dirty;
7310 // TODO: Take into account unconditional branches, as below
7311 delayslot_alloc(&temp,i);
7312 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7313 regs[i].wasdirty=temp.wasdirty;
7314 regs[i].dirty=temp.dirty;
7315 regs[i].isconst=0;
7316 regs[i].wasconst=0;
7317 current.isconst=0;
7318 // Create entry (branch target) regmap
7319 for(hr=0;hr<HOST_REGS;hr++)
7320 {
7321 int r=temp.regmap[hr];
7322 if(r>=0) {
7323 if(r!=regmap_pre[i][hr]) {
7324 regs[i].regmap_entry[hr]=-1;
7325 }
7326 else
7327 {
7328 assert(r < 64);
7329 if((current.u>>r)&1) {
7330 regs[i].regmap_entry[hr]=-1;
7331 regs[i].regmap[hr]=-1;
7332 //Don't clear regs in the delay slot as the branch might need them
7333 //current.regmap[hr]=-1;
7334 }else
7335 regs[i].regmap_entry[hr]=r;
7336 }
7337 } else {
7338 // First instruction expects CCREG to be allocated
7339 if(i==0&&hr==HOST_CCREG)
7340 regs[i].regmap_entry[hr]=CCREG;
7341 else
7342 regs[i].regmap_entry[hr]=-1;
7343 }
7344 }
7345 }
7346 else { // Not delay slot
7347 current.noevict = 0;
7348 switch(dops[i].itype) {
7349 case UJUMP:
7350 //current.isconst=0; // DEBUG
7351 //current.wasconst=0; // DEBUG
7352 //regs[i].wasconst=0; // DEBUG
7353 clear_const(&current,dops[i].rt1);
7354 alloc_cc(&current,i);
7355 dirty_reg(&current,CCREG);
7356 if (dops[i].rt1==31) {
7357 alloc_reg(&current,i,31);
7358 dirty_reg(&current,31);
7359 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7360 //assert(dops[i+1].rt1!=dops[i].rt1);
7361 #ifdef REG_PREFETCH
7362 alloc_reg(&current,i,PTEMP);
7363 #endif
7364 }
7365 dops[i].ooo=1;
7366 delayslot_alloc(&current,i+1);
7367 //current.isconst=0; // DEBUG
7368 ds=1;
7369 break;
7370 case RJUMP:
7371 //current.isconst=0;
7372 //current.wasconst=0;
7373 //regs[i].wasconst=0;
7374 clear_const(&current,dops[i].rs1);
7375 clear_const(&current,dops[i].rt1);
7376 alloc_cc(&current,i);
7377 dirty_reg(&current,CCREG);
7378 if (!ds_writes_rjump_rs(i)) {
7379 alloc_reg(&current,i,dops[i].rs1);
7380 if (dops[i].rt1!=0) {
7381 alloc_reg(&current,i,dops[i].rt1);
7382 dirty_reg(&current,dops[i].rt1);
7383 #ifdef REG_PREFETCH
7384 alloc_reg(&current,i,PTEMP);
7385 #endif
7386 }
7387 #ifdef USE_MINI_HT
7388 if(dops[i].rs1==31) { // JALR
7389 alloc_reg(&current,i,RHASH);
7390 alloc_reg(&current,i,RHTBL);
7391 }
7392 #endif
7393 delayslot_alloc(&current,i+1);
7394 } else {
7395 // The delay slot overwrites our source register,
7396 // allocate a temporary register to hold the old value.
7397 current.isconst=0;
7398 current.wasconst=0;
7399 regs[i].wasconst=0;
7400 delayslot_alloc(&current,i+1);
7401 current.isconst=0;
7402 alloc_reg(&current,i,RTEMP);
7403 }
7404 //current.isconst=0; // DEBUG
7405 dops[i].ooo=1;
7406 ds=1;
7407 break;
7408 case CJUMP:
7409 //current.isconst=0;
7410 //current.wasconst=0;
7411 //regs[i].wasconst=0;
7412 clear_const(&current,dops[i].rs1);
7413 clear_const(&current,dops[i].rs2);
7414 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7415 {
7416 alloc_cc(&current,i);
7417 dirty_reg(&current,CCREG);
7418 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7419 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7420 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7421 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7422 // The delay slot overwrites one of our conditions.
7423 // Allocate the branch condition registers instead.
7424 current.isconst=0;
7425 current.wasconst=0;
7426 regs[i].wasconst=0;
7427 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7428 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7429 }
7430 else
7431 {
7432 dops[i].ooo=1;
7433 delayslot_alloc(&current,i+1);
7434 }
7435 }
7436 else
7437 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7438 {
7439 alloc_cc(&current,i);
7440 dirty_reg(&current,CCREG);
7441 alloc_reg(&current,i,dops[i].rs1);
7442 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7443 // The delay slot overwrites one of our conditions.
7444 // Allocate the branch condition registers instead.
7445 current.isconst=0;
7446 current.wasconst=0;
7447 regs[i].wasconst=0;
7448 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7449 }
7450 else
7451 {
7452 dops[i].ooo=1;
7453 delayslot_alloc(&current,i+1);
7454 }
7455 }
7456 else
7457 // Don't alloc the delay slot yet because we might not execute it
7458 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7459 {
7460 current.isconst=0;
7461 current.wasconst=0;
7462 regs[i].wasconst=0;
7463 alloc_cc(&current,i);
7464 dirty_reg(&current,CCREG);
7465 alloc_reg(&current,i,dops[i].rs1);
7466 alloc_reg(&current,i,dops[i].rs2);
7467 }
7468 else
7469 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7470 {
7471 current.isconst=0;
7472 current.wasconst=0;
7473 regs[i].wasconst=0;
7474 alloc_cc(&current,i);
7475 dirty_reg(&current,CCREG);
7476 alloc_reg(&current,i,dops[i].rs1);
7477 }
7478 ds=1;
7479 //current.isconst=0;
7480 break;
7481 case SJUMP:
7482 clear_const(&current,dops[i].rs1);
7483 clear_const(&current,dops[i].rt1);
7484 {
7485 alloc_cc(&current,i);
7486 dirty_reg(&current,CCREG);
7487 alloc_reg(&current,i,dops[i].rs1);
7488 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
7489 alloc_reg(&current,i,31);
7490 dirty_reg(&current,31);
7491 }
7492 if ((dops[i].rs1 &&
7493 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7494 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
7495 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7496 // Allocate the branch condition registers instead.
7497 current.isconst=0;
7498 current.wasconst=0;
7499 regs[i].wasconst=0;
7500 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7501 }
7502 else
7503 {
7504 dops[i].ooo=1;
7505 delayslot_alloc(&current,i+1);
7506 }
7507 }
7508 ds=1;
7509 //current.isconst=0;
7510 break;
7511 case IMM16:
7512 imm16_alloc(&current,i);
7513 break;
7514 case LOAD:
7515 case LOADLR:
7516 load_alloc(&current,i);
7517 break;
7518 case STORE:
7519 case STORELR:
7520 store_alloc(&current,i);
7521 break;
7522 case ALU:
7523 alu_alloc(&current,i);
7524 break;
7525 case SHIFT:
7526 shift_alloc(&current,i);
7527 break;
7528 case MULTDIV:
7529 multdiv_alloc(&current,i);
7530 break;
7531 case SHIFTIMM:
7532 shiftimm_alloc(&current,i);
7533 break;
7534 case MOV:
7535 mov_alloc(&current,i);
7536 break;
7537 case COP0:
7538 cop0_alloc(&current,i);
7539 break;
7540 case RFE:
7541 rfe_alloc(&current,i);
7542 break;
7543 case COP2:
7544 cop2_alloc(&current,i);
7545 break;
7546 case C2LS:
7547 c2ls_alloc(&current,i);
7548 break;
7549 case C2OP:
7550 c2op_alloc(&current,i);
7551 break;
7552 case SYSCALL:
7553 case HLECALL:
7554 case INTCALL:
7555 syscall_alloc(&current,i);
7556 break;
7557 }
7558
7559 // Create entry (branch target) regmap
7560 for(hr=0;hr<HOST_REGS;hr++)
7561 {
7562 int r,or;
7563 r=current.regmap[hr];
7564 if(r>=0) {
7565 if(r!=regmap_pre[i][hr]) {
7566 // TODO: delay slot (?)
7567 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7568 if(or<0||r>=TEMPREG){
7569 regs[i].regmap_entry[hr]=-1;
7570 }
7571 else
7572 {
7573 // Just move it to a different register
7574 regs[i].regmap_entry[hr]=r;
7575 // If it was dirty before, it's still dirty
7576 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
7577 }
7578 }
7579 else
7580 {
7581 // Unneeded
7582 if(r==0){
7583 regs[i].regmap_entry[hr]=0;
7584 }
7585 else
7586 {
7587 assert(r<64);
7588 if((current.u>>r)&1) {
7589 regs[i].regmap_entry[hr]=-1;
7590 //regs[i].regmap[hr]=-1;
7591 current.regmap[hr]=-1;
7592 }else
7593 regs[i].regmap_entry[hr]=r;
7594 }
7595 }
7596 } else {
7597 // Branches expect CCREG to be allocated at the target
7598 if(regmap_pre[i][hr]==CCREG)
7599 regs[i].regmap_entry[hr]=CCREG;
7600 else
7601 regs[i].regmap_entry[hr]=-1;
7602 }
7603 }
7604 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7605 }
7606
7607#if 0 // see do_store_smc_check()
7608 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
7609 current.waswritten|=1<<dops[i-1].rs1;
7610 current.waswritten&=~(1<<dops[i].rt1);
7611 current.waswritten&=~(1<<dops[i].rt2);
7612 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
7613 current.waswritten&=~(1<<dops[i].rs1);
7614#endif
7615
7616 /* Branch post-alloc */
7617 if(i>0)
7618 {
7619 current.wasdirty=current.dirty;
7620 switch(dops[i-1].itype) {
7621 case UJUMP:
7622 memcpy(&branch_regs[i-1],&current,sizeof(current));
7623 branch_regs[i-1].isconst=0;
7624 branch_regs[i-1].wasconst=0;
7625 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7626 alloc_cc(&branch_regs[i-1],i-1);
7627 dirty_reg(&branch_regs[i-1],CCREG);
7628 if(dops[i-1].rt1==31) { // JAL
7629 alloc_reg(&branch_regs[i-1],i-1,31);
7630 dirty_reg(&branch_regs[i-1],31);
7631 }
7632 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7633 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7634 break;
7635 case RJUMP:
7636 memcpy(&branch_regs[i-1],&current,sizeof(current));
7637 branch_regs[i-1].isconst=0;
7638 branch_regs[i-1].wasconst=0;
7639 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7640 alloc_cc(&branch_regs[i-1],i-1);
7641 dirty_reg(&branch_regs[i-1],CCREG);
7642 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7643 if(dops[i-1].rt1!=0) { // JALR
7644 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7645 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7646 }
7647 #ifdef USE_MINI_HT
7648 if(dops[i-1].rs1==31) { // JALR
7649 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7650 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7651 }
7652 #endif
7653 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7654 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7655 break;
7656 case CJUMP:
7657 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7658 {
7659 alloc_cc(&current,i-1);
7660 dirty_reg(&current,CCREG);
7661 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7662 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7663 // The delay slot overwrote one of our conditions
7664 // Delay slot goes after the test (in order)
7665 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7666 current.u|=1;
7667 delayslot_alloc(&current,i);
7668 current.isconst=0;
7669 }
7670 else
7671 {
7672 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7673 // Alloc the branch condition registers
7674 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7675 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
7676 }
7677 memcpy(&branch_regs[i-1],&current,sizeof(current));
7678 branch_regs[i-1].isconst=0;
7679 branch_regs[i-1].wasconst=0;
7680 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7681 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7682 }
7683 else
7684 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7685 {
7686 alloc_cc(&current,i-1);
7687 dirty_reg(&current,CCREG);
7688 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7689 // The delay slot overwrote the branch condition
7690 // Delay slot goes after the test (in order)
7691 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7692 current.u|=1;
7693 delayslot_alloc(&current,i);
7694 current.isconst=0;
7695 }
7696 else
7697 {
7698 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7699 // Alloc the branch condition register
7700 alloc_reg(&current,i-1,dops[i-1].rs1);
7701 }
7702 memcpy(&branch_regs[i-1],&current,sizeof(current));
7703 branch_regs[i-1].isconst=0;
7704 branch_regs[i-1].wasconst=0;
7705 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7706 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7707 }
7708 break;
7709 case SJUMP:
7710 {
7711 alloc_cc(&current,i-1);
7712 dirty_reg(&current,CCREG);
7713 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7714 // The delay slot overwrote the branch condition
7715 // Delay slot goes after the test (in order)
7716 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7717 current.u|=1;
7718 delayslot_alloc(&current,i);
7719 current.isconst=0;
7720 }
7721 else
7722 {
7723 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7724 // Alloc the branch condition register
7725 alloc_reg(&current,i-1,dops[i-1].rs1);
7726 }
7727 memcpy(&branch_regs[i-1],&current,sizeof(current));
7728 branch_regs[i-1].isconst=0;
7729 branch_regs[i-1].wasconst=0;
7730 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7731 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7732 }
7733 break;
7734 }
7735
7736 if (dops[i-1].is_ujump)
7737 {
7738 if(dops[i-1].rt1==31) // JAL/JALR
7739 {
7740 // Subroutine call will return here, don't alloc any registers
7741 current.dirty=0;
7742 clear_all_regs(current.regmap);
7743 alloc_reg(&current,i,CCREG);
7744 dirty_reg(&current,CCREG);
7745 }
7746 else if(i+1<slen)
7747 {
7748 // Internal branch will jump here, match registers to caller
7749 current.dirty=0;
7750 clear_all_regs(current.regmap);
7751 alloc_reg(&current,i,CCREG);
7752 dirty_reg(&current,CCREG);
7753 for(j=i-1;j>=0;j--)
7754 {
7755 if(cinfo[j].ba==start+i*4+4) {
7756 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7757 current.dirty=branch_regs[j].dirty;
7758 break;
7759 }
7760 }
7761 while(j>=0) {
7762 if(cinfo[j].ba==start+i*4+4) {
7763 for(hr=0;hr<HOST_REGS;hr++) {
7764 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7765 current.regmap[hr]=-1;
7766 }
7767 current.dirty&=branch_regs[j].dirty;
7768 }
7769 }
7770 j--;
7771 }
7772 }
7773 }
7774 }
7775
7776 // Count cycles in between branches
7777 cinfo[i].ccadj = CLOCK_ADJUST(cc);
7778 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
7779 {
7780 cc=0;
7781 }
7782#if !defined(DRC_DBG)
7783 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
7784 {
7785 // this should really be removed since the real stalls have been implemented,
7786 // but doing so causes sizeable perf regression against the older version
7787 u_int gtec = gte_cycletab[source[i] & 0x3f];
7788 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7789 }
7790 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7791 {
7792 cc+=4;
7793 }
7794 else if(dops[i].itype==C2LS)
7795 {
7796 // same as with C2OP
7797 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7798 }
7799#endif
7800 else
7801 {
7802 cc++;
7803 }
7804
7805 if(!dops[i].is_ds) {
7806 regs[i].dirty=current.dirty;
7807 regs[i].isconst=current.isconst;
7808 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7809 }
7810 for(hr=0;hr<HOST_REGS;hr++) {
7811 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7812 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7813 regs[i].wasconst&=~(1<<hr);
7814 }
7815 }
7816 }
7817 //regs[i].waswritten=current.waswritten;
7818 }
7819}
7820
7821static noinline void pass4_cull_unused_regs(void)
7822{
7823 u_int last_needed_regs[4] = {0,0,0,0};
7824 u_int nr=0;
7825 int i;
7826
7827 for (i=slen-1;i>=0;i--)
7828 {
7829 int hr;
7830 __builtin_prefetch(regs[i-2].regmap);
7831 if(dops[i].is_jump)
7832 {
7833 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7834 {
7835 // Branch out of this block, don't need anything
7836 nr=0;
7837 }
7838 else
7839 {
7840 // Internal branch
7841 // Need whatever matches the target
7842 nr=0;
7843 int t=(cinfo[i].ba-start)>>2;
7844 for(hr=0;hr<HOST_REGS;hr++)
7845 {
7846 if(regs[i].regmap_entry[hr]>=0) {
7847 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7848 }
7849 }
7850 }
7851 // Conditional branch may need registers for following instructions
7852 if (!dops[i].is_ujump)
7853 {
7854 if(i<slen-2) {
7855 nr |= last_needed_regs[(i+2) & 3];
7856 for(hr=0;hr<HOST_REGS;hr++)
7857 {
7858 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7859 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7860 }
7861 }
7862 }
7863 // Don't need stuff which is overwritten
7864 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7865 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7866 // Merge in delay slot
7867 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7868 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7869 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7870 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7871 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7872 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7873 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7874 nr |= get_regm(regmap_pre[i], ROREG);
7875 nr |= get_regm(regs[i].regmap_entry, ROREG);
7876 }
7877 if (dops[i+1].is_store) {
7878 nr |= get_regm(regmap_pre[i], INVCP);
7879 nr |= get_regm(regs[i].regmap_entry, INVCP);
7880 }
7881 }
7882 else if (dops[i].is_exception)
7883 {
7884 // SYSCALL instruction, etc
7885 nr=0;
7886 }
7887 else // Non-branch
7888 {
7889 if(i<slen-1) {
7890 for(hr=0;hr<HOST_REGS;hr++) {
7891 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7892 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7893 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7894 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7895 }
7896 }
7897 }
7898 // Overwritten registers are not needed
7899 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7900 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7901 nr &= ~get_regm(regs[i].regmap, FTEMP);
7902 // Source registers are needed
7903 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7904 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7905 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7906 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7907 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7908 nr |= get_regm(regmap_pre[i], ROREG);
7909 nr |= get_regm(regs[i].regmap_entry, ROREG);
7910 }
7911 if (dops[i].is_store) {
7912 nr |= get_regm(regmap_pre[i], INVCP);
7913 nr |= get_regm(regs[i].regmap_entry, INVCP);
7914 }
7915
7916 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7917 for(hr=0;hr<HOST_REGS;hr++)
7918 {
7919 // Don't store a register immediately after writing it,
7920 // may prevent dual-issue.
7921 // But do so if this is a branch target, otherwise we
7922 // might have to load the register before the branch.
7923 if((regs[i].wasdirty>>hr)&1) {
7924 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7925 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7926 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7927 }
7928 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7929 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7930 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7931 }
7932 }
7933 }
7934 // Cycle count is needed at branches. Assume it is needed at the target too.
7935 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
7936 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7937 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7938 }
7939 // Save it
7940 last_needed_regs[i & 3] = nr;
7941
7942 // Deallocate unneeded registers
7943 for(hr=0;hr<HOST_REGS;hr++)
7944 {
7945 if(!((nr>>hr)&1)) {
7946 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7947 if(dops[i].is_jump)
7948 {
7949 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7950 if (dops[i+1].is_load || dops[i+1].is_store)
7951 map1 = ROREG;
7952 if (dops[i+1].is_store)
7953 map2 = INVCP;
7954 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7955 temp = FTEMP;
7956 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7957 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7958 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7959 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7960 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7961 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7962 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7963 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7964 {
7965 regs[i].regmap[hr]=-1;
7966 regs[i].isconst&=~(1<<hr);
7967 regs[i].dirty&=~(1<<hr);
7968 regs[i+1].wasdirty&=~(1<<hr);
7969 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7970 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7971 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7972 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7973 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7974 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7975 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7976 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7977 {
7978 branch_regs[i].regmap[hr]=-1;
7979 branch_regs[i].regmap_entry[hr]=-1;
7980 if (!dops[i].is_ujump)
7981 {
7982 if (i < slen-2) {
7983 regmap_pre[i+2][hr]=-1;
7984 regs[i+2].wasconst&=~(1<<hr);
7985 }
7986 }
7987 }
7988 }
7989 }
7990 else
7991 {
7992 // Non-branch
7993 if(i>0)
7994 {
7995 int map1 = -1, map2 = -1, temp=-1;
7996 if (dops[i].is_load || dops[i].is_store)
7997 map1 = ROREG;
7998 if (dops[i].is_store)
7999 map2 = INVCP;
8000 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8001 temp = FTEMP;
8002 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8003 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8004 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8005 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8006 regs[i].regmap[hr] != CCREG)
8007 {
8008 if(i<slen-1&&!dops[i].is_ds) {
8009 assert(regs[i].regmap[hr]<64);
8010 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8011 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8012 {
8013 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8014 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8015 }
8016 regmap_pre[i+1][hr]=-1;
8017 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8018 regs[i+1].wasconst&=~(1<<hr);
8019 }
8020 regs[i].regmap[hr]=-1;
8021 regs[i].isconst&=~(1<<hr);
8022 regs[i].dirty&=~(1<<hr);
8023 regs[i+1].wasdirty&=~(1<<hr);
8024 }
8025 }
8026 }
8027 } // if needed
8028 } // for hr
8029 }
8030}
8031
8032// If a register is allocated during a loop, try to allocate it for the
8033// entire loop, if possible. This avoids loading/storing registers
8034// inside of the loop.
8035static noinline void pass5a_preallocate1(void)
8036{
8037 int i, j, hr;
8038 signed char f_regmap[HOST_REGS];
8039 clear_all_regs(f_regmap);
8040 for(i=0;i<slen-1;i++)
8041 {
8042 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8043 {
8044 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
8045 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8046 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8047 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8048 ||dops[i+1].itype==SHIFT
8049 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8050 {
8051 int t=(cinfo[i].ba-start)>>2;
8052 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8053 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8054 for(hr=0;hr<HOST_REGS;hr++)
8055 {
8056 if(regs[i].regmap[hr]>=0) {
8057 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8058 // dealloc old register
8059 int n;
8060 for(n=0;n<HOST_REGS;n++)
8061 {
8062 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8063 }
8064 // and alloc new one
8065 f_regmap[hr]=regs[i].regmap[hr];
8066 }
8067 }
8068 if(branch_regs[i].regmap[hr]>=0) {
8069 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8070 // dealloc old register
8071 int n;
8072 for(n=0;n<HOST_REGS;n++)
8073 {
8074 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8075 }
8076 // and alloc new one
8077 f_regmap[hr]=branch_regs[i].regmap[hr];
8078 }
8079 }
8080 if(dops[i].ooo) {
8081 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
8082 f_regmap[hr]=branch_regs[i].regmap[hr];
8083 }else{
8084 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
8085 f_regmap[hr]=branch_regs[i].regmap[hr];
8086 }
8087 // Avoid dirty->clean transition
8088 #ifdef DESTRUCTIVE_WRITEBACK
8089 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8090 #endif
8091 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8092 // case above, however it's always a good idea. We can't hoist the
8093 // load if the register was already allocated, so there's no point
8094 // wasting time analyzing most of these cases. It only "succeeds"
8095 // when the mapping was different and the load can be replaced with
8096 // a mov, which is of negligible benefit. So such cases are
8097 // skipped below.
8098 if(f_regmap[hr]>0) {
8099 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8100 int r=f_regmap[hr];
8101 for(j=t;j<=i;j++)
8102 {
8103 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8104 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8105 assert(r < 64);
8106 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8107 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8108 int k;
8109 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8110 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8111 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8112 k=i;
8113 while(k>1&&regs[k-1].regmap[hr]==-1) {
8114 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8115 //printf("no free regs for store %x\n",start+(k-1)*4);
8116 break;
8117 }
8118 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8119 //printf("no-match due to different register\n");
8120 break;
8121 }
8122 if (dops[k-2].is_jump) {
8123 //printf("no-match due to branch\n");
8124 break;
8125 }
8126 // call/ret fast path assumes no registers allocated
8127 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8128 break;
8129 }
8130 k--;
8131 }
8132 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8133 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8134 while(k<i) {
8135 regs[k].regmap_entry[hr]=f_regmap[hr];
8136 regs[k].regmap[hr]=f_regmap[hr];
8137 regmap_pre[k+1][hr]=f_regmap[hr];
8138 regs[k].wasdirty&=~(1<<hr);
8139 regs[k].dirty&=~(1<<hr);
8140 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8141 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8142 regs[k].wasconst&=~(1<<hr);
8143 regs[k].isconst&=~(1<<hr);
8144 k++;
8145 }
8146 }
8147 else {
8148 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8149 break;
8150 }
8151 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8152 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8153 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8154 regs[i].regmap_entry[hr]=f_regmap[hr];
8155 regs[i].regmap[hr]=f_regmap[hr];
8156 regs[i].wasdirty&=~(1<<hr);
8157 regs[i].dirty&=~(1<<hr);
8158 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8159 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8160 regs[i].wasconst&=~(1<<hr);
8161 regs[i].isconst&=~(1<<hr);
8162 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8163 branch_regs[i].wasdirty&=~(1<<hr);
8164 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8165 branch_regs[i].regmap[hr]=f_regmap[hr];
8166 branch_regs[i].dirty&=~(1<<hr);
8167 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8168 branch_regs[i].wasconst&=~(1<<hr);
8169 branch_regs[i].isconst&=~(1<<hr);
8170 if (!dops[i].is_ujump) {
8171 regmap_pre[i+2][hr]=f_regmap[hr];
8172 regs[i+2].wasdirty&=~(1<<hr);
8173 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
8174 }
8175 }
8176 }
8177 for(k=t;k<j;k++) {
8178 // Alloc register clean at beginning of loop,
8179 // but may dirty it in pass 6
8180 regs[k].regmap_entry[hr]=f_regmap[hr];
8181 regs[k].regmap[hr]=f_regmap[hr];
8182 regs[k].dirty&=~(1<<hr);
8183 regs[k].wasconst&=~(1<<hr);
8184 regs[k].isconst&=~(1<<hr);
8185 if (dops[k].is_jump) {
8186 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8187 branch_regs[k].regmap[hr]=f_regmap[hr];
8188 branch_regs[k].dirty&=~(1<<hr);
8189 branch_regs[k].wasconst&=~(1<<hr);
8190 branch_regs[k].isconst&=~(1<<hr);
8191 if (!dops[k].is_ujump) {
8192 regmap_pre[k+2][hr]=f_regmap[hr];
8193 regs[k+2].wasdirty&=~(1<<hr);
8194 }
8195 }
8196 else
8197 {
8198 regmap_pre[k+1][hr]=f_regmap[hr];
8199 regs[k+1].wasdirty&=~(1<<hr);
8200 }
8201 }
8202 if(regs[j].regmap[hr]==f_regmap[hr])
8203 regs[j].regmap_entry[hr]=f_regmap[hr];
8204 break;
8205 }
8206 if(j==i) break;
8207 if(regs[j].regmap[hr]>=0)
8208 break;
8209 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8210 //printf("no-match due to different register\n");
8211 break;
8212 }
8213 if (dops[j].is_ujump)
8214 {
8215 // Stop on unconditional branch
8216 break;
8217 }
8218 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8219 {
8220 if(dops[j].ooo) {
8221 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
8222 break;
8223 }else{
8224 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
8225 break;
8226 }
8227 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8228 //printf("no-match due to different register (branch)\n");
8229 break;
8230 }
8231 }
8232 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8233 //printf("No free regs for store %x\n",start+j*4);
8234 break;
8235 }
8236 assert(f_regmap[hr]<64);
8237 }
8238 }
8239 }
8240 }
8241 }
8242 }else{
8243 // Non branch or undetermined branch target
8244 for(hr=0;hr<HOST_REGS;hr++)
8245 {
8246 if(hr!=EXCLUDE_REG) {
8247 if(regs[i].regmap[hr]>=0) {
8248 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8249 // dealloc old register
8250 int n;
8251 for(n=0;n<HOST_REGS;n++)
8252 {
8253 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8254 }
8255 // and alloc new one
8256 f_regmap[hr]=regs[i].regmap[hr];
8257 }
8258 }
8259 }
8260 }
8261 // Try to restore cycle count at branch targets
8262 if(dops[i].bt) {
8263 for(j=i;j<slen-1;j++) {
8264 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8265 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8266 //printf("no free regs for store %x\n",start+j*4);
8267 break;
8268 }
8269 }
8270 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8271 int k=i;
8272 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8273 while(k<j) {
8274 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8275 regs[k].regmap[HOST_CCREG]=CCREG;
8276 regmap_pre[k+1][HOST_CCREG]=CCREG;
8277 regs[k+1].wasdirty|=1<<HOST_CCREG;
8278 regs[k].dirty|=1<<HOST_CCREG;
8279 regs[k].wasconst&=~(1<<HOST_CCREG);
8280 regs[k].isconst&=~(1<<HOST_CCREG);
8281 k++;
8282 }
8283 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8284 }
8285 // Work backwards from the branch target
8286 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8287 {
8288 //printf("Extend backwards\n");
8289 int k;
8290 k=i;
8291 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8292 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8293 //printf("no free regs for store %x\n",start+(k-1)*4);
8294 break;
8295 }
8296 k--;
8297 }
8298 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8299 //printf("Extend CC, %x ->\n",start+k*4);
8300 while(k<=i) {
8301 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8302 regs[k].regmap[HOST_CCREG]=CCREG;
8303 regmap_pre[k+1][HOST_CCREG]=CCREG;
8304 regs[k+1].wasdirty|=1<<HOST_CCREG;
8305 regs[k].dirty|=1<<HOST_CCREG;
8306 regs[k].wasconst&=~(1<<HOST_CCREG);
8307 regs[k].isconst&=~(1<<HOST_CCREG);
8308 k++;
8309 }
8310 }
8311 else {
8312 //printf("Fail Extend CC, %x ->\n",start+k*4);
8313 }
8314 }
8315 }
8316 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
8317 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8318 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
8319 {
8320 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8321 }
8322 }
8323 }
8324}
8325
8326// This allocates registers (if possible) one instruction prior
8327// to use, which can avoid a load-use penalty on certain CPUs.
8328static noinline void pass5b_preallocate2(void)
8329{
8330 int i, hr;
8331 for(i=0;i<slen-1;i++)
8332 {
8333 if (!i || !dops[i-1].is_jump)
8334 {
8335 if(!dops[i+1].bt)
8336 {
8337 int j, can_steal = 1;
8338 for (j = i; j < i + 2; j++) {
8339 int free_regs = 0;
8340 if (cinfo[j].min_free_regs == 0)
8341 continue;
8342 for (hr = 0; hr < HOST_REGS; hr++)
8343 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8344 free_regs++;
8345 if (free_regs <= cinfo[j].min_free_regs) {
8346 can_steal = 0;
8347 break;
8348 }
8349 }
8350 if (!can_steal)
8351 continue;
8352 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8353 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
8354 {
8355 if(dops[i+1].rs1) {
8356 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8357 {
8358 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8359 {
8360 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8361 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8362 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8363 regs[i].isconst&=~(1<<hr);
8364 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8365 constmap[i][hr]=constmap[i+1][hr];
8366 regs[i+1].wasdirty&=~(1<<hr);
8367 regs[i].dirty&=~(1<<hr);
8368 }
8369 }
8370 }
8371 if(dops[i+1].rs2) {
8372 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8373 {
8374 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8375 {
8376 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8377 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8378 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8379 regs[i].isconst&=~(1<<hr);
8380 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8381 constmap[i][hr]=constmap[i+1][hr];
8382 regs[i+1].wasdirty&=~(1<<hr);
8383 regs[i].dirty&=~(1<<hr);
8384 }
8385 }
8386 }
8387 // Preload target address for load instruction (non-constant)
8388 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8389 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8390 {
8391 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8392 {
8393 regs[i].regmap[hr]=dops[i+1].rs1;
8394 regmap_pre[i+1][hr]=dops[i+1].rs1;
8395 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8396 regs[i].isconst&=~(1<<hr);
8397 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8398 constmap[i][hr]=constmap[i+1][hr];
8399 regs[i+1].wasdirty&=~(1<<hr);
8400 regs[i].dirty&=~(1<<hr);
8401 }
8402 }
8403 }
8404 // Load source into target register
8405 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8406 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8407 {
8408 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8409 {
8410 regs[i].regmap[hr]=dops[i+1].rs1;
8411 regmap_pre[i+1][hr]=dops[i+1].rs1;
8412 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8413 regs[i].isconst&=~(1<<hr);
8414 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8415 constmap[i][hr]=constmap[i+1][hr];
8416 regs[i+1].wasdirty&=~(1<<hr);
8417 regs[i].dirty&=~(1<<hr);
8418 }
8419 }
8420 }
8421 // Address for store instruction (non-constant)
8422 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
8423 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8424 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8425 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8426 else {
8427 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8428 regs[i+1].isconst&=~(1<<hr);
8429 regs[i+1].dirty&=~(1<<hr);
8430 regs[i+2].wasdirty&=~(1<<hr);
8431 }
8432 assert(hr>=0);
8433 #if 0 // what is this for? double allocs $0 in ps1_rom.bin
8434 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8435 {
8436 regs[i].regmap[hr]=dops[i+1].rs1;
8437 regmap_pre[i+1][hr]=dops[i+1].rs1;
8438 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8439 regs[i].isconst&=~(1<<hr);
8440 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8441 constmap[i][hr]=constmap[i+1][hr];
8442 regs[i+1].wasdirty&=~(1<<hr);
8443 regs[i].dirty&=~(1<<hr);
8444 }
8445 #endif
8446 }
8447 }
8448 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
8449 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8450 int nr;
8451 hr=get_reg(regs[i+1].regmap,FTEMP);
8452 assert(hr>=0);
8453 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8454 {
8455 regs[i].regmap[hr]=dops[i+1].rs1;
8456 regmap_pre[i+1][hr]=dops[i+1].rs1;
8457 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8458 regs[i].isconst&=~(1<<hr);
8459 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8460 constmap[i][hr]=constmap[i+1][hr];
8461 regs[i+1].wasdirty&=~(1<<hr);
8462 regs[i].dirty&=~(1<<hr);
8463 }
8464 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8465 {
8466 // move it to another register
8467 regs[i+1].regmap[hr]=-1;
8468 regmap_pre[i+2][hr]=-1;
8469 regs[i+1].regmap[nr]=FTEMP;
8470 regmap_pre[i+2][nr]=FTEMP;
8471 regs[i].regmap[nr]=dops[i+1].rs1;
8472 regmap_pre[i+1][nr]=dops[i+1].rs1;
8473 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8474 regs[i].isconst&=~(1<<nr);
8475 regs[i+1].isconst&=~(1<<nr);
8476 regs[i].dirty&=~(1<<nr);
8477 regs[i+1].wasdirty&=~(1<<nr);
8478 regs[i+1].dirty&=~(1<<nr);
8479 regs[i+2].wasdirty&=~(1<<nr);
8480 }
8481 }
8482 }
8483 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
8484 hr = -1;
8485 if(dops[i+1].itype==LOAD)
8486 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
8487 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
8488 hr=get_reg(regs[i+1].regmap,FTEMP);
8489 if (dops[i+1].is_store) {
8490 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8491 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8492 }
8493 if(hr>=0&&regs[i].regmap[hr]<0) {
8494 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8495 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8496 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8497 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8498 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8499 regs[i].isconst&=~(1<<hr);
8500 regs[i+1].wasdirty&=~(1<<hr);
8501 regs[i].dirty&=~(1<<hr);
8502 }
8503 }
8504 }
8505 }
8506 }
8507 }
8508 }
8509}
8510
8511// Write back dirty registers as soon as we will no longer modify them,
8512// so that we don't end up with lots of writes at the branches.
8513static noinline void pass6_clean_registers(int istart, int iend, int wr)
8514{
8515 static u_int wont_dirty[MAXBLOCK];
8516 static u_int will_dirty[MAXBLOCK];
8517 int i;
8518 int r;
8519 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8520 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8521 if(iend==slen-1) {
8522 will_dirty_i=will_dirty_next=0;
8523 wont_dirty_i=wont_dirty_next=0;
8524 }else{
8525 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8526 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8527 }
8528 for (i=iend;i>=istart;i--)
8529 {
8530 signed char rregmap_i[RRMAP_SIZE];
8531 u_int hr_candirty = 0;
8532 assert(HOST_REGS < 32);
8533 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8534 __builtin_prefetch(regs[i-1].regmap);
8535 if(dops[i].is_jump)
8536 {
8537 signed char branch_rregmap_i[RRMAP_SIZE];
8538 u_int branch_hr_candirty = 0;
8539 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8540 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
8541 {
8542 // Branch out of this block, flush all regs
8543 will_dirty_i = 0;
8544 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8545 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8546 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8547 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8548 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8549 will_dirty_i &= branch_hr_candirty;
8550 if (dops[i].is_ujump)
8551 {
8552 // Unconditional branch
8553 wont_dirty_i = 0;
8554 // Merge in delay slot (will dirty)
8555 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8556 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8557 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8558 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8559 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8560 will_dirty_i &= hr_candirty;
8561 }
8562 else
8563 {
8564 // Conditional branch
8565 wont_dirty_i = wont_dirty_next;
8566 // Merge in delay slot (will dirty)
8567 // (the original code had no explanation why these 2 are commented out)
8568 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8569 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8570 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8571 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8572 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8573 will_dirty_i &= hr_candirty;
8574 }
8575 // Merge in delay slot (wont dirty)
8576 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8577 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8578 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8579 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8580 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8581 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8582 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8583 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8584 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8585 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8586 wont_dirty_i &= ~(1u << 31);
8587 if(wr) {
8588 #ifndef DESTRUCTIVE_WRITEBACK
8589 branch_regs[i].dirty&=wont_dirty_i;
8590 #endif
8591 branch_regs[i].dirty|=will_dirty_i;
8592 }
8593 }
8594 else
8595 {
8596 // Internal branch
8597 if(cinfo[i].ba<=start+i*4) {
8598 // Backward branch
8599 if (dops[i].is_ujump)
8600 {
8601 // Unconditional branch
8602 temp_will_dirty=0;
8603 temp_wont_dirty=0;
8604 // Merge in delay slot (will dirty)
8605 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8606 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8607 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8608 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8609 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8610 temp_will_dirty &= branch_hr_candirty;
8611 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8612 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8613 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8614 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8615 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8616 temp_will_dirty &= hr_candirty;
8617 } else {
8618 // Conditional branch (not taken case)
8619 temp_will_dirty=will_dirty_next;
8620 temp_wont_dirty=wont_dirty_next;
8621 // Merge in delay slot (will dirty)
8622 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8623 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8624 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8625 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8626 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8627 temp_will_dirty &= branch_hr_candirty;
8628 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8629 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8630 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8631 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8632 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8633 temp_will_dirty &= hr_candirty;
8634 }
8635 // Merge in delay slot (wont dirty)
8636 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8637 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8638 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8639 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8640 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8641 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8642 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8643 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8644 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8645 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8646 temp_wont_dirty &= ~(1u << 31);
8647 // Deal with changed mappings
8648 if(i<iend) {
8649 for(r=0;r<HOST_REGS;r++) {
8650 if(r!=EXCLUDE_REG) {
8651 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8652 temp_will_dirty&=~(1<<r);
8653 temp_wont_dirty&=~(1<<r);
8654 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8655 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8656 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8657 } else {
8658 temp_will_dirty|=1<<r;
8659 temp_wont_dirty|=1<<r;
8660 }
8661 }
8662 }
8663 }
8664 }
8665 if(wr) {
8666 will_dirty[i]=temp_will_dirty;
8667 wont_dirty[i]=temp_wont_dirty;
8668 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
8669 }else{
8670 // Limit recursion. It can take an excessive amount
8671 // of time if there are a lot of nested loops.
8672 will_dirty[(cinfo[i].ba-start)>>2]=0;
8673 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
8674 }
8675 }
8676 /*else*/ if(1)
8677 {
8678 if (dops[i].is_ujump)
8679 {
8680 // Unconditional branch
8681 will_dirty_i=0;
8682 wont_dirty_i=0;
8683 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
8684 for(r=0;r<HOST_REGS;r++) {
8685 if(r!=EXCLUDE_REG) {
8686 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8687 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8688 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8689 }
8690 if(branch_regs[i].regmap[r]>=0) {
8691 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8692 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8693 }
8694 }
8695 }
8696 //}
8697 // Merge in delay slot
8698 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8699 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8700 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8701 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8702 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8703 will_dirty_i &= branch_hr_candirty;
8704 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8705 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8706 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8707 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8708 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8709 will_dirty_i &= hr_candirty;
8710 } else {
8711 // Conditional branch
8712 will_dirty_i=will_dirty_next;
8713 wont_dirty_i=wont_dirty_next;
8714 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
8715 for(r=0;r<HOST_REGS;r++) {
8716 if(r!=EXCLUDE_REG) {
8717 signed char target_reg=branch_regs[i].regmap[r];
8718 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8719 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8720 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8721 }
8722 else if(target_reg>=0) {
8723 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8724 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8725 }
8726 }
8727 }
8728 // Merge in delay slot
8729 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8730 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8731 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8732 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8733 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8734 will_dirty_i &= branch_hr_candirty;
8735 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8736 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8737 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8738 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8739 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8740 will_dirty_i &= hr_candirty;
8741 }
8742 // Merge in delay slot (won't dirty)
8743 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8744 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8745 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8746 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8747 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8748 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8749 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8750 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8751 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8752 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8753 wont_dirty_i &= ~(1u << 31);
8754 if(wr) {
8755 #ifndef DESTRUCTIVE_WRITEBACK
8756 branch_regs[i].dirty&=wont_dirty_i;
8757 #endif
8758 branch_regs[i].dirty|=will_dirty_i;
8759 }
8760 }
8761 }
8762 }
8763 else if (dops[i].is_exception)
8764 {
8765 // SYSCALL instruction, etc
8766 will_dirty_i=0;
8767 wont_dirty_i=0;
8768 }
8769 will_dirty_next=will_dirty_i;
8770 wont_dirty_next=wont_dirty_i;
8771 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8772 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8773 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8774 will_dirty_i &= hr_candirty;
8775 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8776 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8777 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8778 wont_dirty_i &= ~(1u << 31);
8779 if (i > istart && !dops[i].is_jump) {
8780 // Don't store a register immediately after writing it,
8781 // may prevent dual-issue.
8782 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8783 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8784 }
8785 // Save it
8786 will_dirty[i]=will_dirty_i;
8787 wont_dirty[i]=wont_dirty_i;
8788 // Mark registers that won't be dirtied as not dirty
8789 if(wr) {
8790 regs[i].dirty|=will_dirty_i;
8791 #ifndef DESTRUCTIVE_WRITEBACK
8792 regs[i].dirty&=wont_dirty_i;
8793 if(dops[i].is_jump)
8794 {
8795 if (i < iend-1 && !dops[i].is_ujump) {
8796 for(r=0;r<HOST_REGS;r++) {
8797 if(r!=EXCLUDE_REG) {
8798 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8799 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8800 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8801 }
8802 }
8803 }
8804 }
8805 else
8806 {
8807 if(i<iend) {
8808 for(r=0;r<HOST_REGS;r++) {
8809 if(r!=EXCLUDE_REG) {
8810 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8811 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8812 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8813 }
8814 }
8815 }
8816 }
8817 #endif
8818 }
8819 // Deal with changed mappings
8820 temp_will_dirty=will_dirty_i;
8821 temp_wont_dirty=wont_dirty_i;
8822 for(r=0;r<HOST_REGS;r++) {
8823 if(r!=EXCLUDE_REG) {
8824 int nr;
8825 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8826 if(wr) {
8827 #ifndef DESTRUCTIVE_WRITEBACK
8828 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8829 #endif
8830 regs[i].wasdirty|=will_dirty_i&(1<<r);
8831 }
8832 }
8833 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8834 // Register moved to a different register
8835 will_dirty_i&=~(1<<r);
8836 wont_dirty_i&=~(1<<r);
8837 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8838 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8839 if(wr) {
8840 #ifndef DESTRUCTIVE_WRITEBACK
8841 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8842 #endif
8843 regs[i].wasdirty|=will_dirty_i&(1<<r);
8844 }
8845 }
8846 else {
8847 will_dirty_i&=~(1<<r);
8848 wont_dirty_i&=~(1<<r);
8849 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8850 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8851 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8852 } else {
8853 wont_dirty_i|=1<<r;
8854 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8855 }
8856 }
8857 }
8858 }
8859 }
8860}
8861
8862static noinline void pass10_expire_blocks(void)
8863{
8864 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8865 // not sizeof(ndrc->translation_cache) due to vita hack
8866 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8867 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8868 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8869 int hit;
8870
8871 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8872 {
8873 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8874 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8875 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8876 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8877 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8878 (long)(out - ndrc->translation_cache), phase);
8879 }
8880
8881 if (!phase) {
8882 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8883 if (hit) {
8884 do_clear_cache();
8885 #ifdef USE_MINI_HT
8886 memset(mini_ht, -1, sizeof(mini_ht));
8887 #endif
8888 }
8889 }
8890 else
8891 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8892 }
8893}
8894
8895static struct block_info *new_block_info(u_int start, u_int len,
8896 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8897{
8898 struct block_info **b_pptr;
8899 struct block_info *block;
8900 u_int page = get_page(start);
8901
8902 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8903 assert(block);
8904 assert(jump_in_count > 0);
8905 block->source = source;
8906 block->copy = copy;
8907 block->start = start;
8908 block->len = len;
8909 block->reg_sv_flags = 0;
8910 block->tc_offs = beginning - ndrc->translation_cache;
8911 //block->tc_len = out - beginning;
8912 block->is_dirty = 0;
8913 block->inv_near_misses = 0;
8914 block->jump_in_cnt = jump_in_count;
8915
8916 // insert sorted by start mirror-unmasked vaddr
8917 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8918 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8919 block->next = *b_pptr;
8920 *b_pptr = block;
8921 break;
8922 }
8923 }
8924 stat_inc(stat_blocks);
8925 return block;
8926}
8927
8928static int new_recompile_block(u_int addr)
8929{
8930 u_int pagelimit = 0;
8931 u_int state_rflags = 0;
8932 int i;
8933
8934 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8935
8936 if (addr & 3) {
8937 if (addr != hack_addr) {
8938 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8939 hack_addr = addr;
8940 }
8941 return -1;
8942 }
8943
8944 // this is just for speculation
8945 for (i = 1; i < 32; i++) {
8946 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8947 state_rflags |= 1 << i;
8948 }
8949
8950 start = addr;
8951 new_dynarec_did_compile=1;
8952 if (Config.HLE && start == 0x80001000) // hlecall
8953 {
8954 void *beginning = start_block();
8955
8956 emit_movimm(start,0);
8957 emit_writeword(0,&pcaddr);
8958 emit_far_jump(new_dyna_leave);
8959 literal_pool(0);
8960 end_block(beginning);
8961 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8962 block->jump_in[0].vaddr = start;
8963 block->jump_in[0].addr = beginning;
8964 return 0;
8965 }
8966 else if (f1_hack && hack_addr == 0) {
8967 void *beginning = start_block();
8968 emit_movimm(start, 0);
8969 emit_writeword(0, &hack_addr);
8970 emit_readword(&psxRegs.GPR.n.sp, 0);
8971 emit_readptr(&mem_rtab, 1);
8972 emit_shrimm(0, 12, 2);
8973 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8974 emit_addimm(0, 0x18, 0);
8975 emit_adds_ptr(1, 1, 1);
8976 emit_ldr_dualindexed(1, 0, 0);
8977 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8978 emit_far_call(ndrc_get_addr_ht);
8979 emit_jmpreg(0); // jr k0
8980 literal_pool(0);
8981 end_block(beginning);
8982
8983 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8984 block->jump_in[0].vaddr = start;
8985 block->jump_in[0].addr = beginning;
8986 SysPrintf("F1 hack to %08x\n", start);
8987 return 0;
8988 }
8989
8990 cycle_multiplier_active = get_cycle_multiplier();
8991
8992 source = get_source_start(start, &pagelimit);
8993 if (source == NULL) {
8994 if (addr != hack_addr) {
8995 SysPrintf("Compile at bogus memory address: %08x, ra=%x\n",
8996 addr, psxRegs.GPR.n.ra);
8997 hack_addr = addr;
8998 }
8999 //abort();
9000 return -1;
9001 }
9002
9003 /* Pass 1: disassemble */
9004 /* Pass 2: register dependencies, branch targets */
9005 /* Pass 3: register allocation */
9006 /* Pass 4: branch dependencies */
9007 /* Pass 5: pre-alloc */
9008 /* Pass 6: optimize clean/dirty state */
9009 /* Pass 7: flag 32-bit registers */
9010 /* Pass 8: assembly */
9011 /* Pass 9: linker */
9012 /* Pass 10: garbage collection / free memory */
9013
9014 /* Pass 1 disassembly */
9015
9016 pass1_disassemble(pagelimit);
9017
9018 int clear_hack_addr = apply_hacks();
9019
9020 /* Pass 2 - Register dependencies and branch targets */
9021
9022 pass2_unneeded_regs(0,slen-1,0);
9023
9024 pass2a_unneeded_other();
9025
9026 /* Pass 3 - Register allocation */
9027
9028 pass3_register_alloc(addr);
9029
9030 /* Pass 4 - Cull unused host registers */
9031
9032 pass4_cull_unused_regs();
9033
9034 /* Pass 5 - Pre-allocate registers */
9035
9036 pass5a_preallocate1();
9037 pass5b_preallocate2();
9038
9039 /* Pass 6 - Optimize clean/dirty state */
9040 pass6_clean_registers(0, slen-1, 1);
9041
9042 /* Pass 7 */
9043 for (i=slen-1;i>=0;i--)
9044 {
9045 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9046 {
9047 // Conditional branch
9048 if((source[i]>>16)!=0x1000&&i<slen-2) {
9049 // Mark this address as a branch target since it may be called
9050 // upon return from interrupt
9051 dops[i+2].bt=1;
9052 }
9053 }
9054 }
9055
9056 /* Pass 8 - Assembly */
9057 linkcount=0;stubcount=0;
9058 is_delayslot=0;
9059 u_int dirty_pre=0;
9060 void *beginning=start_block();
9061 void *instr_addr0_override = NULL;
9062 int ds = 0;
9063
9064 if (start == 0x80030000) {
9065 // nasty hack for the fastbios thing
9066 // override block entry to this code
9067 instr_addr0_override = out;
9068 emit_movimm(start,0);
9069 // abuse io address var as a flag that we
9070 // have already returned here once
9071 emit_readword(&address,1);
9072 emit_writeword(0,&pcaddr);
9073 emit_writeword(0,&address);
9074 emit_cmp(0,1);
9075 #ifdef __aarch64__
9076 emit_jeq(out + 4*2);
9077 emit_far_jump(new_dyna_leave);
9078 #else
9079 emit_jne(new_dyna_leave);
9080 #endif
9081 }
9082 for(i=0;i<slen;i++)
9083 {
9084 __builtin_prefetch(regs[i+1].regmap);
9085 check_regmap(regmap_pre[i]);
9086 check_regmap(regs[i].regmap_entry);
9087 check_regmap(regs[i].regmap);
9088 //if(ds) printf("ds: ");
9089 disassemble_inst(i);
9090 if(ds) {
9091 ds=0; // Skip delay slot
9092 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9093 instr_addr[i] = NULL;
9094 } else {
9095 speculate_register_values(i);
9096 #ifndef DESTRUCTIVE_WRITEBACK
9097 if (i < 2 || !dops[i-2].is_ujump)
9098 {
9099 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9100 }
9101 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9102 dirty_pre=branch_regs[i].dirty;
9103 }else{
9104 dirty_pre=regs[i].dirty;
9105 }
9106 #endif
9107 // write back
9108 if (i < 2 || !dops[i-2].is_ujump)
9109 {
9110 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9111 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9112 }
9113 // branch target entry point
9114 instr_addr[i] = out;
9115 assem_debug("<->\n");
9116 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
9117 if (clear_hack_addr) {
9118 emit_movimm(0, 0);
9119 emit_writeword(0, &hack_addr);
9120 clear_hack_addr = 0;
9121 }
9122
9123 // load regs
9124 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
9125 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9126 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9127 address_generation(i,&regs[i],regs[i].regmap_entry);
9128 load_consts(regmap_pre[i],regs[i].regmap,i);
9129 if(dops[i].is_jump)
9130 {
9131 // Load the delay slot registers if necessary
9132 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9133 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9134 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9135 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9136 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9137 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9138 if (dops[i+1].is_store)
9139 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9140 }
9141 else if(i+1<slen)
9142 {
9143 // Preload registers for following instruction
9144 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9145 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9146 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9147 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9148 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9149 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9150 }
9151 // TODO: if(is_ooo(i)) address_generation(i+1);
9152 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9153 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9154 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9155 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9156 if (dops[i].is_store)
9157 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9158
9159 ds = assemble(i, &regs[i], cinfo[i].ccadj);
9160
9161 drc_dbg_emit_wb_dirtys(i, &regs[i]);
9162 if (dops[i].is_ujump)
9163 literal_pool(1024);
9164 else
9165 literal_pool_jumpover(256);
9166 }
9167 }
9168
9169 assert(slen > 0);
9170 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9171 // no ending needed for this block since INTCALL never returns
9172 }
9173 // If the block did not end with an unconditional branch,
9174 // add a jump to the next instruction.
9175 else if (i > 1) {
9176 if (!dops[i-2].is_ujump) {
9177 assert(!dops[i-1].is_jump);
9178 assert(i==slen);
9179 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9180 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9181 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9182 emit_loadreg(CCREG,HOST_CCREG);
9183 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9184 }
9185 else
9186 {
9187 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9188 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9189 }
9190 add_to_linker(out,start+i*4,0);
9191 emit_jmp(0);
9192 }
9193 }
9194 else
9195 {
9196 assert(i>0);
9197 assert(!dops[i-1].is_jump);
9198 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9199 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9200 emit_loadreg(CCREG,HOST_CCREG);
9201 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9202 add_to_linker(out,start+i*4,0);
9203 emit_jmp(0);
9204 }
9205
9206 // Stubs
9207 for(i = 0; i < stubcount; i++)
9208 {
9209 switch(stubs[i].type)
9210 {
9211 case LOADB_STUB:
9212 case LOADH_STUB:
9213 case LOADW_STUB:
9214 case LOADBU_STUB:
9215 case LOADHU_STUB:
9216 do_readstub(i);break;
9217 case STOREB_STUB:
9218 case STOREH_STUB:
9219 case STOREW_STUB:
9220 do_writestub(i);break;
9221 case CC_STUB:
9222 do_ccstub(i);break;
9223 case INVCODE_STUB:
9224 do_invstub(i);break;
9225 case STORELR_STUB:
9226 do_unalignedwritestub(i);break;
9227 case OVERFLOW_STUB:
9228 do_overflowstub(i); break;
9229 case ALIGNMENT_STUB:
9230 do_alignmentstub(i); break;
9231 default:
9232 assert(0);
9233 }
9234 }
9235
9236 if (instr_addr0_override)
9237 instr_addr[0] = instr_addr0_override;
9238
9239#if 0
9240 /* check for improper expiration */
9241 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9242 int j;
9243 if (!jumps[i])
9244 continue;
9245 for (j = 0; j < jumps[i]->count; j++)
9246 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9247 }
9248#endif
9249
9250 /* Pass 9 - Linker */
9251 for(i=0;i<linkcount;i++)
9252 {
9253 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9254 literal_pool(64);
9255 if (!link_addr[i].internal)
9256 {
9257 void *stub = out;
9258 void *addr = check_addr(link_addr[i].target);
9259 emit_extjump(link_addr[i].addr, link_addr[i].target);
9260 if (addr) {
9261 set_jump_target(link_addr[i].addr, addr);
9262 ndrc_add_jump_out(link_addr[i].target,stub);
9263 }
9264 else
9265 set_jump_target(link_addr[i].addr, stub);
9266 }
9267 else
9268 {
9269 // Internal branch
9270 int target=(link_addr[i].target-start)>>2;
9271 assert(target>=0&&target<slen);
9272 assert(instr_addr[target]);
9273 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9274 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9275 //#else
9276 set_jump_target(link_addr[i].addr, instr_addr[target]);
9277 //#endif
9278 }
9279 }
9280
9281 u_int source_len = slen*4;
9282 if (dops[slen-1].itype == INTCALL && source_len > 4)
9283 // no need to treat the last instruction as compiled
9284 // as interpreter fully handles it
9285 source_len -= 4;
9286
9287 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9288 copy = shadow;
9289
9290 // External Branch Targets (jump_in)
9291 int jump_in_count = 1;
9292 assert(instr_addr[0]);
9293 for (i = 1; i < slen; i++)
9294 {
9295 if (dops[i].bt && instr_addr[i])
9296 jump_in_count++;
9297 }
9298
9299 struct block_info *block =
9300 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9301 block->reg_sv_flags = state_rflags;
9302
9303 int jump_in_i = 0;
9304 for (i = 0; i < slen; i++)
9305 {
9306 if ((i == 0 || dops[i].bt) && instr_addr[i])
9307 {
9308 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9309 u_int vaddr = start + i*4;
9310
9311 literal_pool(256);
9312 void *entry = out;
9313 load_regs_entry(i);
9314 if (entry == out)
9315 entry = instr_addr[i];
9316 else
9317 emit_jmp(instr_addr[i]);
9318
9319 block->jump_in[jump_in_i].vaddr = vaddr;
9320 block->jump_in[jump_in_i].addr = entry;
9321 jump_in_i++;
9322 }
9323 }
9324 assert(jump_in_i == jump_in_count);
9325 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9326 // Write out the literal pool if necessary
9327 literal_pool(0);
9328 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9329 // Align code
9330 if(((u_int)out)&7) emit_addnop(13);
9331 #endif
9332 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9333 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9334 memcpy(copy, source, source_len);
9335 copy += source_len;
9336
9337 end_block(beginning);
9338
9339 // If we're within 256K of the end of the buffer,
9340 // start over from the beginning. (Is 256K enough?)
9341 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9342 out = ndrc->translation_cache;
9343
9344 // Trap writes to any of the pages we compiled
9345 mark_invalid_code(start, slen*4, 0);
9346
9347 /* Pass 10 - Free memory by expiring oldest blocks */
9348
9349 pass10_expire_blocks();
9350
9351#ifdef ASSEM_PRINT
9352 fflush(stdout);
9353#endif
9354 stat_inc(stat_bc_direct);
9355 return 0;
9356}
9357
9358// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork