| 1 | diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c |
| 2 | index 2df259b..2a15e6e 100644 |
| 3 | --- a/libpcsxcore/new_dynarec/emu_if.c |
| 4 | +++ b/libpcsxcore/new_dynarec/emu_if.c |
| 5 | @@ -417,13 +417,17 @@ static void ari64_shutdown() |
| 6 | { |
| 7 | new_dynarec_cleanup(); |
| 8 | new_dyna_pcsx_mem_shutdown(); |
| 9 | + (void)ari64_execute; |
| 10 | } |
| 11 | |
| 12 | +extern void intExecuteT(); |
| 13 | +extern void intExecuteBlockT(); |
| 14 | + |
| 15 | R3000Acpu psxRec = { |
| 16 | ari64_init, |
| 17 | ari64_reset, |
| 18 | - ari64_execute, |
| 19 | - ari64_execute_until, |
| 20 | + intExecuteT, |
| 21 | + intExecuteBlockT, |
| 22 | ari64_clear, |
| 23 | #ifdef ICACHE_EMULATION |
| 24 | ari64_notify, |
| 25 | @@ -489,7 +493,7 @@ static u32 memcheck_read(u32 a) |
| 26 | return *(u32 *)(psxM + (a & 0x1ffffc)); |
| 27 | } |
| 28 | |
| 29 | -#if 0 |
| 30 | +#if 1 |
| 31 | void do_insn_trace(void) |
| 32 | { |
| 33 | static psxRegisters oldregs; |
| 34 | diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c |
| 35 | index dbcb989..0716f5e 100644 |
| 36 | --- a/libpcsxcore/psxhw.c |
| 37 | +++ b/libpcsxcore/psxhw.c |
| 38 | @@ -373,13 +373,14 @@ void psxHwWrite8(u32 add, u8 value) { |
| 39 | case 0x1f801803: cdrWrite3(value); break; |
| 40 | |
| 41 | default: |
| 42 | + if (add < 0x1f802000) |
| 43 | psxHu8(add) = value; |
| 44 | #ifdef PSXHW_LOG |
| 45 | PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value); |
| 46 | #endif |
| 47 | return; |
| 48 | } |
| 49 | - psxHu8(add) = value; |
| 50 | + //psxHu8(add) = value; |
| 51 | #ifdef PSXHW_LOG |
| 52 | PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value); |
| 53 | #endif |
| 54 | @@ -504,6 +505,7 @@ void psxHwWrite16(u32 add, u16 value) { |
| 55 | return; |
| 56 | } |
| 57 | |
| 58 | + if (add < 0x1f802000) |
| 59 | psxHu16ref(add) = SWAPu16(value); |
| 60 | #ifdef PSXHW_LOG |
| 61 | PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value); |
| 62 | @@ -699,9 +701,9 @@ void psxHwWrite32(u32 add, u32 value) { |
| 63 | return; |
| 64 | |
| 65 | case 0x1f801820: |
| 66 | - mdecWrite0(value); break; |
| 67 | + mdecWrite0(value); return; |
| 68 | case 0x1f801824: |
| 69 | - mdecWrite1(value); break; |
| 70 | + mdecWrite1(value); return; |
| 71 | |
| 72 | case 0x1f801100: |
| 73 | #ifdef PSXHW_LOG |
| 74 | @@ -759,6 +761,7 @@ void psxHwWrite32(u32 add, u32 value) { |
| 75 | return; |
| 76 | } |
| 77 | |
| 78 | + if (add < 0x1f802000) |
| 79 | psxHu32ref(add) = SWAPu32(value); |
| 80 | #ifdef PSXHW_LOG |
| 81 | PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); |
| 82 | diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c |
| 83 | index 61c60ed..0fa5283 100644 |
| 84 | --- a/libpcsxcore/psxinterpreter.c |
| 85 | +++ b/libpcsxcore/psxinterpreter.c |
| 86 | @@ -511,8 +511,9 @@ static void doBranch(u32 tar) { |
| 87 | debugI(); |
| 88 | |
| 89 | psxRegs.pc += 4; |
| 90 | - psxRegs.cycle += BIAS; |
| 91 | |
| 92 | + (void)tmp; |
| 93 | +#if 0 |
| 94 | // check for load delay |
| 95 | tmp = psxRegs.code >> 26; |
| 96 | switch (tmp) { |
| 97 | @@ -546,13 +547,15 @@ static void doBranch(u32 tar) { |
| 98 | } |
| 99 | break; |
| 100 | } |
| 101 | - |
| 102 | +#endif |
| 103 | psxBSC[psxRegs.code >> 26](); |
| 104 | |
| 105 | branch = 0; |
| 106 | psxRegs.pc = branchPC; |
| 107 | |
| 108 | psxBranchTest(); |
| 109 | + |
| 110 | + psxRegs.cycle += BIAS; |
| 111 | } |
| 112 | |
| 113 | /********************************************************* |
| 114 | @@ -635,12 +638,13 @@ void psxMULTU() { |
| 115 | psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff); |
| 116 | } |
| 117 | |
| 118 | +#define doBranchNotTaken() do { psxRegs.cycle -= BIAS; execI(); psxBranchTest(); psxRegs.cycle += BIAS; } while(0) |
| 119 | /********************************************************* |
| 120 | * Register branch logic * |
| 121 | * Format: OP rs, offset * |
| 122 | *********************************************************/ |
| 123 | -#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); |
| 124 | -#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } } |
| 125 | +#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); else doBranchNotTaken(); |
| 126 | +#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } else doBranchNotTaken(); } |
| 127 | |
| 128 | void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0 |
| 129 | void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link |
| 130 | @@ -710,7 +714,7 @@ void psxRFE() { |
| 131 | * Register branch logic * |
| 132 | * Format: OP rs, rt, offset * |
| 133 | *********************************************************/ |
| 134 | -#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); |
| 135 | +#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); else doBranchNotTaken(); |
| 136 | |
| 137 | void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt |
| 138 | void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt |
| 139 | @@ -894,6 +898,9 @@ void MTC0(int reg, u32 val) { |
| 140 | case 12: // Status |
| 141 | psxRegs.CP0.r[12] = val; |
| 142 | psxTestSWInts(); |
| 143 | +#ifndef __arm__ |
| 144 | + psxBranchTest(); |
| 145 | +#endif |
| 146 | break; |
| 147 | |
| 148 | case 13: // Cause |
| 149 | @@ -1056,6 +1063,23 @@ void intExecuteBlock() { |
| 150 | while (!branch2) execI(); |
| 151 | } |
| 152 | |
| 153 | +extern void do_insn_trace(void); |
| 154 | + |
| 155 | +void intExecuteT() { |
| 156 | + for (;;) { |
| 157 | + do_insn_trace(); |
| 158 | + execI(); |
| 159 | + } |
| 160 | +} |
| 161 | + |
| 162 | +void intExecuteBlockT() { |
| 163 | + branch2 = 0; |
| 164 | + while (!branch2) { |
| 165 | + do_insn_trace(); |
| 166 | + execI(); |
| 167 | + } |
| 168 | +} |
| 169 | + |
| 170 | static void intClear(u32 Addr, u32 Size) { |
| 171 | } |
| 172 | |
| 173 | diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c |
| 174 | index c09965d..135a5d0 100644 |
| 175 | --- a/libpcsxcore/psxmem.c |
| 176 | +++ b/libpcsxcore/psxmem.c |
| 177 | @@ -219,11 +219,13 @@ void psxMemShutdown() { |
| 178 | } |
| 179 | |
| 180 | static int writeok = 1; |
| 181 | +u32 last_io_addr; |
| 182 | |
| 183 | u8 psxMemRead8(u32 mem) { |
| 184 | char *p; |
| 185 | u32 t; |
| 186 | |
| 187 | + last_io_addr = mem; |
| 188 | t = mem >> 16; |
| 189 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 190 | if ((mem & 0xffff) < 0x400) |
| 191 | @@ -249,6 +251,7 @@ u16 psxMemRead16(u32 mem) { |
| 192 | char *p; |
| 193 | u32 t; |
| 194 | |
| 195 | + last_io_addr = mem; |
| 196 | t = mem >> 16; |
| 197 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 198 | if ((mem & 0xffff) < 0x400) |
| 199 | @@ -274,6 +277,7 @@ u32 psxMemRead32(u32 mem) { |
| 200 | char *p; |
| 201 | u32 t; |
| 202 | |
| 203 | + last_io_addr = mem; |
| 204 | t = mem >> 16; |
| 205 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 206 | if ((mem & 0xffff) < 0x400) |
| 207 | @@ -299,6 +303,7 @@ void psxMemWrite8(u32 mem, u8 value) { |
| 208 | char *p; |
| 209 | u32 t; |
| 210 | |
| 211 | + last_io_addr = mem; |
| 212 | t = mem >> 16; |
| 213 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 214 | if ((mem & 0xffff) < 0x400) |
| 215 | @@ -326,6 +331,7 @@ void psxMemWrite16(u32 mem, u16 value) { |
| 216 | char *p; |
| 217 | u32 t; |
| 218 | |
| 219 | + last_io_addr = mem; |
| 220 | t = mem >> 16; |
| 221 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 222 | if ((mem & 0xffff) < 0x400) |
| 223 | @@ -353,6 +359,7 @@ void psxMemWrite32(u32 mem, u32 value) { |
| 224 | char *p; |
| 225 | u32 t; |
| 226 | |
| 227 | + last_io_addr = mem; |
| 228 | // if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n"); |
| 229 | t = mem >> 16; |
| 230 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |