| 1 | /* |
| 2 | * This software is released into the public domain. |
| 3 | * See UNLICENSE file in top level directory. |
| 4 | */ |
| 5 | #include <stdlib.h> |
| 6 | #include <stdarg.h> |
| 7 | #include "common.h" |
| 8 | #include "asmtools.h" |
| 9 | |
| 10 | #define VDP_DATA_PORT 0xC00000 |
| 11 | #define VDP_CTRL_PORT 0xC00004 |
| 12 | #define VDP_HV_COUNTER 0xC00008 |
| 13 | |
| 14 | #define TILE_MEM_END 0xB000 |
| 15 | |
| 16 | #define FONT_LEN 128 |
| 17 | #define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32) |
| 18 | |
| 19 | /* note: using ED menu's layout here.. */ |
| 20 | #define WPLANE (TILE_MEM_END + 0x0000) |
| 21 | #define HSCRL (TILE_MEM_END + 0x0800) |
| 22 | #define SLIST (TILE_MEM_END + 0x0C00) |
| 23 | #define APLANE (TILE_MEM_END + 0x1000) |
| 24 | #define BPLANE (TILE_MEM_END + 0x3000) |
| 25 | |
| 26 | #define write16_z80le(a, d) \ |
| 27 | ((volatile u8 *)(a))[0] = (u8)(d), \ |
| 28 | ((volatile u8 *)(a))[1] = ((d) >> 8) |
| 29 | |
| 30 | static inline u16 read16_z80le(const void *a_) |
| 31 | { |
| 32 | volatile const u8 *a = (volatile const u8 *)a_; |
| 33 | return a[0] | ((u16)a[1] << 8); |
| 34 | } |
| 35 | |
| 36 | #define CTL_WRITE_VRAM(adr) \ |
| 37 | (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00) |
| 38 | #define CTL_WRITE_VSRAM(adr) \ |
| 39 | (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10) |
| 40 | #define CTL_WRITE_CRAM(adr) \ |
| 41 | (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00) |
| 42 | #define CTL_READ_VRAM(adr) \ |
| 43 | (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00) |
| 44 | #define CTL_READ_VSRAM(adr) \ |
| 45 | (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10) |
| 46 | #define CTL_READ_CRAM(adr) \ |
| 47 | (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20) |
| 48 | |
| 49 | #define CTL_WRITE_DMA 0x80 |
| 50 | |
| 51 | #define VDP_setReg(r, v) \ |
| 52 | write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff)) |
| 53 | |
| 54 | enum { |
| 55 | VDP_MODE1 = 0x00, |
| 56 | VDP_MODE2 = 0x01, |
| 57 | VDP_NT_SCROLLA = 0x02, |
| 58 | VDP_NT_WIN = 0x03, |
| 59 | VDP_NT_SCROLLB = 0x04, |
| 60 | VDP_SAT_BASE = 0x05, |
| 61 | VDP_BACKDROP = 0x07, |
| 62 | VDP_MODE3 = 0x0b, |
| 63 | VDP_MODE4 = 0x0c, |
| 64 | VDP_HSCROLL = 0x0d, |
| 65 | VDP_AUTOINC = 0x0f, |
| 66 | VDP_SCROLLSZ = 0x10, |
| 67 | VDP_DMA_LEN0 = 0x13, |
| 68 | VDP_DMA_LEN1 = 0x14, |
| 69 | VDP_DMA_SRC0 = 0x15, |
| 70 | VDP_DMA_SRC1 = 0x16, |
| 71 | VDP_DMA_SRC2 = 0x17, |
| 72 | }; |
| 73 | |
| 74 | #define VDP_MODE1_PS 0x04 |
| 75 | #define VDP_MODE1_IE1 0x10 // h int |
| 76 | #define VDP_MODE2_MD 0x04 |
| 77 | #define VDP_MODE2_PAL 0x08 // 30 col |
| 78 | #define VDP_MODE2_DMA 0x10 |
| 79 | #define VDP_MODE2_IE0 0x20 // v int |
| 80 | #define VDP_MODE2_DISP 0x40 |
| 81 | #define VDP_MODE2_128K 0x80 |
| 82 | |
| 83 | #define SR_PAL (1 << 0) |
| 84 | #define SR_DMA (1 << 1) |
| 85 | #define SR_HB (1 << 2) |
| 86 | #define SR_VB (1 << 3) |
| 87 | #define SR_ODD (1 << 4) |
| 88 | #define SR_C (1 << 5) |
| 89 | #define SR_SOVR (1 << 6) |
| 90 | #define SR_F (1 << 7) |
| 91 | #define SR_FULL (1 << 8) |
| 92 | #define SR_EMPT (1 << 9) |
| 93 | |
| 94 | /* cell counts */ |
| 95 | #define LEFT_BORDER 1 /* lame TV */ |
| 96 | #define PLANE_W 64 |
| 97 | #define PLANE_H 32 |
| 98 | #define CSCREEN_H 28 |
| 99 | |
| 100 | /* data.s */ |
| 101 | extern const u32 font_base[]; |
| 102 | extern const u8 z80_test[]; |
| 103 | extern const u8 z80_test_end[]; |
| 104 | |
| 105 | static int text_pal; |
| 106 | |
| 107 | static noinline void VDP_drawTextML(const char *str, u16 plane_base, |
| 108 | u16 x, u16 y) |
| 109 | { |
| 110 | const u8 *src = (const u8 *)str; |
| 111 | u16 basetile = text_pal << 13; |
| 112 | int max_len = 40 - LEFT_BORDER; |
| 113 | int len; |
| 114 | u32 addr; |
| 115 | |
| 116 | x += LEFT_BORDER; |
| 117 | |
| 118 | for (len = 0; str[len] && len < max_len; len++) |
| 119 | ; |
| 120 | if (len > (PLANE_W - x)) |
| 121 | len = PLANE_W - x; |
| 122 | |
| 123 | addr = plane_base + ((x + (PLANE_W * y)) << 1); |
| 124 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr)); |
| 125 | |
| 126 | while (len-- > 0) { |
| 127 | write16(VDP_DATA_PORT, |
| 128 | basetile | ((*src++) - 32 + TILE_FONT_BASE / 32)); |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | static int printf_ypos; |
| 133 | |
| 134 | static void printf_line(int x, const char *buf) |
| 135 | { |
| 136 | u32 addr; |
| 137 | int i; |
| 138 | |
| 139 | VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1)); |
| 140 | |
| 141 | if (printf_ypos >= CSCREEN_H) { |
| 142 | /* clear next line */ |
| 143 | addr = APLANE; |
| 144 | addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1; |
| 145 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr)); |
| 146 | for (i = 0; i < 40 / 2; i++) |
| 147 | write32(VDP_DATA_PORT, 0); |
| 148 | |
| 149 | /* scroll plane */ |
| 150 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 151 | write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | #define PRINTF_LEN 40 |
| 156 | |
| 157 | static int printf_xpos; |
| 158 | |
| 159 | static noinline int printf(const char *fmt, ...) |
| 160 | { |
| 161 | static const char hexchars[] = "0123456789abcdef"; |
| 162 | char c, buf[PRINTF_LEN + 11 + 1]; |
| 163 | const char *s; |
| 164 | va_list ap; |
| 165 | int ival; |
| 166 | u32 uval; |
| 167 | int d = 0; |
| 168 | int i, j; |
| 169 | |
| 170 | va_start(ap, fmt); |
| 171 | for (d = 0; *fmt; ) { |
| 172 | int prefix0 = 0; |
| 173 | int fwidth = 0; |
| 174 | |
| 175 | c = *fmt++; |
| 176 | if (d < PRINTF_LEN) |
| 177 | buf[d] = c; |
| 178 | |
| 179 | if (c != '%') { |
| 180 | if (c == '\n') { |
| 181 | buf[d] = 0; |
| 182 | printf_line(printf_xpos, buf); |
| 183 | d = 0; |
| 184 | printf_xpos = 0; |
| 185 | continue; |
| 186 | } |
| 187 | d++; |
| 188 | continue; |
| 189 | } |
| 190 | if (d >= PRINTF_LEN) |
| 191 | continue; |
| 192 | |
| 193 | if (*fmt == '0') { |
| 194 | prefix0 = 1; |
| 195 | fmt++; |
| 196 | } |
| 197 | |
| 198 | while ('1' <= *fmt && *fmt <= '9') { |
| 199 | fwidth = fwidth * 10 + *fmt - '0'; |
| 200 | fmt++; |
| 201 | } |
| 202 | |
| 203 | switch (*fmt++) { |
| 204 | case '%': |
| 205 | d++; |
| 206 | break; |
| 207 | case 'd': |
| 208 | case 'i': |
| 209 | ival = va_arg(ap, int); |
| 210 | if (ival < 0) { |
| 211 | buf[d++] = '-'; |
| 212 | ival = -ival; |
| 213 | } |
| 214 | for (i = 1000000000; i >= 10; i /= 10) |
| 215 | if (ival >= i) |
| 216 | break; |
| 217 | for (; i >= 10; i /= 10) { |
| 218 | buf[d++] = '0' + ival / i; |
| 219 | ival %= i; |
| 220 | } |
| 221 | buf[d++] = '0' + ival; |
| 222 | break; |
| 223 | case 'x': |
| 224 | uval = va_arg(ap, int); |
| 225 | while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) { |
| 226 | buf[d++] = prefix0 ? '0' : ' '; |
| 227 | fwidth--; |
| 228 | } |
| 229 | for (j = 1; j < 8 && uval >= (1 << j * 4); j++) |
| 230 | ; |
| 231 | for (j--; j >= 0; j--) |
| 232 | buf[d++] = hexchars[(uval >> j * 4) & 0x0f]; |
| 233 | break; |
| 234 | case 's': |
| 235 | s = va_arg(ap, char *); |
| 236 | while (*s && d < PRINTF_LEN) |
| 237 | buf[d++] = *s++; |
| 238 | break; |
| 239 | default: |
| 240 | // don't handle, for now |
| 241 | d++; |
| 242 | va_arg(ap, void *); |
| 243 | break; |
| 244 | } |
| 245 | } |
| 246 | buf[d] = 0; |
| 247 | va_end(ap); |
| 248 | |
| 249 | if (d != 0) { |
| 250 | // line without \n |
| 251 | VDP_drawTextML(buf, APLANE, printf_xpos, |
| 252 | printf_ypos & (PLANE_H - 1)); |
| 253 | printf_xpos += d; |
| 254 | } |
| 255 | |
| 256 | return d; // wrong.. |
| 257 | } |
| 258 | |
| 259 | static const char *exc_names[] = { |
| 260 | NULL, |
| 261 | NULL, |
| 262 | "Bus Error", |
| 263 | "Address Error", |
| 264 | "Illegal Instruction", |
| 265 | "Zero Divide", |
| 266 | "CHK Instruction", |
| 267 | "TRAPV Instruction", |
| 268 | "Privilege Violation", /* 8 8 */ |
| 269 | "Trace", |
| 270 | "Line 1010 Emulator", |
| 271 | "Line 1111 Emulator", |
| 272 | NULL, |
| 273 | NULL, |
| 274 | NULL, |
| 275 | "Uninitialized Interrupt", |
| 276 | NULL, /* 10 16 */ |
| 277 | NULL, |
| 278 | NULL, |
| 279 | NULL, |
| 280 | NULL, |
| 281 | NULL, |
| 282 | NULL, |
| 283 | NULL, |
| 284 | "Spurious Interrupt", /* 18 24 */ |
| 285 | "l1 irq", |
| 286 | "l2 irq", |
| 287 | "l3 irq", |
| 288 | "l4 irq", |
| 289 | "l5 irq", |
| 290 | "l6 irq", |
| 291 | "l7 irq", |
| 292 | }; |
| 293 | |
| 294 | struct exc_frame { |
| 295 | u32 dr[8]; |
| 296 | u32 ar[8]; |
| 297 | u16 ecxnum; // from handler |
| 298 | union { |
| 299 | struct { |
| 300 | u16 sr; |
| 301 | u32 pc; |
| 302 | } g _packed; |
| 303 | struct { |
| 304 | u16 fc; |
| 305 | u32 addr; |
| 306 | u16 ir; |
| 307 | u16 sr; |
| 308 | u32 pc; |
| 309 | } bae _packed; // bus/address error frame |
| 310 | }; |
| 311 | } _packed; |
| 312 | |
| 313 | void exception(const struct exc_frame *f) |
| 314 | { |
| 315 | u32 *sp, sp_add; |
| 316 | int i; |
| 317 | |
| 318 | while (read16(VDP_CTRL_PORT) & 2) |
| 319 | ; |
| 320 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 321 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP); |
| 322 | /* adjust scroll */ |
| 323 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 324 | write16(VDP_DATA_PORT, |
| 325 | printf_ypos >= CSCREEN_H ? |
| 326 | (printf_ypos - CSCREEN_H + 1) * 8 : 0); |
| 327 | |
| 328 | printf("exception %i ", f->ecxnum); |
| 329 | if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL) |
| 330 | printf("(%s)", exc_names[f->ecxnum]); |
| 331 | if (f->ecxnum < 4) |
| 332 | printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w"); |
| 333 | printf(" \n"); |
| 334 | |
| 335 | if (f->ecxnum < 4) { |
| 336 | printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr); |
| 337 | printf("addr: %08x IR: %04x FC: %02x \n", |
| 338 | f->bae.addr, f->bae.ir, f->bae.fc); |
| 339 | sp_add = 14; |
| 340 | } |
| 341 | else { |
| 342 | printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr); |
| 343 | sp_add = 6; |
| 344 | } |
| 345 | for (i = 0; i < 8; i++) |
| 346 | printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]); |
| 347 | printf(" \n"); |
| 348 | sp = (u32 *)(f->ar[7] + sp_add); |
| 349 | printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]); |
| 350 | printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]); |
| 351 | } |
| 352 | |
| 353 | // --- |
| 354 | |
| 355 | static void setup_default_palette(void) |
| 356 | { |
| 357 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0)); |
| 358 | write32(VDP_DATA_PORT, 0); |
| 359 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal |
| 360 | write16(VDP_DATA_PORT, 0xeee); |
| 361 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green |
| 362 | write16(VDP_DATA_PORT, 0x0e0); |
| 363 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red |
| 364 | write16(VDP_DATA_PORT, 0x00e); |
| 365 | } |
| 366 | |
| 367 | static void do_setup_dma(const void *src_, u16 words) |
| 368 | { |
| 369 | u32 src = (u32)src_; |
| 370 | // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA); |
| 371 | VDP_setReg(VDP_DMA_LEN0, words); |
| 372 | VDP_setReg(VDP_DMA_LEN1, words >> 8); |
| 373 | VDP_setReg(VDP_DMA_SRC0, src >> 1); |
| 374 | VDP_setReg(VDP_DMA_SRC1, src >> 9); |
| 375 | VDP_setReg(VDP_DMA_SRC2, src >> 17); |
| 376 | // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA); |
| 377 | } |
| 378 | |
| 379 | static void vdp_wait_for_fifo_empty(void) |
| 380 | { |
| 381 | while (!(read16(VDP_CTRL_PORT) & 0x200)) |
| 382 | /* fifo not empty */; |
| 383 | } |
| 384 | |
| 385 | static void vdp_wait_for_dma_idle(void) |
| 386 | { |
| 387 | while (read16(VDP_CTRL_PORT) & 2) |
| 388 | /* dma busy */; |
| 389 | } |
| 390 | |
| 391 | static void vdp_wait_for_line_0(void) |
| 392 | { |
| 393 | // in PAL vcounter reports 0 twice in a frame, |
| 394 | // so wait for vblank to clear first |
| 395 | while (!(read16(VDP_CTRL_PORT) & 8)) |
| 396 | /* not blanking */; |
| 397 | while (read16(VDP_CTRL_PORT) & 8) |
| 398 | /* blanking */; |
| 399 | while (read8(VDP_HV_COUNTER) != 0) |
| 400 | ; |
| 401 | } |
| 402 | |
| 403 | static void t_dma_zero_wrap_early(void) |
| 404 | { |
| 405 | const u32 *src = (const u32 *)0x3c0000; |
| 406 | u32 *ram = (u32 *)0xff0000; |
| 407 | |
| 408 | do_setup_dma(src + 4, 2); |
| 409 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA); |
| 410 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA); |
| 411 | |
| 412 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0)); |
| 413 | ram[0] = read32(VDP_DATA_PORT); |
| 414 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc)); |
| 415 | ram[1] = read32(VDP_DATA_PORT); |
| 416 | } |
| 417 | |
| 418 | static void t_dma_zero_fill_early(void) |
| 419 | { |
| 420 | u32 *ram = (u32 *)0xff0000; |
| 421 | |
| 422 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0)); |
| 423 | write32(VDP_DATA_PORT, 0); |
| 424 | write32(VDP_DATA_PORT, 0); |
| 425 | write32(VDP_DATA_PORT, 0); |
| 426 | write32(VDP_DATA_PORT, 0); |
| 427 | |
| 428 | VDP_setReg(VDP_AUTOINC, 1); |
| 429 | VDP_setReg(VDP_DMA_SRC2, 0x80); |
| 430 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA); |
| 431 | write16(VDP_DATA_PORT, 0x1122); |
| 432 | ram[2] = read16(VDP_CTRL_PORT); |
| 433 | vdp_wait_for_dma_idle(); |
| 434 | |
| 435 | VDP_setReg(VDP_AUTOINC, 2); |
| 436 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0)); |
| 437 | ram[3] = read32(VDP_DATA_PORT); |
| 438 | } |
| 439 | |
| 440 | #define expect(ok_, v0_, v1_) \ |
| 441 | do { if ((v0_) != (v1_)) { \ |
| 442 | printf("%s: %08x %08x\n", #v0_, v0_, v1_); \ |
| 443 | ok_ = 0; \ |
| 444 | }} while (0) |
| 445 | |
| 446 | #define expect_range(ok_, v0_, vmin_, vmax_) \ |
| 447 | do { if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \ |
| 448 | printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \ |
| 449 | ok_ = 0; \ |
| 450 | }} while (0) |
| 451 | |
| 452 | #define expect_bits(ok_, v0_, val_, mask_) \ |
| 453 | do { if (((v0_) & (mask_)) != (val_)) { \ |
| 454 | printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \ |
| 455 | ok_ = 0; \ |
| 456 | }} while (0) |
| 457 | |
| 458 | static int t_dma_zero_wrap(void) |
| 459 | { |
| 460 | const u32 *src = (const u32 *)0x3c0000; |
| 461 | const u32 *ram = (const u32 *)0xff0000; |
| 462 | int ok = 1; |
| 463 | |
| 464 | expect(ok, ram[0], src[5 + 0x10000/4]); |
| 465 | expect(ok, ram[1], src[4]); |
| 466 | return ok; |
| 467 | } |
| 468 | |
| 469 | static int t_dma_zero_fill(void) |
| 470 | { |
| 471 | const u32 *ram = (const u32 *)0xff0000; |
| 472 | u32 v0 = ram[2] & 2; |
| 473 | int ok = 1; |
| 474 | |
| 475 | expect(ok, v0, 2); |
| 476 | expect(ok, ram[3], 0x11111111); |
| 477 | return ok; |
| 478 | } |
| 479 | |
| 480 | static int t_dma_ram_wrap(void) |
| 481 | { |
| 482 | u32 *ram = (u32 *)0xff0000; |
| 483 | u32 saved, v0, v1; |
| 484 | int ok = 1; |
| 485 | |
| 486 | saved = read32(&ram[0x10000/4 - 1]); |
| 487 | ram[0x10000/4 - 1] = 0x01020304; |
| 488 | ram[0] = 0x05060708; |
| 489 | do_setup_dma(&ram[0x10000/4 - 1], 4); |
| 490 | mem_barrier(); |
| 491 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); |
| 492 | |
| 493 | mem_barrier(); |
| 494 | write32(&ram[0x10000/4 - 1], saved); |
| 495 | |
| 496 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 497 | v0 = read32(VDP_DATA_PORT); |
| 498 | v1 = read32(VDP_DATA_PORT); |
| 499 | |
| 500 | expect(ok, v0, 0x01020304); |
| 501 | expect(ok, v1, 0x05060708); |
| 502 | return ok; |
| 503 | } |
| 504 | |
| 505 | // test no src reprogram, only len0 |
| 506 | static int t_dma_multi(void) |
| 507 | { |
| 508 | const u32 *src = (const u32 *)0x3c0000; |
| 509 | u32 v0, v1; |
| 510 | int ok = 1; |
| 511 | |
| 512 | do_setup_dma(src, 2); |
| 513 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); |
| 514 | VDP_setReg(VDP_DMA_LEN0, 2); |
| 515 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA); |
| 516 | |
| 517 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 518 | v0 = read32(VDP_DATA_PORT); |
| 519 | v1 = read32(VDP_DATA_PORT); |
| 520 | |
| 521 | expect(ok, v0, src[0]); |
| 522 | expect(ok, v1, src[1]); |
| 523 | return ok; |
| 524 | } |
| 525 | |
| 526 | static int t_dma_cram_wrap(void) |
| 527 | { |
| 528 | u32 *ram = (u32 *)0xff0000; |
| 529 | u32 v0, v1; |
| 530 | int ok = 1; |
| 531 | |
| 532 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0)); |
| 533 | write32(VDP_DATA_PORT, 0); |
| 534 | |
| 535 | ram[0] = 0x0ec20ec4; |
| 536 | ram[1] = 0x0ec60ec8; |
| 537 | mem_barrier(); |
| 538 | do_setup_dma(ram, 4); |
| 539 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA); |
| 540 | |
| 541 | write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c)); |
| 542 | v0 = read32(VDP_DATA_PORT) & 0x0eee0eee; |
| 543 | write32(VDP_CTRL_PORT, CTL_READ_CRAM(0)); |
| 544 | v1 = read32(VDP_DATA_PORT) & 0x0eee0eee; |
| 545 | |
| 546 | setup_default_palette(); |
| 547 | |
| 548 | expect(ok, v0, ram[0]); |
| 549 | expect(ok, v1, ram[1]); |
| 550 | return ok; |
| 551 | } |
| 552 | |
| 553 | static int t_dma_vsram_wrap(void) |
| 554 | { |
| 555 | u32 *ram32 = (u32 *)0xff0000; |
| 556 | u16 *ram16 = (u16 *)0xff0000; |
| 557 | u32 v0, v1; |
| 558 | int ok = 1; |
| 559 | int i; |
| 560 | |
| 561 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 562 | write32(VDP_DATA_PORT, 0); |
| 563 | |
| 564 | for (i = 0; i < 0x48/2; i++) |
| 565 | ram16[i] = i + 1; |
| 566 | mem_barrier(); |
| 567 | do_setup_dma(ram16, 0x48/2); |
| 568 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA); |
| 569 | |
| 570 | write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c)); |
| 571 | v0 = read32(VDP_DATA_PORT) & 0x03ff03ff; |
| 572 | write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0)); |
| 573 | v1 = read32(VDP_DATA_PORT) & 0x03ff03ff; |
| 574 | |
| 575 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 576 | write32(VDP_DATA_PORT, 0); |
| 577 | |
| 578 | expect(ok, v0, ram32[0]); |
| 579 | expect(ok, v1, ram32[0x48/4 - 1]); |
| 580 | return ok; |
| 581 | } |
| 582 | |
| 583 | static int t_dma_and_data(void) |
| 584 | { |
| 585 | const u32 *src = (const u32 *)0x3c0000; |
| 586 | u32 v0, v1; |
| 587 | int ok = 1; |
| 588 | |
| 589 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 590 | write32(VDP_DATA_PORT, 0); |
| 591 | |
| 592 | do_setup_dma(src, 2); |
| 593 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA); |
| 594 | write32(VDP_DATA_PORT, 0x5ec8a248); |
| 595 | |
| 596 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc)); |
| 597 | v0 = read32(VDP_DATA_PORT); |
| 598 | v1 = read32(VDP_DATA_PORT); |
| 599 | |
| 600 | expect(ok, v0, src[0]); |
| 601 | expect(ok, v1, 0x5ec8a248); |
| 602 | return ok; |
| 603 | } |
| 604 | |
| 605 | static int t_dma_short_cmd(void) |
| 606 | { |
| 607 | const u32 *src = (const u32 *)0x3c0000; |
| 608 | u32 v0, v1, v2; |
| 609 | int ok = 1; |
| 610 | |
| 611 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4)); |
| 612 | write32(VDP_DATA_PORT, 0x10111213); |
| 613 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0)); |
| 614 | write32(VDP_DATA_PORT, 0x20212223); |
| 615 | write32(VDP_DATA_PORT, 0x30313233); |
| 616 | vdp_wait_for_fifo_empty(); |
| 617 | |
| 618 | do_setup_dma(src, 2); |
| 619 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA); |
| 620 | write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16); |
| 621 | write32(VDP_DATA_PORT, 0x40414243); |
| 622 | |
| 623 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4)); |
| 624 | v0 = read32(VDP_DATA_PORT); |
| 625 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0)); |
| 626 | v1 = read32(VDP_DATA_PORT); |
| 627 | v2 = read32(VDP_DATA_PORT); |
| 628 | |
| 629 | expect(ok, v0, 0x10111213); |
| 630 | expect(ok, v1, src[0]); |
| 631 | expect(ok, v2, 0x40414243); |
| 632 | return ok; |
| 633 | } |
| 634 | |
| 635 | static int t_dma_fill3_odd(void) |
| 636 | { |
| 637 | u32 v0, v1, v2; |
| 638 | int ok = 1; |
| 639 | |
| 640 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 641 | write32(VDP_DATA_PORT, 0); |
| 642 | write32(VDP_DATA_PORT, 0); |
| 643 | write32(VDP_DATA_PORT, 0); |
| 644 | vdp_wait_for_fifo_empty(); |
| 645 | |
| 646 | VDP_setReg(VDP_AUTOINC, 3); |
| 647 | VDP_setReg(VDP_DMA_LEN0, 3); |
| 648 | VDP_setReg(VDP_DMA_SRC2, 0x80); |
| 649 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA); |
| 650 | write16(VDP_DATA_PORT, 0x1122); |
| 651 | vdp_wait_for_dma_idle(); |
| 652 | |
| 653 | VDP_setReg(VDP_AUTOINC, 2); |
| 654 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 655 | v0 = read32(VDP_DATA_PORT); |
| 656 | v1 = read32(VDP_DATA_PORT); |
| 657 | v2 = read32(VDP_DATA_PORT); |
| 658 | |
| 659 | expect(ok, v0, 0x22110000); |
| 660 | expect(ok, v1, 0x00111100); |
| 661 | expect(ok, v2, 0x00000011); |
| 662 | return ok; |
| 663 | } |
| 664 | |
| 665 | static int t_dma_fill3_even(void) |
| 666 | { |
| 667 | u32 v0, v1, v2; |
| 668 | int ok = 1; |
| 669 | |
| 670 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 671 | write32(VDP_DATA_PORT, 0); |
| 672 | write32(VDP_DATA_PORT, 0); |
| 673 | write32(VDP_DATA_PORT, 0); |
| 674 | vdp_wait_for_fifo_empty(); |
| 675 | |
| 676 | VDP_setReg(VDP_AUTOINC, 3); |
| 677 | VDP_setReg(VDP_DMA_LEN0, 3); |
| 678 | VDP_setReg(VDP_DMA_SRC2, 0x80); |
| 679 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); |
| 680 | write16(VDP_DATA_PORT, 0x1122); |
| 681 | vdp_wait_for_dma_idle(); |
| 682 | |
| 683 | VDP_setReg(VDP_AUTOINC, 2); |
| 684 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 685 | v0 = read32(VDP_DATA_PORT); |
| 686 | v1 = read32(VDP_DATA_PORT); |
| 687 | v2 = read32(VDP_DATA_PORT); |
| 688 | |
| 689 | expect(ok, v0, 0x11221100); |
| 690 | expect(ok, v1, 0x00000011); |
| 691 | expect(ok, v2, 0x11000000); |
| 692 | return ok; |
| 693 | } |
| 694 | |
| 695 | static unused int t_dma_fill3_vsram(void) |
| 696 | { |
| 697 | u32 v0, v1, v2; |
| 698 | int ok = 1; |
| 699 | |
| 700 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 701 | write32(VDP_DATA_PORT, 0); |
| 702 | write32(VDP_DATA_PORT, 0); |
| 703 | write32(VDP_DATA_PORT, 0); |
| 704 | |
| 705 | write16(VDP_DATA_PORT, 0x0111); |
| 706 | write16(VDP_DATA_PORT, 0x0222); |
| 707 | write16(VDP_DATA_PORT, 0x0333); |
| 708 | vdp_wait_for_fifo_empty(); |
| 709 | |
| 710 | VDP_setReg(VDP_AUTOINC, 3); |
| 711 | VDP_setReg(VDP_DMA_LEN0, 3); |
| 712 | VDP_setReg(VDP_DMA_SRC2, 0x80); |
| 713 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA); |
| 714 | write16(VDP_DATA_PORT, 0x0102); |
| 715 | vdp_wait_for_dma_idle(); |
| 716 | |
| 717 | VDP_setReg(VDP_AUTOINC, 2); |
| 718 | write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0)); |
| 719 | v0 = read32(VDP_DATA_PORT); |
| 720 | v1 = read32(VDP_DATA_PORT); |
| 721 | v2 = read32(VDP_DATA_PORT); |
| 722 | |
| 723 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 724 | write32(VDP_DATA_PORT, 0); |
| 725 | |
| 726 | expect(ok, v0, 0x01020000); |
| 727 | expect(ok, v1, 0x01110111); |
| 728 | expect(ok, v2, 0x00000111); |
| 729 | return ok; |
| 730 | } |
| 731 | |
| 732 | static int t_dma_fill_dis(void) |
| 733 | { |
| 734 | u32 v0, v1; |
| 735 | int ok = 1; |
| 736 | |
| 737 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 738 | write32(VDP_DATA_PORT, 0); |
| 739 | write32(VDP_DATA_PORT, 0); |
| 740 | |
| 741 | VDP_setReg(VDP_DMA_LEN0, 1); |
| 742 | VDP_setReg(VDP_DMA_SRC2, 0x80); |
| 743 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); |
| 744 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD); |
| 745 | write16(VDP_DATA_PORT, 0x1122); |
| 746 | vdp_wait_for_dma_idle(); |
| 747 | |
| 748 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 749 | write16(VDP_DATA_PORT, 0x3344); |
| 750 | vdp_wait_for_dma_idle(); |
| 751 | |
| 752 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 753 | v0 = read32(VDP_DATA_PORT); |
| 754 | v1 = read32(VDP_DATA_PORT); |
| 755 | |
| 756 | expect(ok, v0, 0); |
| 757 | expect(ok, v1, 0); |
| 758 | return ok; |
| 759 | } |
| 760 | |
| 761 | static int t_dma_fill_src(void) |
| 762 | { |
| 763 | const u32 *src = (const u32 *)0x3c0000; |
| 764 | u32 v0, v1; |
| 765 | int ok = 1; |
| 766 | |
| 767 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 768 | write32(VDP_DATA_PORT, 0); |
| 769 | |
| 770 | // do_setup_dma(src, 2); // hang, can't write src2 twice |
| 771 | VDP_setReg(VDP_DMA_LEN0, 2); |
| 772 | VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1); |
| 773 | VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9); |
| 774 | VDP_setReg(VDP_DMA_SRC2, 0x80); |
| 775 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); |
| 776 | write16(VDP_DATA_PORT, 0x1122); |
| 777 | vdp_wait_for_dma_idle(); |
| 778 | |
| 779 | VDP_setReg(VDP_DMA_LEN0, 2); |
| 780 | VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17); |
| 781 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA); |
| 782 | |
| 783 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 784 | v0 = read32(VDP_DATA_PORT); |
| 785 | v1 = read32(VDP_DATA_PORT); |
| 786 | |
| 787 | expect(ok, v0, 0x11220011); |
| 788 | expect(ok, v1, src[1]); |
| 789 | return ok; |
| 790 | } |
| 791 | |
| 792 | // (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1) |
| 793 | static int t_dma_128k(void) |
| 794 | { |
| 795 | u16 *ram = (u16 *)0xff0000; |
| 796 | u32 v0, v1; |
| 797 | int ok = 1; |
| 798 | |
| 799 | ram[0] = 0x5a11; |
| 800 | ram[1] = 0x5a22; |
| 801 | ram[2] = 0x5a33; |
| 802 | |
| 803 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 804 | write32(VDP_DATA_PORT, 0x01020304); |
| 805 | write32(VDP_DATA_PORT, 0x05060708); |
| 806 | vdp_wait_for_fifo_empty(); |
| 807 | |
| 808 | mem_barrier(); |
| 809 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K); |
| 810 | do_setup_dma(ram, 3); |
| 811 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); |
| 812 | vdp_wait_for_fifo_empty(); |
| 813 | |
| 814 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 815 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 816 | v0 = read32(VDP_DATA_PORT); |
| 817 | v1 = read32(VDP_DATA_PORT); |
| 818 | |
| 819 | expect(ok, v0, 0x22110304); |
| 820 | expect(ok, v1, 0x05330708); |
| 821 | return ok; |
| 822 | } |
| 823 | |
| 824 | static int t_vdp_128k_b16(void) |
| 825 | { |
| 826 | u32 v0, v1; |
| 827 | int ok = 1; |
| 828 | |
| 829 | VDP_setReg(VDP_AUTOINC, 0); |
| 830 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100)); |
| 831 | write32(VDP_DATA_PORT, 0x01020304); |
| 832 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100)); |
| 833 | write32(VDP_DATA_PORT, 0x05060708); |
| 834 | vdp_wait_for_fifo_empty(); |
| 835 | |
| 836 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K); |
| 837 | write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd |
| 838 | write32(VDP_DATA_PORT, 0x11223344); |
| 839 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102)); |
| 840 | write32(VDP_DATA_PORT, 0x55667788); |
| 841 | vdp_wait_for_fifo_empty(); |
| 842 | |
| 843 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 844 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100)); |
| 845 | v0 = read16(VDP_DATA_PORT); |
| 846 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100)); |
| 847 | v1 = read16(VDP_DATA_PORT); |
| 848 | |
| 849 | VDP_setReg(VDP_AUTOINC, 2); |
| 850 | |
| 851 | expect(ok, v0, 0x8844); |
| 852 | expect(ok, v1, 0x0708); |
| 853 | return ok; |
| 854 | } |
| 855 | |
| 856 | static unused int t_vdp_128k_b16_inc(void) |
| 857 | { |
| 858 | u32 v0, v1; |
| 859 | int ok = 1; |
| 860 | |
| 861 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0)); |
| 862 | write32(VDP_DATA_PORT, 0x01020304); |
| 863 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000)); |
| 864 | write32(VDP_DATA_PORT, 0x05060708); |
| 865 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe)); |
| 866 | write32(VDP_DATA_PORT, 0x090a0b0c); |
| 867 | vdp_wait_for_fifo_empty(); |
| 868 | |
| 869 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K); |
| 870 | write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd |
| 871 | write16(VDP_DATA_PORT, 0x1122); |
| 872 | vdp_wait_for_fifo_empty(); |
| 873 | |
| 874 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 875 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0)); |
| 876 | v0 = read32(VDP_DATA_PORT); |
| 877 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000)); |
| 878 | v1 = read32(VDP_DATA_PORT); |
| 879 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0)); |
| 880 | write32(VDP_DATA_PORT, 0); |
| 881 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000)); |
| 882 | write32(VDP_DATA_PORT, 0); |
| 883 | |
| 884 | expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere? |
| 885 | expect(ok, v1, 0x05060708); |
| 886 | return ok; |
| 887 | } |
| 888 | |
| 889 | static int t_vdp_reg_cmd(void) |
| 890 | { |
| 891 | u32 v0; |
| 892 | int ok = 1; |
| 893 | |
| 894 | VDP_setReg(VDP_AUTOINC, 0); |
| 895 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 896 | write32(VDP_DATA_PORT, 0x01020304); |
| 897 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 898 | write32(VDP_DATA_PORT, 0x05060708); |
| 899 | |
| 900 | VDP_setReg(VDP_AUTOINC, 2); |
| 901 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100)); |
| 902 | v0 = read16(VDP_DATA_PORT); |
| 903 | |
| 904 | expect(ok, v0, 0x0304); |
| 905 | return ok; |
| 906 | } |
| 907 | |
| 908 | static int t_vdp_sr_vb(void) |
| 909 | { |
| 910 | u16 sr[4]; |
| 911 | int ok = 1; |
| 912 | |
| 913 | while (read8(VDP_HV_COUNTER) != 242) |
| 914 | ; |
| 915 | sr[0] = read16(VDP_CTRL_PORT); |
| 916 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD); |
| 917 | sr[1] = read16(VDP_CTRL_PORT); |
| 918 | while (read8(VDP_HV_COUNTER) != 4) |
| 919 | ; |
| 920 | sr[2] = read16(VDP_CTRL_PORT); |
| 921 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 922 | sr[3] = read16(VDP_CTRL_PORT); |
| 923 | |
| 924 | expect_bits(ok, sr[0], SR_VB, SR_VB); |
| 925 | expect_bits(ok, sr[1], SR_VB, SR_VB); |
| 926 | expect_bits(ok, sr[2], SR_VB, SR_VB); |
| 927 | expect_bits(ok, sr[3], 0, SR_VB); |
| 928 | return ok; |
| 929 | } |
| 930 | |
| 931 | /* z80 tests assume busreq state */ |
| 932 | static int t_z80mem_long_mirror(void) |
| 933 | { |
| 934 | u8 *zram = (u8 *)0xa00000; |
| 935 | int ok = 1; |
| 936 | |
| 937 | write8(&zram[0x1100], 0x11); |
| 938 | write8(&zram[0x1101], 0x22); |
| 939 | write8(&zram[0x1102], 0x33); |
| 940 | write8(&zram[0x1103], 0x44); |
| 941 | mem_barrier(); |
| 942 | write32(&zram[0x3100], 0x55667788); |
| 943 | mem_barrier(); |
| 944 | |
| 945 | expect(ok, zram[0x1100], 0x55); |
| 946 | expect(ok, zram[0x1101], 0x22); |
| 947 | expect(ok, zram[0x1102], 0x77); |
| 948 | expect(ok, zram[0x1103], 0x44); |
| 949 | return ok; |
| 950 | } |
| 951 | |
| 952 | static int t_z80mem_noreq_w(void) |
| 953 | { |
| 954 | u8 *zram = (u8 *)0xa00000; |
| 955 | int ok = 1; |
| 956 | |
| 957 | write8(&zram[0x1100], 0x11); |
| 958 | mem_barrier(); |
| 959 | write16(0xa11100, 0x000); |
| 960 | write8(&zram[0x1100], 0x22); |
| 961 | mem_barrier(); |
| 962 | |
| 963 | write16(0xa11100, 0x100); |
| 964 | while (read16(0xa11100) & 0x100) |
| 965 | ; |
| 966 | |
| 967 | expect(ok, zram[0x1100], 0x11); |
| 968 | return ok; |
| 969 | } |
| 970 | |
| 971 | #define Z80_C_DISPATCH 113 // see z80_test.s80 |
| 972 | #define Z80_C_END 17 |
| 973 | #define Z80_C_END_VCNT 67 |
| 974 | |
| 975 | #define Z80_CYLES_TEST1(b) (Z80_C_DISPATCH + ((b) - 1) * 21 + 26 + Z80_C_END) |
| 976 | |
| 977 | static int t_z80mem_vdp_r(void) |
| 978 | { |
| 979 | u8 *zram = (u8 *)0xa00000; |
| 980 | int ok = 1; |
| 981 | |
| 982 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 983 | write32(VDP_DATA_PORT, 0x11223344); |
| 984 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 985 | |
| 986 | zram[0x1000] = 1; // cp |
| 987 | write16_z80le(&zram[0x1002], 0x7f00); // src |
| 988 | write16_z80le(&zram[0x1004], 0x1100); // dst |
| 989 | write16_z80le(&zram[0x1006], 2); // len |
| 990 | zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a; |
| 991 | mem_barrier(); |
| 992 | write16(0xa11100, 0x000); |
| 993 | burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10); |
| 994 | |
| 995 | write16(0xa11100, 0x100); |
| 996 | while (read16(0xa11100) & 0x100) |
| 997 | ; |
| 998 | |
| 999 | expect(ok, zram[0x1000], 0); |
| 1000 | expect(ok, zram[0x1100], 0x11); |
| 1001 | expect(ok, zram[0x1101], 0x44); |
| 1002 | expect(ok, zram[0x1102], 0x5a); |
| 1003 | return ok; |
| 1004 | } |
| 1005 | |
| 1006 | static unused int t_z80mem_vdp_w(void) |
| 1007 | { |
| 1008 | u8 *zram = (u8 *)0xa00000; |
| 1009 | u32 v0; |
| 1010 | int ok = 1; |
| 1011 | |
| 1012 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 1013 | write32(VDP_DATA_PORT, 0x11223344); |
| 1014 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 1015 | vdp_wait_for_fifo_empty(); |
| 1016 | |
| 1017 | zram[0x1000] = 1; // cp |
| 1018 | write16_z80le(&zram[0x1002], 0x1100); // src |
| 1019 | write16_z80le(&zram[0x1004], 0x7f00); // dst |
| 1020 | write16_z80le(&zram[0x1006], 2); // len |
| 1021 | zram[0x1100] = 0x55; |
| 1022 | zram[0x1101] = 0x66; |
| 1023 | mem_barrier(); |
| 1024 | write16(0xa11100, 0x000); |
| 1025 | burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10); |
| 1026 | |
| 1027 | write16(0xa11100, 0x100); |
| 1028 | while (read16(0xa11100) & 0x100) |
| 1029 | ; |
| 1030 | |
| 1031 | write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); |
| 1032 | v0 = read32(VDP_DATA_PORT); |
| 1033 | |
| 1034 | expect(ok, zram[0x1000], 0); |
| 1035 | expect(ok, v0, 0x55556666); |
| 1036 | return ok; |
| 1037 | } |
| 1038 | |
| 1039 | static int t_tim_loop(void) |
| 1040 | { |
| 1041 | u8 vcnt; |
| 1042 | int ok = 1; |
| 1043 | |
| 1044 | vdp_wait_for_line_0(); |
| 1045 | burn10(488*220/10); |
| 1046 | vcnt = read8(VDP_HV_COUNTER); |
| 1047 | mem_barrier(); |
| 1048 | |
| 1049 | //expect_range(ok, vcnt, 0x80, 0x80); |
| 1050 | expect(ok, vcnt, 223); |
| 1051 | return ok; |
| 1052 | } |
| 1053 | |
| 1054 | static int t_tim_z80_loop(void) |
| 1055 | { |
| 1056 | u8 pal = read8(0xa10001) & 0x40; |
| 1057 | u8 *zram = (u8 *)0xa00000; |
| 1058 | u16 z80_loops = pal ? 3420*(313*2+1)/15/100 : 3420*(262*2+1)/15/100; // 2fr + 1ln |
| 1059 | u16 _68k_loops = pal ? 3420*(313*2+1)/7/10 : 3420*(262*2+1)/7/10; |
| 1060 | int ok = 1; |
| 1061 | |
| 1062 | zram[0x1000] = 3; // idle loop, save vcnt |
| 1063 | write16_z80le(&zram[0x1002], 0); // src (unused) |
| 1064 | write16_z80le(&zram[0x1004], 0x1100); // vcnt dst |
| 1065 | write16_z80le(&zram[0x1006], z80_loops); // x100 cycles |
| 1066 | zram[0x1100] = 0; |
| 1067 | mem_barrier(); |
| 1068 | |
| 1069 | vdp_wait_for_line_0(); |
| 1070 | write16(0xa11100, 0x000); |
| 1071 | burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10); |
| 1072 | |
| 1073 | write16(0xa11100, 0x100); |
| 1074 | while (read16(0xa11100) & 0x100) |
| 1075 | ; |
| 1076 | expect(ok, zram[0x1000], 0); |
| 1077 | expect(ok, zram[0x1100], 1); |
| 1078 | return ok; |
| 1079 | } |
| 1080 | |
| 1081 | #define Z80_CYCLES_TEST2(b) (Z80_C_DISPATCH + (b) * 38 + Z80_C_END_VCNT) |
| 1082 | |
| 1083 | // 80 80 91 95-96 |
| 1084 | static void z80_read_loop(u8 *zram, u16 src) |
| 1085 | { |
| 1086 | const int pairs = 512 + 256; |
| 1087 | |
| 1088 | zram[0x1000] = 2; // read loop, save vcnt |
| 1089 | write16_z80le(&zram[0x1002], src); // src |
| 1090 | write16_z80le(&zram[0x1004], 0x1100); // vcnt dst |
| 1091 | write16_z80le(&zram[0x1006], pairs); // reads/2 |
| 1092 | zram[0x1100] = 0; |
| 1093 | mem_barrier(); |
| 1094 | |
| 1095 | vdp_wait_for_line_0(); |
| 1096 | write16(0xa11100, 0x000); |
| 1097 | burn10(Z80_CYCLES_TEST2(pairs) * 15 / 7 * 2 / 10); |
| 1098 | |
| 1099 | write16(0xa11100, 0x100); |
| 1100 | while (read16(0xa11100) & 0x100) |
| 1101 | ; |
| 1102 | } |
| 1103 | |
| 1104 | static int t_tim_z80_ram(void) |
| 1105 | { |
| 1106 | u8 *zram = (u8 *)0xa00000; |
| 1107 | int ok = 1; |
| 1108 | |
| 1109 | z80_read_loop(zram, 0); |
| 1110 | |
| 1111 | expect(ok, zram[0x1000], 0); |
| 1112 | expect_range(ok, zram[0x1100], 0x80, 0x80); |
| 1113 | return ok; |
| 1114 | } |
| 1115 | |
| 1116 | static int t_tim_z80_ym(void) |
| 1117 | { |
| 1118 | u8 *zram = (u8 *)0xa00000; |
| 1119 | int ok = 1; |
| 1120 | |
| 1121 | z80_read_loop(zram, 0x4000); |
| 1122 | |
| 1123 | expect(ok, zram[0x1000], 0); |
| 1124 | expect_range(ok, zram[0x1100], 0x80, 0x80); |
| 1125 | return ok; |
| 1126 | } |
| 1127 | |
| 1128 | static int t_tim_z80_vdp(void) |
| 1129 | { |
| 1130 | u8 *zram = (u8 *)0xa00000; |
| 1131 | int ok = 1; |
| 1132 | |
| 1133 | z80_read_loop(zram, 0x7f08); |
| 1134 | |
| 1135 | expect(ok, zram[0x1000], 0); |
| 1136 | expect_range(ok, zram[0x1100], 0x91, 0x91); |
| 1137 | return ok; |
| 1138 | } |
| 1139 | |
| 1140 | static int t_tim_z80_bank_rom(void) |
| 1141 | { |
| 1142 | u8 *zram = (u8 *)0xa00000; |
| 1143 | int i, ok = 1; |
| 1144 | |
| 1145 | for (i = 0; i < 17; i++) |
| 1146 | write8(0xa06000, 0); // bank 0 |
| 1147 | |
| 1148 | z80_read_loop(zram, 0x8000); |
| 1149 | |
| 1150 | expect(ok, zram[0x1000], 0); |
| 1151 | expect_range(ok, zram[0x1100], 0x95, 0x96); |
| 1152 | return ok; |
| 1153 | } |
| 1154 | |
| 1155 | /* borderline too slow */ |
| 1156 | #if 0 |
| 1157 | static void test_vcnt_vb(void) |
| 1158 | { |
| 1159 | const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter |
| 1160 | u32 *ram = (u32 *)0xff0000; |
| 1161 | u16 vcnt, vcnt_expect = 0; |
| 1162 | u16 sr, count = 0; |
| 1163 | u32 val, old; |
| 1164 | |
| 1165 | vdp_wait_for_line_0(); |
| 1166 | old = read32(srhv); |
| 1167 | *ram++ = old; |
| 1168 | for (;;) { |
| 1169 | val = read32(srhv); |
| 1170 | vcnt = val & 0xff00; |
| 1171 | if (vcnt == vcnt_expect) |
| 1172 | continue; |
| 1173 | sr = val >> 16; |
| 1174 | if (vcnt == 0 && !(sr & SR_VB)) // not VB |
| 1175 | break; // wrapped to start of frame |
| 1176 | // count++; |
| 1177 | vcnt_expect += 0x100; |
| 1178 | if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) { |
| 1179 | old = val; |
| 1180 | continue; |
| 1181 | } |
| 1182 | // should have a vcnt jump here |
| 1183 | *ram++ = old; |
| 1184 | *ram++ = val; |
| 1185 | vcnt_expect = vcnt; |
| 1186 | old = val; |
| 1187 | } |
| 1188 | *ram++ = val; |
| 1189 | *ram = count; |
| 1190 | mem_barrier(); |
| 1191 | } |
| 1192 | #endif |
| 1193 | |
| 1194 | static int t_tim_vcnt(void) |
| 1195 | { |
| 1196 | const u32 *ram32 = (u32 *)0xff0000; |
| 1197 | const u8 *ram = (u8 *)0xff0000; |
| 1198 | u8 pal = read8(0xa10001) & 0x40; |
| 1199 | u8 vc_jmp_b = pal ? 0x02 : 0xea; |
| 1200 | u8 vc_jmp_a = pal ? 0xca : 0xe5; |
| 1201 | u16 lines = pal ? 313 : 262; |
| 1202 | int ok = 1; |
| 1203 | |
| 1204 | test_vcnt_vb(); |
| 1205 | expect(ok, ram[0*4+2], 0); // line 0 |
| 1206 | expect_bits(ok, ram[0*4+1], 0, SR_VB); |
| 1207 | expect(ok, ram[1*4+2], 223); // last no blank |
| 1208 | expect_bits(ok, ram[1*4+1], 0, SR_VB); |
| 1209 | expect(ok, ram[2*4+2], 224); // 1st blank |
| 1210 | expect_bits(ok, ram[2*4+1], SR_VB, SR_VB); |
| 1211 | expect(ok, ram[3*4+2], vc_jmp_b); // before jump |
| 1212 | expect_bits(ok, ram[3*4+1], SR_VB, SR_VB); |
| 1213 | expect(ok, ram[4*4+2], vc_jmp_a); // after jump |
| 1214 | expect_bits(ok, ram[4*4+1], SR_VB, SR_VB); |
| 1215 | expect(ok, ram[5*4+2], 0xfe); // before vb clear |
| 1216 | expect_bits(ok, ram[5*4+1], SR_VB, SR_VB); |
| 1217 | expect(ok, ram[6*4+2], 0xff); // after vb clear |
| 1218 | expect_bits(ok, ram[6*4+1], 0, SR_VB); |
| 1219 | expect(ok, ram[7*4+2], 0); // next line 0 |
| 1220 | expect_bits(ok, ram[7*4+1], 0, SR_VB); |
| 1221 | expect(ok, ram32[8], lines - 1); |
| 1222 | return ok; |
| 1223 | } |
| 1224 | |
| 1225 | static int t_tim_vcnt_loops(void) |
| 1226 | { |
| 1227 | const u16 *ram16 = (u16 *)0xfff004; |
| 1228 | u8 pal = read8(0xa10001) & 0x40; |
| 1229 | u16 i, lines = pal ? 313 : 262; |
| 1230 | int ok = 1; |
| 1231 | |
| 1232 | test_vcnt_loops(); |
| 1233 | expect(ok, ram16[-1*2+0], 0xff); |
| 1234 | expect_range(ok, ram16[-1*2+1], 21, 22); |
| 1235 | for (i = 0; i < lines; i++) |
| 1236 | expect_range(ok, ram16[i*2+1], 19, 21); |
| 1237 | expect(ok, ram16[lines*2+0], 0); |
| 1238 | expect_range(ok, ram16[lines*2+1], 19, 21); |
| 1239 | return ok; |
| 1240 | } |
| 1241 | |
| 1242 | static int t_tim_hblank_h40(void) |
| 1243 | { |
| 1244 | const u8 *r = (u8 *)0xff0000; |
| 1245 | int ok = 1; |
| 1246 | |
| 1247 | test_hb(); |
| 1248 | |
| 1249 | // set: 0-2 |
| 1250 | expect_bits(ok, r[2], SR_HB, SR_HB); |
| 1251 | expect_bits(ok, r[5], SR_HB, SR_HB); |
| 1252 | // <wait> |
| 1253 | expect_bits(ok, r[7], SR_HB, SR_HB); |
| 1254 | // clear: 8-11 |
| 1255 | expect_bits(ok, r[12], 0, SR_HB); |
| 1256 | return ok; |
| 1257 | } |
| 1258 | |
| 1259 | static int t_tim_hblank_h32(void) |
| 1260 | { |
| 1261 | const u8 *r = (u8 *)0xff0000; |
| 1262 | int ok = 1; |
| 1263 | |
| 1264 | VDP_setReg(VDP_MODE4, 0x00); |
| 1265 | test_hb(); |
| 1266 | VDP_setReg(VDP_MODE4, 0x81); |
| 1267 | |
| 1268 | expect_bits(ok, r[0], 0, SR_HB); |
| 1269 | // set: 1-4 |
| 1270 | expect_bits(ok, r[4], SR_HB, SR_HB); |
| 1271 | expect_bits(ok, r[5], SR_HB, SR_HB); |
| 1272 | // <wait> |
| 1273 | expect_bits(ok, r[8], SR_HB, SR_HB); |
| 1274 | // clear: 9-11 |
| 1275 | expect_bits(ok, r[12], 0, SR_HB); |
| 1276 | return ok; |
| 1277 | } |
| 1278 | |
| 1279 | static int t_tim_vdp_as_vram_w(void) |
| 1280 | { |
| 1281 | int ok = 1; |
| 1282 | u8 vcnt; |
| 1283 | |
| 1284 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); |
| 1285 | vdp_wait_for_line_0(); |
| 1286 | write16_x16(VDP_DATA_PORT, 112*18 / 16, 0); |
| 1287 | vcnt = read8(VDP_HV_COUNTER); |
| 1288 | mem_barrier(); |
| 1289 | |
| 1290 | expect(ok, vcnt, 112*2-1); |
| 1291 | return ok; |
| 1292 | } |
| 1293 | |
| 1294 | static int t_tim_vdp_as_cram_w(void) |
| 1295 | { |
| 1296 | int ok = 1; |
| 1297 | u8 vcnt; |
| 1298 | |
| 1299 | write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0)); |
| 1300 | vdp_wait_for_line_0(); |
| 1301 | write16_x16(VDP_DATA_PORT, 112*18 / 16, 0); |
| 1302 | vcnt = read8(VDP_HV_COUNTER); |
| 1303 | mem_barrier(); |
| 1304 | |
| 1305 | setup_default_palette(); |
| 1306 | |
| 1307 | expect(ok, vcnt, 112); |
| 1308 | return ok; |
| 1309 | } |
| 1310 | |
| 1311 | static const u8 hcnt2tm[] = |
| 1312 | { |
| 1313 | 0x0a, 0x1d, 0x31, 0x44, 0x58, 0x6b, 0x7f, 0x92, |
| 1314 | 0xa6, 0xb9, 0xcc, 0x00, 0x00, 0x00, 0xe2, 0xf6 |
| 1315 | }; |
| 1316 | |
| 1317 | static int t_tim_ym_timer_z80(int is_b) |
| 1318 | { |
| 1319 | u8 pal = read8(0xa10001) & 0x40; |
| 1320 | u8 *zram = (u8 *)0xa00000; |
| 1321 | u8 *z80 = zram; |
| 1322 | u16 _68k_loops = 3420*(302+5+1)/7/10; // ~ (72*1024*2)/(3420./7) |
| 1323 | u16 start, end, diff; |
| 1324 | int ok = 1; |
| 1325 | |
| 1326 | zram[0x1000] = 4 + is_b; // ym2612 timer a/b test |
| 1327 | zram[0x1100] = zram[0x1101] = zram[0x1102] = zram[0x1103] = 0; |
| 1328 | mem_barrier(); |
| 1329 | |
| 1330 | vdp_wait_for_line_0(); |
| 1331 | write16(0xa11100, 0x000); |
| 1332 | |
| 1333 | burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10); |
| 1334 | |
| 1335 | write16(0xa11100, 0x100); |
| 1336 | while (read16(0xa11100) & 0x100) |
| 1337 | ; |
| 1338 | mem_barrier(); |
| 1339 | expect(ok, zram[0x1000], 0); |
| 1340 | (void)hcnt2tm; |
| 1341 | //start = ((u16)zram[0x1102] << 8) | hcnt2tm[zram[0x1103] >> 4]; |
| 1342 | //end = ((u16)zram[0x1100] << 8) | hcnt2tm[zram[0x1101] >> 4]; |
| 1343 | start = zram[0x1102]; |
| 1344 | end = zram[0x1100]; |
| 1345 | diff = end - start; |
| 1346 | if (pal) |
| 1347 | expect_range(ok, diff, 0xf4, 0xf6); |
| 1348 | else |
| 1349 | expect_range(ok, diff, 0x27, 0x29); |
| 1350 | write8(&z80[0x4001], 0); // stop, but should keep the flag |
| 1351 | mem_barrier(); |
| 1352 | burn10(32*6/10); // busy bit, 32 FM ticks (M/7/6) |
| 1353 | if (is_b) { |
| 1354 | expect(ok, z80[0x4000], 2); |
| 1355 | write8(&z80[0x4001], 0x20); // reset flag (reg 0x27, set up by z80) |
| 1356 | } |
| 1357 | else { |
| 1358 | expect(ok, z80[0x4000], 1); |
| 1359 | write8(&z80[0x4001], 0x10); |
| 1360 | } |
| 1361 | mem_barrier(); |
| 1362 | burn10(32*6/10); |
| 1363 | expect(ok, z80[0x4000], 0); |
| 1364 | return ok; |
| 1365 | } |
| 1366 | |
| 1367 | static int t_tim_ym_timera_z80(void) |
| 1368 | { |
| 1369 | return t_tim_ym_timer_z80(0); |
| 1370 | } |
| 1371 | |
| 1372 | static int t_tim_ym_timerb_z80(void) |
| 1373 | { |
| 1374 | return t_tim_ym_timer_z80(1); |
| 1375 | } |
| 1376 | |
| 1377 | static int t_tim_ym_timerb_stop(void) |
| 1378 | { |
| 1379 | const struct { |
| 1380 | //u8 vcnt_start; |
| 1381 | //u8 hcnt_start; |
| 1382 | u16 vcnt_start; |
| 1383 | u16 stat0; |
| 1384 | //u8 vcnt_end; |
| 1385 | //u8 hcnt_end; |
| 1386 | u16 vcnt_end; |
| 1387 | u16 stat1; |
| 1388 | } *t = (void *)0xfff000; |
| 1389 | u8 *z80 = (u8 *)0xa00000; |
| 1390 | u16 diff; |
| 1391 | int ok = 1; |
| 1392 | write16(0xa11100, 0x100); |
| 1393 | while (read16(0xa11100) & 0x100) |
| 1394 | ; |
| 1395 | test_ym_stopped_tick(); |
| 1396 | mem_barrier(); |
| 1397 | //start = ((u16)t->vcnt_start << 8) | hcnt2tm[t->hcnt_start >> 4]; |
| 1398 | //end = ((u16)t->vcnt_end << 8) | hcnt2tm[t->hcnt_end >> 4]; |
| 1399 | //diff = end - start; |
| 1400 | diff = t->vcnt_end - t->vcnt_start; |
| 1401 | //expect_range(ok, diff, 0x492, 0x5c2); // why so much variation? |
| 1402 | expect_range(ok, diff, 4, 5); |
| 1403 | expect(ok, t->stat0, 0); |
| 1404 | expect(ok, t->stat1, 2); |
| 1405 | expect(ok, z80[0x4000], 2); |
| 1406 | write8(&z80[0x4001], 0x30); |
| 1407 | return ok; |
| 1408 | } |
| 1409 | |
| 1410 | static int t_tim_ym_timer_ab_sync(void) |
| 1411 | { |
| 1412 | u16 v1, v2, v3, v4, v5, ln0, ln1, ln2; |
| 1413 | int ok = 1; |
| 1414 | |
| 1415 | vdp_wait_for_line_0(); |
| 1416 | v1 = test_ym_ab_sync(); |
| 1417 | |
| 1418 | ln0 = get_line(); |
| 1419 | burn10(3420*15/7/10); // ~15 scanlines |
| 1420 | write8(0xa04001, 0x3f); // clear, no reload |
| 1421 | burn10(12); // wait for busy to clear |
| 1422 | v2 = read8(0xa04000); |
| 1423 | v3 = test_ym_ab_sync2(); |
| 1424 | |
| 1425 | ln1 = get_line(); |
| 1426 | burn10(3420*15/7/10); // ~15 scanlines |
| 1427 | v4 = test_ym_ab_sync2(); |
| 1428 | |
| 1429 | ln2 = get_line(); |
| 1430 | burn10(3420*30/7/10); // ~35 scanlines |
| 1431 | v5 = read8(0xa04000); |
| 1432 | |
| 1433 | expect(ok, v1, 3); |
| 1434 | expect(ok, v2, 0); |
| 1435 | expect(ok, v3, 3); |
| 1436 | expect(ok, v4, 2); |
| 1437 | expect(ok, v5, 0); |
| 1438 | expect_range(ok, ln1-ln0, 18, 19); |
| 1439 | expect_range(ok, ln2-ln1, 32, 34); // almost always 33 |
| 1440 | return ok; |
| 1441 | } |
| 1442 | |
| 1443 | struct irq_test { |
| 1444 | u16 cnt; |
| 1445 | union { |
| 1446 | u16 hv; |
| 1447 | u8 v; |
| 1448 | } first, last; |
| 1449 | u16 pad; |
| 1450 | }; |
| 1451 | |
| 1452 | // broken on fresh boot due to uknown reasons |
| 1453 | static int t_irq_hint(void) |
| 1454 | { |
| 1455 | struct irq_test *it = (void *)0xfff000; |
| 1456 | struct irq_test *itv = it + 1; |
| 1457 | int ok = 1; |
| 1458 | |
| 1459 | memset_(it, 0, sizeof(*it) * 2); |
| 1460 | memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); |
| 1461 | memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); |
| 1462 | |
| 1463 | // without this, tests fail after cold boot |
| 1464 | while (!(read16(VDP_CTRL_PORT) & 8)) |
| 1465 | /* not blanking */; |
| 1466 | |
| 1467 | // for more fun, disable the display |
| 1468 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD); |
| 1469 | |
| 1470 | VDP_setReg(10, 0); |
| 1471 | while (read8(VDP_HV_COUNTER) != 100) |
| 1472 | ; |
| 1473 | while (read8(VDP_HV_COUNTER) != 229) |
| 1474 | ; |
| 1475 | // take the pending irq |
| 1476 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); |
| 1477 | move_sr(0x2000); |
| 1478 | burn10(488 * 2 / 10); |
| 1479 | move_sr(0x2700); |
| 1480 | expect(ok, it->first.v, 229); // pending irq trigger |
| 1481 | expect(ok, it->cnt, 1); |
| 1482 | expect(ok, itv->cnt, 0); |
| 1483 | |
| 1484 | // count irqs |
| 1485 | it->cnt = it->first.hv = it->last.hv = 0; |
| 1486 | move_sr(0x2000); |
| 1487 | while (read8(VDP_HV_COUNTER) != 4) |
| 1488 | ; |
| 1489 | while (read8(VDP_HV_COUNTER) != 228) |
| 1490 | ; |
| 1491 | move_sr(0x2700); |
| 1492 | expect(ok, it->cnt, 225); |
| 1493 | expect(ok, it->first.v, 0); |
| 1494 | expect(ok, it->last.v, 224); |
| 1495 | |
| 1496 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1497 | |
| 1498 | // detect reload line |
| 1499 | it->cnt = it->first.hv = it->last.hv = 0; |
| 1500 | VDP_setReg(10, 17); |
| 1501 | move_sr(0x2000); |
| 1502 | while (read16(VDP_CTRL_PORT) & 8) |
| 1503 | /* blanking */; |
| 1504 | VDP_setReg(10, 255); |
| 1505 | while (read8(VDP_HV_COUNTER) != 228) |
| 1506 | ; |
| 1507 | move_sr(0x2700); |
| 1508 | expect(ok, it->cnt, 1); |
| 1509 | expect(ok, it->first.v, 17); |
| 1510 | expect(ok, it->last.v, 17); |
| 1511 | |
| 1512 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 1513 | |
| 1514 | return ok; |
| 1515 | } |
| 1516 | |
| 1517 | static int t_irq_both_cpu_unmask(void) |
| 1518 | { |
| 1519 | struct irq_test *ith = (void *)0xfff000; |
| 1520 | struct irq_test *itv = ith + 1; |
| 1521 | u16 s0, s1; |
| 1522 | int ok = 1; |
| 1523 | |
| 1524 | memset_(ith, 0, sizeof(*ith) * 2); |
| 1525 | memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); |
| 1526 | memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); |
| 1527 | VDP_setReg(10, 0); |
| 1528 | while (read8(VDP_HV_COUNTER) != 100) |
| 1529 | ; |
| 1530 | while (read8(VDP_HV_COUNTER) != 226) |
| 1531 | ; |
| 1532 | VDP_setReg(10, 99); |
| 1533 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); |
| 1534 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP); |
| 1535 | /* go to active display line 100 */ |
| 1536 | while (read8(VDP_HV_COUNTER) != 100) |
| 1537 | ; |
| 1538 | s0 = read16(VDP_CTRL_PORT); |
| 1539 | s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT); |
| 1540 | move_sr(0x2700); |
| 1541 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 1542 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1543 | |
| 1544 | expect(ok, itv->cnt, 1); // vint count |
| 1545 | expect(ok, itv->first.v, 100); // vint line |
| 1546 | expect(ok, ith->cnt, 1); // hint count |
| 1547 | expect(ok, ith->first.v, 100); // hint line |
| 1548 | expect_bits(ok, s0, SR_F, SR_F); |
| 1549 | expect_bits(ok, s1, 0, SR_F); |
| 1550 | return ok; |
| 1551 | } |
| 1552 | |
| 1553 | static int t_irq_ack_v_h(void) |
| 1554 | { |
| 1555 | struct irq_test *ith = (void *)0xfff000; |
| 1556 | struct irq_test *itv = ith + 1; |
| 1557 | u16 s0, s1, s2; |
| 1558 | int ok = 1; |
| 1559 | |
| 1560 | memset_(ith, 0, sizeof(*ith) * 2); |
| 1561 | memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); |
| 1562 | memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); |
| 1563 | VDP_setReg(10, 0); |
| 1564 | /* ensure hcnt reload */ |
| 1565 | while (!(read16(VDP_CTRL_PORT) & 8)) |
| 1566 | /* not blanking */; |
| 1567 | while (read16(VDP_CTRL_PORT) & 8) |
| 1568 | /* blanking */; |
| 1569 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); |
| 1570 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0); |
| 1571 | while (read8(VDP_HV_COUNTER) != 100) |
| 1572 | ; |
| 1573 | while (read8(VDP_HV_COUNTER) != 226) |
| 1574 | ; |
| 1575 | s0 = read16(VDP_CTRL_PORT); |
| 1576 | s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT); |
| 1577 | burn10(666 / 10); |
| 1578 | s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT); |
| 1579 | burn10(488 / 10); |
| 1580 | move_sr(0x2700); |
| 1581 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 1582 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1583 | |
| 1584 | expect(ok, itv->cnt, 1); // vint count |
| 1585 | expect(ok, itv->first.v, 226); // vint line |
| 1586 | expect(ok, ith->cnt, 1); // hint count |
| 1587 | expect(ok, ith->first.v, 228); // hint line |
| 1588 | expect_bits(ok, s0, SR_F, SR_F); |
| 1589 | expect_bits(ok, s1, 0, SR_F); |
| 1590 | expect_bits(ok, s2, 0, SR_F); |
| 1591 | return ok; |
| 1592 | } |
| 1593 | |
| 1594 | static int t_irq_ack_v_h_2(void) |
| 1595 | { |
| 1596 | struct irq_test *ith = (void *)0xfff000; |
| 1597 | struct irq_test *itv = ith + 1; |
| 1598 | u16 s0, s1; |
| 1599 | int ok = 1; |
| 1600 | |
| 1601 | memset_(ith, 0, sizeof(*ith) * 2); |
| 1602 | memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); |
| 1603 | memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); |
| 1604 | VDP_setReg(10, 0); |
| 1605 | while (read8(VDP_HV_COUNTER) != 100) |
| 1606 | ; |
| 1607 | while (read8(VDP_HV_COUNTER) != 226) |
| 1608 | ; |
| 1609 | s0 = read16(VDP_CTRL_PORT); |
| 1610 | test_v_h_2(); |
| 1611 | s1 = read16(VDP_CTRL_PORT); |
| 1612 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 1613 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1614 | |
| 1615 | expect(ok, itv->cnt, 2); // vint count |
| 1616 | expect(ok, itv->first.v, 226); // vint line |
| 1617 | expect(ok, ith->cnt, 1); // hint count |
| 1618 | expect(ok, ith->first.v, 227); // hint line |
| 1619 | expect_bits(ok, s0, SR_F, SR_F); |
| 1620 | expect_bits(ok, s1, 0, SR_F); |
| 1621 | return ok; |
| 1622 | } |
| 1623 | |
| 1624 | static int t_irq_ack_h_v(void) |
| 1625 | { |
| 1626 | u16 *ram = (u16 *)0xfff000; |
| 1627 | u8 *ram8 = (u8 *)0xfff000; |
| 1628 | u16 s0, s1, s[4]; |
| 1629 | int ok = 1; |
| 1630 | |
| 1631 | ram[0] = ram[1] = ram[2] = |
| 1632 | ram[4] = ram[5] = ram[6] = 0; |
| 1633 | memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); |
| 1634 | memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); |
| 1635 | VDP_setReg(10, 0); |
| 1636 | while (read8(VDP_HV_COUNTER) != 100) |
| 1637 | ; |
| 1638 | while (read8(VDP_HV_COUNTER) != 226) |
| 1639 | ; |
| 1640 | s0 = read16(VDP_CTRL_PORT); |
| 1641 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); |
| 1642 | move_sr(0x2000); |
| 1643 | burn10(666 / 10); |
| 1644 | s1 = read16(VDP_CTRL_PORT); |
| 1645 | write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8) |
| 1646 | | VDP_MODE2_MD | VDP_MODE2_IE0, s); |
| 1647 | move_sr(0x2700); |
| 1648 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 1649 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1650 | |
| 1651 | expect(ok, ram[0], 1); // hint count |
| 1652 | expect(ok, ram8[2], 226); // hint line |
| 1653 | expect(ok, ram[4], 1); // vint count |
| 1654 | expect(ok, ram8[10], 228); // vint line |
| 1655 | expect_bits(ok, s0, SR_F, SR_F); |
| 1656 | expect_bits(ok, s1, SR_F, SR_F); |
| 1657 | expect_bits(ok, s[0], SR_F, SR_F); |
| 1658 | expect_bits(ok, s[1], SR_F, SR_F); |
| 1659 | expect_bits(ok, s[2], 0, SR_F); |
| 1660 | expect_bits(ok, s[3], 0, SR_F); |
| 1661 | return ok; |
| 1662 | } |
| 1663 | |
| 1664 | static int t_irq_ack_h_v_2(void) |
| 1665 | { |
| 1666 | u16 *ram = (u16 *)0xfff000; |
| 1667 | u8 *ram8 = (u8 *)0xfff000; |
| 1668 | u16 s0, s1; |
| 1669 | int ok = 1; |
| 1670 | |
| 1671 | ram[0] = ram[1] = ram[2] = |
| 1672 | ram[4] = ram[5] = ram[6] = 0; |
| 1673 | memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); |
| 1674 | memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); |
| 1675 | VDP_setReg(10, 0); |
| 1676 | while (read8(VDP_HV_COUNTER) != 100) |
| 1677 | ; |
| 1678 | while (read8(VDP_HV_COUNTER) != 226) |
| 1679 | ; |
| 1680 | s0 = read16(VDP_CTRL_PORT); |
| 1681 | test_h_v_2(); |
| 1682 | s1 = read16(VDP_CTRL_PORT); |
| 1683 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 1684 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1685 | |
| 1686 | expect(ok, ram[0], 2); // hint count |
| 1687 | expect(ok, ram8[2], 226); // hint first line |
| 1688 | expect(ok, ram8[4], 226); // hint last line |
| 1689 | expect(ok, ram[4], 0); // vint count |
| 1690 | expect(ok, ram8[10], 0); // vint line |
| 1691 | expect_bits(ok, s0, SR_F, SR_F); |
| 1692 | expect_bits(ok, s1, 0, SR_F); |
| 1693 | return ok; |
| 1694 | } |
| 1695 | |
| 1696 | static void t_irq_f_flag(void) |
| 1697 | { |
| 1698 | memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint); |
| 1699 | memset_((void *)0xff0000, 0, 10); |
| 1700 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP); |
| 1701 | test_f(); |
| 1702 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 1703 | } |
| 1704 | |
| 1705 | static int t_irq_f_flag_h40(void) |
| 1706 | { |
| 1707 | u8 f, *r = (u8 *)0xff0000; |
| 1708 | int ok = 1; |
| 1709 | |
| 1710 | t_irq_f_flag(); |
| 1711 | |
| 1712 | expect_bits(ok, r[0], 0, SR_F); |
| 1713 | expect_bits(ok, r[1], 0, SR_F); |
| 1714 | expect_bits(ok, r[2], 0, SR_F); |
| 1715 | // hits 1-3 times in range 3-9, usually ~5 |
| 1716 | f = r[3] | r[4] | r[5] | r[6] | r[7]; |
| 1717 | |
| 1718 | expect_bits(ok, r[10], 0, SR_F); |
| 1719 | expect_bits(ok, r[11], 0, SR_F); |
| 1720 | expect_bits(ok, f, SR_F, SR_F); |
| 1721 | return ok; |
| 1722 | } |
| 1723 | |
| 1724 | static int t_irq_f_flag_h32(void) |
| 1725 | { |
| 1726 | u8 f, *r = (u8 *)0xff0000; |
| 1727 | int ok = 1; |
| 1728 | |
| 1729 | VDP_setReg(VDP_MODE4, 0x00); |
| 1730 | t_irq_f_flag(); |
| 1731 | VDP_setReg(VDP_MODE4, 0x81); |
| 1732 | |
| 1733 | expect_bits(ok, r[0], 0, SR_F); |
| 1734 | expect_bits(ok, r[1], 0, SR_F); |
| 1735 | // hits 1-3 times in range 2-7, usually 3 |
| 1736 | f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7]; |
| 1737 | |
| 1738 | expect_bits(ok, r[8], 0, SR_F); |
| 1739 | expect_bits(ok, r[9], 0, SR_F); |
| 1740 | expect_bits(ok, r[10], 0, SR_F); |
| 1741 | expect_bits(ok, r[11], 0, SR_F); |
| 1742 | expect_bits(ok, f, SR_F, SR_F); |
| 1743 | return ok; |
| 1744 | } |
| 1745 | |
| 1746 | // 32X |
| 1747 | |
| 1748 | static int t_32x_init(void) |
| 1749 | { |
| 1750 | void (*do_32x_enable)(void) = (void *)0xff0040; |
| 1751 | u32 M_OK = MKLONG('M','_','O','K'); |
| 1752 | u32 S_OK = MKLONG('S','_','O','K'); |
| 1753 | u32 *r = (u32 *)0xa15100; |
| 1754 | u16 *r16 = (u16 *)r; |
| 1755 | int i, ok = 1; |
| 1756 | |
| 1757 | //v1070 = read32(0x1070); |
| 1758 | |
| 1759 | /* what does REN mean exactly? |
| 1760 | * Seems to be sometimes clear after reset */ |
| 1761 | for (i = 0; i < 1000000; i++) |
| 1762 | if (read16(r16) & 0x80) |
| 1763 | break; |
| 1764 | expect(ok, r16[0x00/2], 0x82); |
| 1765 | expect(ok, r16[0x02/2], 0); |
| 1766 | expect(ok, r16[0x04/2], 0); |
| 1767 | expect(ok, r16[0x06/2], 0); |
| 1768 | expect(ok, r[0x14/4], 0); |
| 1769 | expect(ok, r[0x18/4], 0); |
| 1770 | expect(ok, r[0x1c/4], 0); |
| 1771 | write32(&r[0x20/4], 0); // master resp |
| 1772 | write32(&r[0x24/4], 0); // slave resp |
| 1773 | write32(&r[0x28/4], 0); |
| 1774 | write32(&r[0x2c/4], 0); |
| 1775 | |
| 1776 | // could just set RV, but BIOS reads ROM, so can't |
| 1777 | memcpy_(do_32x_enable, x32x_enable, |
| 1778 | x32x_enable_end - x32x_enable); |
| 1779 | do_32x_enable(); |
| 1780 | |
| 1781 | expect(ok, r16[0x00/2], 0x83); |
| 1782 | expect(ok, r16[0x02/2], 0); |
| 1783 | expect(ok, r16[0x04/2], 0); |
| 1784 | expect(ok, r16[0x06/2], 1); // RV |
| 1785 | expect(ok, r[0x14/4], 0); |
| 1786 | expect(ok, r[0x18/4], 0); |
| 1787 | expect(ok, r[0x1c/4], 0); |
| 1788 | expect(ok, r[0x20/4], M_OK); |
| 1789 | while (!read16(&r16[0x24/2])) |
| 1790 | ; |
| 1791 | expect(ok, r[0x24/4], S_OK); |
| 1792 | write32(&r[0x20/4], 0); |
| 1793 | return ok; |
| 1794 | } |
| 1795 | |
| 1796 | static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave) |
| 1797 | { |
| 1798 | u16 v, *r = (u16 *)0xa15120; |
| 1799 | u16 cmd_s = cmd | (is_slave << 15); |
| 1800 | int i; |
| 1801 | |
| 1802 | write32(&r[4/2], a0); |
| 1803 | write32(&r[8/2], a1); |
| 1804 | mem_barrier(); |
| 1805 | write16(r, cmd_s); |
| 1806 | mem_barrier(); |
| 1807 | for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++) |
| 1808 | burn10(1); |
| 1809 | if (v != 0) { |
| 1810 | printf("cmd clr: %x\n", v); |
| 1811 | mem_barrier(); |
| 1812 | printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]); |
| 1813 | write16(r, 0); |
| 1814 | } |
| 1815 | v = read16(&r[1]); |
| 1816 | if (v != 0) { |
| 1817 | printf("cmd err: %x\n", v); |
| 1818 | write16(&r[1], 0); |
| 1819 | } |
| 1820 | } |
| 1821 | |
| 1822 | static int t_32x_echo(void) |
| 1823 | { |
| 1824 | u16 *r = (u16 *)0xa15120; |
| 1825 | int ok = 1; |
| 1826 | |
| 1827 | x32_cmd(CMD_ECHO, 0x12340000, 0, 0); |
| 1828 | expect(ok, r[0x06/2], 0x1234); |
| 1829 | x32_cmd(CMD_ECHO, 0x23450000, 0, 1); |
| 1830 | expect(ok, r[0x06/2], 0xa345); |
| 1831 | return ok; |
| 1832 | } |
| 1833 | |
| 1834 | static int t_32x_md_bios(void) |
| 1835 | { |
| 1836 | void (*do_call_c0)(int a, int d) = (void *)0xff0040; |
| 1837 | u8 *rmb = (u8 *)0xff0000; |
| 1838 | u32 *rl = (u32 *)0; |
| 1839 | int ok = 1; |
| 1840 | |
| 1841 | memcpy_(do_call_c0, test_32x_b_c0, |
| 1842 | test_32x_b_c0_end - test_32x_b_c0); |
| 1843 | write8(rmb, 0); |
| 1844 | do_call_c0(0xff0000, 0x5a); |
| 1845 | |
| 1846 | expect(ok, rmb[0], 0x5a); |
| 1847 | expect(ok, rl[0x04/4], 0x880200); |
| 1848 | expect(ok, rl[0x10/4], 0x880212); |
| 1849 | expect(ok, rl[0x94/4], 0x8802d8); |
| 1850 | return ok; |
| 1851 | } |
| 1852 | |
| 1853 | static int t_32x_md_rom(void) |
| 1854 | { |
| 1855 | u32 *rl = (u32 *)0; |
| 1856 | int ok = 1; |
| 1857 | |
| 1858 | expect(ok, rl[0x004/4], 0x880200); |
| 1859 | expect(ok, rl[0x100/4], 0x53454741); |
| 1860 | expect(ok, rl[0x70/4], 0); |
| 1861 | write32(&rl[0x70/4], 0xa5123456); |
| 1862 | write32(&rl[0x78/4], ~0); |
| 1863 | mem_barrier(); |
| 1864 | expect(ok, rl[0x78/4], 0x8802ae); |
| 1865 | expect(ok, rl[0x70/4], 0xa5123456); |
| 1866 | //expect(ok, rl[0x1070/4], v1070); |
| 1867 | write32(&rl[0x70/4], 0); |
| 1868 | // with RV 0x880000/0x900000 hangs, can't test |
| 1869 | return ok; |
| 1870 | } |
| 1871 | |
| 1872 | static int t_32x_md_fb(void) |
| 1873 | { |
| 1874 | u8 *fbb = (u8 *)0x840000; |
| 1875 | u16 *fbw = (u16 *)fbb; |
| 1876 | u32 *fbl = (u32 *)fbb; |
| 1877 | u8 *fob = (u8 *)0x860000; |
| 1878 | u16 *fow = (u16 *)fob; |
| 1879 | u32 *fol = (u32 *)fob; |
| 1880 | int ok = 1; |
| 1881 | |
| 1882 | fbl[0] = 0x12345678; |
| 1883 | fol[1] = 0x89abcdef; |
| 1884 | mem_barrier(); |
| 1885 | expect(ok, fbw[1], 0x5678); |
| 1886 | expect(ok, fow[2], 0x89ab); |
| 1887 | fbb[0] = 0; |
| 1888 | fob[1] = 0; |
| 1889 | fbw[1] = 0; |
| 1890 | fow[2] = 0; |
| 1891 | fow[3] = 1; |
| 1892 | mem_barrier(); |
| 1893 | fow[3] = 0x200; |
| 1894 | mem_barrier(); |
| 1895 | expect(ok, fol[0], 0x12340000); |
| 1896 | expect(ok, fbl[1], 0x89ab0201); |
| 1897 | return ok; |
| 1898 | } |
| 1899 | |
| 1900 | static int t_32x_sh_fb(void) |
| 1901 | { |
| 1902 | u32 *fbl = (u32 *)0x840000; |
| 1903 | int ok = 1; |
| 1904 | |
| 1905 | fbl[0] = 0x12345678; |
| 1906 | fbl[1] = 0x89abcdef; |
| 1907 | mem_barrier(); |
| 1908 | write8(0xa15100, 0x80); // FM=1 |
| 1909 | x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); |
| 1910 | x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); |
| 1911 | x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); |
| 1912 | x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); |
| 1913 | x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1); |
| 1914 | write8(0xa15100, 0x00); // FM=0 |
| 1915 | mem_barrier(); |
| 1916 | expect(ok, fbl[0], 0x12340000); |
| 1917 | expect(ok, fbl[1], 0x5aabcda5); |
| 1918 | return ok; |
| 1919 | } |
| 1920 | |
| 1921 | static int t_32x_disable(void) |
| 1922 | { |
| 1923 | void (*do_32x_disable)(void) = (void *)0xff0040; |
| 1924 | u32 *r = (u32 *)0xa15100; |
| 1925 | u16 *r16 = (u16 *)r; |
| 1926 | u32 *rl = (u32 *)0; |
| 1927 | int ok = 1; |
| 1928 | |
| 1929 | expect(ok, r16[0x00/2], 0x83); |
| 1930 | |
| 1931 | memcpy_(do_32x_disable, x32x_disable, |
| 1932 | x32x_disable_end - x32x_disable); |
| 1933 | do_32x_disable(); |
| 1934 | |
| 1935 | expect(ok, r16[0x00/2], 0x82); |
| 1936 | expect(ok, r16[0x02/2], 0); |
| 1937 | expect(ok, r16[0x04/2], 0); |
| 1938 | expect(ok, r16[0x06/2], 1); // RV |
| 1939 | expect(ok, r[0x14/4], 0); |
| 1940 | expect(ok, r[0x18/4], 0); |
| 1941 | expect(ok, r[0x1c/4], 0); |
| 1942 | expect(ok, rl[0x04/4], 0x000800); |
| 1943 | |
| 1944 | write16(&r16[0x06/2], 0); // can just set without ADEN |
| 1945 | mem_barrier(); |
| 1946 | expect(ok, r16[0x06/2], 0); // RV |
| 1947 | return ok; |
| 1948 | } |
| 1949 | |
| 1950 | enum { |
| 1951 | T_MD = 0, |
| 1952 | T_32 = 1, // 32X |
| 1953 | }; |
| 1954 | |
| 1955 | static const struct { |
| 1956 | u8 type; |
| 1957 | int (*test)(void); |
| 1958 | const char *name; |
| 1959 | } g_tests[] = { |
| 1960 | { T_MD, t_dma_zero_wrap, "dma zero len + wrap" }, |
| 1961 | { T_MD, t_dma_zero_fill, "dma zero len + fill" }, |
| 1962 | { T_MD, t_dma_ram_wrap, "dma ram wrap" }, |
| 1963 | { T_MD, t_dma_multi, "dma multi" }, |
| 1964 | { T_MD, t_dma_cram_wrap, "dma cram wrap" }, |
| 1965 | { T_MD, t_dma_vsram_wrap, "dma vsram wrap" }, |
| 1966 | { T_MD, t_dma_and_data, "dma and data" }, |
| 1967 | { T_MD, t_dma_short_cmd, "dma short cmd" }, |
| 1968 | { T_MD, t_dma_fill3_odd, "dma fill3 odd" }, |
| 1969 | { T_MD, t_dma_fill3_even, "dma fill3 even" }, |
| 1970 | { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" }, |
| 1971 | { T_MD, t_dma_fill_dis, "dma fill disabled" }, |
| 1972 | { T_MD, t_dma_fill_src, "dma fill src incr" }, |
| 1973 | { T_MD, t_dma_128k, "dma 128k mode" }, |
| 1974 | { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" }, |
| 1975 | // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery |
| 1976 | { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" }, |
| 1977 | { T_MD, t_vdp_sr_vb, "vdp status reg vb" }, |
| 1978 | { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" }, |
| 1979 | { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" }, |
| 1980 | { T_MD, t_z80mem_vdp_r, "z80 vdp read" }, |
| 1981 | // { t_z80mem_vdp_w, "z80 vdp write" }, // hang |
| 1982 | { T_MD, t_tim_loop, "time loop" }, |
| 1983 | { T_MD, t_tim_z80_loop, "time z80 loop" }, |
| 1984 | { T_MD, t_tim_z80_ram, "time z80 ram" }, |
| 1985 | { T_MD, t_tim_z80_ym, "time z80 ym2612" }, |
| 1986 | { T_MD, t_tim_z80_vdp, "time z80 vdp" }, |
| 1987 | { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" }, |
| 1988 | { T_MD, t_tim_vcnt, "time V counter" }, |
| 1989 | { T_MD, t_tim_vcnt_loops, "time vcnt loops" }, |
| 1990 | { T_MD, t_tim_hblank_h40, "time hblank h40" }, |
| 1991 | { T_MD, t_tim_hblank_h32, "time hblank h32" }, |
| 1992 | { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" }, |
| 1993 | { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" }, |
| 1994 | { T_MD, t_tim_ym_timera_z80, "time timer a z80" }, |
| 1995 | { T_MD, t_tim_ym_timerb_z80, "time timer b z80" }, |
| 1996 | { T_MD, t_tim_ym_timerb_stop, "timer b stop" }, |
| 1997 | { T_MD, t_tim_ym_timer_ab_sync,"timer ab sync" }, |
| 1998 | { T_MD, t_irq_hint, "irq4 / line" }, |
| 1999 | { T_MD, t_irq_both_cpu_unmask, "irq both umask" }, |
| 2000 | { T_MD, t_irq_ack_v_h, "irq ack v-h" }, |
| 2001 | { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" }, |
| 2002 | { T_MD, t_irq_ack_h_v, "irq ack h-v" }, |
| 2003 | { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" }, |
| 2004 | { T_MD, t_irq_f_flag_h40, "irq f flag h40" }, |
| 2005 | { T_MD, t_irq_f_flag_h32, "irq f flag h32" }, |
| 2006 | |
| 2007 | // the first one enables 32X, so must be kept |
| 2008 | // all tests assume RV=1 FM=0 |
| 2009 | { T_32, t_32x_init, "32x init" }, |
| 2010 | { T_32, t_32x_echo, "32x echo" }, |
| 2011 | { T_32, t_32x_md_bios, "32x md bios" }, |
| 2012 | { T_32, t_32x_md_rom, "32x md rom" }, |
| 2013 | { T_32, t_32x_md_fb, "32x md fb" }, |
| 2014 | { T_32, t_32x_sh_fb, "32x sh fb" }, |
| 2015 | { T_32, t_32x_disable, "32x disable" }, // must be last 32x |
| 2016 | }; |
| 2017 | |
| 2018 | static void setup_z80(void) |
| 2019 | { |
| 2020 | u8 *zram = (u8 *)0xa00000; |
| 2021 | int i, len; |
| 2022 | |
| 2023 | /* z80 */ |
| 2024 | write16(0xa11100, 0x100); |
| 2025 | write16(0xa11200, 0x100); |
| 2026 | |
| 2027 | while (read16(0xa11100) & 0x100) |
| 2028 | ; |
| 2029 | |
| 2030 | // load the default test program, clear it's data |
| 2031 | len = z80_test_end - z80_test; |
| 2032 | for (i = 0; i < len; i++) |
| 2033 | write8(&zram[i], z80_test[i]); |
| 2034 | for (i = 0x1000; i < 0x1007; i++) |
| 2035 | write8(&zram[i], 0); |
| 2036 | |
| 2037 | // reset |
| 2038 | write16(0xa11200, 0x000); |
| 2039 | write16(0xa11100, 0x000); |
| 2040 | burn10(1); |
| 2041 | write16(0xa11200, 0x100); |
| 2042 | |
| 2043 | burn10(50 * 15 / 7 / 10); // see z80_test.s80 |
| 2044 | |
| 2045 | // take back the bus |
| 2046 | write16(0xa11100, 0x100); |
| 2047 | while (read16(0xa11100) & 0x100) |
| 2048 | ; |
| 2049 | } |
| 2050 | |
| 2051 | static void wait_next_vsync(void) |
| 2052 | { |
| 2053 | while (read16(VDP_CTRL_PORT) & SR_VB) |
| 2054 | /* blanking */; |
| 2055 | while (!(read16(VDP_CTRL_PORT) & SR_VB)) |
| 2056 | /* not blanking */; |
| 2057 | } |
| 2058 | |
| 2059 | static unused int hexinc(char *c) |
| 2060 | { |
| 2061 | (*c)++; |
| 2062 | if (*c > 'f') { |
| 2063 | *c = '0'; |
| 2064 | return 1; |
| 2065 | } |
| 2066 | if (*c == '9' + 1) |
| 2067 | *c = 'a'; |
| 2068 | return 0; |
| 2069 | } |
| 2070 | |
| 2071 | int main() |
| 2072 | { |
| 2073 | int passed = 0; |
| 2074 | int skipped = 0; |
| 2075 | int have_32x; |
| 2076 | int en_32x; |
| 2077 | int ret; |
| 2078 | u8 v8; |
| 2079 | int i; |
| 2080 | |
| 2081 | setup_z80(); |
| 2082 | |
| 2083 | /* io */ |
| 2084 | write8(0xa10009, 0x40); |
| 2085 | |
| 2086 | /* setup VDP */ |
| 2087 | while (read16(VDP_CTRL_PORT) & 2) |
| 2088 | ; |
| 2089 | |
| 2090 | VDP_setReg(VDP_MODE1, VDP_MODE1_PS); |
| 2091 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA); |
| 2092 | VDP_setReg(VDP_MODE3, 0x00); |
| 2093 | VDP_setReg(VDP_MODE4, 0x81); |
| 2094 | VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10); |
| 2095 | VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13); |
| 2096 | VDP_setReg(VDP_SAT_BASE, SLIST >> 9); |
| 2097 | VDP_setReg(VDP_HSCROLL, HSCRL >> 10); |
| 2098 | VDP_setReg(VDP_AUTOINC, 2); |
| 2099 | VDP_setReg(VDP_SCROLLSZ, 0x01); |
| 2100 | VDP_setReg(VDP_BACKDROP, 0); |
| 2101 | |
| 2102 | // early tests |
| 2103 | t_dma_zero_wrap_early(); |
| 2104 | t_dma_zero_fill_early(); |
| 2105 | |
| 2106 | /* pattern 0 */ |
| 2107 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0)); |
| 2108 | for (i = 0; i < 32 / 4; i++) |
| 2109 | write32(VDP_DATA_PORT, 0); |
| 2110 | |
| 2111 | /* clear name tables */ |
| 2112 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE)); |
| 2113 | for (i = 0; i < PLANE_W * PLANE_H / 2; i++) |
| 2114 | write32(VDP_DATA_PORT, 0); |
| 2115 | |
| 2116 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE)); |
| 2117 | for (i = 0; i < PLANE_W * PLANE_H / 2; i++) |
| 2118 | write32(VDP_DATA_PORT, 0); |
| 2119 | |
| 2120 | /* SAT, h. scroll */ |
| 2121 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST)); |
| 2122 | write32(VDP_DATA_PORT, 0); |
| 2123 | |
| 2124 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL)); |
| 2125 | write32(VDP_DATA_PORT, 0); |
| 2126 | |
| 2127 | /* scroll plane vscroll */ |
| 2128 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 2129 | write32(VDP_DATA_PORT, 0); |
| 2130 | printf_ypos = 1; |
| 2131 | |
| 2132 | /* load font */ |
| 2133 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE)); |
| 2134 | for (i = 0; i < FONT_LEN * 32 / 4; i++) |
| 2135 | write32(VDP_DATA_PORT, font_base[i]); |
| 2136 | |
| 2137 | /* set colors */ |
| 2138 | setup_default_palette(); |
| 2139 | |
| 2140 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 2141 | |
| 2142 | have_32x = read32(0xa130ec) == MKLONG('M','A','R','S'); |
| 2143 | en_32x = have_32x && (read32(0xa15100) & 1); |
| 2144 | v8 = read8(0xa10001); |
| 2145 | printf("MD version: %02x %s %s %s%s\n", v8, |
| 2146 | (v8 & 0x80) ? "world" : "jap", |
| 2147 | (v8 & 0x40) ? "pal" : "ntsc", |
| 2148 | have_32x ? "32X" : "", |
| 2149 | en_32x ? "+" : ""); |
| 2150 | |
| 2151 | for (i = 0; i < ARRAY_SIZE(g_tests); i++) { |
| 2152 | // print test number if we haven't scrolled away |
| 2153 | if (printf_ypos < CSCREEN_H) { |
| 2154 | int old_ypos = printf_ypos; |
| 2155 | printf_ypos = 0; |
| 2156 | printf("%02d/%02d", i, ARRAY_SIZE(g_tests)); |
| 2157 | printf_ypos = old_ypos; |
| 2158 | printf_xpos = 0; |
| 2159 | } |
| 2160 | if ((g_tests[i].type & T_32) && !have_32x) { |
| 2161 | skipped++; |
| 2162 | continue; |
| 2163 | } |
| 2164 | ret = g_tests[i].test(); |
| 2165 | if (ret != 1) { |
| 2166 | text_pal = 2; |
| 2167 | printf("failed %d: %s\n", i, g_tests[i].name); |
| 2168 | text_pal = 0; |
| 2169 | } |
| 2170 | else |
| 2171 | passed++; |
| 2172 | } |
| 2173 | |
| 2174 | text_pal = 0; |
| 2175 | printf("%d/%d passed, %d skipped.\n", |
| 2176 | passed, ARRAY_SIZE(g_tests), skipped); |
| 2177 | |
| 2178 | printf_ypos = 0; |
| 2179 | printf(" "); |
| 2180 | |
| 2181 | for (i = 0; i < 60*60 && !(get_input() & BTNM_A); i++) |
| 2182 | wait_next_vsync(); |
| 2183 | #ifndef PICO |
| 2184 | // blank due to my lame tv being burn-in prone |
| 2185 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD); |
| 2186 | #endif |
| 2187 | while (!(get_input() & BTNM_A)) |
| 2188 | burn10(488*100/10); |
| 2189 | VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); |
| 2190 | |
| 2191 | |
| 2192 | { |
| 2193 | char c[3] = { '0', '0', '0' }; |
| 2194 | short hscroll = 0, vscroll = 0; |
| 2195 | short hsz = 1, vsz = 0; |
| 2196 | short cellmode = 0; |
| 2197 | |
| 2198 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE)); |
| 2199 | |
| 2200 | #if 0 |
| 2201 | for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) { |
| 2202 | write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32); |
| 2203 | c[0]++; |
| 2204 | if (c[0] == 'z' + 1) |
| 2205 | c[0] = 'a'; |
| 2206 | } |
| 2207 | #else |
| 2208 | for (i = 0; i < 8 * 1024 / 2 / 4; i++) { |
| 2209 | write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32); |
| 2210 | write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32); |
| 2211 | write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32); |
| 2212 | write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32); |
| 2213 | if (hexinc(&c[0])) |
| 2214 | if (hexinc(&c[1])) |
| 2215 | hexinc(&c[2]); |
| 2216 | } |
| 2217 | #endif |
| 2218 | while (get_input() & BTNM_A) |
| 2219 | wait_next_vsync(); |
| 2220 | |
| 2221 | wait_next_vsync(); |
| 2222 | for (;;) { |
| 2223 | int b = get_input(); |
| 2224 | |
| 2225 | if (b & BTNM_C) { |
| 2226 | hscroll = 1, vscroll = -1; |
| 2227 | do { |
| 2228 | wait_next_vsync(); |
| 2229 | } while (get_input() & BTNM_C); |
| 2230 | cellmode ^= 1; |
| 2231 | } |
| 2232 | if (b & (BTNM_L | BTNM_R | BTNM_C)) { |
| 2233 | hscroll += (b & BTNM_L) ? 1 : -1; |
| 2234 | write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL)); |
| 2235 | write16(VDP_DATA_PORT, hscroll); |
| 2236 | } |
| 2237 | if (b & (BTNM_U | BTNM_D | BTNM_C)) { |
| 2238 | vscroll += (b & BTNM_U) ? -1 : 1; |
| 2239 | write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); |
| 2240 | if (cellmode) { |
| 2241 | int end = (int)vscroll + 21; |
| 2242 | for (i = vscroll; i < end; i++) |
| 2243 | write32(VDP_DATA_PORT, i << 17); |
| 2244 | VDP_setReg(VDP_MODE3, 0x04); |
| 2245 | } |
| 2246 | else { |
| 2247 | write16(VDP_DATA_PORT, vscroll); |
| 2248 | VDP_setReg(VDP_MODE3, 0x00); |
| 2249 | } |
| 2250 | } |
| 2251 | if (b & BTNM_A) { |
| 2252 | hsz = (hsz + 1) & 3; |
| 2253 | do { |
| 2254 | wait_next_vsync(); |
| 2255 | } while (get_input() & BTNM_A); |
| 2256 | } |
| 2257 | if (b & BTNM_B) { |
| 2258 | vsz = (vsz + 1) & 3; |
| 2259 | do { |
| 2260 | wait_next_vsync(); |
| 2261 | } while (get_input() & BTNM_B); |
| 2262 | } |
| 2263 | VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz); |
| 2264 | |
| 2265 | printf_xpos = 1; |
| 2266 | printf_ypos = 0; |
| 2267 | text_pal = 1; |
| 2268 | printf(" %d %d ", hsz, vsz); |
| 2269 | |
| 2270 | wait_next_vsync(); |
| 2271 | } |
| 2272 | } |
| 2273 | |
| 2274 | for (;;) |
| 2275 | ; |
| 2276 | |
| 2277 | return 0; |
| 2278 | } |
| 2279 | |
| 2280 | // vim:ts=4:sw=4:expandtab |