| 1 | /* |
| 2 | * PicoDrive |
| 3 | * (C) notaz, 2009,2010,2013 |
| 4 | * |
| 5 | * This work is licensed under the terms of MAME license. |
| 6 | * See COPYING file in the top-level directory. |
| 7 | */ |
| 8 | #include "../pico_int.h" |
| 9 | #include "../sound/ym2612.h" |
| 10 | |
| 11 | struct Pico32x Pico32x; |
| 12 | SH2 sh2s[2]; |
| 13 | |
| 14 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
| 15 | { |
| 16 | if (sh2->pending_irl > sh2->pending_int_irq) { |
| 17 | elprintf(EL_32X, "%csh2 ack/irl %d @ %08x", |
| 18 | sh2->is_slave ? 's' : 'm', level, sh2->pc); |
| 19 | return 64 + sh2->pending_irl / 2; |
| 20 | } else { |
| 21 | elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x", |
| 22 | sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc); |
| 23 | sh2->pending_int_irq = 0; // auto-clear |
| 24 | sh2->pending_level = sh2->pending_irl; |
| 25 | return sh2->pending_int_vector; |
| 26 | } |
| 27 | } |
| 28 | |
| 29 | // if !nested_call, must sync CPUs before calling this |
| 30 | void p32x_update_irls(int nested_call) |
| 31 | { |
| 32 | int irqs, mlvl = 0, slvl = 0; |
| 33 | int mrun, srun; |
| 34 | |
| 35 | // msh2 |
| 36 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
| 37 | while ((irqs >>= 1)) |
| 38 | mlvl++; |
| 39 | mlvl *= 2; |
| 40 | |
| 41 | // ssh2 |
| 42 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
| 43 | while ((irqs >>= 1)) |
| 44 | slvl++; |
| 45 | slvl *= 2; |
| 46 | |
| 47 | mrun = sh2_irl_irq(&msh2, mlvl, nested_call); |
| 48 | srun = sh2_irl_irq(&ssh2, slvl, nested_call); |
| 49 | p32x_poll_event(mrun | (srun << 1), 0); |
| 50 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
| 51 | } |
| 52 | |
| 53 | void Pico32xStartup(void) |
| 54 | { |
| 55 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
| 56 | |
| 57 | // TODO: OOM handling |
| 58 | PicoAHW |= PAHW_32X; |
| 59 | sh2_init(&msh2, 0); |
| 60 | msh2.irq_callback = sh2_irq_cb; |
| 61 | sh2_init(&ssh2, 1); |
| 62 | ssh2.irq_callback = sh2_irq_cb; |
| 63 | |
| 64 | PicoMemSetup32x(); |
| 65 | p32x_timers_recalc(); |
| 66 | |
| 67 | if (!Pico.m.pal) |
| 68 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
| 69 | |
| 70 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
| 71 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
| 72 | |
| 73 | rendstatus_old = -1; |
| 74 | |
| 75 | emu_32x_startup(); |
| 76 | } |
| 77 | |
| 78 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
| 79 | void p32x_reset_sh2s(void) |
| 80 | { |
| 81 | elprintf(EL_32X, "sh2 reset"); |
| 82 | |
| 83 | sh2_reset(&msh2); |
| 84 | sh2_reset(&ssh2); |
| 85 | |
| 86 | // if we don't have BIOS set, perform it's work here. |
| 87 | // MSH2 |
| 88 | if (p32x_bios_m == NULL) { |
| 89 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
| 90 | unsigned int vbr; |
| 91 | |
| 92 | // initial data |
| 93 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
| 94 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
| 95 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
| 96 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
| 97 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
| 98 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
| 99 | idl_src, idl_dst, idl_size); |
| 100 | } |
| 101 | else |
| 102 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
| 103 | |
| 104 | // GBR/VBR |
| 105 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
| 106 | sh2_set_gbr(0, 0x20004000); |
| 107 | sh2_set_vbr(0, vbr); |
| 108 | |
| 109 | // checksum and M_OK |
| 110 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
| 111 | // program will set M_OK |
| 112 | } |
| 113 | |
| 114 | // SSH2 |
| 115 | if (p32x_bios_s == NULL) { |
| 116 | unsigned int vbr; |
| 117 | |
| 118 | // GBR/VBR |
| 119 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
| 120 | sh2_set_gbr(1, 0x20004000); |
| 121 | sh2_set_vbr(1, vbr); |
| 122 | // program will set S_OK |
| 123 | } |
| 124 | |
| 125 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); |
| 126 | } |
| 127 | |
| 128 | void Pico32xInit(void) |
| 129 | { |
| 130 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
| 131 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
| 132 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
| 133 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
| 134 | } |
| 135 | |
| 136 | void PicoPower32x(void) |
| 137 | { |
| 138 | memset(&Pico32x, 0, sizeof(Pico32x)); |
| 139 | |
| 140 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
| 141 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
| 142 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
| 143 | } |
| 144 | |
| 145 | void PicoUnload32x(void) |
| 146 | { |
| 147 | if (Pico32xMem != NULL) |
| 148 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
| 149 | Pico32xMem = NULL; |
| 150 | sh2_finish(&msh2); |
| 151 | sh2_finish(&ssh2); |
| 152 | |
| 153 | PicoAHW &= ~PAHW_32X; |
| 154 | } |
| 155 | |
| 156 | void PicoReset32x(void) |
| 157 | { |
| 158 | if (PicoAHW & PAHW_32X) { |
| 159 | Pico32x.sh2irqs |= P32XI_VRES; |
| 160 | p32x_update_irls(0); |
| 161 | p32x_poll_event(3, 0); |
| 162 | p32x_timers_recalc(); |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | static void p32x_start_blank(void) |
| 167 | { |
| 168 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
| 169 | int offs, lines; |
| 170 | |
| 171 | pprof_start(draw); |
| 172 | |
| 173 | offs = 8; lines = 224; |
| 174 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
| 175 | offs = 0; |
| 176 | lines = 240; |
| 177 | } |
| 178 | |
| 179 | // XXX: no proper handling of 32col mode.. |
| 180 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
| 181 | (Pico.video.reg[12] & 1) && // 40col mode |
| 182 | (PicoDrawMask & PDRAW_32X_ON)) |
| 183 | { |
| 184 | int md_bg = Pico.video.reg[7] & 0x3f; |
| 185 | |
| 186 | // we draw full layer (not line-by-line) |
| 187 | PicoDraw32xLayer(offs, lines, md_bg); |
| 188 | } |
| 189 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
| 190 | PicoDraw32xLayerMdOnly(offs, lines); |
| 191 | |
| 192 | pprof_end(draw); |
| 193 | } |
| 194 | |
| 195 | // enter vblank |
| 196 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
| 197 | |
| 198 | // FB swap waits until vblank |
| 199 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
| 200 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
| 201 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
| 202 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
| 203 | } |
| 204 | |
| 205 | Pico32x.sh2irqs |= P32XI_VINT; |
| 206 | p32x_update_irls(0); |
| 207 | p32x_poll_event(3, 1); |
| 208 | } |
| 209 | |
| 210 | /* events */ |
| 211 | static void pwm_irq_event(unsigned int now) |
| 212 | { |
| 213 | Pico32x.emu_flags &= ~P32XF_PWM_PEND; |
| 214 | p32x_pwm_schedule(now); |
| 215 | |
| 216 | Pico32x.sh2irqs |= P32XI_PWM; |
| 217 | p32x_update_irls(0); |
| 218 | } |
| 219 | |
| 220 | static void fillend_event(unsigned int now) |
| 221 | { |
| 222 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
| 223 | p32x_poll_event(3, 1); |
| 224 | } |
| 225 | |
| 226 | typedef void (event_cb)(unsigned int now); |
| 227 | |
| 228 | unsigned int event_times[P32X_EVENT_COUNT]; |
| 229 | static unsigned int event_time_next; |
| 230 | static event_cb *event_cbs[] = { |
| 231 | [P32X_EVENT_PWM] = pwm_irq_event, |
| 232 | [P32X_EVENT_FILLEND] = fillend_event, |
| 233 | }; |
| 234 | |
| 235 | // schedule event at some time (in m68k clocks) |
| 236 | void p32x_event_schedule(enum p32x_event event, unsigned int now, int after) |
| 237 | { |
| 238 | unsigned int when = (now + after) | 1; |
| 239 | |
| 240 | elprintf(EL_32X, "new event #%u %u->%u", event, now, when); |
| 241 | event_times[event] = when; |
| 242 | |
| 243 | if (event_time_next == 0 || (int)(event_time_next - now) > after) |
| 244 | event_time_next = when; |
| 245 | } |
| 246 | |
| 247 | static void run_events(unsigned int until) |
| 248 | { |
| 249 | int oldest, oldest_diff, time; |
| 250 | int i, diff; |
| 251 | |
| 252 | while (1) { |
| 253 | oldest = -1, oldest_diff = 0x7fffffff; |
| 254 | |
| 255 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
| 256 | if (event_times[i]) { |
| 257 | diff = event_times[i] - until; |
| 258 | if (diff < oldest_diff) { |
| 259 | oldest_diff = diff; |
| 260 | oldest = i; |
| 261 | } |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | if (oldest_diff <= 0) { |
| 266 | time = event_times[oldest]; |
| 267 | event_times[oldest] = 0; |
| 268 | elprintf(EL_32X, "run event #%d %u", oldest, time); |
| 269 | event_cbs[oldest](time); |
| 270 | } |
| 271 | else if (oldest_diff < 0x7fffffff) { |
| 272 | event_time_next = event_times[oldest]; |
| 273 | break; |
| 274 | } |
| 275 | else { |
| 276 | event_time_next = 0; |
| 277 | break; |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | if (oldest != -1) |
| 282 | elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next); |
| 283 | } |
| 284 | |
| 285 | // compare cycles, handling overflows |
| 286 | // check if a > b |
| 287 | #define CYCLES_GT(a, b) \ |
| 288 | ((int)((a) - (b)) > 0) |
| 289 | // check if a >= b |
| 290 | #define CYCLES_GE(a, b) \ |
| 291 | ((int)((a) - (b)) >= 0) |
| 292 | |
| 293 | #define sync_sh2s_normal p32x_sync_sh2s |
| 294 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
| 295 | |
| 296 | /* most timing is in 68k clock */ |
| 297 | void sync_sh2s_normal(unsigned int m68k_target) |
| 298 | { |
| 299 | unsigned int now, target, timer_cycles; |
| 300 | int cycles, done; |
| 301 | |
| 302 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
| 303 | |
| 304 | if (!(Pico32x.regs[0] & P32XS_nRES)) |
| 305 | return; // rare |
| 306 | |
| 307 | now = msh2.m68krcycles_done; |
| 308 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
| 309 | now = ssh2.m68krcycles_done; |
| 310 | timer_cycles = now; |
| 311 | |
| 312 | while (CYCLES_GT(m68k_target, now)) |
| 313 | { |
| 314 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
| 315 | run_events(now); |
| 316 | |
| 317 | target = m68k_target; |
| 318 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
| 319 | target = event_time_next; |
| 320 | |
| 321 | while (CYCLES_GT(target, now)) |
| 322 | { |
| 323 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
| 324 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
| 325 | m68k_target - now, Pico32x.emu_flags); |
| 326 | |
| 327 | if (Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL)) { |
| 328 | ssh2.m68krcycles_done = target; |
| 329 | } |
| 330 | else { |
| 331 | cycles = target - ssh2.m68krcycles_done; |
| 332 | if (cycles > 0) { |
| 333 | done = sh2_execute(&ssh2, C_M68K_TO_SH2(ssh2, cycles)); |
| 334 | ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done); |
| 335 | |
| 336 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
| 337 | target = event_time_next; |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | if (Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL)) { |
| 342 | msh2.m68krcycles_done = target; |
| 343 | } |
| 344 | else { |
| 345 | cycles = target - msh2.m68krcycles_done; |
| 346 | if (cycles > 0) { |
| 347 | done = sh2_execute(&msh2, C_M68K_TO_SH2(msh2, cycles)); |
| 348 | msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done); |
| 349 | |
| 350 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
| 351 | target = event_time_next; |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | now = msh2.m68krcycles_done; |
| 356 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
| 357 | now = ssh2.m68krcycles_done; |
| 358 | } |
| 359 | |
| 360 | p32x_timers_do(now - timer_cycles); |
| 361 | timer_cycles = now; |
| 362 | } |
| 363 | } |
| 364 | |
| 365 | #define STEP_68K 24 |
| 366 | |
| 367 | void sync_sh2s_lockstep(unsigned int m68k_target) |
| 368 | { |
| 369 | unsigned int mcycles; |
| 370 | |
| 371 | mcycles = msh2.m68krcycles_done; |
| 372 | if (ssh2.m68krcycles_done < mcycles) |
| 373 | mcycles = ssh2.m68krcycles_done; |
| 374 | |
| 375 | while (mcycles < m68k_target) { |
| 376 | mcycles += STEP_68K; |
| 377 | sync_sh2s_normal(mcycles); |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \ |
| 382 | SekRunM68k(m68k_cycles); \ |
| 383 | if (Pico32x.emu_flags & P32XF_68KPOLL) \ |
| 384 | p32x_sync_sh2s(SekCycleCntT + SekCycleCnt); \ |
| 385 | } while (0) |
| 386 | |
| 387 | #define PICO_32X |
| 388 | #include "../pico_cmn.c" |
| 389 | |
| 390 | void PicoFrame32x(void) |
| 391 | { |
| 392 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
| 393 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
| 394 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
| 395 | |
| 396 | p32x_poll_event(3, 1); |
| 397 | |
| 398 | PicoFrameStart(); |
| 399 | PicoFrameHints(); |
| 400 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
| 401 | } |
| 402 | |
| 403 | // calculate multipliers against 68k clock (7670442) |
| 404 | // normally * 3, but effectively slower due to high latencies everywhere |
| 405 | // however using something lower breaks MK2 animations |
| 406 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
| 407 | { |
| 408 | float m68k_clk = (float)(OSC_NTSC / 7); |
| 409 | if (msh2_hz > 0) { |
| 410 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
| 411 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
| 412 | } |
| 413 | if (ssh2_hz > 0) { |
| 414 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
| 415 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | // vim:shiftwidth=2:ts=2:expandtab |