32x: improve irq handling + few bugfixes
[picodrive.git] / pico / 32x / 32x.c
... / ...
CommitLineData
1#include "../pico_int.h"
2#include "../sound/ym2612.h"
3
4struct Pico32x Pico32x;
5SH2 sh2s[2];
6
7static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
8{
9 if (sh2->pending_irl > sh2->pending_int_irq) {
10 elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
11 sh2->is_slave ? 's' : 'm', level, sh2->pc);
12 return 64 + sh2->pending_irl / 2;
13 } else {
14 elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
15 sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
16 sh2->pending_int_irq = 0; // auto-clear
17 sh2->pending_level = sh2->pending_irl;
18 return sh2->pending_int_vector;
19 }
20}
21
22void p32x_update_irls(int nested_call)
23{
24 int irqs, mlvl = 0, slvl = 0;
25
26 // msh2
27 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
28 while ((irqs >>= 1))
29 mlvl++;
30 mlvl *= 2;
31
32 // ssh2
33 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
34 while ((irqs >>= 1))
35 slvl++;
36 slvl *= 2;
37
38 elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl);
39 sh2_irl_irq(&msh2, mlvl, nested_call);
40 sh2_irl_irq(&ssh2, slvl, nested_call);
41 mlvl = mlvl ? 1 : 0;
42 slvl = slvl ? 1 : 0;
43 p32x_poll_event(mlvl | (slvl << 1), 0);
44}
45
46void Pico32xStartup(void)
47{
48 elprintf(EL_STATUS|EL_32X, "32X startup");
49
50 // TODO: OOM handling
51 PicoAHW |= PAHW_32X;
52 sh2_init(&msh2, 0);
53 msh2.irq_callback = sh2_irq_cb;
54 sh2_init(&ssh2, 1);
55 ssh2.irq_callback = sh2_irq_cb;
56
57 PicoMemSetup32x();
58
59 if (!Pico.m.pal)
60 Pico32x.vdp_regs[0] |= P32XV_nPAL;
61
62 PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
63 PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
64
65 emu_32x_startup();
66}
67
68#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
69void p32x_reset_sh2s(void)
70{
71 elprintf(EL_32X, "sh2 reset");
72
73 sh2_reset(&msh2);
74 sh2_reset(&ssh2);
75
76 // if we don't have BIOS set, perform it's work here.
77 // MSH2
78 if (p32x_bios_m == NULL) {
79 unsigned int idl_src, idl_dst, idl_size; // initial data load
80 unsigned int vbr;
81
82 // initial data
83 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
84 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
85 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
86 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
87 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
88 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
89 idl_src, idl_dst, idl_size);
90 }
91 else
92 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
93
94 // GBR/VBR
95 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
96 sh2_set_gbr(0, 0x20004000);
97 sh2_set_vbr(0, vbr);
98
99 // checksum and M_OK
100 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
101 // program will set M_OK
102 }
103
104 // SSH2
105 if (p32x_bios_s == NULL) {
106 unsigned int vbr;
107
108 // GBR/VBR
109 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
110 sh2_set_gbr(1, 0x20004000);
111 sh2_set_vbr(1, vbr);
112 // program will set S_OK
113 }
114}
115
116void Pico32xInit(void)
117{
118}
119
120void PicoPower32x(void)
121{
122 memset(&Pico32x, 0, sizeof(Pico32x));
123
124 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
125 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
126 Pico32x.sh2_regs[0] = P32XS2_ADEN;
127}
128
129void PicoUnload32x(void)
130{
131 if (Pico32xMem != NULL)
132 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
133 Pico32xMem = NULL;
134 sh2_finish(&msh2);
135 sh2_finish(&ssh2);
136
137 PicoAHW &= ~PAHW_32X;
138}
139
140void PicoReset32x(void)
141{
142 if (PicoAHW & PAHW_32X) {
143 Pico32x.sh2irqs |= P32XI_VRES;
144 p32x_update_irls(0);
145 p32x_poll_event(3, 0);
146 }
147}
148
149static void p32x_start_blank(void)
150{
151 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
152 int offs, lines;
153
154 pprof_start(draw);
155
156 offs = 8; lines = 224;
157 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
158 offs = 0;
159 lines = 240;
160 }
161
162 // XXX: no proper handling of 32col mode..
163 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
164 (Pico.video.reg[12] & 1) && // 40col mode
165 (PicoDrawMask & PDRAW_32X_ON))
166 {
167 int md_bg = Pico.video.reg[7] & 0x3f;
168
169 // we draw full layer (not line-by-line)
170 PicoDraw32xLayer(offs, lines, md_bg);
171 }
172 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
173 PicoDraw32xLayerMdOnly(offs, lines);
174
175 pprof_end(draw);
176 }
177
178 // enter vblank
179 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
180
181 // FB swap waits until vblank
182 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
183 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
184 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
185 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
186 }
187
188 Pico32x.sh2irqs |= P32XI_VINT;
189 p32x_update_irls(0);
190 p32x_poll_event(3, 1);
191}
192
193static __inline void run_m68k(int cyc)
194{
195 pprof_start(m68k);
196
197#if defined(EMU_C68K)
198 PicoCpuCM68k.cycles = cyc;
199 CycloneRun(&PicoCpuCM68k);
200 SekCycleCnt += cyc - PicoCpuCM68k.cycles;
201#elif defined(EMU_M68K)
202 SekCycleCnt += m68k_execute(cyc);
203#elif defined(EMU_F68K)
204 SekCycleCnt += fm68k_emulate(cyc+1, 0, 0);
205#endif
206
207 pprof_end(m68k);
208}
209
210// ~1463.8, but due to cache misses and slow mem
211// it's much lower than that
212//#define SH2_LINE_CYCLES 735
213#define CYCLES_M68K2SH2(x) ((x) * 6 / 4)
214
215#define PICO_32X
216#define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \
217{ \
218 int slice; \
219 SekCycleAim += m68k_cycles; \
220 while (SekCycleCnt < SekCycleAim) { \
221 slice = SekCycleCnt; \
222 run_m68k(SekCycleAim - SekCycleCnt); \
223 if (!(Pico32x.regs[0] & P32XS_nRES)) \
224 continue; /* SH2s reseting */ \
225 slice = SekCycleCnt - slice; /* real count from 68k */ \
226 if (SekCycleCnt < SekCycleAim) \
227 elprintf(EL_32X, "slice %d", slice); \
228 if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) { \
229 pprof_start(ssh2); \
230 sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \
231 pprof_end(ssh2); \
232 } \
233 if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) { \
234 pprof_start(msh2); \
235 sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \
236 pprof_end(msh2); \
237 } \
238 pprof_start(dummy); \
239 pprof_end(dummy); \
240 } \
241}
242
243#define STEP_68K 24
244#define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \
245{ \
246 int i; \
247 for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \
248 run_m68k(STEP_68K); \
249 if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \
250 sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \
251 if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \
252 sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \
253 } \
254 /* last step */ \
255 i = (m68k_cycles) - i; \
256 run_m68k(i); \
257 if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \
258 sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \
259 if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \
260 sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \
261}
262
263#define CPUS_RUN CPUS_RUN_SIMPLE
264//#define CPUS_RUN CPUS_RUN_LOCKSTEP
265
266#include "../pico_cmn.c"
267
268void PicoFrame32x(void)
269{
270 pwm_frame_smp_cnt = 0;
271
272 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
273 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
274 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
275
276 p32x_poll_event(3, 1);
277
278 PicoFrameStart();
279 PicoFrameHints();
280 elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags);
281}
282