| 1 | #include "../pico_int.h" |
| 2 | #include "../sound/ym2612.h" |
| 3 | |
| 4 | SH2 sh2s[2]; |
| 5 | struct Pico32x Pico32x; |
| 6 | |
| 7 | static void sh2_irq_cb(int id, int level) |
| 8 | { |
| 9 | // diagnostic for now |
| 10 | elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id)); |
| 11 | } |
| 12 | |
| 13 | void p32x_update_irls(void) |
| 14 | { |
| 15 | int irqs, mlvl = 0, slvl = 0; |
| 16 | |
| 17 | // msh2 |
| 18 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
| 19 | while ((irqs >>= 1)) |
| 20 | mlvl++; |
| 21 | mlvl *= 2; |
| 22 | |
| 23 | // ssh2 |
| 24 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
| 25 | while ((irqs >>= 1)) |
| 26 | slvl++; |
| 27 | slvl *= 2; |
| 28 | |
| 29 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
| 30 | sh2_irl_irq(&msh2, mlvl); |
| 31 | sh2_irl_irq(&ssh2, slvl); |
| 32 | mlvl = mlvl ? 1 : 0; |
| 33 | slvl = slvl ? 1 : 0; |
| 34 | p32x_poll_event(mlvl | (slvl << 1), 0); |
| 35 | } |
| 36 | |
| 37 | void Pico32xStartup(void) |
| 38 | { |
| 39 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
| 40 | |
| 41 | PicoAHW |= PAHW_32X; |
| 42 | PicoMemSetup32x(); |
| 43 | |
| 44 | sh2_init(&msh2, 0); |
| 45 | msh2.irq_callback = sh2_irq_cb; |
| 46 | sh2_reset(&msh2); |
| 47 | |
| 48 | sh2_init(&ssh2, 1); |
| 49 | ssh2.irq_callback = sh2_irq_cb; |
| 50 | sh2_reset(&ssh2); |
| 51 | |
| 52 | if (!Pico.m.pal) |
| 53 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
| 54 | |
| 55 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
| 56 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
| 57 | |
| 58 | emu_32x_startup(); |
| 59 | } |
| 60 | |
| 61 | void Pico32xInit(void) |
| 62 | { |
| 63 | } |
| 64 | |
| 65 | void PicoPower32x(void) |
| 66 | { |
| 67 | memset(&Pico32x, 0, sizeof(Pico32x)); |
| 68 | |
| 69 | Pico32x.regs[0] = 0x0082; // SH2 reset? |
| 70 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
| 71 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
| 72 | } |
| 73 | |
| 74 | void PicoUnload32x(void) |
| 75 | { |
| 76 | if (Pico32xMem != NULL) |
| 77 | free(Pico32xMem); |
| 78 | Pico32xMem = NULL; |
| 79 | |
| 80 | PicoAHW &= ~PAHW_32X; |
| 81 | } |
| 82 | |
| 83 | void PicoReset32x(void) |
| 84 | { |
| 85 | extern int p32x_csum_faked; |
| 86 | p32x_csum_faked = 0; // tmp |
| 87 | } |
| 88 | |
| 89 | static void p32x_start_blank(void) |
| 90 | { |
| 91 | // enter vblank |
| 92 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
| 93 | |
| 94 | // FB swap waits until vblank |
| 95 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
| 96 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
| 97 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
| 98 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
| 99 | } |
| 100 | |
| 101 | Pico32x.sh2irqs |= P32XI_VINT; |
| 102 | p32x_update_irls(); |
| 103 | p32x_poll_event(3, 1); |
| 104 | } |
| 105 | |
| 106 | static __inline void run_m68k(int cyc) |
| 107 | { |
| 108 | #if defined(EMU_C68K) |
| 109 | PicoCpuCM68k.cycles = cyc; |
| 110 | CycloneRun(&PicoCpuCM68k); |
| 111 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
| 112 | #elif defined(EMU_M68K) |
| 113 | SekCycleCnt += m68k_execute(cyc); |
| 114 | #elif defined(EMU_F68K) |
| 115 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
| 116 | #endif |
| 117 | } |
| 118 | |
| 119 | // ~1463.8, but due to cache misses and slow mem |
| 120 | // it's much lower than that |
| 121 | //#define SH2_LINE_CYCLES 735 |
| 122 | #define CYCLES_M68K2SH2(x) ((x) * 6 / 4) |
| 123 | |
| 124 | #define PICO_32X |
| 125 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
| 126 | { \ |
| 127 | int slice; \ |
| 128 | SekCycleAim += m68k_cycles; \ |
| 129 | while (SekCycleCnt < SekCycleAim) { \ |
| 130 | slice = SekCycleCnt; \ |
| 131 | run_m68k(SekCycleAim - SekCycleCnt); \ |
| 132 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
| 133 | if (SekCycleCnt < SekCycleAim) \ |
| 134 | elprintf(EL_32X, "slice %d", slice); \ |
| 135 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
| 136 | sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \ |
| 137 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
| 138 | sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \ |
| 139 | } \ |
| 140 | } |
| 141 | |
| 142 | #define STEP_68K 24 |
| 143 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
| 144 | { \ |
| 145 | int i; \ |
| 146 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
| 147 | run_m68k(STEP_68K); \ |
| 148 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
| 149 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
| 150 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
| 151 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
| 152 | } \ |
| 153 | /* last step */ \ |
| 154 | i = (m68k_cycles) - i; \ |
| 155 | run_m68k(i); \ |
| 156 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
| 157 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
| 158 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
| 159 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
| 160 | } |
| 161 | |
| 162 | #define CPUS_RUN CPUS_RUN_SIMPLE |
| 163 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
| 164 | |
| 165 | #include "../pico_cmn.c" |
| 166 | |
| 167 | void PicoFrame32x(void) |
| 168 | { |
| 169 | pwm_frame_smp_cnt = 0; |
| 170 | |
| 171 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
| 172 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
| 173 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
| 174 | |
| 175 | p32x_poll_event(3, 1); |
| 176 | |
| 177 | PicoFrameStart(); |
| 178 | PicoFrameHints(); |
| 179 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
| 180 | } |
| 181 | |