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cd: delay gfx ops again
[picodrive.git] / pico / 32x / memory.c
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1/*
2 * PicoDrive
3 * (C) notaz, 2009,2010,2013
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 *
8 * Register map:
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 0 (16bit VRES clr) 4014
18 * a15116 0 (16bit Vint clr) 4016
19 * a15118 0 (16bit Hint clr) 4018
20 * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
21 * a1511c 0 (16bit PWM clr) 401c
22 * a1511e 0 ? 401e
23 * a15120 (16 bytes comm) 2020
24 * a15130 (PWM) 2030
25 *
26 * SH2 addr lines:
27 * iii. .cc. ..xx * // Internal, Cs, x
28 *
29 * sh2 map, wait/bus cycles (from docs):
30 * r w
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * cart 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
39 * d.a. c0000000-?
40 */
41#include "../pico_int.h"
42#include "../memory.h"
43#include "../../cpu/sh2/compiler.h"
44
45static const char str_mars[] = "MARS";
46
47void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48struct Pico32xMem *Pico32xMem;
49
50static void bank_switch(int b);
51
52// addressing byte in 16bit reg
53#define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
54
55// poll detection
56#define POLL_THRESHOLD 3
57
58static struct {
59 u32 addr, cycles;
60 int cnt;
61} m68k_poll;
62
63static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
64{
65 int ret = 0;
66
67 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
68 && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
69 {
70 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
71 if (!(Pico32x.emu_flags & flags)) {
72 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
73 a, cycles - m68k_poll.cycles);
74 ret = 1;
75 }
76 Pico32x.emu_flags |= flags;
77 }
78 }
79 else {
80 m68k_poll.cnt = 0;
81 m68k_poll.addr = a;
82 SekNotPolling = 0;
83 }
84 m68k_poll.cycles = cycles;
85
86 return ret;
87}
88
89void p32x_m68k_poll_event(u32 flags)
90{
91 if (Pico32x.emu_flags & flags) {
92 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
93 Pico32x.emu_flags & ~flags);
94 Pico32x.emu_flags &= ~flags;
95 SekSetStop(0);
96 }
97 m68k_poll.addr = m68k_poll.cnt = 0;
98}
99
100static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
101{
102 int cycles_left = sh2_cycles_left(sh2);
103
104 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
105 if (sh2->poll_cnt++ > maxcnt) {
106 if (!(sh2->state & flags))
107 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
108 sh2->state, sh2->state | flags);
109
110 sh2->state |= flags;
111 sh2_end_run(sh2, 1);
112 pevt_log_sh2(sh2, EVT_POLL_START);
113 return;
114 }
115 }
116 else
117 sh2->poll_cnt = 0;
118 sh2->poll_addr = a;
119 sh2->poll_cycles = cycles_left;
120}
121
122void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
123{
124 if (sh2->state & flags) {
125 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
126 sh2->state & ~flags);
127
128 if (sh2->m68krcycles_done < m68k_cycles)
129 sh2->m68krcycles_done = m68k_cycles;
130
131 pevt_log_sh2_o(sh2, EVT_POLL_END);
132 }
133
134 sh2->state &= ~flags;
135 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
136}
137
138static void sh2s_sync_on_read(SH2 *sh2)
139{
140 int cycles;
141 if (sh2->poll_cnt != 0)
142 return;
143
144 cycles = sh2_cycles_done(sh2);
145 if (cycles > 600)
146 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
147}
148
149// SH2 faking
150//#define FAKE_SH2
151#ifdef FAKE_SH2
152static int p32x_csum_faked;
153static const u16 comm_fakevals[] = {
154 0x4d5f, 0x4f4b, // M_OK
155 0x535f, 0x4f4b, // S_OK
156 0x4D41, 0x5346, // MASF - Brutal Unleashed
157 0x5331, 0x4d31, // Darxide
158 0x5332, 0x4d32,
159 0x5333, 0x4d33,
160 0x0000, 0x0000, // eq for doom
161 0x0002, // Mortal Kombat
162// 0, // pad
163};
164
165static u32 sh2_comm_faker(u32 a)
166{
167 static int f = 0;
168 if (a == 0x28 && !p32x_csum_faked) {
169 p32x_csum_faked = 1;
170 return *(unsigned short *)(Pico.rom + 0x18e);
171 }
172 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
173 f = 0;
174 return comm_fakevals[f++];
175}
176#endif
177
178// ------------------------------------------------------------------
179// 68k regs
180
181static u32 p32x_reg_read16(u32 a)
182{
183 a &= 0x3e;
184
185#if 0
186 if ((a & 0x30) == 0x20)
187 return sh2_comm_faker(a);
188#else
189 if ((a & 0x30) == 0x20) {
190 unsigned int cycles = SekCyclesDone();
191 int comreg = 1 << (a & 0x0f) / 2;
192
193 if (cycles - msh2.m68krcycles_done > 244
194 || (Pico32x.comm_dirty_68k & comreg))
195 p32x_sync_sh2s(cycles);
196
197 if (Pico32x.comm_dirty_sh2 & comreg)
198 Pico32x.comm_dirty_sh2 &= ~comreg;
199 else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
200 SekSetStop(1);
201 SekEndRun(16);
202 }
203 goto out;
204 }
205#endif
206
207 if (a == 2) { // INTM, INTS
208 unsigned int cycles = SekCyclesDone();
209 if (cycles - msh2.m68krcycles_done > 64)
210 p32x_sync_sh2s(cycles);
211 goto out;
212 }
213
214 if ((a & 0x30) == 0x30)
215 return p32x_pwm_read16(a, NULL, SekCyclesDone());
216
217out:
218 return Pico32x.regs[a / 2];
219}
220
221static void dreq0_write(u16 *r, u32 d)
222{
223 if (!(r[6 / 2] & P32XS_68S)) {
224 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
225 return; // ignored - tested
226 }
227 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
228 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
229 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
230 r[6 / 2] |= P32XS_FULL;
231 // tested: len register decrements and 68S clears
232 // even if SH2s/DMAC aren't active..
233 r[0x10 / 2]--;
234 if (r[0x10 / 2] == 0)
235 r[6 / 2] &= ~P32XS_68S;
236
237 if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
238 p32x_sync_sh2s(SekCyclesDone());
239 p32x_dreq0_trigger();
240 }
241 }
242 else
243 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
244}
245
246// writable bits tested
247static void p32x_reg_write8(u32 a, u32 d)
248{
249 u16 *r = Pico32x.regs;
250 a &= 0x3f;
251
252 // for things like bset on comm port
253 m68k_poll.cnt = 0;
254
255 switch (a) {
256 case 0x00: // adapter ctl: FM writable
257 REG8IN16(r, 0x00) = d & 0x80;
258 return;
259 case 0x01: // adapter ctl: RES and ADEN writable
260 if ((d ^ r[0]) & d & P32XS_nRES)
261 p32x_reset_sh2s();
262 REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
263 REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
264 return;
265 case 0x02: // ignored, always 0
266 return;
267 case 0x03: // irq ctl
268 if ((d ^ r[0x02 / 2]) & 3) {
269 int cycles = SekCyclesDone();
270 p32x_sync_sh2s(cycles);
271 r[0x02 / 2] = d & 3;
272 p32x_update_cmd_irq(NULL, cycles);
273 }
274 return;
275 case 0x04: // ignored, always 0
276 return;
277 case 0x05: // bank
278 d &= 3;
279 if (r[0x04 / 2] != d) {
280 r[0x04 / 2] = d;
281 bank_switch(d);
282 }
283 return;
284 case 0x06: // ignored, always 0
285 return;
286 case 0x07: // DREQ ctl
287 REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
288 if (!(d & P32XS_68S)) {
289 Pico32x.dmac0_fifo_ptr = 0;
290 REG8IN16(r, 0x07) &= ~P32XS_FULL;
291 }
292 REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
293 return;
294 case 0x08: // ignored, always 0
295 return;
296 case 0x09: // DREQ src
297 REG8IN16(r, 0x09) = d;
298 return;
299 case 0x0a:
300 REG8IN16(r, 0x0a) = d;
301 return;
302 case 0x0b:
303 REG8IN16(r, 0x0b) = d & 0xfe;
304 return;
305 case 0x0c: // ignored, always 0
306 return;
307 case 0x0d: // DREQ dest
308 case 0x0e:
309 case 0x0f:
310 case 0x10: // DREQ len
311 REG8IN16(r, a) = d;
312 return;
313 case 0x11:
314 REG8IN16(r, a) = d & 0xfc;
315 return;
316 // DREQ FIFO - writes to odd addr go to fifo
317 // do writes to even work? Reads return 0
318 case 0x12:
319 REG8IN16(r, a) = d;
320 return;
321 case 0x13:
322 d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
323 REG8IN16(r, 0x12) = 0;
324 dreq0_write(r, d);
325 return;
326 case 0x14: // ignored, always 0
327 case 0x15:
328 case 0x16:
329 case 0x17:
330 case 0x18:
331 case 0x19:
332 return;
333 case 0x1a: // what's this?
334 elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
335 REG8IN16(r, a) = d & 0x01;
336 return;
337 case 0x1b: // TV
338 REG8IN16(r, a) = d & 0x01;
339 return;
340 case 0x1c: // ignored, always 0
341 case 0x1d:
342 case 0x1e:
343 case 0x1f:
344 case 0x30:
345 return;
346 case 0x31: // PWM control
347 REG8IN16(r, a) &= ~0x0f;
348 REG8IN16(r, a) |= d & 0x0f;
349 d = r[0x30 / 2];
350 goto pwm_write;
351 case 0x32: // PWM cycle
352 REG8IN16(r, a) = d & 0x0f;
353 d = r[0x32 / 2];
354 goto pwm_write;
355 case 0x33:
356 REG8IN16(r, a) = d;
357 d = r[0x32 / 2];
358 goto pwm_write;
359 // PWM pulse regs.. Only writes to odd address send a value
360 // to FIFO; reads are 0 (except status bits)
361 case 0x34:
362 case 0x36:
363 case 0x38:
364 REG8IN16(r, a) = d;
365 return;
366 case 0x35:
367 case 0x37:
368 case 0x39:
369 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
370 REG8IN16(r, a ^ 1) = 0;
371 goto pwm_write;
372 case 0x3a: // ignored, always 0
373 case 0x3b:
374 case 0x3c:
375 case 0x3d:
376 case 0x3e:
377 case 0x3f:
378 return;
379 pwm_write:
380 p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
381 return;
382 }
383
384 if ((a & 0x30) == 0x20) {
385 int cycles = SekCyclesDone();
386 int comreg;
387
388 if (REG8IN16(r, a) == d)
389 return;
390
391 comreg = 1 << (a & 0x0f) / 2;
392 if (Pico32x.comm_dirty_68k & comreg)
393 p32x_sync_sh2s(cycles);
394
395 REG8IN16(r, a) = d;
396 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
397 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
398 Pico32x.comm_dirty_68k |= comreg;
399
400 if (cycles - (int)msh2.m68krcycles_done > 120)
401 p32x_sync_sh2s(cycles);
402 return;
403 }
404}
405
406static void p32x_reg_write16(u32 a, u32 d)
407{
408 u16 *r = Pico32x.regs;
409 a &= 0x3e;
410
411 // for things like bset on comm port
412 m68k_poll.cnt = 0;
413
414 switch (a) {
415 case 0x00: // adapter ctl
416 if ((d ^ r[0]) & d & P32XS_nRES)
417 p32x_reset_sh2s();
418 r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
419 r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
420 return;
421 case 0x08: // DREQ src
422 r[a / 2] = d & 0xff;
423 return;
424 case 0x0a:
425 r[a / 2] = d & ~1;
426 return;
427 case 0x0c: // DREQ dest
428 r[a / 2] = d & 0xff;
429 return;
430 case 0x0e:
431 r[a / 2] = d;
432 return;
433 case 0x10: // DREQ len
434 r[a / 2] = d & ~3;
435 return;
436 case 0x12: // FIFO reg
437 dreq0_write(r, d);
438 return;
439 case 0x1a: // TV + mystery bit
440 r[a / 2] = d & 0x0101;
441 return;
442 case 0x30: // PWM control
443 d = (r[a / 2] & ~0x0f) | (d & 0x0f);
444 r[a / 2] = d;
445 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
446 return;
447 }
448
449 // comm port
450 if ((a & 0x30) == 0x20) {
451 int cycles = SekCyclesDone();
452 int comreg;
453
454 if (r[a / 2] == d)
455 return;
456
457 comreg = 1 << (a & 0x0f) / 2;
458 if (Pico32x.comm_dirty_68k & comreg)
459 p32x_sync_sh2s(cycles);
460
461 r[a / 2] = d;
462 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
463 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
464 Pico32x.comm_dirty_68k |= comreg;
465
466 if (cycles - (int)msh2.m68krcycles_done > 120)
467 p32x_sync_sh2s(cycles);
468 return;
469 }
470 // PWM
471 else if ((a & 0x30) == 0x30) {
472 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
473 return;
474 }
475
476 p32x_reg_write8(a + 1, d);
477}
478
479// ------------------------------------------------------------------
480// VDP regs
481static u32 p32x_vdp_read16(u32 a)
482{
483 u32 d;
484 a &= 0x0e;
485
486 d = Pico32x.vdp_regs[a / 2];
487 if (a == 0x0a) {
488 // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
489 // most often at 0xb1-0xb5, even during vblank,
490 // what's the deal with that?
491 // we'll just fake it along with hblank for now
492 Pico32x.vdp_fbcr_fake++;
493 if (Pico32x.vdp_fbcr_fake & 4)
494 d |= P32XV_HBLK;
495 if ((Pico32x.vdp_fbcr_fake & 7) == 0)
496 d |= P32XV_nFEN;
497 }
498 return d;
499}
500
501static void p32x_vdp_write8(u32 a, u32 d)
502{
503 u16 *r = Pico32x.vdp_regs;
504 a &= 0x0f;
505
506 // TODO: verify what's writeable
507 switch (a) {
508 case 0x01:
509 // priority inversion is handled in palette
510 if ((r[0] ^ d) & P32XV_PRI)
511 Pico32x.dirty_pal = 1;
512 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
513 break;
514 case 0x03: // shift (for pp mode)
515 r[2 / 2] = d & 1;
516 break;
517 case 0x05: // fill len
518 r[4 / 2] = d & 0xff;
519 break;
520 case 0x0b:
521 d &= 1;
522 Pico32x.pending_fb = d;
523 // if we are blanking and FS bit is changing
524 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
525 r[0x0a/2] ^= P32XV_FS;
526 Pico32xSwapDRAM(d ^ 1);
527 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
528 }
529 break;
530 }
531}
532
533static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
534{
535 a &= 0x0e;
536 if (a == 6) { // fill start
537 Pico32x.vdp_regs[6 / 2] = d;
538 return;
539 }
540 if (a == 8) { // fill data
541 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
542 int len = Pico32x.vdp_regs[4 / 2] + 1;
543 int len1 = len;
544 a = Pico32x.vdp_regs[6 / 2];
545 while (len1--) {
546 dram[a] = d;
547 a = (a & 0xff00) | ((a + 1) & 0xff);
548 }
549 Pico32x.vdp_regs[0x06 / 2] = a;
550 Pico32x.vdp_regs[0x08 / 2] = d;
551 if (sh2 != NULL && len > 4) {
552 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
553 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
554 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
555 }
556 return;
557 }
558
559 p32x_vdp_write8(a | 1, d);
560}
561
562// ------------------------------------------------------------------
563// SH2 regs
564
565static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
566{
567 u16 *r = Pico32x.regs;
568 a &= 0x3e;
569
570 switch (a) {
571 case 0x00: // adapter/irq ctl
572 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
573 | Pico32x.sh2irq_mask[sh2->is_slave];
574 case 0x04: // H count (often as comm too)
575 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
576 sh2s_sync_on_read(sh2);
577 return Pico32x.sh2_regs[4 / 2];
578 case 0x06:
579 return (r[a / 2] & ~P32XS_FULL) | 0x4000;
580 case 0x08: // DREQ src
581 case 0x0a:
582 case 0x0c: // DREQ dst
583 case 0x0e:
584 case 0x10: // DREQ len
585 return r[a / 2];
586 case 0x12: // DREQ FIFO - does this work on hw?
587 if (Pico32x.dmac0_fifo_ptr > 0) {
588 Pico32x.dmac0_fifo_ptr--;
589 r[a / 2] = Pico32x.dmac_fifo[0];
590 memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
591 Pico32x.dmac0_fifo_ptr * 2);
592 }
593 return r[a / 2];
594 case 0x14:
595 case 0x16:
596 case 0x18:
597 case 0x1a:
598 case 0x1c:
599 return 0; // ?
600 }
601
602 // comm port
603 if ((a & 0x30) == 0x20) {
604 int comreg = 1 << (a & 0x0f) / 2;
605 if (Pico32x.comm_dirty_68k & comreg)
606 Pico32x.comm_dirty_68k &= ~comreg;
607 else
608 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
609 sh2s_sync_on_read(sh2);
610 return r[a / 2];
611 }
612 if ((a & 0x30) == 0x30)
613 return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
614
615 elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
616 "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
617 return 0;
618}
619
620static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
621{
622 u16 *r = Pico32x.regs;
623 u32 old;
624
625 a &= 0x3f;
626 sh2->poll_addr = 0;
627
628 switch (a) {
629 case 0x00: // FM
630 r[0] &= ~P32XS_FM;
631 r[0] |= (d << 8) & P32XS_FM;
632 return;
633 case 0x01: // HEN/irq masks
634 old = Pico32x.sh2irq_mask[sh2->is_slave];
635 if ((d ^ old) & 1)
636 p32x_pwm_sync_to_sh2(sh2);
637
638 Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
639 Pico32x.sh2_regs[0] &= ~0x80;
640 Pico32x.sh2_regs[0] |= d & 0x80;
641
642 if ((d ^ old) & 1)
643 p32x_pwm_schedule_sh2(sh2);
644 if ((old ^ d) & 2)
645 p32x_update_cmd_irq(sh2, 0);
646 if ((old ^ d) & 4)
647 p32x_schedule_hint(sh2, 0);
648 return;
649 case 0x04: // ignored?
650 return;
651 case 0x05: // H count
652 d &= 0xff;
653 if (Pico32x.sh2_regs[4 / 2] != d) {
654 Pico32x.sh2_regs[4 / 2] = d;
655 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
656 sh2_cycles_done_m68k(sh2));
657 sh2_end_run(sh2, 4);
658 }
659 return;
660 case 0x30:
661 REG8IN16(r, a) = d & 0x0f;
662 d = r[0x30 / 2];
663 goto pwm_write;
664 case 0x31: // PWM control
665 REG8IN16(r, a) = d & 0x8f;
666 d = r[0x30 / 2];
667 goto pwm_write;
668 case 0x32: // PWM cycle
669 REG8IN16(r, a) = d & 0x0f;
670 d = r[0x32 / 2];
671 goto pwm_write;
672 case 0x33:
673 REG8IN16(r, a) = d;
674 d = r[0x32 / 2];
675 goto pwm_write;
676 // PWM pulse regs.. Only writes to odd address send a value
677 // to FIFO; reads are 0 (except status bits)
678 case 0x34:
679 case 0x36:
680 case 0x38:
681 REG8IN16(r, a) = d;
682 return;
683 case 0x35:
684 case 0x37:
685 case 0x39:
686 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
687 REG8IN16(r, a ^ 1) = 0;
688 goto pwm_write;
689 case 0x3a: // ignored, always 0?
690 case 0x3b:
691 case 0x3c:
692 case 0x3d:
693 case 0x3e:
694 case 0x3f:
695 return;
696 pwm_write:
697 p32x_pwm_write16(a & ~1, d, sh2, 0);
698 return;
699 }
700
701 if ((a & 0x30) == 0x20) {
702 int comreg;
703 if (REG8IN16(r, a) == d)
704 return;
705
706 REG8IN16(r, a) = d;
707 p32x_m68k_poll_event(P32XF_68KCPOLL);
708 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
709 sh2_cycles_done_m68k(sh2));
710 comreg = 1 << (a & 0x0f) / 2;
711 Pico32x.comm_dirty_sh2 |= comreg;
712 return;
713 }
714
715 elprintf(EL_32X|EL_ANOMALY,
716 "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
717}
718
719static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
720{
721 a &= 0x3e;
722
723 sh2->poll_addr = 0;
724
725 // comm
726 if ((a & 0x30) == 0x20) {
727 int comreg;
728 if (Pico32x.regs[a / 2] == d)
729 return;
730
731 Pico32x.regs[a / 2] = d;
732 p32x_m68k_poll_event(P32XF_68KCPOLL);
733 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
734 sh2_cycles_done_m68k(sh2));
735 comreg = 1 << (a & 0x0f) / 2;
736 Pico32x.comm_dirty_sh2 |= comreg;
737 return;
738 }
739 // PWM
740 else if ((a & 0x30) == 0x30) {
741 p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
742 return;
743 }
744
745 switch (a) {
746 case 0: // FM
747 Pico32x.regs[0] &= ~P32XS_FM;
748 Pico32x.regs[0] |= d & P32XS_FM;
749 break;
750 case 0x14:
751 Pico32x.sh2irqs &= ~P32XI_VRES;
752 goto irls;
753 case 0x16:
754 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
755 goto irls;
756 case 0x18:
757 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
758 goto irls;
759 case 0x1a:
760 Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
761 p32x_update_cmd_irq(sh2, 0);
762 return;
763 case 0x1c:
764 p32x_pwm_sync_to_sh2(sh2);
765 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
766 p32x_pwm_schedule_sh2(sh2);
767 goto irls;
768 }
769
770 p32x_sh2reg_write8(a | 1, d, sh2);
771 return;
772
773irls:
774 p32x_update_irls(sh2, 0);
775}
776
777// ------------------------------------------------------------------
778// 32x 68k handlers
779
780// after ADEN
781static u32 PicoRead8_32x_on(u32 a)
782{
783 u32 d = 0;
784 if ((a & 0xffc0) == 0x5100) { // a15100
785 d = p32x_reg_read16(a);
786 goto out_16to8;
787 }
788
789 if ((a & 0xfc00) != 0x5000)
790 return PicoRead8_io(a);
791
792 if ((a & 0xfff0) == 0x5180) { // a15180
793 d = p32x_vdp_read16(a);
794 goto out_16to8;
795 }
796
797 if ((a & 0xfe00) == 0x5200) { // a15200
798 d = Pico32xMem->pal[(a & 0x1ff) / 2];
799 goto out_16to8;
800 }
801
802 if ((a & 0xfffc) == 0x30ec) { // a130ec
803 d = str_mars[a & 3];
804 goto out;
805 }
806
807 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
808 return d;
809
810out_16to8:
811 if (a & 1)
812 d &= 0xff;
813 else
814 d >>= 8;
815
816out:
817 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
818 return d;
819}
820
821static u32 PicoRead16_32x_on(u32 a)
822{
823 u32 d = 0;
824 if ((a & 0xffc0) == 0x5100) { // a15100
825 d = p32x_reg_read16(a);
826 goto out;
827 }
828
829 if ((a & 0xfc00) != 0x5000)
830 return PicoRead16_io(a);
831
832 if ((a & 0xfff0) == 0x5180) { // a15180
833 d = p32x_vdp_read16(a);
834 goto out;
835 }
836
837 if ((a & 0xfe00) == 0x5200) { // a15200
838 d = Pico32xMem->pal[(a & 0x1ff) / 2];
839 goto out;
840 }
841
842 if ((a & 0xfffc) == 0x30ec) { // a130ec
843 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
844 goto out;
845 }
846
847 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
848 return d;
849
850out:
851 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
852 return d;
853}
854
855static void PicoWrite8_32x_on(u32 a, u32 d)
856{
857 if ((a & 0xfc00) == 0x5000)
858 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
859
860 if ((a & 0xffc0) == 0x5100) { // a15100
861 p32x_reg_write8(a, d);
862 return;
863 }
864
865 if ((a & 0xfc00) != 0x5000) {
866 PicoWrite8_io(a, d);
867 if (a == 0xa130f1)
868 bank_switch(Pico32x.regs[4 / 2]);
869 return;
870 }
871
872 if (!(Pico32x.regs[0] & P32XS_FM)) {
873 if ((a & 0xfff0) == 0x5180) { // a15180
874 p32x_vdp_write8(a, d);
875 return;
876 }
877
878 // TODO: verify
879 if ((a & 0xfe00) == 0x5200) { // a15200
880 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
881 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
882 Pico32x.dirty_pal = 1;
883 return;
884 }
885 }
886
887 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
888}
889
890static void PicoWrite16_32x_on(u32 a, u32 d)
891{
892 if ((a & 0xfc00) == 0x5000)
893 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
894
895 if ((a & 0xffc0) == 0x5100) { // a15100
896 p32x_reg_write16(a, d);
897 return;
898 }
899
900 if ((a & 0xfc00) != 0x5000) {
901 PicoWrite16_io(a, d);
902 if (a == 0xa130f0)
903 bank_switch(Pico32x.regs[4 / 2]);
904 return;
905 }
906
907 if (!(Pico32x.regs[0] & P32XS_FM)) {
908 if ((a & 0xfff0) == 0x5180) { // a15180
909 p32x_vdp_write16(a, d, NULL); // FIXME?
910 return;
911 }
912
913 if ((a & 0xfe00) == 0x5200) { // a15200
914 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
915 Pico32x.dirty_pal = 1;
916 return;
917 }
918 }
919
920 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
921}
922
923// before ADEN
924u32 PicoRead8_32x(u32 a)
925{
926 u32 d = 0;
927 if ((a & 0xffc0) == 0x5100) { // a15100
928 // regs are always readable
929 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
930 goto out;
931 }
932
933 if ((a & 0xfffc) == 0x30ec) { // a130ec
934 d = str_mars[a & 3];
935 goto out;
936 }
937
938 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
939 return d;
940
941out:
942 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
943 return d;
944}
945
946u32 PicoRead16_32x(u32 a)
947{
948 u32 d = 0;
949 if ((a & 0xffc0) == 0x5100) { // a15100
950 d = Pico32x.regs[(a & 0x3f) / 2];
951 goto out;
952 }
953
954 if ((a & 0xfffc) == 0x30ec) { // a130ec
955 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
956 goto out;
957 }
958
959 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
960 return d;
961
962out:
963 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
964 return d;
965}
966
967void PicoWrite8_32x(u32 a, u32 d)
968{
969 if ((a & 0xffc0) == 0x5100) { // a15100
970 u16 *r = Pico32x.regs;
971
972 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
973 a &= 0x3f;
974 if (a == 1) {
975 if ((d ^ r[0]) & d & P32XS_ADEN) {
976 Pico32xStartup();
977 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
978 r[0] |= P32XS_ADEN;
979 p32x_reg_write8(a, d); // forward for reset processing
980 }
981 return;
982 }
983
984 // allow only COMM for now
985 if ((a & 0x30) == 0x20) {
986 u8 *r8 = (u8 *)r;
987 r8[a ^ 1] = d;
988 }
989 return;
990 }
991
992 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
993}
994
995void PicoWrite16_32x(u32 a, u32 d)
996{
997 if ((a & 0xffc0) == 0x5100) { // a15100
998 u16 *r = Pico32x.regs;
999
1000 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1001 a &= 0x3e;
1002 if (a == 0) {
1003 if ((d ^ r[0]) & d & P32XS_ADEN) {
1004 Pico32xStartup();
1005 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1006 r[0] |= P32XS_ADEN;
1007 p32x_reg_write16(a, d); // forward for reset processing
1008 }
1009 return;
1010 }
1011
1012 // allow only COMM for now
1013 if ((a & 0x30) == 0x20)
1014 r[a / 2] = d;
1015 return;
1016 }
1017
1018 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1019}
1020
1021/* quirk: in both normal and overwrite areas only nonzero values go through */
1022#define sh2_write8_dramN(n) \
1023 if ((d & 0xff) != 0) { \
1024 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1025 dram[(a & 0x1ffff) ^ 1] = d; \
1026 }
1027
1028static void m68k_write8_dram0_ow(u32 a, u32 d)
1029{
1030 sh2_write8_dramN(0);
1031}
1032
1033static void m68k_write8_dram1_ow(u32 a, u32 d)
1034{
1035 sh2_write8_dramN(1);
1036}
1037
1038#define sh2_write16_dramN(n) \
1039 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1040 if (!(a & 0x20000)) { \
1041 *pd = d; \
1042 return; \
1043 } \
1044 /* overwrite */ \
1045 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1046 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1047 *pd = d;
1048
1049static void m68k_write16_dram0_ow(u32 a, u32 d)
1050{
1051 sh2_write16_dramN(0);
1052}
1053
1054static void m68k_write16_dram1_ow(u32 a, u32 d)
1055{
1056 sh2_write16_dramN(1);
1057}
1058
1059// -----------------------------------------------------------------
1060
1061// hint vector is writeable
1062static void PicoWrite8_hint(u32 a, u32 d)
1063{
1064 if ((a & 0xfffc) == 0x0070) {
1065 Pico32xMem->m68k_rom[a ^ 1] = d;
1066 return;
1067 }
1068
1069 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
1070 a, d & 0xff, SekPc);
1071}
1072
1073static void PicoWrite16_hint(u32 a, u32 d)
1074{
1075 if ((a & 0xfffc) == 0x0070) {
1076 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1077 return;
1078 }
1079
1080 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
1081 a, d & 0xffff, SekPc);
1082}
1083
1084// normally not writable, but somebody could make a RAM cart
1085static void PicoWrite8_cart(u32 a, u32 d)
1086{
1087 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1088
1089 a &= 0xfffff;
1090 m68k_write8(a, d);
1091}
1092
1093static void PicoWrite16_cart(u32 a, u32 d)
1094{
1095 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1096
1097 a &= 0xfffff;
1098 m68k_write16(a, d);
1099}
1100
1101// same with bank, but save ram is sometimes here
1102static u32 PicoRead8_bank(u32 a)
1103{
1104 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1105 return m68k_read8(a);
1106}
1107
1108static u32 PicoRead16_bank(u32 a)
1109{
1110 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1111 return m68k_read16(a);
1112}
1113
1114static void PicoWrite8_bank(u32 a, u32 d)
1115{
1116 if (!(Pico.m.sram_reg & SRR_MAPPED))
1117 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
1118 a, d & 0xff, SekPc);
1119
1120 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1121 m68k_write8(a, d);
1122}
1123
1124static void PicoWrite16_bank(u32 a, u32 d)
1125{
1126 if (!(Pico.m.sram_reg & SRR_MAPPED))
1127 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
1128 a, d & 0xffff, SekPc);
1129
1130 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1131 m68k_write16(a, d);
1132}
1133
1134static void bank_map_handler(void)
1135{
1136 cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
1137 cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
1138}
1139
1140static void bank_switch(int b)
1141{
1142 unsigned int rs, bank;
1143
1144 bank = b << 20;
1145 if ((Pico.m.sram_reg & SRR_MAPPED) && bank == SRam.start) {
1146 bank_map_handler();
1147 return;
1148 }
1149
1150 if (bank >= Pico.romsize) {
1151 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1152 bank_map_handler();
1153 return;
1154 }
1155
1156 // 32X ROM (unbanked, XXX: consider mirroring?)
1157 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1158 rs -= bank;
1159 if (rs > 0x100000)
1160 rs = 0x100000;
1161 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1162 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1163
1164 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1165
1166#ifdef EMU_F68K
1167 // setup FAME fetchmap
1168 for (rs = 0x90; rs < 0xa0; rs++)
1169 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
1170#endif
1171}
1172
1173// -----------------------------------------------------------------
1174// SH2
1175// -----------------------------------------------------------------
1176
1177// read8
1178static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
1179{
1180 elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
1181 a, 0, sh2_pc(sh2));
1182 return 0;
1183}
1184
1185static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
1186{
1187 u32 d = 0;
1188
1189 sh2_burn_cycles(sh2, 1*2);
1190
1191 // 0x3ffc0 is veridied
1192 if ((a & 0x3ffc0) == 0x4000) {
1193 d = p32x_sh2reg_read16(a, sh2);
1194 goto out_16to8;
1195 }
1196
1197 if ((a & 0x3fff0) == 0x4100) {
1198 d = p32x_vdp_read16(a);
1199 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1200 goto out_16to8;
1201 }
1202
1203 // TODO: mirroring?
1204 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1205 return Pico32xMem->sh2_rom_m.b[a ^ 1];
1206 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1207 return Pico32xMem->sh2_rom_s.b[a ^ 1];
1208
1209 if ((a & 0x3fe00) == 0x4200) {
1210 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1211 goto out_16to8;
1212 }
1213
1214 return sh2_read8_unmapped(a, sh2);
1215
1216out_16to8:
1217 if (a & 1)
1218 d &= 0xff;
1219 else
1220 d >>= 8;
1221
1222 elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
1223 a, d, sh2_pc(sh2));
1224 return d;
1225}
1226
1227static u32 sh2_read8_da(u32 a, SH2 *sh2)
1228{
1229 return sh2->data_array[(a & 0xfff) ^ 1];
1230}
1231
1232// read16
1233static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
1234{
1235 elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
1236 a, 0, sh2_pc(sh2));
1237 return 0;
1238}
1239
1240static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
1241{
1242 u32 d = 0;
1243
1244 sh2_burn_cycles(sh2, 1*2);
1245
1246 if ((a & 0x3ffc0) == 0x4000) {
1247 d = p32x_sh2reg_read16(a, sh2);
1248 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1249 return d;
1250 goto out;
1251 }
1252
1253 if ((a & 0x3fff0) == 0x4100) {
1254 d = p32x_vdp_read16(a);
1255 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1256 goto out;
1257 }
1258
1259 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1260 return Pico32xMem->sh2_rom_m.w[a / 2];
1261 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1262 return Pico32xMem->sh2_rom_s.w[a / 2];
1263
1264 if ((a & 0x3fe00) == 0x4200) {
1265 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1266 goto out;
1267 }
1268
1269 return sh2_read16_unmapped(a, sh2);
1270
1271out:
1272 elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
1273 a, d, sh2_pc(sh2));
1274 return d;
1275}
1276
1277static u32 sh2_read16_da(u32 a, SH2 *sh2)
1278{
1279 return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
1280}
1281
1282// writes
1283static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
1284{
1285}
1286
1287// write8
1288static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
1289{
1290 elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
1291 a, d & 0xff, sh2_pc(sh2));
1292}
1293
1294static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
1295{
1296 elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
1297 a, d & 0xff, sh2_pc(sh2));
1298
1299 if (Pico32x.regs[0] & P32XS_FM) {
1300 if ((a & 0x3fff0) == 0x4100) {
1301 sh2->poll_addr = 0;
1302 p32x_vdp_write8(a, d);
1303 return;
1304 }
1305 }
1306
1307 if ((a & 0x3ffc0) == 0x4000) {
1308 p32x_sh2reg_write8(a, d, sh2);
1309 return;
1310 }
1311
1312 sh2_write8_unmapped(a, d, sh2);
1313}
1314
1315static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
1316{
1317 sh2_write8_dramN(0);
1318}
1319
1320static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
1321{
1322 sh2_write8_dramN(1);
1323}
1324
1325static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
1326{
1327 u32 a1 = a & 0x3ffff;
1328#ifdef DRC_SH2
1329 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1330 if (t)
1331 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1332#endif
1333 Pico32xMem->sdram[a1 ^ 1] = d;
1334}
1335
1336static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
1337{
1338 // xmen sync hack..
1339 if (a < 0x26000200)
1340 sh2_end_run(sh2, 32);
1341
1342 sh2_write8_sdram(a, d, sh2);
1343}
1344
1345static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
1346{
1347 u32 a1 = a & 0xfff;
1348#ifdef DRC_SH2
1349 int id = sh2->is_slave;
1350 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1351 if (t)
1352 sh2_drc_wcheck_da(a, t, id);
1353#endif
1354 sh2->data_array[a1 ^ 1] = d;
1355}
1356
1357// write16
1358static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
1359{
1360 elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
1361 a, d & 0xffff, sh2_pc(sh2));
1362}
1363
1364static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
1365{
1366 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1367 elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
1368 a, d & 0xffff, sh2_pc(sh2));
1369
1370 if (Pico32x.regs[0] & P32XS_FM) {
1371 if ((a & 0x3fff0) == 0x4100) {
1372 sh2->poll_addr = 0;
1373 p32x_vdp_write16(a, d, sh2);
1374 return;
1375 }
1376
1377 if ((a & 0x3fe00) == 0x4200) {
1378 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1379 Pico32x.dirty_pal = 1;
1380 return;
1381 }
1382 }
1383
1384 if ((a & 0x3ffc0) == 0x4000) {
1385 p32x_sh2reg_write16(a, d, sh2);
1386 return;
1387 }
1388
1389 sh2_write16_unmapped(a, d, sh2);
1390}
1391
1392static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
1393{
1394 sh2_write16_dramN(0);
1395}
1396
1397static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
1398{
1399 sh2_write16_dramN(1);
1400}
1401
1402static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
1403{
1404 u32 a1 = a & 0x3ffff;
1405#ifdef DRC_SH2
1406 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1407 if (t)
1408 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1409#endif
1410 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1411}
1412
1413static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
1414{
1415 u32 a1 = a & 0xfff;
1416#ifdef DRC_SH2
1417 int id = sh2->is_slave;
1418 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1419 if (t)
1420 sh2_drc_wcheck_da(a, t, id);
1421#endif
1422 ((u16 *)sh2->data_array)[a1 / 2] = d;
1423}
1424
1425
1426typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
1427typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
1428
1429#define SH2MAP_ADDR2OFFS_R(a) \
1430 ((u32)(a) >> SH2_READ_SHIFT)
1431
1432#define SH2MAP_ADDR2OFFS_W(a) \
1433 ((u32)(a) >> SH2_WRITE_SHIFT)
1434
1435u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1436{
1437 const sh2_memmap *sh2_map = sh2->read8_map;
1438 uptr p;
1439
1440 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1441 p = sh2_map->addr;
1442 if (map_flag_set(p))
1443 return ((sh2_read_handler *)(p << 1))(a, sh2);
1444 else
1445 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1446}
1447
1448u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1449{
1450 const sh2_memmap *sh2_map = sh2->read16_map;
1451 uptr p;
1452
1453 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1454 p = sh2_map->addr;
1455 if (map_flag_set(p))
1456 return ((sh2_read_handler *)(p << 1))(a, sh2);
1457 else
1458 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1459}
1460
1461u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1462{
1463 const sh2_memmap *sh2_map = sh2->read16_map;
1464 sh2_read_handler *handler;
1465 u32 offs;
1466 uptr p;
1467
1468 offs = SH2MAP_ADDR2OFFS_R(a);
1469 sh2_map += offs;
1470 p = sh2_map->addr;
1471 if (!map_flag_set(p)) {
1472 // XXX: maybe 32bit access instead with ror?
1473 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1474 return (pd[0] << 16) | pd[1];
1475 }
1476
1477 if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
1478 return sh2_peripheral_read32(a, sh2);
1479
1480 handler = (sh2_read_handler *)(p << 1);
1481 return (handler(a, sh2) << 16) | handler(a + 2, sh2);
1482}
1483
1484void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1485{
1486 const void **sh2_wmap = sh2->write8_tab;
1487 sh2_write_handler *wh;
1488
1489 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1490 wh(a, d, sh2);
1491}
1492
1493void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1494{
1495 const void **sh2_wmap = sh2->write16_tab;
1496 sh2_write_handler *wh;
1497
1498 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1499 wh(a, d, sh2);
1500}
1501
1502void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1503{
1504 const void **sh2_wmap = sh2->write16_tab;
1505 sh2_write_handler *wh;
1506 u32 offs;
1507
1508 offs = SH2MAP_ADDR2OFFS_W(a);
1509
1510 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1511 sh2_peripheral_write32(a, d, sh2);
1512 return;
1513 }
1514
1515 wh = sh2_wmap[offs];
1516 wh(a, d >> 16, sh2);
1517 wh(a + 2, d, sh2);
1518}
1519
1520// -----------------------------------------------------------------
1521
1522static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
1523{
1524 unsigned int addr68k;
1525
1526 addr68k = Pico.m.z80_bank68k << 15;
1527 addr68k += a & 0x7fff;
1528 if ((addr68k & 0xfff000) == 0xa15000)
1529 Pico32x.emu_flags |= P32XF_Z80_32X_IO;
1530
1531 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
1532 m68k_write8(addr68k, d);
1533}
1534
1535// -----------------------------------------------------------------
1536
1537static const u16 msh2_code[] = {
1538 // trap instructions
1539 0xaffe, // bra <self>
1540 0x0009, // nop
1541 // have to wait a bit until m68k initial program finishes clearing stuff
1542 // to avoid races with game SH2 code, like in Tempo
1543 0xd004, // mov.l @(_m_ok,pc), r0
1544 0xd105, // mov.l @(_cnt,pc), r1
1545 0xd205, // mov.l @(_start,pc), r2
1546 0x71ff, // add #-1, r1
1547 0x4115, // cmp/pl r1
1548 0x89fc, // bt -2
1549 0xc208, // mov.l r0, @(h'20,gbr)
1550 0x6822, // mov.l @r2, r8
1551 0x482b, // jmp @r8
1552 0x0009, // nop
1553 ('M'<<8)|'_', ('O'<<8)|'K',
1554 0x0001, 0x0000,
1555 0x2200, 0x03e0 // master start pointer in ROM
1556};
1557
1558static const u16 ssh2_code[] = {
1559 0xaffe, // bra <self>
1560 0x0009, // nop
1561 // code to wait for master, in case authentic master BIOS is used
1562 0xd104, // mov.l @(_m_ok,pc), r1
1563 0xd206, // mov.l @(_start,pc), r2
1564 0xc608, // mov.l @(h'20,gbr), r0
1565 0x3100, // cmp/eq r0, r1
1566 0x8bfc, // bf #-2
1567 0xd003, // mov.l @(_s_ok,pc), r0
1568 0xc209, // mov.l r0, @(h'24,gbr)
1569 0x6822, // mov.l @r2, r8
1570 0x482b, // jmp @r8
1571 0x0009, // nop
1572 ('M'<<8)|'_', ('O'<<8)|'K',
1573 ('S'<<8)|'_', ('O'<<8)|'K',
1574 0x2200, 0x03e4 // slave start pointer in ROM
1575};
1576
1577#define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1578static void get_bios(void)
1579{
1580 u16 *ps;
1581 u32 *pl;
1582 int i;
1583
1584 // M68K ROM
1585 if (p32x_bios_g != NULL) {
1586 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1587 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1588 }
1589 else {
1590 // generate 68k ROM
1591 ps = (u16 *)Pico32xMem->m68k_rom;
1592 pl = (u32 *)ps;
1593 for (i = 1; i < 0xc0/4; i++)
1594 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1595
1596 // fill with nops
1597 for (i = 0xc0/2; i < 0x100/2; i++)
1598 ps[i] = 0x4e71;
1599
1600#if 0
1601 ps[0xc0/2] = 0x46fc;
1602 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1603 ps[0xfe/2] = 0x60fe; // jump to self
1604#else
1605 ps[0xfe/2] = 0x4e75; // rts
1606#endif
1607 }
1608 // fill remaining m68k_rom page with game ROM
1609 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1610 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1611 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1612
1613 // MSH2
1614 if (p32x_bios_m != NULL) {
1615 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1616 Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1617 }
1618 else {
1619 pl = (u32 *)&Pico32xMem->sh2_rom_m;
1620
1621 // fill exception vector table to our trap address
1622 for (i = 0; i < 128; i++)
1623 pl[i] = HWSWAP(0x200);
1624
1625 // startup code
1626 memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
1627
1628 // reset SP
1629 pl[1] = pl[3] = HWSWAP(0x6040000);
1630 // start
1631 pl[0] = pl[2] = HWSWAP(0x204);
1632 }
1633
1634 // SSH2
1635 if (p32x_bios_s != NULL) {
1636 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1637 Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1638 }
1639 else {
1640 pl = (u32 *)&Pico32xMem->sh2_rom_s;
1641
1642 // fill exception vector table to our trap address
1643 for (i = 0; i < 128; i++)
1644 pl[i] = HWSWAP(0x200);
1645
1646 // startup code
1647 memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
1648
1649 // reset SP
1650 pl[1] = pl[3] = HWSWAP(0x603f800);
1651 // start
1652 pl[0] = pl[2] = HWSWAP(0x204);
1653 }
1654}
1655
1656#define MAP_MEMORY(m) ((uptr)(m) >> 1)
1657#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1658
1659static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
1660// for writes we are using handlers only
1661static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1662
1663void Pico32xSwapDRAM(int b)
1664{
1665 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1666 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1667 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1668 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1669 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1670 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1671 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1672 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1673
1674 // SH2
1675 sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
1676 sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1677
1678 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1679 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1680}
1681
1682void PicoMemSetup32x(void)
1683{
1684 unsigned int rs;
1685 int i;
1686
1687 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1688 if (Pico32xMem == NULL) {
1689 elprintf(EL_STATUS, "OOM");
1690 return;
1691 }
1692
1693 get_bios();
1694
1695 // cartridge area becomes unmapped
1696 // XXX: we take the easy way and don't unmap ROM,
1697 // so that we can avoid handling the RV bit.
1698 // m68k_map_unmap(0x000000, 0x3fffff);
1699
1700 // MD ROM area
1701 rs = sizeof(Pico32xMem->m68k_rom_bank);
1702 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1703 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1704 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1705 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1706
1707 // 32X ROM (unbanked, XXX: consider mirroring?)
1708 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1709 if (rs > 0x80000)
1710 rs = 0x80000;
1711 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1712 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1713 cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
1714 cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
1715#ifdef EMU_F68K
1716 // setup FAME fetchmap
1717 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1718 for (rs = 0x88; rs < 0x90; rs++)
1719 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1720#endif
1721
1722 // 32X ROM (banked)
1723 bank_switch(0);
1724 cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
1725 cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
1726
1727 // SYS regs
1728 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1729 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1730 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1731 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1732
1733 // SH2 maps: A31,A30,A29,CS1,CS0
1734 // all unmapped by default
1735 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1736 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1737 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1738 }
1739
1740 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1741 sh2_write8_map[i] = sh2_write8_unmapped;
1742 sh2_write16_map[i] = sh2_write16_unmapped;
1743 }
1744
1745 // "purge area"
1746 for (i = 0x40; i <= 0x5f; i++) {
1747 sh2_write8_map[i >> 1] =
1748 sh2_write16_map[i >> 1] = sh2_write_ignore;
1749 }
1750
1751 // CS0
1752 sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
1753 sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
1754 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1755 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1756 // CS1 - ROM
1757 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
1758 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
1759 sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
1760 sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
1761 // CS2 - DRAM - done by Pico32xSwapDRAM()
1762 sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
1763 sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
1764 // CS3 - SDRAM
1765 sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
1766 sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
1767 sh2_write8_map[0x06/2] = sh2_write8_sdram;
1768 sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
1769 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1770 sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
1771 sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
1772 // SH2 data array
1773 sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
1774 sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
1775 sh2_write8_map[0xc0/2] = sh2_write8_da;
1776 sh2_write16_map[0xc0/2] = sh2_write16_da;
1777 // SH2 IO
1778 sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
1779 sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
1780 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1781 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1782
1783 // map DRAM area, both 68k and SH2
1784 Pico32xSwapDRAM(1);
1785
1786 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1787 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1788 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1789 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1790
1791 sh2_drc_mem_setup(&msh2);
1792 sh2_drc_mem_setup(&ssh2);
1793
1794 // z80 hack
1795 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
1796}
1797
1798void Pico32xMemStateLoaded(void)
1799{
1800 bank_switch(Pico32x.regs[4 / 2]);
1801 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1802 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1803 Pico32x.dirty_pal = 1;
1804
1805 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1806 memset(&m68k_poll, 0, sizeof(m68k_poll));
1807 msh2.state = 0;
1808 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1809 ssh2.state = 0;
1810 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1811
1812 sh2_drc_flush_all();
1813}
1814
1815// vim:shiftwidth=2:ts=2:expandtab
fast MegaDrive/MegaCD/32X emulator