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32x: change ppc handling for better logging
[picodrive.git] / pico / 32x / memory.c
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CommitLineData
1#include "../pico_int.h"
2#include "../memory.h"
3
4static const char str_mars[] = "MARS";
5
6struct Pico32xMem *Pico32xMem;
7
8static void bank_switch(int b);
9
10#define MSB8(x) ((x) >> 8)
11
12// poll detection
13#define POLL_THRESHOLD 6
14
15struct poll_det {
16 int addr, pc, cnt, flag;
17};
18static struct poll_det m68k_poll, sh2_poll[2];
19
20static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 pc, int is_vdp)
21{
22 int ret = 0, flag = pd->flag;
23
24 if (is_vdp)
25 flag <<= 3;
26
27 if (a - 2 <= pd->addr && pd->addr <= a + 2 && pd->pc == pc) {
28 pd->cnt++;
29 if (pd->cnt > POLL_THRESHOLD) {
30 if (!(Pico32x.emu_flags & flag)) {
31 elprintf(EL_32X, "%s poll addr %08x @ %06x",
32 flag == P32XF_68KPOLL ? "m68k" : (flag == P32XF_MSH2POLL ? "msh2" : "ssh2"), a, pc);
33 ret = 1;
34 }
35 Pico32x.emu_flags |= flag;
36 }
37 }
38 else
39 pd->cnt = 0;
40 pd->addr = a;
41 pd->pc = pc;
42
43 return ret;
44}
45
46static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
47{
48 int ret = 0, flag = pd->flag;
49 if (is_vdp)
50 flag <<= 3;
51 if (pd->cnt > POLL_THRESHOLD)
52 ret = 1;
53 pd->addr = pd->cnt = 0;
54 Pico32x.emu_flags &= ~flag;
55 return ret;
56}
57
58void p32x_poll_event(int is_vdp)
59{
60 p32x_poll_undetect(&sh2_poll[0], is_vdp);
61 p32x_poll_undetect(&sh2_poll[1], is_vdp);
62}
63
64// SH2 faking
65//#define FAKE_SH2
66int p32x_csum_faked;
67#ifdef FAKE_SH2
68static const u16 comm_fakevals[] = {
69 0x4d5f, 0x4f4b, // M_OK
70 0x535f, 0x4f4b, // S_OK
71 0x4D41, 0x5346, // MASF - Brutal Unleashed
72 0x5331, 0x4d31, // Darxide
73 0x5332, 0x4d32,
74 0x5333, 0x4d33,
75 0x0000, 0x0000, // eq for doom
76 0x0002, // Mortal Kombat
77// 0, // pad
78};
79
80static u32 sh2_comm_faker(u32 a)
81{
82 static int f = 0;
83 if (a == 0x28 && !p32x_csum_faked) {
84 p32x_csum_faked = 1;
85 return *(unsigned short *)(Pico.rom + 0x18e);
86 }
87 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
88 f = 0;
89 return comm_fakevals[f++];
90}
91#endif
92
93// DMAC handling
94static struct {
95 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
96 unsigned int chcr0; // chan ctl
97 unsigned int sar1, dar1, tcr1; // same for chan 1
98 unsigned int chcr1;
99 int pad[4];
100 unsigned int dmaor;
101} * dmac0;
102
103static void dma_68k2sh2_do(void)
104{
105 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
106 int i;
107
108 if (dmac0->tcr0 != *dreqlen)
109 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
110
111 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
112 extern void p32x_sh2_write16(u32 a, u32 d, int id);
113 elprintf(EL_32X|EL_ANOMALY, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
114 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0);
115 dmac0->dar0 += 2;
116 dmac0->tcr0--;
117 (*dreqlen)--;
118 }
119
120 Pico32x.dmac_ptr = 0; // HACK
121 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
122 if (*dreqlen == 0)
123 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
124 if (dmac0->tcr0 == 0)
125 dmac0->chcr0 |= 2; // DMA has ended normally
126}
127
128// ------------------------------------------------------------------
129// 68k regs
130
131static u32 p32x_reg_read16(u32 a)
132{
133 a &= 0x3e;
134
135#if 0
136 if ((a & 0x30) == 0x20)
137 return sh2_comm_faker(a);
138#else
139 if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekPc, 0)) {
140 SekEndRun(16);
141 }
142#endif
143#ifdef FAKE_SH2
144 // fake only slave for now
145 if (a == 0x24 || a == 0x26)
146 return sh2_comm_faker(a);
147#endif
148 if ((a & 0x30) == 0x30)
149 return p32x_pwm_read16(a);
150
151 return Pico32x.regs[a / 2];
152}
153
154static void p32x_reg_write8(u32 a, u32 d)
155{
156 u16 *r = Pico32x.regs;
157 a &= 0x3f;
158
159 if (a == 1 && !(r[0] & 1)) {
160 r[0] |= 1;
161 Pico32xStartup();
162 return;
163 }
164
165 if (!(r[0] & 1))
166 return;
167
168 switch (a) {
169 case 0: // adapter ctl
170 r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM);
171 break;
172 case 3: // irq ctl
173 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
174 Pico32x.sh2irqi[0] |= P32XI_CMD;
175 p32x_update_irls();
176 }
177 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
178 Pico32x.sh2irqi[1] |= P32XI_CMD;
179 p32x_update_irls();
180 }
181 break;
182 case 5: // bank
183 d &= 7;
184 if (r[4 / 2] != d) {
185 r[4 / 2] = d;
186 bank_switch(d);
187 }
188 break;
189 case 7: // DREQ ctl
190 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_RV));
191 break;
192 }
193}
194
195static void p32x_reg_write16(u32 a, u32 d)
196{
197 u16 *r = Pico32x.regs;
198 a &= 0x3e;
199
200 switch (a) {
201 case 0x00: // adapter ctl
202 r[0] = (r[0] & 0x83) | (d & P32XS_FM);
203 return;
204 case 0x10: // DREQ len
205 r[a / 2] = d & ~3;
206 return;
207 case 0x12: // FIFO reg
208 if (!(r[6 / 2] & P32XS_68S)) {
209 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
210 return;
211 }
212 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
213 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
214 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
215 dma_68k2sh2_do();
216 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
217 r[6 / 2] |= P32XS_FULL;
218 }
219 break;
220 }
221
222 // DREQ src, dst
223 if ((a & 0x38) == 0x08) {
224 r[a / 2] = d;
225 return;
226 }
227 // comm port
228 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
229 r[a / 2] = d;
230 if (p32x_poll_undetect(&sh2_poll[0], 0) || p32x_poll_undetect(&sh2_poll[1], 0))
231 // if some SH2 is busy waiting, it needs to see the result ASAP
232 SekEndRun(16);
233 return;
234 }
235 // PWM
236 else if ((a & 0x30) == 0x30) {
237 p32x_pwm_write16(a, d);
238 return;
239 }
240
241 p32x_reg_write8(a + 1, d);
242}
243
244// ------------------------------------------------------------------
245// VDP regs
246static u32 p32x_vdp_read16(u32 a)
247{
248 a &= 0x0e;
249
250 return Pico32x.vdp_regs[a / 2];
251}
252
253static void p32x_vdp_write8(u32 a, u32 d)
254{
255 u16 *r = Pico32x.vdp_regs;
256 a &= 0x0f;
257
258 // for FEN checks between writes
259 sh2_poll[0].cnt = 0;
260
261 // TODO: verify what's writeable
262 switch (a) {
263 case 0x01:
264 // priority inversion is handled in palette
265 if ((r[0] ^ d) & P32XV_PRI)
266 Pico32x.dirty_pal = 1;
267 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
268 break;
269 case 0x0b:
270 d &= 1;
271 Pico32x.pending_fb = d;
272 // if we are blanking and FS bit is changing
273 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
274 r[0x0a/2] ^= 1;
275 Pico32xSwapDRAM(d ^ 1);
276 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
277 }
278 break;
279 }
280}
281
282static void p32x_vdp_write16(u32 a, u32 d)
283{
284 p32x_vdp_write8(a | 1, d);
285}
286
287// ------------------------------------------------------------------
288// SH2 regs
289
290static u32 p32x_sh2reg_read16(u32 a, int cpuid)
291{
292 u16 *r = Pico32x.regs;
293 a &= 0xfe; // ?
294
295 switch (a) {
296 case 0x00: // adapter/irq ctl
297 return (r[0] & P32XS_FM) | P32XS2_ADEN | Pico32x.sh2irq_mask[cpuid];
298 case 0x10: // DREQ len
299 return r[a / 2];
300 }
301
302 // DREQ src, dst
303 if ((a & 0x38) == 0x08)
304 return r[a / 2];
305 // comm port
306 if ((a & 0x30) == 0x20) {
307 if (p32x_poll_detect(&sh2_poll[cpuid], a, sh2_pc(cpuid), 0))
308 ash2_end_run(8);
309 return r[a / 2];
310 }
311 if ((a & 0x30) == 0x30) {
312 sh2_poll[cpuid].cnt = 0;
313 return p32x_pwm_read16(a);
314 }
315
316 return 0;
317}
318
319static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
320{
321 a &= 0xff;
322 if (a == 1) {
323 Pico32x.sh2irq_mask[cpuid] = d & 0x0f;
324 p32x_update_irls();
325 }
326}
327
328static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
329{
330 a &= 0xfe;
331
332 // comm
333 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
334 Pico32x.regs[a / 2] = d;
335 p32x_poll_undetect(&m68k_poll, 0);
336 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
337 return;
338 }
339 // PWM
340 else if ((a & 0x30) == 0x30) {
341 p32x_pwm_write16(a, d);
342 return;
343 }
344
345 switch (a) {
346 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
347 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
348 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
349 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
350 case 0x1c: Pico32x.sh2irqs &= ~P32XI_PWM; goto irls;
351 }
352
353 p32x_sh2reg_write8(a | 1, d, cpuid);
354 return;
355
356irls:
357 p32x_update_irls();
358}
359
360static u32 sh2_peripheral_read(u32 a, int id)
361{
362 u32 d;
363 a &= 0x1fc;
364 d = Pico32xMem->sh2_peri_regs[0][a / 4];
365
366 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
367 return d;
368}
369
370static void sh2_peripheral_write(u32 a, u32 d, int id)
371{
372 unsigned int *r = Pico32xMem->sh2_peri_regs[0];
373 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
374
375 a &= 0x1fc;
376 r[a / 4] = d;
377
378 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
379 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
380 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
381 dmac0->tcr0 &= 0xffffff;
382 // DREQ is only sent after first 4 words are written.
383 // we do multiple of 4 words to avoid messing up alignment
384 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
385 elprintf(EL_32X, "68k -> sh2 DMA");
386 dma_68k2sh2_do();
387 }
388 }
389}
390
391// ------------------------------------------------------------------
392// default 32x handlers
393u32 PicoRead8_32x(u32 a)
394{
395 u32 d = 0;
396 if ((a & 0xffc0) == 0x5100) { // a15100
397 d = p32x_reg_read16(a);
398 goto out_16to8;
399 }
400
401 if (!(Pico32x.regs[0] & 1))
402 goto no_vdp;
403
404 if ((a & 0xfff0) == 0x5180) { // a15180
405 d = p32x_vdp_read16(a);
406 goto out_16to8;
407 }
408
409 if ((a & 0xfe00) == 0x5200) { // a15200
410 d = Pico32xMem->pal[(a & 0x1ff) / 2];
411 goto out_16to8;
412 }
413
414no_vdp:
415 if ((a & 0xfffc) == 0x30ec) { // a130ec
416 d = str_mars[a & 3];
417 goto out;
418 }
419
420 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
421 return d;
422
423out_16to8:
424 if (a & 1)
425 d &= 0xff;
426 else
427 d >>= 8;
428
429out:
430 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
431 return d;
432}
433
434u32 PicoRead16_32x(u32 a)
435{
436 u32 d = 0;
437 if ((a & 0xffc0) == 0x5100) { // a15100
438 d = p32x_reg_read16(a);
439 goto out;
440 }
441
442 if (!(Pico32x.regs[0] & 1))
443 goto no_vdp;
444
445 if ((a & 0xfff0) == 0x5180) { // a15180
446 d = p32x_vdp_read16(a);
447 goto out;
448 }
449
450 if ((a & 0xfe00) == 0x5200) { // a15200
451 d = Pico32xMem->pal[(a & 0x1ff) / 2];
452 goto out;
453 }
454
455no_vdp:
456 if ((a & 0xfffc) == 0x30ec) { // a130ec
457 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
458 goto out;
459 }
460
461 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
462 return d;
463
464out:
465 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
466 return d;
467}
468
469void PicoWrite8_32x(u32 a, u32 d)
470{
471 if ((a & 0xfc00) == 0x5000)
472 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
473
474 if ((a & 0xffc0) == 0x5100) { // a15100
475 p32x_reg_write8(a, d);
476 return;
477 }
478
479 if (!(Pico32x.regs[0] & 1))
480 goto no_vdp;
481
482 if ((a & 0xfff0) == 0x5180) { // a15180
483 p32x_vdp_write8(a, d);
484 return;
485 }
486
487 // TODO: verify
488 if ((a & 0xfe00) == 0x5200) { // a15200
489 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
490 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
491 Pico32x.dirty_pal = 1;
492 return;
493 }
494
495no_vdp:
496 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
497}
498
499void PicoWrite16_32x(u32 a, u32 d)
500{
501 if ((a & 0xfc00) == 0x5000)
502 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
503
504 if ((a & 0xffc0) == 0x5100) { // a15100
505 p32x_reg_write16(a, d);
506 return;
507 }
508
509 if (!(Pico32x.regs[0] & 1))
510 goto no_vdp;
511
512 if ((a & 0xfff0) == 0x5180) { // a15180
513 p32x_vdp_write16(a, d);
514 return;
515 }
516
517 if ((a & 0xfe00) == 0x5200) { // a15200
518 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
519 Pico32x.dirty_pal = 1;
520 return;
521 }
522
523no_vdp:
524 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
525}
526
527// hint vector is writeable
528static void PicoWrite8_hint(u32 a, u32 d)
529{
530 if ((a & 0xfffc) == 0x0070) {
531 Pico32xMem->m68k_rom[a ^ 1] = d;
532 return;
533 }
534
535 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
536}
537
538static void PicoWrite16_hint(u32 a, u32 d)
539{
540 if ((a & 0xfffc) == 0x0070) {
541 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
542 return;
543 }
544
545 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
546}
547
548void Pico32xSwapDRAM(int b)
549{
550 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
551 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
552 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
553 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
554}
555
556static void bank_switch(int b)
557{
558 unsigned int rs, bank;
559
560 bank = b << 20;
561 if (bank >= Pico.romsize) {
562 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
563 return;
564 }
565
566 // 32X ROM (unbanked, XXX: consider mirroring?)
567 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
568 rs -= bank;
569 if (rs > 0x100000)
570 rs = 0x100000;
571 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
572 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
573
574 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
575}
576
577// -----------------------------------------------------------------
578// SH2
579// -----------------------------------------------------------------
580
581u32 p32x_sh2_read8(u32 a, int id)
582{
583 u32 d = 0;
584
585 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
586 return Pico32xMem->sh2_rom_m[a ^ 1];
587 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
588 return Pico32xMem->sh2_rom_s[a ^ 1];
589
590 if ((a & 0x0ffc0000) == 0x06000000)
591 return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
592
593 if ((a & 0x0fc00000) == 0x02000000)
594 if ((a & 0x003fffff) < Pico.romsize)
595 return Pico.rom[(a & 0x3fffff) ^ 1];
596
597 if ((a & ~0xfff) == 0xc0000000)
598 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
599
600 if ((a & 0x0fffff00) == 0x4000) {
601 d = p32x_sh2reg_read16(a, id);
602 goto out_16to8;
603 }
604
605 if ((a & 0x0fffff00) == 0x4100) {
606 d = p32x_vdp_read16(a);
607 if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1))
608 ash2_end_run(8);
609 goto out_16to8;
610 }
611
612 if ((a & 0x0fffff00) == 0x4200) {
613 d = Pico32xMem->pal[(a & 0x1ff) / 2];
614 goto out_16to8;
615 }
616
617 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
618 id ? 's' : 'm', a, d, sh2_pc(id));
619 return d;
620
621out_16to8:
622 if (a & 1)
623 d &= 0xff;
624 else
625 d >>= 8;
626
627 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
628 id ? 's' : 'm', a, d, sh2_pc(id));
629 return d;
630}
631
632u32 p32x_sh2_read16(u32 a, int id)
633{
634 u32 d = 0;
635
636 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
637 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
638 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
639 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
640
641 if ((a & 0x0ffc0000) == 0x06000000)
642 return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
643
644 if ((a & 0x0fc00000) == 0x02000000)
645 if ((a & 0x003fffff) < Pico.romsize)
646 return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
647
648 if ((a & ~0xfff) == 0xc0000000)
649 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
650
651 if ((a & 0x0fffff00) == 0x4000) {
652 d = p32x_sh2reg_read16(a, id);
653 goto out;
654 }
655
656 if ((a & 0x0fffff00) == 0x4100) {
657 d = p32x_vdp_read16(a);
658 if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1))
659 ash2_end_run(8);
660 goto out;
661 }
662
663 if ((a & 0x0fffff00) == 0x4200) {
664 d = Pico32xMem->pal[(a & 0x1ff) / 2];
665 goto out;
666 }
667
668 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
669 id ? 's' : 'm', a, d, sh2_pc(id));
670 return d;
671
672out:
673 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
674 id ? 's' : 'm', a, d, sh2_pc(id));
675 return d;
676}
677
678u32 p32x_sh2_read32(u32 a, int id)
679{
680 if ((a & 0xfffffe00) == 0xfffffe00)
681 return sh2_peripheral_read(a, id);
682
683// elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
684 return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
685}
686
687void p32x_sh2_write8(u32 a, u32 d, int id)
688{
689 if ((a & 0x0ffffc00) == 0x4000)
690 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
691 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
692
693 if ((a & 0x0ffc0000) == 0x06000000) {
694 Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
695 return;
696 }
697
698 if ((a & 0x0ffe0000) == 0x04000000) {
699 u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
700 dram[(a & 0x1ffff) ^ 1] = d;
701 return;
702 }
703
704 if ((a & ~0xfff) == 0xc0000000) {
705 Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
706 return;
707 }
708
709 if ((a & 0x0fffff00) == 0x4100) {
710 p32x_vdp_write8(a, d);
711 return;
712 }
713
714 if ((a & 0x0fffff00) == 0x4000) {
715 p32x_sh2reg_write8(a, d, id);
716 return;
717 }
718
719 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
720 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
721}
722
723void p32x_sh2_write16(u32 a, u32 d, int id)
724{
725 if ((a & 0x0ffffc00) == 0x4000)
726 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
727 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
728
729 if ((a & 0x0ffc0000) == 0x06000000) {
730 ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
731 return;
732 }
733
734 if ((a & ~0xfff) == 0xc0000000) {
735 ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
736 return;
737 }
738
739 if ((a & 0x0ffe0000) == 0x04000000) {
740 Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2] = d;
741 return;
742 }
743
744 if ((a & 0x0fffff00) == 0x4100) {
745 p32x_vdp_write16(a, d);
746 return;
747 }
748
749 if ((a & 0x0ffffe00) == 0x4200) {
750 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
751 Pico32x.dirty_pal = 1;
752 return;
753 }
754
755 if ((a & 0x0fffff00) == 0x4000) {
756 p32x_sh2reg_write16(a, d, id);
757 return;
758 }
759
760 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
761 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
762}
763
764void p32x_sh2_write32(u32 a, u32 d, int id)
765{
766 if ((a & 0xfffffe00) == 0xfffffe00) {
767 sh2_peripheral_write(a, d, id);
768 return;
769 }
770
771 p32x_sh2_write16(a, d >> 16, id);
772 p32x_sh2_write16(a + 2, d, id);
773}
774
775#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
776void PicoMemSetup32x(void)
777{
778 unsigned short *ps;
779 unsigned int *pl;
780 unsigned int rs;
781 int i;
782
783 Pico32xMem = calloc(1, sizeof(*Pico32xMem));
784 if (Pico32xMem == NULL) {
785 elprintf(EL_STATUS, "OOM");
786 return;
787 }
788
789 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
790
791 // generate 68k ROM
792 ps = (unsigned short *)Pico32xMem->m68k_rom;
793 pl = (unsigned int *)Pico32xMem->m68k_rom;
794 for (i = 1; i < 0xc0/4; i++)
795 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
796
797 // fill with nops
798 for (i = 0xc0/2; i < 0x100/2; i++)
799 ps[i] = 0x4e71;
800
801#if 0
802 ps[0xc0/2] = 0x46fc;
803 ps[0xc2/2] = 0x2700; // move #0x2700,sr
804 ps[0xfe/2] = 0x60fe; // jump to self
805#else
806 ps[0xfe/2] = 0x4e75; // rts
807#endif
808
809 // fill remaining mem with ROM
810 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
811
812 // 32X ROM
813 // TODO: move
814 {
815 FILE *f = fopen("32X_M_BIOS.BIN", "rb");
816 int i;
817 if (f == NULL) {
818 printf("missing 32X_M_BIOS.BIN\n");
819 exit(1);
820 }
821 fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f);
822 fclose(f);
823 f = fopen("32X_S_BIOS.BIN", "rb");
824 if (f == NULL) {
825 printf("missing 32X_S_BIOS.BIN\n");
826 exit(1);
827 }
828 fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f);
829 fclose(f);
830 // byteswap
831 for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) {
832 int t = Pico32xMem->sh2_rom_m[i];
833 Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1];
834 Pico32xMem->sh2_rom_m[i + 1] = t;
835 }
836 for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) {
837 int t = Pico32xMem->sh2_rom_s[i];
838 Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1];
839 Pico32xMem->sh2_rom_s[i + 1] = t;
840 }
841 }
842
843 // cartridge area becomes unmapped
844 // XXX: we take the easy way and don't unmap ROM,
845 // so that we can avoid handling the RV bit.
846 // m68k_map_unmap(0x000000, 0x3fffff);
847
848 // MD ROM area
849 rs = sizeof(Pico32xMem->m68k_rom);
850 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
851 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
852 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
853 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
854
855 // DRAM area
856 Pico32xSwapDRAM(1);
857
858 // 32X ROM (unbanked, XXX: consider mirroring?)
859 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
860 if (rs > 0x80000)
861 rs = 0x80000;
862 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
863 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
864
865 // 32X ROM (banked)
866 bank_switch(0);
867
868 // setup poll detector
869 m68k_poll.flag = P32XF_68KPOLL;
870 sh2_poll[0].flag = P32XF_MSH2POLL;
871 sh2_poll[1].flag = P32XF_SSH2POLL;
872}
873
fast MegaDrive/MegaCD/32X emulator