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platform ps2, handle audio similar to psp
[picodrive.git] / pico / 32x / sh2soc.c
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1/*
2 * SH2 peripherals/"system on chip"
3 * (C) notaz, 2013
4 * (C) irixxxx, 2019-2024
5 *
6 * This work is licensed under the terms of MAME license.
7 * See COPYING file in the top-level directory.
8 *
9 * rough fffffe00-ffffffff map:
10 * e00-e05 SCI serial communication interface
11 * e10-e1a FRT free-running timer
12 * e60-e68 VCRx irq vectors
13 * e71-e72 DRCR dma selection
14 * e80-e83 WDT watchdog timer
15 * e91 SBYCR standby control
16 * e92 CCR cache control
17 * ee0 ICR irq control
18 * ee2 IPRA irq priorities
19 * ee4 VCRWDT WDT irq vectors
20 * f00-f17 DIVU
21 * f40-f7b UBC user break controller
22 * f80-fb3 DMAC
23 * fe0-ffb BSC bus state controller
24 */
25
26#include "../pico_int.h"
27#include "../memory.h"
28
29#include <cpu/sh2/compiler.h>
30DRC_DECLARE_SR;
31
32// DMAC handling
33struct dma_chan {
34 u32 sar, dar; // src, dst addr
35 u32 tcr; // transfer count
36 u32 chcr; // chan ctl
37 // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
38 // ts - transfer size: 1, 2, 4, 16 bytes
39 // ar - auto request if 1, else dreq signal
40 // ie - irq enable
41 // te - transfer end
42 // de - dma enable
43 #define DMA_AR (1 << 9)
44 #define DMA_IE (1 << 2)
45 #define DMA_TE (1 << 1)
46 #define DMA_DE (1 << 0)
47};
48
49struct dmac {
50 struct dma_chan chan[2];
51 u32 vcrdma0;
52 u32 unknown0;
53 u32 vcrdma1;
54 u32 unknown1;
55 u32 dmaor;
56 // -- pr ae nmif dme
57 // pr - priority: chan0 > chan1 or round-robin
58 // ae - address error
59 // nmif - nmi occurred
60 // dme - DMA master enable
61 #define DMA_DME (1 << 0)
62};
63
64static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
65{
66 char *regs = (void *)sh2->peri_regs;
67 struct dmac *dmac = (void *)(regs + 0x180);
68 int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
69 int vector = (chan == &dmac->chan[0]) ?
70 dmac->vcrdma0 : dmac->vcrdma1;
71
72 elprintf(EL_32XP, "dmac irq %d %d", level, vector);
73 sh2_internal_irq(sh2, level, vector & 0x7f);
74}
75
76static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
77{
78 chan->chcr |= DMA_TE; // DMA has ended normally
79
80 p32x_sh2_poll_event(sh2->poll_addr, sh2, SH2_STATE_SLEEP, SekCyclesDone());
81 if (chan->chcr & DMA_IE)
82 dmac_te_irq(sh2, chan);
83}
84
85static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
86{
87 u32 size, d;
88
89 size = (chan->chcr >> 10) & 3;
90 switch (size) {
91 case 0:
92 d = p32x_sh2_read8(chan->sar, sh2);
93 p32x_sh2_write8(chan->dar, d, sh2);
94 break;
95 case 1:
96 d = p32x_sh2_read16(chan->sar, sh2);
97 p32x_sh2_write16(chan->dar, d, sh2);
98 break;
99 case 2:
100 d = p32x_sh2_read32(chan->sar, sh2);
101 p32x_sh2_write32(chan->dar, d, sh2);
102 break;
103 case 3:
104 d = p32x_sh2_read32(chan->sar + 0x00, sh2);
105 p32x_sh2_write32(chan->dar + 0x00, d, sh2);
106 d = p32x_sh2_read32(chan->sar + 0x04, sh2);
107 p32x_sh2_write32(chan->dar + 0x04, d, sh2);
108 d = p32x_sh2_read32(chan->sar + 0x08, sh2);
109 p32x_sh2_write32(chan->dar + 0x08, d, sh2);
110 d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
111 p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
112 chan->sar += 16; // always?
113 if (chan->chcr & (1 << 15))
114 chan->dar -= 16;
115 if (chan->chcr & (1 << 14))
116 chan->dar += 16;
117 chan->tcr -= 4;
118 return;
119 }
120 chan->tcr--;
121
122 size = 1 << size;
123 if (chan->chcr & (1 << 15))
124 chan->dar -= size;
125 if (chan->chcr & (1 << 14))
126 chan->dar += size;
127 if (chan->chcr & (1 << 13))
128 chan->sar -= size;
129 if (chan->chcr & (1 << 12))
130 chan->sar += size;
131}
132
133// optimization for copying around memory with SH2 DMA
134static void dmac_memcpy(struct dma_chan *chan, SH2 *sh2)
135{
136 u32 size = (chan->chcr >> 10) & 3, up = chan->chcr & (1 << 14);
137 int count;
138
139 if (!up || chan->tcr < 4)
140 return;
141
142 if (size == 3) size = 2; // 4-word xfer mode still counts in words
143 // XXX check TCR being a multiple of 4 in 4-word xfer mode?
144 // XXX check alignment of sar/dar, generating a bus error if unaligned?
145 count = p32x_sh2_memcpy(chan->dar, chan->sar, chan->tcr, 1 << size, sh2);
146
147 chan->sar += count << size;
148 chan->dar += count << size;
149 chan->tcr -= count;
150}
151
152// DMA trigger by SH2 register write
153static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
154{
155 elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
156 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
157 chan->tcr &= 0xffffff;
158
159 if (chan->chcr & DMA_AR) {
160 // auto-request transfer
161 sh2->state |= SH2_STATE_SLEEP;
162 if ((((chan->chcr >> 12) ^ (chan->chcr >> 14)) & 3) == 0 &&
163 (((chan->chcr >> 14) ^ (chan->chcr >> 15)) & 1) == 1) {
164 // SM == DM and either DM0 or DM1 are set. check for mem to mem copy
165 dmac_memcpy(chan, sh2);
166 }
167 while ((int)chan->tcr > 0)
168 dmac_transfer_one(sh2, chan);
169 dmac_transfer_complete(sh2, chan);
170 return;
171 }
172
173 // DREQ0 is only sent after first 4 words are written.
174 // we do multiple of 4 words to avoid messing up alignment
175 if ((chan->sar & ~0x20000000) == 0x00004012) {
176 if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
177 elprintf(EL_32XP, "68k -> sh2 DMA");
178 p32x_dreq0_trigger();
179 }
180 return;
181 }
182
183 // DREQ1
184 if ((chan->dar & 0xc7fffff0) == 0x00004030)
185 return;
186
187 elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
188 "%08x->%08x, cnt %d, chcr %04x @%06x",
189 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
190}
191
192// timer state - FIXME
193static u32 timer_cycles[2];
194static u32 timer_tick_cycles[2];
195static u32 timer_tick_factor[2];
196
197// timers
198void p32x_timers_recalc(void)
199{
200 int cycles;
201 int tmp, i;
202
203 // SH2 timer step
204 for (i = 0; i < 2; i++) {
205 sh2s[i].state &= ~SH2_TIMER_RUN;
206 if (PREG8(sh2s[i].peri_regs, 0x80) & 0x20) // TME
207 sh2s[i].state |= SH2_TIMER_RUN;
208 tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
209 // Sclk cycles per timer tick
210 if (tmp)
211 cycles = 0x20 << tmp;
212 else
213 cycles = 2;
214 timer_tick_cycles[i] = cycles;
215 timer_tick_factor[i] = (1ULL << 32) / cycles;
216 timer_cycles[i] = 0;
217 elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles);
218 }
219}
220
221NOINLINE void p32x_timer_do(SH2 *sh2, unsigned int m68k_slice)
222{
223 unsigned int cycles = m68k_slice * 3;
224 void *pregs = sh2->peri_regs;
225 int cnt; int i = sh2->is_slave;
226
227 // WDT timer
228 timer_cycles[i] += cycles;
229 if (timer_cycles[i] > timer_tick_cycles[i]) {
230 // cnt = timer_cycles[i] / timer_tick_cycles[i];
231 cnt = (1ULL * timer_cycles[i] * timer_tick_factor[i]) >> 32;
232 timer_cycles[i] -= timer_tick_cycles[i] * cnt;
233
234 cnt += PREG8(pregs, 0x81);
235 if (cnt >= 0x100) {
236 int level = PREG8(pregs, 0xe3) >> 4;
237 int vector = PREG8(pregs, 0xe4) & 0x7f;
238 elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
239 i ? 's' : 'm', level, vector);
240 sh2_internal_irq(sh2, level, vector);
241 cnt &= 0xff;
242 }
243 PREG8(pregs, 0x81) = cnt;
244 }
245}
246
247void sh2_peripheral_reset(SH2 *sh2)
248{
249 memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
250 PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
251 PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
252 PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
253 PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
254 PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
255}
256
257// ------------------------------------------------------------------
258// SH2 internal peripheral memhandlers
259// we keep them in little endian format
260
261u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
262{
263 u8 *r = (void *)sh2->peri_regs;
264 u32 d;
265
266 DRC_SAVE_SR(sh2);
267 a &= 0x1ff;
268 d = PREG8(r, a);
269
270 elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
271 a | ~0x1ff, d, sh2_pc(sh2));
272 if ((a & 0x1c0) == 0x140) {
273 // abused as comm area
274 p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
275 }
276 DRC_RESTORE_SR(sh2);
277 return d;
278}
279
280u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
281{
282 u16 *r = (void *)sh2->peri_regs;
283 u32 d;
284
285 DRC_SAVE_SR(sh2);
286 a &= 0x1fe;
287 d = r[MEM_BE2(a / 2)];
288
289 elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
290 a | ~0x1ff, d, sh2_pc(sh2));
291 if ((a & 0x1c0) == 0x140) {
292 // abused as comm area
293 p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
294 }
295 DRC_RESTORE_SR(sh2);
296 return d;
297}
298
299u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
300{
301 u32 d;
302
303 DRC_SAVE_SR(sh2);
304 a &= 0x1fc;
305 d = sh2->peri_regs[a / 4];
306
307 elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
308 a | ~0x1ff, d, sh2_pc(sh2));
309 if (a == 0x18c)
310 // kludge for polling COMM while polling for end of DMA
311 sh2->poll_cnt = 0;
312 else if ((a & 0x1c0) == 0x140) {
313 // abused as comm area
314 p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
315 }
316 DRC_RESTORE_SR(sh2);
317 return d;
318}
319
320static void sci_trigger(SH2 *sh2, u8 *r)
321{
322 u8 *oregs;
323
324 if (!(PREG8(r, 2) & 0x20))
325 return; // transmitter not enabled
326 if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
327 return;
328
329 oregs = (u8 *)sh2->other_sh2->peri_regs;
330 if (!(PREG8(oregs, 2) & 0x10))
331 return; // receiver not enabled
332
333 PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
334 PREG8(r, 4) |= 0x80; // TDRE - TDR empty
335 PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
336
337 // might need to delay these a bit..
338 if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
339 int level = PREG8(oregs, 0x60) >> 4;
340 int vector = PREG8(oregs, 0x64) & 0x7f;
341 elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
342 level, vector);
343 sh2_internal_irq(sh2, level, vector);
344 }
345 // TODO: TEIE
346 if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
347 int level = PREG8(oregs, 0x60) >> 4;
348 int vector = PREG8(oregs, 0x63) & 0x7f;
349 elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
350 level, vector);
351 sh2_internal_irq(sh2->other_sh2, level, vector);
352 }
353}
354
355void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
356{
357 u8 *r = (void *)sh2->peri_regs;
358 u8 old;
359
360 DRC_SAVE_SR(sh2);
361 elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
362 a, d, sh2_pc(sh2));
363
364 a &= 0x1ff;
365 old = PREG8(r, a);
366 PREG8(r, a) = d;
367
368 switch (a) {
369 case 0x002: // SCR - serial control
370 if (!(old & 0x20) && (d & 0x20)) // TE being set
371 sci_trigger(sh2, r);
372 break;
373 case 0x003: // TDR - transmit data
374 break;
375 case 0x004: // SSR - serial status
376 d = (old & (d | 0x06)) | (d & 1);
377 PREG8(r, a) = d;
378 sci_trigger(sh2, r);
379 break;
380 case 0x005: // RDR - receive data
381 break;
382 case 0x010: // TIER
383 if (d & 0x8e)
384 elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
385 d = (d & 0x8e) | 1;
386 PREG8(r, a) = d;
387 break;
388 case 0x017: // TOCR
389 d |= 0xe0;
390 PREG8(r, a) = d;
391 break;
392 default:
393 if ((a & 0x1c0) == 0x140)
394 p32x_sh2_poll_event(a, sh2, SH2_STATE_CPOLL, SekCyclesDone());
395 }
396 DRC_RESTORE_SR(sh2);
397}
398
399void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
400{
401 u16 *r = (void *)sh2->peri_regs;
402
403 DRC_SAVE_SR(sh2);
404 elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
405 a, d, sh2_pc(sh2));
406
407 a &= 0x1fe;
408
409 // evil WDT
410 if (a == 0x80) {
411 if ((d & 0xff00) == 0xa500) { // WTCSR
412 PREG8(r, 0x80) = d;
413 p32x_timers_recalc();
414 }
415 if ((d & 0xff00) == 0x5a00) // WTCNT
416 PREG8(r, 0x81) = d;
417 } else {
418 r[MEM_BE2(a / 2)] = d;
419 if ((a & 0x1c0) == 0x140)
420 p32x_sh2_poll_event(a, sh2, SH2_STATE_CPOLL, SekCyclesDone());
421 }
422 DRC_RESTORE_SR(sh2);
423}
424
425void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
426{
427 u32 *r = sh2->peri_regs;
428 u32 old;
429 struct dmac *dmac;
430
431 DRC_SAVE_SR(sh2);
432 elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
433 a, d, sh2_pc(sh2));
434
435 a &= 0x1fc;
436 old = r[a / 4];
437 r[a / 4] = d;
438
439 // TODO: DRC doesn't correctly extend 'd' parameter register to 64bit :-/
440 switch (a) {
441 // division unit (TODO: verify):
442 case 0x104: // DVDNT: divident L, starts divide
443 elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
444 r[0x104 / 4], r[0x100 / 4]);
445 if (r[0x100 / 4]) {
446 signed int divisor = r[0x100 / 4];
447 r[0x118 / 4] = r[0x110 / 4] = (signed int)r[0x104 / 4] % divisor;
448 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)r[0x104 / 4] / divisor;
449 }
450 else
451 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
452 break;
453 case 0x114:
454 elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
455 r[0x110 / 4], r[0x114 / 4], r[0x100 / 4], sh2_pc(sh2));
456 if (r[0x100 / 4]) {
457 signed long long divident = (signed long long)r[0x110 / 4] << 32 | r[0x114 / 4];
458 signed int divisor = r[0x100 / 4];
459 // XXX: undocumented mirroring to 0x118,0x11c?
460 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
461 divident /= divisor;
462 r[0x11c / 4] = r[0x114 / 4] = divident;
463 divident >>= 31;
464 if ((unsigned long long)divident + 1 > 1) {
465 //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
466 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
467 }
468 }
469 else
470 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
471 break;
472 // perhaps starting a DMA?
473 case 0x18c:
474 case 0x19c:
475 case 0x1b0:
476 dmac = (void *)&sh2->peri_regs[0x180 / 4];
477 if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
478 return;
479 if (!(dmac->dmaor & DMA_DME))
480 return;
481
482 if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
483 dmac_trigger(sh2, &dmac->chan[0]);
484 if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
485 dmac_trigger(sh2, &dmac->chan[1]);
486 break;
487 default:
488 if ((a & 0x1c0) == 0x140)
489 p32x_sh2_poll_event(a, sh2, SH2_STATE_CPOLL, SekCyclesDone());
490 }
491
492 DRC_RESTORE_SR(sh2);
493}
494
495/* 32X specific */
496static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
497{
498 unsigned short dreqlen = Pico32x.regs[0x10 / 2];
499 int i;
500
501 // debug/sanity checks
502 if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
503 elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
504 chan->tcr, dreqlen);
505 // note: DACK is not connected, single addr mode should not be used
506 if ((chan->chcr & 0x3f08) != 0x0400)
507 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
508 if ((chan->sar & ~0x20000000) != 0x00004012)
509 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
510
511 // HACK: assume bus is busy and SH2 is halted
512 sh2->state |= SH2_STATE_SLEEP;
513
514 for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
515 elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
516 chan->dar, Pico32x.dmac_fifo[i], dreqlen);
517 p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
518 chan->dar += 2;
519 chan->tcr--;
520 }
521
522 if (Pico32x.dmac0_fifo_ptr != i)
523 memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
524 (Pico32x.dmac0_fifo_ptr - i) * 2);
525 Pico32x.dmac0_fifo_ptr -= i;
526
527 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
528 if (chan->tcr == 0)
529 dmac_transfer_complete(sh2, chan);
530 else
531 sh2_end_run(sh2, 16);
532}
533
534static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
535{
536 // debug/sanity checks
537 if ((chan->chcr & 0xc308) != 0x0000)
538 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
539 if ((chan->dar & ~0xf) != 0x20004030)
540 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
541
542 sh2->state |= SH2_STATE_SLEEP;
543 dmac_transfer_one(sh2, chan);
544 sh2->state &= ~SH2_STATE_SLEEP;
545 if (chan->tcr == 0)
546 dmac_transfer_complete(sh2, chan);
547}
548
549void p32x_dreq0_trigger(void)
550{
551 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
552 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
553
554 elprintf(EL_32XP, "dreq0_trigger");
555 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
556 dreq0_do(&msh2, &mdmac->chan[0]);
557 }
558 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
559 dreq0_do(&ssh2, &sdmac->chan[0]);
560 }
561}
562
563void p32x_dreq1_trigger(void)
564{
565 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
566 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
567 int hit = 0;
568
569 elprintf(EL_32XP, "dreq1_trigger");
570 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
571 dreq1_do(&msh2, &mdmac->chan[1]);
572 hit = 1;
573 }
574 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
575 dreq1_do(&ssh2, &sdmac->chan[1]);
576 hit = 1;
577 }
578
579 // debug
580#if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
581 {
582 static int miss_count;
583 if (!hit) {
584 if (++miss_count == 4)
585 elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
586 }
587 else
588 miss_count = 0;
589 }
590#endif
591 (void)hit;
592}
593
594// vim:shiftwidth=2:ts=2:expandtab
fast MegaDrive/MegaCD/32X emulator