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fix operator spr change ARM code bugs
[picodrive.git] / pico / cd / LC89510.c
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1/***********************************************************\r
2 * *\r
3 * This source file was taken from the Gens project *\r
4 * Written by Stéphane Dallongeville *\r
5 * Copyright (c) 2002 by Stéphane Dallongeville *\r
6 * Modified/adapted for PicoDrive by notaz, 2007 *\r
7 * *\r
8 ***********************************************************/\r
9\r
10#include "../pico_int.h"\r
11\r
12#define CDC_DMA_SPEED 256\r
13\r
14\r
15static void CDD_Reset(void)\r
16{\r
17 // Reseting CDD\r
18\r
19 memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
20 Pico_mcd->cdd.Status = 0;\r
21 Pico_mcd->cdd.Minute = 0;\r
22 Pico_mcd->cdd.Seconde = 0;\r
23 Pico_mcd->cdd.Frame = 0;\r
24 Pico_mcd->cdd.Ext = 0;\r
25\r
26 // clear receive status and transfer command\r
27 memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
28 Pico_mcd->s68k_regs[0x38+9] = 0xF; // Default checksum\r
29}\r
30\r
31\r
32static void CDC_Reset(void)\r
33{\r
34 // Reseting CDC\r
35\r
36 memset(Pico_mcd->cdc.Buffer, 0, sizeof(Pico_mcd->cdc.Buffer));\r
37\r
38 Pico_mcd->cdc.COMIN = 0;\r
39 Pico_mcd->cdc.IFSTAT = 0xFF;\r
40 Pico_mcd->cdc.DAC.N = 0;\r
41 Pico_mcd->cdc.DBC.N = 0;\r
42 Pico_mcd->cdc.HEAD.N = 0x01000000;\r
43 Pico_mcd->cdc.PT.N = 0;\r
44 Pico_mcd->cdc.WA.N = 2352 * 2;\r
45 Pico_mcd->cdc.STAT.N = 0x00000080;\r
46 Pico_mcd->cdc.SBOUT = 0;\r
47 Pico_mcd->cdc.IFCTRL = 0;\r
48 Pico_mcd->cdc.CTRL.N = 0;\r
49\r
50 Pico_mcd->cdc.Decode_Reg_Read = 0;\r
51 Pico_mcd->scd.Status_CDC &= ~0x08;\r
52}\r
53\r
54\r
55PICO_INTERNAL void LC89510_Reset(void)\r
56{\r
57 CDD_Reset();\r
58 CDC_Reset();\r
59\r
60 // clear DMA_Adr & Stop_Watch\r
61 memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
62}\r
63\r
64\r
65PICO_INTERNAL void Update_CDC_TRansfer(int which)\r
66{\r
67 unsigned int DMA_Adr, dep, length;\r
68 unsigned short *dest;\r
69 unsigned char *src;\r
70\r
71 if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
72 {\r
73 length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
74 Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
75 Pico_mcd->s68k_regs[4] |= 0x80; // End data transfer\r
76 Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
77 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
78\r
79 if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Trasnfer End Interrupt Enable ?\r
80 {\r
81 Pico_mcd->cdc.IFSTAT &= ~0x40;\r
82\r
83 if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
84 {\r
85 elprintf(EL_INTS, "cdc DTE irq 5");\r
86 SekInterruptS68k(5);\r
87 }\r
88 }\r
89 }\r
90 else length = CDC_DMA_SPEED;\r
91\r
92\r
93 // TODO: dst bounds checking?\r
94 src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
95 DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB];\r
96\r
97 if (which == 7) // WORD RAM\r
98 {\r
99 if (Pico_mcd->s68k_regs[3] & 4)\r
100 {\r
101 // test: Final Fight\r
102 int bank = !(Pico_mcd->s68k_regs[3]&1);\r
103 dep = ((DMA_Adr & 0x3FFF) << 3);\r
104 cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
105 Pico_mcd->cdc.DAC.N, dep, length);\r
106\r
107 dest = (unsigned short *) (Pico_mcd->word_ram1M[bank] + dep);\r
108\r
109 memcpy16bswap(dest, src, length);\r
110\r
111 /*{ // debug\r
112 unsigned char *b1 = Pico_mcd->word_ram1M[bank] + dep;\r
113 unsigned char *b2 = (unsigned char *)(dest+length) - 8;\r
114 dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
115 b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
116 }*/\r
117 }\r
118 else\r
119 {\r
120 dep = ((DMA_Adr & 0x7FFF) << 3);\r
121 cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
122 Pico_mcd->cdc.DAC.N, dep, length);\r
123 dest = (unsigned short *) (Pico_mcd->word_ram2M + dep);\r
124\r
125 memcpy16bswap(dest, src, length);\r
126\r
127 /*{ // debug\r
128 unsigned char *b1 = Pico_mcd->word_ram2M + dep;\r
129 unsigned char *b2 = (unsigned char *)(dest+length) - 4;\r
130 dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
131 b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
132 }*/\r
133 }\r
134 }\r
135 else if (which == 4) // PCM RAM (check: popful Mail)\r
136 {\r
137 dep = (DMA_Adr & 0x03FF) << 2;\r
138 cdprintf("CD DMA # %04x -> PCM[%i] # %04x, len=%i",\r
139 Pico_mcd->cdc.DAC.N, Pico_mcd->pcm.bank, dep, length);\r
140 dest = (unsigned short *) (Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank] + dep);\r
141\r
142 if (Pico_mcd->cdc.DAC.N & 1) /* unaligned src? */\r
143 memcpy(dest, src, length*2);\r
144 else memcpy16(dest, (unsigned short *) src, length);\r
145 }\r
146 else if (which == 5) // PRG RAM\r
147 {\r
148 dep = DMA_Adr << 3;\r
149 dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
150 cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
151 Pico_mcd->cdc.DAC.N, dep, length);\r
152\r
153 memcpy16bswap(dest, src, length);\r
154\r
155 /*{ // debug\r
156 unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
157 unsigned char *b2 = (unsigned char *)(dest+length) - 4;\r
158 dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
159 b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
160 }*/\r
161 }\r
162\r
163 length <<= 1;\r
164 Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
165 if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
166 else Pico_mcd->cdc.DBC.N = 0;\r
167\r
168 // update DMA_Adr\r
169 length >>= 2;\r
170 if (which != 4) length >>= 1;\r
171 DMA_Adr += length;\r
172 Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
173 Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
174}\r
175\r
176\r
177PICO_INTERNAL_ASM unsigned short Read_CDC_Host(int is_sub)\r
178{\r
179 int addr;\r
180\r
181 if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
182 {\r
183 // Transfer data disabled\r
184 cdprintf("Read_CDC_Host FIXME: Transfer data disabled");\r
185 return 0;\r
186 }\r
187\r
188 if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) ||\r
189 (!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
190 {\r
191 // Wrong setting\r
192 cdprintf("Read_CDC_Host FIXME: Wrong setting");\r
193 return 0;\r
194 }\r
195\r
196 Pico_mcd->cdc.DBC.N -= 2;\r
197\r
198 if (Pico_mcd->cdc.DBC.N <= 0)\r
199 {\r
200 Pico_mcd->cdc.DBC.N = 0;\r
201 Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
202 Pico_mcd->s68k_regs[4] |= 0x80; // End data transfer\r
203 Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
204 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
205\r
206 if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Transfer End Interrupt Enable ?\r
207 {\r
208 Pico_mcd->cdc.IFSTAT &= ~0x40;\r
209\r
210 if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
211 elprintf(EL_INTS, "m68k: s68k irq 5");\r
212 SekInterruptS68k(5);\r
213 }\r
214\r
215 cdprintf("CDC - DTE interrupt");\r
216 }\r
217 }\r
218\r
219 addr = Pico_mcd->cdc.DAC.N;\r
220 Pico_mcd->cdc.DAC.N += 2;\r
221\r
222 cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
223 (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
224\r
225 return (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1];\r
226}\r
227\r
228\r
229PICO_INTERNAL void CDC_Update_Header(void)\r
230{\r
231 if (Pico_mcd->cdc.CTRL.B.B1 & 0x01) // Sub-Header wanted ?\r
232 {\r
233 Pico_mcd->cdc.HEAD.B.B0 = 0;\r
234 Pico_mcd->cdc.HEAD.B.B1 = 0;\r
235 Pico_mcd->cdc.HEAD.B.B2 = 0;\r
236 Pico_mcd->cdc.HEAD.B.B3 = 0;\r
237 }\r
238 else\r
239 {\r
240 _msf MSF;\r
241\r
242 LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
243\r
244 Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
245 Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
246 Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
247 Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
248 }\r
249}\r
250\r
251\r
252PICO_INTERNAL unsigned char CDC_Read_Reg(void)\r
253{\r
254 unsigned char ret;\r
255\r
256 switch(Pico_mcd->s68k_regs[5] & 0xF)\r
257 {\r
258 case 0x0: // COMIN\r
259 cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
260\r
261 Pico_mcd->s68k_regs[5] = 0x1;\r
262 return Pico_mcd->cdc.COMIN;\r
263\r
264 case 0x1: // IFSTAT\r
265 cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
266\r
267 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 1); // Reg 1 (decoding)\r
268 Pico_mcd->s68k_regs[5] = 0x2;\r
269 return Pico_mcd->cdc.IFSTAT;\r
270\r
271 case 0x2: // DBCL\r
272 cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
273\r
274 Pico_mcd->s68k_regs[5] = 0x3;\r
275 return Pico_mcd->cdc.DBC.B.L;\r
276\r
277 case 0x3: // DBCH\r
278 cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
279\r
280 Pico_mcd->s68k_regs[5] = 0x4;\r
281 return Pico_mcd->cdc.DBC.B.H;\r
282\r
283 case 0x4: // HEAD0\r
284 cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
285\r
286 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 4); // Reg 4 (decoding)\r
287 Pico_mcd->s68k_regs[5] = 0x5;\r
288 return Pico_mcd->cdc.HEAD.B.B0;\r
289\r
290 case 0x5: // HEAD1\r
291 cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
292\r
293 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 5); // Reg 5 (decoding)\r
294 Pico_mcd->s68k_regs[5] = 0x6;\r
295 return Pico_mcd->cdc.HEAD.B.B1;\r
296\r
297 case 0x6: // HEAD2\r
298 cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
299\r
300 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 6); // Reg 6 (decoding)\r
301 Pico_mcd->s68k_regs[5] = 0x7;\r
302 return Pico_mcd->cdc.HEAD.B.B2;\r
303\r
304 case 0x7: // HEAD3\r
305 cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
306\r
307 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 7); // Reg 7 (decoding)\r
308 Pico_mcd->s68k_regs[5] = 0x8;\r
309 return Pico_mcd->cdc.HEAD.B.B3;\r
310\r
311 case 0x8: // PTL\r
312 cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
313\r
314 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 8); // Reg 8 (decoding)\r
315 Pico_mcd->s68k_regs[5] = 0x9;\r
316 return Pico_mcd->cdc.PT.B.L;\r
317\r
318 case 0x9: // PTH\r
319 cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
320\r
321 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 9); // Reg 9 (decoding)\r
322 Pico_mcd->s68k_regs[5] = 0xA;\r
323 return Pico_mcd->cdc.PT.B.H;\r
324\r
325 case 0xA: // WAL\r
326 cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
327\r
328 Pico_mcd->s68k_regs[5] = 0xB;\r
329 return Pico_mcd->cdc.WA.B.L;\r
330\r
331 case 0xB: // WAH\r
332 cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
333\r
334 Pico_mcd->s68k_regs[5] = 0xC;\r
335 return Pico_mcd->cdc.WA.B.H;\r
336\r
337 case 0xC: // STAT0\r
338 cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
339\r
340 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 12); // Reg 12 (decoding)\r
341 Pico_mcd->s68k_regs[5] = 0xD;\r
342 return Pico_mcd->cdc.STAT.B.B0;\r
343\r
344 case 0xD: // STAT1\r
345 cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
346\r
347 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 13); // Reg 13 (decoding)\r
348 Pico_mcd->s68k_regs[5] = 0xE;\r
349 return Pico_mcd->cdc.STAT.B.B1;\r
350\r
351 case 0xE: // STAT2\r
352 cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
353\r
354 Pico_mcd->cdc.Decode_Reg_Read |= (1 << 14); // Reg 14 (decoding)\r
355 Pico_mcd->s68k_regs[5] = 0xF;\r
356 return Pico_mcd->cdc.STAT.B.B2;\r
357\r
358 case 0xF: // STAT3\r
359 cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
360\r
361 ret = Pico_mcd->cdc.STAT.B.B3;\r
362 Pico_mcd->cdc.IFSTAT |= 0x20; // decoding interrupt flag cleared\r
363 if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
364 {\r
365 if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
366 Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
367 }\r
368 return ret;\r
369 }\r
370\r
371 return 0;\r
372}\r
373\r
374\r
375PICO_INTERNAL void CDC_Write_Reg(unsigned char Data)\r
376{\r
377 cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
378\r
379 switch (Pico_mcd->s68k_regs[5] & 0xF)\r
380 {\r
381 case 0x0: // SBOUT\r
382 Pico_mcd->s68k_regs[5] = 0x1;\r
383 Pico_mcd->cdc.SBOUT = Data;\r
384\r
385 break;\r
386\r
387 case 0x1: // IFCTRL\r
388 Pico_mcd->s68k_regs[5] = 0x2;\r
389 Pico_mcd->cdc.IFCTRL = Data;\r
390\r
391 if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0) // Stop data transfer\r
392 {\r
393 Pico_mcd->cdc.DBC.N = 0;\r
394 Pico_mcd->scd.Status_CDC &= ~0x08;\r
395 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
396 }\r
397 break;\r
398\r
399 case 0x2: // DBCL\r
400 Pico_mcd->s68k_regs[5] = 0x3;\r
401 Pico_mcd->cdc.DBC.B.L = Data;\r
402\r
403 break;\r
404\r
405 case 0x3: // DBCH\r
406 Pico_mcd->s68k_regs[5] = 0x4;\r
407 Pico_mcd->cdc.DBC.B.H = Data;\r
408\r
409 break;\r
410\r
411 case 0x4: // DACL\r
412 Pico_mcd->s68k_regs[5] = 0x5;\r
413 Pico_mcd->cdc.DAC.B.L = Data;\r
414\r
415 break;\r
416\r
417 case 0x5: // DACH\r
418 Pico_mcd->s68k_regs[5] = 0x6;\r
419 Pico_mcd->cdc.DAC.B.H = Data;\r
420\r
421 break;\r
422\r
423 case 0x6: // DTTRG\r
424 if (Pico_mcd->cdc.IFCTRL & 0x02) // Data transfer enable ?\r
425 {\r
426 Pico_mcd->cdc.IFSTAT &= ~0x08; // Data transfer in progress\r
427 Pico_mcd->scd.Status_CDC |= 0x08; // Data transfer in progress\r
428 Pico_mcd->s68k_regs[4] &= 0x7F; // A data transfer start\r
429\r
430 cdprintf("************** Starting Data Transfer ***********");\r
431 cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
432 Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
433 }\r
434 break;\r
435\r
436 case 0x7: // DTACK\r
437 Pico_mcd->cdc.IFSTAT |= 0x40; // end data transfer interrupt flag cleared\r
438 break;\r
439\r
440 case 0x8: // WAL\r
441 Pico_mcd->s68k_regs[5] = 0x9;\r
442 Pico_mcd->cdc.WA.B.L = Data;\r
443\r
444 break;\r
445\r
446 case 0x9: // WAH\r
447 Pico_mcd->s68k_regs[5] = 0xA;\r
448 Pico_mcd->cdc.WA.B.H = Data;\r
449\r
450 break;\r
451\r
452 case 0xA: // CTRL0\r
453 Pico_mcd->s68k_regs[5] = 0xB;\r
454 Pico_mcd->cdc.CTRL.B.B0 = Data;\r
455\r
456 break;\r
457\r
458 case 0xB: // CTRL1\r
459 Pico_mcd->s68k_regs[5] = 0xC;\r
460 Pico_mcd->cdc.CTRL.B.B1 = Data;\r
461\r
462 break;\r
463\r
464 case 0xC: // PTL\r
465 Pico_mcd->s68k_regs[5] = 0xD;\r
466 Pico_mcd->cdc.PT.B.L = Data;\r
467\r
468 break;\r
469\r
470 case 0xD: // PTH\r
471 Pico_mcd->s68k_regs[5] = 0xE;\r
472 Pico_mcd->cdc.PT.B.H = Data;\r
473\r
474 break;\r
475\r
476 case 0xE: // CTRL2\r
477 Pico_mcd->cdc.CTRL.B.B2 = Data;\r
478 break;\r
479\r
480 case 0xF: // RESET\r
481 CDC_Reset();\r
482 break;\r
483 }\r
484}\r
485\r
486\r
487static int bswapwrite(int a, unsigned short d)\r
488{\r
489 *(unsigned short *)(Pico_mcd->s68k_regs + a) = (d>>8)|(d<<8);\r
490 return d + (d >> 8);\r
491}\r
492\r
493PICO_INTERNAL void CDD_Export_Status(void)\r
494{\r
495 unsigned int csum;\r
496\r
497 csum = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
498 csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
499 csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
500 csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
501 Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
502 csum += Pico_mcd->cdd.Ext;\r
503 Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
504\r
505 Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
506\r
507 if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
508 {\r
509 elprintf(EL_INTS, "cdd export irq 4");\r
510 SekInterruptS68k(4);\r
511 }\r
512\r
513// cdprintf("CDD exported status\n");\r
514 cdprintf("out: Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
515 (Pico_mcd->s68k_regs[0x38+0] << 8) | Pico_mcd->s68k_regs[0x38+1],\r
516 (Pico_mcd->s68k_regs[0x38+2] << 8) | Pico_mcd->s68k_regs[0x38+3],\r
517 (Pico_mcd->s68k_regs[0x38+4] << 8) | Pico_mcd->s68k_regs[0x38+5],\r
518 (Pico_mcd->s68k_regs[0x38+6] << 8) | Pico_mcd->s68k_regs[0x38+7],\r
519 (Pico_mcd->s68k_regs[0x38+8] << 8) | Pico_mcd->s68k_regs[0x38+9]);\r
520}\r
521\r
522\r
523PICO_INTERNAL void CDD_Import_Command(void)\r
524{\r
525// cdprintf("CDD importing command\n");\r
526 cdprintf("in: Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
527 (Pico_mcd->s68k_regs[0x38+10+0] << 8) | Pico_mcd->s68k_regs[0x38+10+1],\r
528 (Pico_mcd->s68k_regs[0x38+10+2] << 8) | Pico_mcd->s68k_regs[0x38+10+3],\r
529 (Pico_mcd->s68k_regs[0x38+10+4] << 8) | Pico_mcd->s68k_regs[0x38+10+5],\r
530 (Pico_mcd->s68k_regs[0x38+10+6] << 8) | Pico_mcd->s68k_regs[0x38+10+7],\r
531 (Pico_mcd->s68k_regs[0x38+10+8] << 8) | Pico_mcd->s68k_regs[0x38+10+9]);\r
532\r
533 switch (Pico_mcd->s68k_regs[0x38+10+0])\r
534 {\r
535 case 0x0: // STATUS (?)\r
536 Get_Status_CDD_c0();\r
537 break;\r
538\r
539 case 0x1: // STOP ALL (?)\r
540 Stop_CDD_c1();\r
541 break;\r
542\r
543 case 0x2: // GET TOC INFORMATIONS\r
544 switch(Pico_mcd->s68k_regs[0x38+10+3])\r
545 {\r
546 case 0x0: // get current position (MSF format)\r
547 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
548 Get_Pos_CDD_c20();\r
549 break;\r
550\r
551 case 0x1: // get elapsed time of current track played/scanned (relative MSF format)\r
552 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 1;\r
553 Get_Track_Pos_CDD_c21();\r
554 break;\r
555\r
556 case 0x2: // get current track in RS2-RS3\r
557 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 2;\r
558 Get_Current_Track_CDD_c22();\r
559 break;\r
560\r
561 case 0x3: // get total length (MSF format)\r
562 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 3;\r
563 Get_Total_Lenght_CDD_c23();\r
564 break;\r
565\r
566 case 0x4: // first & last track number\r
567 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 4;\r
568 Get_First_Last_Track_CDD_c24();\r
569 break;\r
570\r
571 case 0x5: // get track addresse (MSF format)\r
572 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 5;\r
573 Get_Track_Adr_CDD_c25();\r
574 break;\r
575\r
576 default : // invalid, then we return status\r
577 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 0xF;\r
578 Get_Status_CDD_c0();\r
579 break;\r
580 }\r
581 break;\r
582\r
583 case 0x3: // READ\r
584 Play_CDD_c3();\r
585 break;\r
586\r
587 case 0x4: // SEEK\r
588 Seek_CDD_c4();\r
589 break;\r
590\r
591 case 0x6: // PAUSE/STOP\r
592 Pause_CDD_c6();\r
593 break;\r
594\r
595 case 0x7: // RESUME\r
596 Resume_CDD_c7();\r
597 break;\r
598\r
599 case 0x8: // FAST FOWARD\r
600 Fast_Foward_CDD_c8();\r
601 break;\r
602\r
603 case 0x9: // FAST REWIND\r
604 Fast_Rewind_CDD_c9();\r
605 break;\r
606\r
607 case 0xA: // RECOVER INITIAL STATE (?)\r
608 CDD_cA();\r
609 break;\r
610\r
611 case 0xC: // CLOSE TRAY\r
612 Close_Tray_CDD_cC();\r
613 break;\r
614\r
615 case 0xD: // OPEN TRAY\r
616 Open_Tray_CDD_cD();\r
617 break;\r
618\r
619 default: // UNKNOWN\r
620 CDD_Def();\r
621 break;\r
622 }\r
623}\r
624\r
fast MegaDrive/MegaCD/32X emulator