| 1 | /*************************************************************************************** |
| 2 | * Genesis Plus |
| 3 | * CD data controller (LC89510 compatible) |
| 4 | * |
| 5 | * Copyright (C) 2012 Eke-Eke (Genesis Plus GX) |
| 6 | * |
| 7 | * Redistribution and use of this code or any derivative works are permitted |
| 8 | * provided that the following conditions are met: |
| 9 | * |
| 10 | * - Redistributions may not be sold, nor may they be used in a commercial |
| 11 | * product or activity. |
| 12 | * |
| 13 | * - Redistributions that are modified from the original source must include the |
| 14 | * complete source code, including the source code for all components used by a |
| 15 | * binary built from the modified sources. However, as a special exception, the |
| 16 | * source code distributed need not include anything that is normally distributed |
| 17 | * (in either source or binary form) with the major components (compiler, kernel, |
| 18 | * and so on) of the operating system on which the executable runs, unless that |
| 19 | * component itself accompanies the executable. |
| 20 | * |
| 21 | * - Redistributions must reproduce the above copyright notice, this list of |
| 22 | * conditions and the following disclaimer in the documentation and/or other |
| 23 | * materials provided with the distribution. |
| 24 | * |
| 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 28 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 29 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 35 | * POSSIBILITY OF SUCH DAMAGE. |
| 36 | * |
| 37 | ****************************************************************************************/ |
| 38 | |
| 39 | #include "../pico_int.h" |
| 40 | #include "genplus_macros.h" |
| 41 | |
| 42 | /* IFSTAT register bitmasks */ |
| 43 | #define BIT_DTEI 0x40 |
| 44 | #define BIT_DECI 0x20 |
| 45 | #define BIT_DTBSY 0x08 |
| 46 | #define BIT_DTEN 0x02 |
| 47 | |
| 48 | /* IFCTRL register bitmasks */ |
| 49 | #define BIT_DTEIEN 0x40 |
| 50 | #define BIT_DECIEN 0x20 |
| 51 | #define BIT_DOUTEN 0x02 |
| 52 | |
| 53 | /* CTRL0 register bitmasks */ |
| 54 | #define BIT_DECEN 0x80 |
| 55 | #define BIT_E01RQ 0x20 |
| 56 | #define BIT_AUTORQ 0x10 |
| 57 | #define BIT_WRRQ 0x04 |
| 58 | |
| 59 | /* CTRL1 register bitmasks */ |
| 60 | #define BIT_MODRQ 0x08 |
| 61 | #define BIT_FORMRQ 0x04 |
| 62 | #define BIT_SHDREN 0x01 |
| 63 | |
| 64 | /* CTRL2 register bitmask */ |
| 65 | #define BIT_VALST 0x80 |
| 66 | |
| 67 | /* PicoDrive: doing DMA at once, not using callbacks */ |
| 68 | //#define DMA_BYTES_PER_LINE 512 |
| 69 | |
| 70 | enum dma_type { |
| 71 | word_ram_0_dma_w = 1, |
| 72 | word_ram_1_dma_w = 2, |
| 73 | word_ram_2M_dma_w = 3, |
| 74 | pcm_ram_dma_w = 4, |
| 75 | prg_ram_dma_w = 5, |
| 76 | }; |
| 77 | |
| 78 | /* CDC hardware */ |
| 79 | typedef struct |
| 80 | { |
| 81 | uint8 ifstat; |
| 82 | uint8 ifctrl; |
| 83 | uint16 dbc; |
| 84 | uint16 dac; |
| 85 | uint16 pt; |
| 86 | uint16 wa; |
| 87 | uint8 ctrl[2]; |
| 88 | uint8 head[2][4]; |
| 89 | uint8 stat[4]; |
| 90 | int cycles; |
| 91 | //void (*dma_w)(unsigned int words); |
| 92 | int dma_w; |
| 93 | uint8 ram[0x4000 + 2352]; /* 16K external RAM (with one block overhead to handle buffer overrun) */ |
| 94 | } cdc_t; |
| 95 | |
| 96 | static cdc_t cdc; |
| 97 | |
| 98 | void cdc_init(void) |
| 99 | { |
| 100 | memset(&cdc, 0, sizeof(cdc_t)); |
| 101 | } |
| 102 | |
| 103 | void cdc_reset(void) |
| 104 | { |
| 105 | /* reset CDC register index */ |
| 106 | Pico_mcd->s68k_regs[0x04+1] = 0x00; |
| 107 | |
| 108 | /* reset CDC registers */ |
| 109 | cdc.ifstat = 0xff; |
| 110 | cdc.ifctrl = 0x00; |
| 111 | cdc.ctrl[0] = 0x00; |
| 112 | cdc.ctrl[1] = 0x00; |
| 113 | cdc.stat[0] = 0x00; |
| 114 | cdc.stat[1] = 0x00; |
| 115 | cdc.stat[2] = 0x00; |
| 116 | cdc.stat[3] = 0x80; |
| 117 | cdc.head[0][0] = 0x00; |
| 118 | cdc.head[0][1] = 0x00; |
| 119 | cdc.head[0][2] = 0x00; |
| 120 | cdc.head[0][3] = 0x01; |
| 121 | cdc.head[1][0] = 0x00; |
| 122 | cdc.head[1][1] = 0x00; |
| 123 | cdc.head[1][2] = 0x00; |
| 124 | cdc.head[1][3] = 0x00; |
| 125 | |
| 126 | /* reset CDC cycle counter */ |
| 127 | cdc.cycles = 0; |
| 128 | |
| 129 | /* DMA transfer disabled */ |
| 130 | cdc.dma_w = 0; |
| 131 | } |
| 132 | |
| 133 | int cdc_context_save(uint8 *state) |
| 134 | { |
| 135 | uint8 tmp8; |
| 136 | int bufferptr = 0; |
| 137 | |
| 138 | if (cdc.dma_w == pcm_ram_dma_w) |
| 139 | { |
| 140 | tmp8 = 1; |
| 141 | } |
| 142 | else if (cdc.dma_w == prg_ram_dma_w) |
| 143 | { |
| 144 | tmp8 = 2; |
| 145 | } |
| 146 | else if (cdc.dma_w == word_ram_0_dma_w) |
| 147 | { |
| 148 | tmp8 = 3; |
| 149 | } |
| 150 | else if (cdc.dma_w == word_ram_1_dma_w) |
| 151 | { |
| 152 | tmp8 = 4; |
| 153 | } |
| 154 | else if (cdc.dma_w == word_ram_2M_dma_w) |
| 155 | { |
| 156 | tmp8 = 5; |
| 157 | } |
| 158 | else |
| 159 | { |
| 160 | tmp8 = 0; |
| 161 | } |
| 162 | |
| 163 | save_param(&cdc, sizeof(cdc)); |
| 164 | save_param(&tmp8, 1); |
| 165 | |
| 166 | return bufferptr; |
| 167 | } |
| 168 | |
| 169 | int cdc_context_load(uint8 *state) |
| 170 | { |
| 171 | uint8 tmp8; |
| 172 | int bufferptr = 0; |
| 173 | |
| 174 | load_param(&cdc, sizeof(cdc)); |
| 175 | load_param(&tmp8, 1); |
| 176 | |
| 177 | switch (tmp8) |
| 178 | { |
| 179 | case 1: |
| 180 | cdc.dma_w = pcm_ram_dma_w; |
| 181 | break; |
| 182 | case 2: |
| 183 | cdc.dma_w = prg_ram_dma_w; |
| 184 | break; |
| 185 | case 3: |
| 186 | cdc.dma_w = word_ram_0_dma_w; |
| 187 | break; |
| 188 | case 4: |
| 189 | cdc.dma_w = word_ram_1_dma_w; |
| 190 | break; |
| 191 | case 5: |
| 192 | cdc.dma_w = word_ram_2M_dma_w; |
| 193 | break; |
| 194 | default: |
| 195 | cdc.dma_w = 0; |
| 196 | break; |
| 197 | } |
| 198 | |
| 199 | return bufferptr; |
| 200 | } |
| 201 | |
| 202 | int cdc_context_load_old(uint8 *state) |
| 203 | { |
| 204 | #define old_load(v, ofs) \ |
| 205 | memcpy(&cdc.v, state + ofs, sizeof(cdc.v)) |
| 206 | |
| 207 | memcpy(cdc.ram, state, 0x4000); |
| 208 | old_load(ifstat, 67892); |
| 209 | old_load(ifctrl, 67924); |
| 210 | old_load(dbc, 67896); |
| 211 | old_load(dac, 67900); |
| 212 | old_load(pt, 67908); |
| 213 | old_load(wa, 67912); |
| 214 | old_load(ctrl, 67928); |
| 215 | old_load(head[0], 67904); |
| 216 | old_load(stat, 67916); |
| 217 | |
| 218 | cdc.dma_w = 0; |
| 219 | switch (Pico_mcd->s68k_regs[0x04+0] & 0x07) |
| 220 | { |
| 221 | case 4: /* PCM RAM DMA */ |
| 222 | cdc.dma_w = pcm_ram_dma_w; |
| 223 | break; |
| 224 | case 5: /* PRG-RAM DMA */ |
| 225 | cdc.dma_w = prg_ram_dma_w; |
| 226 | break; |
| 227 | case 7: /* WORD-RAM DMA */ |
| 228 | if (Pico_mcd->s68k_regs[0x02+1] & 0x04) |
| 229 | { |
| 230 | if (Pico_mcd->s68k_regs[0x02+1] & 0x01) |
| 231 | cdc.dma_w = word_ram_0_dma_w; |
| 232 | else |
| 233 | cdc.dma_w = word_ram_1_dma_w; |
| 234 | } |
| 235 | else |
| 236 | { |
| 237 | if (Pico_mcd->s68k_regs[0x02+1] & 0x02) |
| 238 | cdc.dma_w = word_ram_2M_dma_w; |
| 239 | } |
| 240 | break; |
| 241 | } |
| 242 | |
| 243 | return 0x10960; // sizeof(old_cdc) |
| 244 | #undef old_load |
| 245 | } |
| 246 | |
| 247 | static void do_dma(enum dma_type type, int words_in) |
| 248 | { |
| 249 | int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b]; |
| 250 | int src_addr = cdc.dac & 0x3ffe; |
| 251 | int dst_addr = dma_addr; |
| 252 | int words = words_in; |
| 253 | int dst_limit = 0; |
| 254 | uint8 *dst; |
| 255 | int len; |
| 256 | |
| 257 | elprintf(EL_CD, "dma %d %04x->%04x %x", |
| 258 | type, cdc.dac, dst_addr, words_in); |
| 259 | |
| 260 | switch (type) |
| 261 | { |
| 262 | case pcm_ram_dma_w: |
| 263 | dst_addr = (dst_addr << 2) & 0xffc; |
| 264 | if (dst_addr + words * 2 > 0x1000) { |
| 265 | elprintf(EL_ANOMALY, "pcm dma oflow: %x %x", dst_addr, words); |
| 266 | words = (0x1000 - dst_addr) / 2; |
| 267 | } |
| 268 | dst = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank]; |
| 269 | dst = dst + dst_addr; |
| 270 | while (words > 0) |
| 271 | { |
| 272 | if (src_addr + words * 2 > 0x4000) { |
| 273 | len = 0x4000 - src_addr; |
| 274 | memcpy(dst, cdc.ram + src_addr, len); |
| 275 | dst += len; |
| 276 | src_addr = 0; |
| 277 | words -= len / 2; |
| 278 | continue; |
| 279 | } |
| 280 | memcpy(dst, cdc.ram + src_addr, words * 2); |
| 281 | break; |
| 282 | } |
| 283 | goto update_dma; |
| 284 | |
| 285 | case prg_ram_dma_w: |
| 286 | dst_addr <<= 3; |
| 287 | dst = Pico_mcd->prg_ram + dst_addr; |
| 288 | dst_limit = 0x80000; |
| 289 | break; |
| 290 | |
| 291 | case word_ram_0_dma_w: |
| 292 | dst_addr = (dst_addr << 3) & 0x1fffe; |
| 293 | dst = Pico_mcd->word_ram1M[0] + dst_addr; |
| 294 | dst_limit = 0x20000; |
| 295 | break; |
| 296 | |
| 297 | case word_ram_1_dma_w: |
| 298 | dst_addr = (dst_addr << 3) & 0x1fffe; |
| 299 | dst = Pico_mcd->word_ram1M[1] + dst_addr; |
| 300 | dst_limit = 0x20000; |
| 301 | break; |
| 302 | |
| 303 | case word_ram_2M_dma_w: |
| 304 | dst_addr = (dst_addr << 3) & 0x3fffe; |
| 305 | dst = Pico_mcd->word_ram2M + dst_addr; |
| 306 | dst_limit = 0x40000; |
| 307 | break; |
| 308 | |
| 309 | default: |
| 310 | elprintf(EL_ANOMALY, "invalid dma: %d", type); |
| 311 | goto update_dma; |
| 312 | } |
| 313 | |
| 314 | if (dst_addr + words * 2 > dst_limit) { |
| 315 | elprintf(EL_ANOMALY, "cd dma %d oflow: %x %x", type, dst_addr, words); |
| 316 | words = (dst_limit - dst_addr) / 2; |
| 317 | } |
| 318 | while (words > 0) |
| 319 | { |
| 320 | if (src_addr + words * 2 > 0x4000) { |
| 321 | len = 0x4000 - src_addr; |
| 322 | memcpy16bswap((void *)dst, cdc.ram + src_addr, len / 2); |
| 323 | dst += len; |
| 324 | src_addr = 0; |
| 325 | words -= len / 2; |
| 326 | continue; |
| 327 | } |
| 328 | memcpy16bswap((void *)dst, cdc.ram + src_addr, words); |
| 329 | break; |
| 330 | } |
| 331 | |
| 332 | update_dma: |
| 333 | /* update DMA addresses */ |
| 334 | cdc.dac += words_in * 2; |
| 335 | if (type == pcm_ram_dma_w) |
| 336 | dma_addr += words_in >> 1; |
| 337 | else |
| 338 | dma_addr += words_in >> 2; |
| 339 | |
| 340 | Pico_mcd->s68k_regs[0x0a] = dma_addr >> 8; |
| 341 | Pico_mcd->s68k_regs[0x0b] = dma_addr; |
| 342 | } |
| 343 | |
| 344 | void cdc_dma_update(void) |
| 345 | { |
| 346 | /* end of DMA transfer ? */ |
| 347 | //if (cdc.dbc < DMA_BYTES_PER_LINE) |
| 348 | { |
| 349 | /* transfer remaining words using 16-bit DMA */ |
| 350 | //cdc.dma_w((cdc.dbc + 1) >> 1); |
| 351 | do_dma(cdc.dma_w, (cdc.dbc + 1) >> 1); |
| 352 | |
| 353 | /* reset data byte counter (DBCH bits 4-7 should be set to 1) */ |
| 354 | cdc.dbc = 0xf000; |
| 355 | |
| 356 | /* clear !DTEN and !DTBSY */ |
| 357 | cdc.ifstat |= (BIT_DTBSY | BIT_DTEN); |
| 358 | |
| 359 | /* pending Data Transfer End interrupt */ |
| 360 | cdc.ifstat &= ~BIT_DTEI; |
| 361 | |
| 362 | /* Data Transfer End interrupt enabled ? */ |
| 363 | if (cdc.ifctrl & BIT_DTEIEN) |
| 364 | { |
| 365 | /* level 5 interrupt enabled ? */ |
| 366 | if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5) |
| 367 | { |
| 368 | /* update IRQ level */ |
| 369 | elprintf(EL_INTS, "cdc DTE irq 5"); |
| 370 | SekInterruptS68k(5); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | /* clear DSR bit & set EDT bit (SCD register $04) */ |
| 375 | Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80; |
| 376 | |
| 377 | /* disable DMA transfer */ |
| 378 | cdc.dma_w = 0; |
| 379 | } |
| 380 | #if 0 |
| 381 | else |
| 382 | { |
| 383 | /* transfer all words using 16-bit DMA */ |
| 384 | cdc.dma_w(DMA_BYTES_PER_LINE >> 1); |
| 385 | |
| 386 | /* decrement data byte counter */ |
| 387 | cdc.dbc -= length; |
| 388 | } |
| 389 | #endif |
| 390 | } |
| 391 | |
| 392 | int cdc_decoder_update(uint8 header[4]) |
| 393 | { |
| 394 | /* data decoding enabled ? */ |
| 395 | if (cdc.ctrl[0] & BIT_DECEN) |
| 396 | { |
| 397 | /* update HEAD registers */ |
| 398 | memcpy(cdc.head[0], header, sizeof(cdc.head[0])); |
| 399 | |
| 400 | /* set !VALST */ |
| 401 | cdc.stat[3] = 0x00; |
| 402 | |
| 403 | /* pending decoder interrupt */ |
| 404 | cdc.ifstat &= ~BIT_DECI; |
| 405 | |
| 406 | /* decoder interrupt enabled ? */ |
| 407 | if (cdc.ifctrl & BIT_DECIEN) |
| 408 | { |
| 409 | /* level 5 interrupt enabled ? */ |
| 410 | if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5) |
| 411 | { |
| 412 | /* update IRQ level */ |
| 413 | elprintf(EL_INTS, "cdc DEC irq 5"); |
| 414 | SekInterruptS68k(5); |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | /* buffer RAM write enabled ? */ |
| 419 | if (cdc.ctrl[0] & BIT_WRRQ) |
| 420 | { |
| 421 | uint16 offset; |
| 422 | |
| 423 | /* increment block pointer */ |
| 424 | cdc.pt += 2352; |
| 425 | |
| 426 | /* increment write address */ |
| 427 | cdc.wa += 2352; |
| 428 | |
| 429 | /* CDC buffer address */ |
| 430 | offset = cdc.pt & 0x3fff; |
| 431 | |
| 432 | /* write CDD block header (4 bytes) */ |
| 433 | memcpy(cdc.ram + offset, header, 4); |
| 434 | |
| 435 | /* write CDD block data (2048 bytes) */ |
| 436 | cdd_read_data(cdc.ram + 4 + offset); |
| 437 | |
| 438 | /* take care of buffer overrun */ |
| 439 | if (offset > (0x4000 - 2048 - 4)) |
| 440 | { |
| 441 | /* data should be written at the start of buffer */ |
| 442 | memcpy(cdc.ram, cdc.ram + 0x4000, offset + 2048 + 4 - 0x4000); |
| 443 | } |
| 444 | |
| 445 | /* read next data block */ |
| 446 | return 1; |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | /* keep decoding same data block if Buffer Write is disabled */ |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | void cdc_reg_w(unsigned char data) |
| 455 | { |
| 456 | #ifdef LOG_CDC |
| 457 | elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->s68k_regs[0x04+1] & 0x0F, data); |
| 458 | #endif |
| 459 | switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F) |
| 460 | { |
| 461 | case 0x01: /* IFCTRL */ |
| 462 | { |
| 463 | /* pending interrupts ? */ |
| 464 | if (((data & BIT_DTEIEN) && !(cdc.ifstat & BIT_DTEI)) || |
| 465 | ((data & BIT_DECIEN) && !(cdc.ifstat & BIT_DECI))) |
| 466 | { |
| 467 | /* level 5 interrupt enabled ? */ |
| 468 | if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5) |
| 469 | { |
| 470 | /* update IRQ level */ |
| 471 | elprintf(EL_INTS, "cdc pending irq 5"); |
| 472 | SekInterruptS68k(5); |
| 473 | } |
| 474 | } |
| 475 | else // if (scd.pending & (1 << 5)) |
| 476 | { |
| 477 | /* clear pending level 5 interrupts */ |
| 478 | SekInterruptClearS68k(5); |
| 479 | } |
| 480 | |
| 481 | /* abort any data transfer if data output is disabled */ |
| 482 | if (!(data & BIT_DOUTEN)) |
| 483 | { |
| 484 | /* clear !DTBSY and !DTEN */ |
| 485 | cdc.ifstat |= (BIT_DTBSY | BIT_DTEN); |
| 486 | } |
| 487 | |
| 488 | cdc.ifctrl = data; |
| 489 | Pico_mcd->s68k_regs[0x04+1] = 0x02; |
| 490 | break; |
| 491 | } |
| 492 | |
| 493 | case 0x02: /* DBCL */ |
| 494 | cdc.dbc &= 0xff00; |
| 495 | cdc.dbc |= data; |
| 496 | Pico_mcd->s68k_regs[0x04+1] = 0x03; |
| 497 | break; |
| 498 | |
| 499 | case 0x03: /* DBCH */ |
| 500 | cdc.dbc &= 0x00ff; |
| 501 | cdc.dbc |= data << 8; |
| 502 | Pico_mcd->s68k_regs[0x04+1] = 0x04; |
| 503 | break; |
| 504 | |
| 505 | case 0x04: /* DACL */ |
| 506 | cdc.dac &= 0xff00; |
| 507 | cdc.dac |= data; |
| 508 | Pico_mcd->s68k_regs[0x04+1] = 0x05; |
| 509 | break; |
| 510 | |
| 511 | case 0x05: /* DACH */ |
| 512 | cdc.dac &= 0x00ff; |
| 513 | cdc.dac |= data << 8; |
| 514 | Pico_mcd->s68k_regs[0x04+1] = 0x06; |
| 515 | break; |
| 516 | |
| 517 | case 0x06: /* DTRG */ |
| 518 | { |
| 519 | /* start data transfer if data output is enabled */ |
| 520 | if (cdc.ifctrl & BIT_DOUTEN) |
| 521 | { |
| 522 | /* set !DTBSY */ |
| 523 | cdc.ifstat &= ~BIT_DTBSY; |
| 524 | |
| 525 | /* clear DBCH bits 4-7 */ |
| 526 | cdc.dbc &= 0x0fff; |
| 527 | |
| 528 | /* clear EDT & DSR bits (SCD register $04) */ |
| 529 | Pico_mcd->s68k_regs[0x04+0] &= 0x07; |
| 530 | |
| 531 | cdc.dma_w = 0; |
| 532 | |
| 533 | /* setup data transfer destination */ |
| 534 | switch (Pico_mcd->s68k_regs[0x04+0] & 0x07) |
| 535 | { |
| 536 | case 2: /* MAIN-CPU host read */ |
| 537 | case 3: /* SUB-CPU host read */ |
| 538 | { |
| 539 | /* set !DTEN */ |
| 540 | cdc.ifstat &= ~BIT_DTEN; |
| 541 | |
| 542 | /* set DSR bit (register $04) */ |
| 543 | Pico_mcd->s68k_regs[0x04+0] |= 0x40; |
| 544 | break; |
| 545 | } |
| 546 | |
| 547 | case 4: /* PCM RAM DMA */ |
| 548 | { |
| 549 | cdc.dma_w = pcm_ram_dma_w; |
| 550 | break; |
| 551 | } |
| 552 | |
| 553 | case 5: /* PRG-RAM DMA */ |
| 554 | { |
| 555 | cdc.dma_w = prg_ram_dma_w; |
| 556 | break; |
| 557 | } |
| 558 | |
| 559 | case 7: /* WORD-RAM DMA */ |
| 560 | { |
| 561 | /* check memory mode */ |
| 562 | if (Pico_mcd->s68k_regs[0x02+1] & 0x04) |
| 563 | { |
| 564 | /* 1M mode */ |
| 565 | if (Pico_mcd->s68k_regs[0x02+1] & 0x01) |
| 566 | { |
| 567 | /* Word-RAM bank 0 is assigned to SUB-CPU */ |
| 568 | cdc.dma_w = word_ram_0_dma_w; |
| 569 | } |
| 570 | else |
| 571 | { |
| 572 | /* Word-RAM bank 1 is assigned to SUB-CPU */ |
| 573 | cdc.dma_w = word_ram_1_dma_w; |
| 574 | } |
| 575 | } |
| 576 | else |
| 577 | { |
| 578 | /* 2M mode */ |
| 579 | if (Pico_mcd->s68k_regs[0x02+1] & 0x02) |
| 580 | { |
| 581 | /* only process DMA if Word-RAM is assigned to SUB-CPU */ |
| 582 | cdc.dma_w = word_ram_2M_dma_w; |
| 583 | } |
| 584 | } |
| 585 | break; |
| 586 | } |
| 587 | |
| 588 | default: /* invalid */ |
| 589 | { |
| 590 | elprintf(EL_ANOMALY, "invalid CDC tranfer destination (%d)", |
| 591 | Pico_mcd->s68k_regs[0x04+0] & 0x07); |
| 592 | break; |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | if (cdc.dma_w) |
| 597 | pcd_event_schedule_s68k(PCD_EVENT_DMA, cdc.dbc / 2); |
| 598 | } |
| 599 | |
| 600 | Pico_mcd->s68k_regs[0x04+1] = 0x07; |
| 601 | break; |
| 602 | } |
| 603 | |
| 604 | case 0x07: /* DTACK */ |
| 605 | { |
| 606 | /* clear pending data transfer end interrupt */ |
| 607 | cdc.ifstat |= BIT_DTEI; |
| 608 | |
| 609 | /* clear DBCH bits 4-7 */ |
| 610 | cdc.dbc &= 0x0fff; |
| 611 | |
| 612 | #if 0 |
| 613 | /* no pending decoder interrupt ? */ |
| 614 | if ((cdc.ifstat | BIT_DECI) || !(cdc.ifctrl & BIT_DECIEN)) |
| 615 | { |
| 616 | /* clear pending level 5 interrupt */ |
| 617 | SekInterruptClearS68k(5); |
| 618 | } |
| 619 | #endif |
| 620 | Pico_mcd->s68k_regs[0x04+1] = 0x08; |
| 621 | break; |
| 622 | } |
| 623 | |
| 624 | case 0x08: /* WAL */ |
| 625 | cdc.wa &= 0xff00; |
| 626 | cdc.wa |= data; |
| 627 | Pico_mcd->s68k_regs[0x04+1] = 0x09; |
| 628 | break; |
| 629 | |
| 630 | case 0x09: /* WAH */ |
| 631 | cdc.wa &= 0x00ff; |
| 632 | cdc.wa |= data << 8; |
| 633 | Pico_mcd->s68k_regs[0x04+1] = 0x0a; |
| 634 | break; |
| 635 | |
| 636 | case 0x0a: /* CTRL0 */ |
| 637 | { |
| 638 | /* set CRCOK bit only if decoding is enabled */ |
| 639 | cdc.stat[0] = data & BIT_DECEN; |
| 640 | |
| 641 | /* update decoding mode */ |
| 642 | if (data & BIT_AUTORQ) |
| 643 | { |
| 644 | /* set MODE bit according to CTRL1 register & clear FORM bit */ |
| 645 | cdc.stat[2] = cdc.ctrl[1] & BIT_MODRQ; |
| 646 | } |
| 647 | else |
| 648 | { |
| 649 | /* set MODE & FORM bits according to CTRL1 register */ |
| 650 | cdc.stat[2] = cdc.ctrl[1] & (BIT_MODRQ | BIT_FORMRQ); |
| 651 | } |
| 652 | |
| 653 | cdc.ctrl[0] = data; |
| 654 | Pico_mcd->s68k_regs[0x04+1] = 0x0b; |
| 655 | break; |
| 656 | } |
| 657 | |
| 658 | case 0x0b: /* CTRL1 */ |
| 659 | { |
| 660 | /* update decoding mode */ |
| 661 | if (cdc.ctrl[0] & BIT_AUTORQ) |
| 662 | { |
| 663 | /* set MODE bit according to CTRL1 register & clear FORM bit */ |
| 664 | cdc.stat[2] = data & BIT_MODRQ; |
| 665 | } |
| 666 | else |
| 667 | { |
| 668 | /* set MODE & FORM bits according to CTRL1 register */ |
| 669 | cdc.stat[2] = data & (BIT_MODRQ | BIT_FORMRQ); |
| 670 | } |
| 671 | |
| 672 | cdc.ctrl[1] = data; |
| 673 | Pico_mcd->s68k_regs[0x04+1] = 0x0c; |
| 674 | break; |
| 675 | } |
| 676 | |
| 677 | case 0x0c: /* PTL */ |
| 678 | cdc.pt &= 0xff00; |
| 679 | cdc.pt |= data; |
| 680 | Pico_mcd->s68k_regs[0x04+1] = 0x0d; |
| 681 | break; |
| 682 | |
| 683 | case 0x0d: /* PTH */ |
| 684 | cdc.pt &= 0x00ff; |
| 685 | cdc.pt |= data << 8; |
| 686 | Pico_mcd->s68k_regs[0x04+1] = 0x0e; |
| 687 | break; |
| 688 | |
| 689 | case 0x0e: /* CTRL2 (unused) */ |
| 690 | Pico_mcd->s68k_regs[0x04+1] = 0x0f; |
| 691 | break; |
| 692 | |
| 693 | case 0x0f: /* RESET */ |
| 694 | cdc_reset(); |
| 695 | break; |
| 696 | |
| 697 | default: /* by default, SBOUT is not used */ |
| 698 | break; |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | unsigned char cdc_reg_r(void) |
| 703 | { |
| 704 | switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F) |
| 705 | { |
| 706 | case 0x01: /* IFSTAT */ |
| 707 | Pico_mcd->s68k_regs[0x04+1] = 0x02; |
| 708 | return cdc.ifstat; |
| 709 | |
| 710 | case 0x02: /* DBCL */ |
| 711 | Pico_mcd->s68k_regs[0x04+1] = 0x03; |
| 712 | return cdc.dbc & 0xff; |
| 713 | |
| 714 | case 0x03: /* DBCH */ |
| 715 | Pico_mcd->s68k_regs[0x04+1] = 0x04; |
| 716 | return (cdc.dbc >> 8) & 0xff; |
| 717 | |
| 718 | case 0x04: /* HEAD0 */ |
| 719 | Pico_mcd->s68k_regs[0x04+1] = 0x05; |
| 720 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][0]; |
| 721 | |
| 722 | case 0x05: /* HEAD1 */ |
| 723 | Pico_mcd->s68k_regs[0x04+1] = 0x06; |
| 724 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][1]; |
| 725 | |
| 726 | case 0x06: /* HEAD2 */ |
| 727 | Pico_mcd->s68k_regs[0x04+1] = 0x07; |
| 728 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][2]; |
| 729 | |
| 730 | case 0x07: /* HEAD3 */ |
| 731 | Pico_mcd->s68k_regs[0x04+1] = 0x08; |
| 732 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][3]; |
| 733 | |
| 734 | case 0x08: /* PTL */ |
| 735 | Pico_mcd->s68k_regs[0x04+1] = 0x09; |
| 736 | return cdc.pt & 0xff; |
| 737 | |
| 738 | case 0x09: /* PTH */ |
| 739 | Pico_mcd->s68k_regs[0x04+1] = 0x0a; |
| 740 | return (cdc.pt >> 8) & 0xff; |
| 741 | |
| 742 | case 0x0a: /* WAL */ |
| 743 | Pico_mcd->s68k_regs[0x04+1] = 0x0b; |
| 744 | return cdc.wa & 0xff; |
| 745 | |
| 746 | case 0x0b: /* WAH */ |
| 747 | Pico_mcd->s68k_regs[0x04+1] = 0x0c; |
| 748 | return (cdc.wa >> 8) & 0xff; |
| 749 | |
| 750 | case 0x0c: /* STAT0 */ |
| 751 | Pico_mcd->s68k_regs[0x04+1] = 0x0d; |
| 752 | return cdc.stat[0]; |
| 753 | |
| 754 | case 0x0d: /* STAT1 (always return 0) */ |
| 755 | Pico_mcd->s68k_regs[0x04+1] = 0x0e; |
| 756 | return 0x00; |
| 757 | |
| 758 | case 0x0e: /* STAT2 */ |
| 759 | Pico_mcd->s68k_regs[0x04+1] = 0x0f; |
| 760 | return cdc.stat[2]; |
| 761 | |
| 762 | case 0x0f: /* STAT3 */ |
| 763 | { |
| 764 | uint8 data = cdc.stat[3]; |
| 765 | |
| 766 | /* clear !VALST (note: this is not 100% correct but BIOS do not seem to care) */ |
| 767 | cdc.stat[3] = BIT_VALST; |
| 768 | |
| 769 | /* clear pending decoder interrupt */ |
| 770 | cdc.ifstat |= BIT_DECI; |
| 771 | |
| 772 | #if 0 |
| 773 | /* no pending data transfer end interrupt */ |
| 774 | if ((cdc.ifstat | BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN)) |
| 775 | { |
| 776 | /* clear pending level 5 interrupt */ |
| 777 | SekInterruptClearS68k(5); |
| 778 | } |
| 779 | #endif |
| 780 | |
| 781 | Pico_mcd->s68k_regs[0x04+1] = 0x00; |
| 782 | return data; |
| 783 | } |
| 784 | |
| 785 | default: /* by default, COMIN is always empty */ |
| 786 | return 0xff; |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | unsigned short cdc_host_r(void) |
| 791 | { |
| 792 | /* check if data is available */ |
| 793 | if (!(cdc.ifstat & BIT_DTEN)) |
| 794 | { |
| 795 | /* read data word from CDC RAM buffer */ |
| 796 | uint8 *datap = cdc.ram + (cdc.dac & 0x3ffe); |
| 797 | uint16 data = (datap[0] << 8) | datap[1]; |
| 798 | |
| 799 | #ifdef LOG_CDC |
| 800 | error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac, data, cdc.dbc, s68k.pc); |
| 801 | #endif |
| 802 | |
| 803 | /* increment data address counter */ |
| 804 | cdc.dac += 2; |
| 805 | |
| 806 | /* decrement data byte counter */ |
| 807 | cdc.dbc -= 2; |
| 808 | |
| 809 | /* end of transfer ? */ |
| 810 | if ((int16)cdc.dbc <= 0) |
| 811 | { |
| 812 | /* reset data byte counter (DBCH bits 4-7 should be set to 1) */ |
| 813 | cdc.dbc = 0xf000; |
| 814 | |
| 815 | /* clear !DTEN and !DTBSY */ |
| 816 | cdc.ifstat |= (BIT_DTBSY | BIT_DTEN); |
| 817 | |
| 818 | /* pending Data Transfer End interrupt */ |
| 819 | cdc.ifstat &= ~BIT_DTEI; |
| 820 | |
| 821 | /* Data Transfer End interrupt enabled ? */ |
| 822 | if (cdc.ifctrl & BIT_DTEIEN) |
| 823 | { |
| 824 | /* level 5 interrupt enabled ? */ |
| 825 | if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5) |
| 826 | { |
| 827 | /* update IRQ level */ |
| 828 | elprintf(EL_INTS, "cdc DTE irq 5"); |
| 829 | SekInterruptS68k(5); |
| 830 | } |
| 831 | } |
| 832 | |
| 833 | /* clear DSR bit & set EDT bit (SCD register $04) */ |
| 834 | Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80; |
| 835 | } |
| 836 | |
| 837 | return data; |
| 838 | } |
| 839 | |
| 840 | #ifdef LOG_CDC |
| 841 | error("error reading CDC host (data transfer disabled)\n"); |
| 842 | #endif |
| 843 | return 0xffff; |
| 844 | } |
| 845 | |
| 846 | // vim:shiftwidth=2:ts=2:expandtab |