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fix underalloc
[picodrive.git] / pico / memory.c
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1/*\r
2 * memory handling\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#include "pico_int.h"\r
11#include "memory.h"\r
12\r
13#include "sound/ym2612.h"\r
14#include "sound/sn76496.h"\r
15\r
16extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
17\r
18uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
19uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
20uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
21uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
22\r
23static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,\r
24 const void *func_or_mh, int is_func)\r
25{\r
26#ifdef __clang__\r
27 // workaround bug (segfault) in \r
28 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)\r
29 volatile \r
30#endif\r
31 uptr addr = (uptr)func_or_mh;\r
32 int mask = (1 << shift) - 1;\r
33 int i;\r
34\r
35 if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {\r
36 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",\r
37 start_addr, end_addr);\r
38 return;\r
39 }\r
40\r
41 if (addr & 1) {\r
42 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);\r
43 return;\r
44 }\r
45\r
46 if (!is_func)\r
47 addr -= start_addr;\r
48\r
49 for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r
50 map[i] = addr >> 1;\r
51 if (is_func)\r
52 map[i] |= MAP_FLAG;\r
53 }\r
54}\r
55\r
56void z80_map_set(uptr *map, int start_addr, int end_addr,\r
57 const void *func_or_mh, int is_func)\r
58{\r
59 xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
60}\r
61\r
62void cpu68k_map_set(uptr *map, int start_addr, int end_addr,\r
63 const void *func_or_mh, int is_func)\r
64{\r
65 xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
66#ifdef EMU_F68K\r
67 // setup FAME fetchmap\r
68 if (!is_func)\r
69 {\r
70 int shiftout = 24 - FAMEC_FETCHBITS;\r
71 int i = start_addr >> shiftout;\r
72 uptr base = (uptr)func_or_mh - (i << shiftout);\r
73 for (; i <= (end_addr >> shiftout); i++)\r
74 PicoCpuFM68k.Fetch[i] = base;\r
75 }\r
76#endif\r
77}\r
78\r
79// more specialized/optimized function (does same as above)\r
80void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)\r
81{\r
82 uptr *r8map, *r16map, *w8map, *w16map;\r
83 uptr addr = (uptr)ptr;\r
84 int shift = M68K_MEM_SHIFT;\r
85 int i;\r
86\r
87 if (!is_sub) {\r
88 r8map = m68k_read8_map;\r
89 r16map = m68k_read16_map;\r
90 w8map = m68k_write8_map;\r
91 w16map = m68k_write16_map;\r
92 } else {\r
93 r8map = s68k_read8_map;\r
94 r16map = s68k_read16_map;\r
95 w8map = s68k_write8_map;\r
96 w16map = s68k_write16_map;\r
97 }\r
98\r
99 addr -= start_addr;\r
100 addr >>= 1;\r
101 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
102 r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;\r
103#ifdef EMU_F68K\r
104 // setup FAME fetchmap\r
105 {\r
106 M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;\r
107 int shiftout = 24 - FAMEC_FETCHBITS;\r
108 i = start_addr >> shiftout;\r
109 addr = (uptr)ptr - (i << shiftout);\r
110 for (; i <= (end_addr >> shiftout); i++)\r
111 ctx->Fetch[i] = addr;\r
112 }\r
113#endif\r
114}\r
115\r
116static u32 m68k_unmapped_read8(u32 a)\r
117{\r
118 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);\r
119 return 0; // assume pulldown, as if MegaCD2 was attached\r
120}\r
121\r
122static u32 m68k_unmapped_read16(u32 a)\r
123{\r
124 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);\r
125 return 0;\r
126}\r
127\r
128static void m68k_unmapped_write8(u32 a, u32 d)\r
129{\r
130 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
131}\r
132\r
133static void m68k_unmapped_write16(u32 a, u32 d)\r
134{\r
135 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
136}\r
137\r
138void m68k_map_unmap(int start_addr, int end_addr)\r
139{\r
140#ifdef __clang__\r
141 // workaround bug (segfault) in \r
142 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)\r
143 volatile \r
144#endif\r
145 uptr addr;\r
146 int shift = M68K_MEM_SHIFT;\r
147 int i;\r
148\r
149 addr = (uptr)m68k_unmapped_read8;\r
150 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
151 m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;\r
152\r
153 addr = (uptr)m68k_unmapped_read16;\r
154 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
155 m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;\r
156\r
157 addr = (uptr)m68k_unmapped_write8;\r
158 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
159 m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;\r
160\r
161 addr = (uptr)m68k_unmapped_write16;\r
162 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
163 m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;\r
164}\r
165\r
166MAKE_68K_READ8(m68k_read8, m68k_read8_map)\r
167MAKE_68K_READ16(m68k_read16, m68k_read16_map)\r
168MAKE_68K_READ32(m68k_read32, m68k_read16_map)\r
169MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)\r
170MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)\r
171MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)\r
172\r
173// -----------------------------------------------------------------\r
174\r
175static u32 ym2612_read_local_68k(void);\r
176static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
177static void z80_mem_setup(void);\r
178\r
179#ifdef _ASM_MEMORY_C\r
180u32 PicoRead8_sram(u32 a);\r
181u32 PicoRead16_sram(u32 a);\r
182#endif\r
183\r
184#ifdef EMU_CORE_DEBUG\r
185u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
186int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
187extern unsigned int ppop;\r
188#endif\r
189\r
190#ifdef IO_STATS\r
191void log_io(unsigned int addr, int bits, int rw);\r
192#elif defined(_MSC_VER)\r
193#define log_io\r
194#else\r
195#define log_io(...)\r
196#endif\r
197\r
198#if defined(EMU_C68K)\r
199void cyclone_crashed(u32 pc, struct Cyclone *context)\r
200{\r
201 elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",\r
202 context == &PicoCpuCM68k ? 'm' : 's', pc);\r
203 context->membase = (u32)Pico.rom;\r
204 context->pc = (u32)Pico.rom + Pico.romsize;\r
205}\r
206#endif\r
207\r
208// -----------------------------------------------------------------\r
209// memmap helpers\r
210\r
211static u32 read_pad_3btn(int i, u32 out_bits)\r
212{\r
213 u32 pad = ~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
214 u32 value;\r
215\r
216 if (out_bits & 0x40) // TH\r
217 value = pad & 0x3f; // ?1CB RLDU\r
218 else\r
219 value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU\r
220\r
221 value |= out_bits & 0x40;\r
222 return value;\r
223}\r
224\r
225static u32 read_pad_6btn(int i, u32 out_bits)\r
226{\r
227 u32 pad = ~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
228 int phase = Pico.m.padTHPhase[i];\r
229 u32 value;\r
230\r
231 if (phase == 2 && !(out_bits & 0x40)) {\r
232 value = (pad & 0xc0) >> 2; // ?0SA 0000\r
233 goto out;\r
234 }\r
235 else if(phase == 3) {\r
236 if (out_bits & 0x40)\r
237 return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ\r
238 else\r
239 return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111\r
240 goto out;\r
241 }\r
242\r
243 if (out_bits & 0x40) // TH\r
244 value = pad & 0x3f; // ?1CB RLDU\r
245 else\r
246 value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU\r
247\r
248out:\r
249 value |= out_bits & 0x40;\r
250 return value;\r
251}\r
252\r
253static u32 read_nothing(int i, u32 out_bits)\r
254{\r
255 return 0xff;\r
256}\r
257\r
258typedef u32 (port_read_func)(int index, u32 out_bits);\r
259\r
260static port_read_func *port_readers[3] = {\r
261 read_pad_3btn,\r
262 read_pad_3btn,\r
263 read_nothing\r
264};\r
265\r
266static NOINLINE u32 port_read(int i)\r
267{\r
268 u32 data_reg = Pico.ioports[i + 1];\r
269 u32 ctrl_reg = Pico.ioports[i + 4] | 0x80;\r
270 u32 in, out;\r
271\r
272 out = data_reg & ctrl_reg;\r
273 out |= 0x7f & ~ctrl_reg; // pull-ups\r
274\r
275 in = port_readers[i](i, out);\r
276\r
277 return (in & ~ctrl_reg) | (data_reg & ctrl_reg);\r
278}\r
279\r
280void PicoSetInputDevice(int port, enum input_device device)\r
281{\r
282 port_read_func *func;\r
283\r
284 if (port < 0 || port > 2)\r
285 return;\r
286\r
287 switch (device) {\r
288 case PICO_INPUT_PAD_3BTN:\r
289 func = read_pad_3btn;\r
290 break;\r
291\r
292 case PICO_INPUT_PAD_6BTN:\r
293 func = read_pad_6btn;\r
294 break;\r
295\r
296 default:\r
297 func = read_nothing;\r
298 break;\r
299 }\r
300\r
301 port_readers[port] = func;\r
302}\r
303\r
304NOINLINE u32 io_ports_read(u32 a)\r
305{\r
306 u32 d;\r
307 a = (a>>1) & 0xf;\r
308 switch (a) {\r
309 case 0: d = Pico.m.hardware; break; // Hardware value (Version register)\r
310 case 1: d = port_read(0); break;\r
311 case 2: d = port_read(1); break;\r
312 case 3: d = port_read(2); break;\r
313 default: d = Pico.ioports[a]; break; // IO ports can be used as RAM\r
314 }\r
315 return d;\r
316}\r
317\r
318NOINLINE void io_ports_write(u32 a, u32 d)\r
319{\r
320 a = (a>>1) & 0xf;\r
321\r
322 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
323 if (1 <= a && a <= 2)\r
324 {\r
325 Pico.m.padDelay[a - 1] = 0;\r
326 if (!(Pico.ioports[a] & 0x40) && (d & 0x40))\r
327 Pico.m.padTHPhase[a - 1]++;\r
328 }\r
329\r
330 // certain IO ports can be used as RAM\r
331 Pico.ioports[a] = d;\r
332}\r
333\r
334// lame..\r
335static int z80_cycles_from_68k(void)\r
336{\r
337 return z80_cycle_aim\r
338 + cycles_68k_to_z80(SekCyclesDone() - last_z80_sync);\r
339}\r
340\r
341void NOINLINE ctl_write_z80busreq(u32 d)\r
342{\r
343 d&=1; d^=1;\r
344 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
345 if (d ^ Pico.m.z80Run)\r
346 {\r
347 if (d)\r
348 {\r
349 z80_cycle_cnt = z80_cycles_from_68k();\r
350 }\r
351 else\r
352 {\r
353 if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {\r
354 pprof_start(m68k);\r
355 PicoSyncZ80(SekCyclesDone());\r
356 pprof_end_sub(m68k);\r
357 }\r
358 }\r
359 Pico.m.z80Run = d;\r
360 }\r
361}\r
362\r
363void NOINLINE ctl_write_z80reset(u32 d)\r
364{\r
365 d&=1; d^=1;\r
366 elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
367 if (d ^ Pico.m.z80_reset)\r
368 {\r
369 if (d)\r
370 {\r
371 if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run) {\r
372 pprof_start(m68k);\r
373 PicoSyncZ80(SekCyclesDone());\r
374 pprof_end_sub(m68k);\r
375 }\r
376 YM2612ResetChip();\r
377 timers_reset();\r
378 }\r
379 else\r
380 {\r
381 z80_cycle_cnt = z80_cycles_from_68k();\r
382 z80_reset();\r
383 }\r
384 Pico.m.z80_reset = d;\r
385 }\r
386}\r
387\r
388static int get_scanline(int is_from_z80);\r
389\r
390static void psg_write_68k(u32 d)\r
391{\r
392 // look for volume write and update if needed\r
393 if ((d & 0x90) == 0x90 && PsndPsgLine < Pico.m.scanline)\r
394 PsndDoPSG(Pico.m.scanline);\r
395\r
396 SN76496Write(d);\r
397}\r
398\r
399static void psg_write_z80(u32 d)\r
400{\r
401 if ((d & 0x90) == 0x90) {\r
402 int scanline = get_scanline(1);\r
403 if (PsndPsgLine < scanline)\r
404 PsndDoPSG(scanline);\r
405 }\r
406\r
407 SN76496Write(d);\r
408}\r
409\r
410// -----------------------------------------------------------------\r
411\r
412#ifndef _ASM_MEMORY_C\r
413\r
414// cart (save) RAM area (usually 0x200000 - ...)\r
415static u32 PicoRead8_sram(u32 a)\r
416{\r
417 u32 d;\r
418 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
419 {\r
420 if (SRam.flags & SRF_EEPROM) {\r
421 d = EEPROM_read();\r
422 if (!(a & 1))\r
423 d >>= 8;\r
424 } else\r
425 d = *(u8 *)(SRam.data - SRam.start + a);\r
426 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
427 return d;\r
428 }\r
429\r
430 // XXX: this is banking unfriendly\r
431 if (a < Pico.romsize)\r
432 return Pico.rom[a ^ 1];\r
433 \r
434 return m68k_unmapped_read8(a);\r
435}\r
436\r
437static u32 PicoRead16_sram(u32 a)\r
438{\r
439 u32 d;\r
440 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
441 {\r
442 if (SRam.flags & SRF_EEPROM)\r
443 d = EEPROM_read();\r
444 else {\r
445 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
446 d = pm[0] << 8;\r
447 d |= pm[1];\r
448 }\r
449 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
450 return d;\r
451 }\r
452\r
453 if (a < Pico.romsize)\r
454 return *(u16 *)(Pico.rom + a);\r
455\r
456 return m68k_unmapped_read16(a);\r
457}\r
458\r
459#endif // _ASM_MEMORY_C\r
460\r
461static void PicoWrite8_sram(u32 a, u32 d)\r
462{\r
463 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
464 m68k_unmapped_write8(a, d);\r
465 return;\r
466 }\r
467\r
468 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);\r
469 if (SRam.flags & SRF_EEPROM)\r
470 {\r
471 EEPROM_write8(a, d);\r
472 }\r
473 else {\r
474 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
475 if (*pm != (u8)d) {\r
476 SRam.changed = 1;\r
477 *pm = (u8)d;\r
478 }\r
479 }\r
480}\r
481\r
482static void PicoWrite16_sram(u32 a, u32 d)\r
483{\r
484 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
485 m68k_unmapped_write16(a, d);\r
486 return;\r
487 }\r
488\r
489 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);\r
490 if (SRam.flags & SRF_EEPROM)\r
491 {\r
492 EEPROM_write16(d);\r
493 }\r
494 else {\r
495 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
496 if (pm[0] != (u8)(d >> 8)) {\r
497 SRam.changed = 1;\r
498 pm[0] = (u8)(d >> 8);\r
499 }\r
500 if (pm[1] != (u8)d) {\r
501 SRam.changed = 1;\r
502 pm[1] = (u8)d;\r
503 }\r
504 }\r
505}\r
506\r
507// z80 area (0xa00000 - 0xa0ffff)\r
508// TODO: verify mirrors VDP and bank reg (bank area mirroring verified)\r
509static u32 PicoRead8_z80(u32 a)\r
510{\r
511 u32 d = 0xff;\r
512 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
513 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);\r
514 // open bus. Pulled down if MegaCD2 is attached.\r
515 return 0;\r
516 }\r
517\r
518 if ((a & 0x4000) == 0x0000)\r
519 d = Pico.zram[a & 0x1fff];\r
520 else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r
521 d = ym2612_read_local_68k(); \r
522 else\r
523 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
524 return d;\r
525}\r
526\r
527static u32 PicoRead16_z80(u32 a)\r
528{\r
529 u32 d = PicoRead8_z80(a);\r
530 return d | (d << 8);\r
531}\r
532\r
533static void PicoWrite8_z80(u32 a, u32 d)\r
534{\r
535 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
536 // verified on real hw\r
537 elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
538 return;\r
539 }\r
540\r
541 if ((a & 0x4000) == 0x0000) { // z80 RAM\r
542 SekCyclesBurnRun(2); // FIXME hack\r
543 Pico.zram[a & 0x1fff] = (u8)d;\r
544 return;\r
545 }\r
546 if ((a & 0x6000) == 0x4000) { // FM Sound\r
547 if (PicoOpt & POPT_EN_FM)\r
548 emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;\r
549 return;\r
550 }\r
551 // TODO: probably other VDP access too? Maybe more mirrors?\r
552 if ((a & 0x7ff9) == 0x7f11) { // PSG Sound\r
553 psg_write_68k(d);\r
554 return;\r
555 }\r
556 if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
557 {\r
558 Pico.m.z80_bank68k >>= 1;\r
559 Pico.m.z80_bank68k |= d << 8;\r
560 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
561 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
562 return;\r
563 }\r
564 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
565}\r
566\r
567static void PicoWrite16_z80(u32 a, u32 d)\r
568{\r
569 // for RAM, only most significant byte is sent\r
570 // TODO: verify remaining accesses\r
571 PicoWrite8_z80(a, d >> 8);\r
572}\r
573\r
574#ifndef _ASM_MEMORY_C\r
575\r
576// IO/control area (0xa10000 - 0xa1ffff)\r
577u32 PicoRead8_io(u32 a)\r
578{\r
579 u32 d;\r
580\r
581 if ((a & 0xffe0) == 0x0000) { // I/O ports\r
582 d = io_ports_read(a);\r
583 goto end;\r
584 }\r
585\r
586 // faking open bus (MegaCD pulldowns don't work here curiously)\r
587 d = Pico.m.rotate++;\r
588 d ^= d << 6;\r
589\r
590 if ((a & 0xfc00) == 0x1000) {\r
591 // bit8 seems to be readable in this range\r
592 if (!(a & 1))\r
593 d &= ~0x01;\r
594\r
595 if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
596 d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
597 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
598 }\r
599 goto end;\r
600 }\r
601\r
602 if (PicoOpt & POPT_EN_32X) {\r
603 d = PicoRead8_32x(a);\r
604 goto end;\r
605 }\r
606\r
607 d = m68k_unmapped_read8(a);\r
608end:\r
609 return d;\r
610}\r
611\r
612u32 PicoRead16_io(u32 a)\r
613{\r
614 u32 d;\r
615\r
616 if ((a & 0xffe0) == 0x0000) { // I/O ports\r
617 d = io_ports_read(a);\r
618 d |= d << 8;\r
619 goto end;\r
620 }\r
621\r
622 // faking open bus\r
623 d = (Pico.m.rotate += 0x41);\r
624 d ^= (d << 5) ^ (d << 8);\r
625\r
626 // bit8 seems to be readable in this range\r
627 if ((a & 0xfc00) == 0x1000) {\r
628 d &= ~0x0100;\r
629\r
630 if ((a & 0xff00) == 0x1100) { // z80 busreq\r
631 d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
632 elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
633 }\r
634 goto end;\r
635 }\r
636\r
637 if (PicoOpt & POPT_EN_32X) {\r
638 d = PicoRead16_32x(a);\r
639 goto end;\r
640 }\r
641\r
642 d = m68k_unmapped_read16(a);\r
643end:\r
644 return d;\r
645}\r
646\r
647void PicoWrite8_io(u32 a, u32 d)\r
648{\r
649 if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)\r
650 io_ports_write(a, d);\r
651 return;\r
652 }\r
653 if ((a & 0xff01) == 0x1100) { // z80 busreq\r
654 ctl_write_z80busreq(d);\r
655 return;\r
656 }\r
657 if ((a & 0xff01) == 0x1200) { // z80 reset\r
658 ctl_write_z80reset(d);\r
659 return;\r
660 }\r
661 if (a == 0xa130f1) { // sram access register\r
662 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
663 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
664 Pico.m.sram_reg |= (u8)(d & 3);\r
665 return;\r
666 }\r
667 if (PicoOpt & POPT_EN_32X) {\r
668 PicoWrite8_32x(a, d);\r
669 return;\r
670 }\r
671\r
672 m68k_unmapped_write8(a, d);\r
673}\r
674\r
675void PicoWrite16_io(u32 a, u32 d)\r
676{\r
677 if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)\r
678 io_ports_write(a, d);\r
679 return;\r
680 }\r
681 if ((a & 0xff00) == 0x1100) { // z80 busreq\r
682 ctl_write_z80busreq(d >> 8);\r
683 return;\r
684 }\r
685 if ((a & 0xff00) == 0x1200) { // z80 reset\r
686 ctl_write_z80reset(d >> 8);\r
687 return;\r
688 }\r
689 if (a == 0xa130f0) { // sram access register\r
690 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
691 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
692 Pico.m.sram_reg |= (u8)(d & 3);\r
693 return;\r
694 }\r
695 if (PicoOpt & POPT_EN_32X) {\r
696 PicoWrite16_32x(a, d);\r
697 return;\r
698 }\r
699 m68k_unmapped_write16(a, d);\r
700}\r
701\r
702#endif // _ASM_MEMORY_C\r
703\r
704// VDP area (0xc00000 - 0xdfffff)\r
705// TODO: verify if lower byte goes to PSG on word writes\r
706u32 PicoRead8_vdp(u32 a)\r
707{\r
708 if ((a & 0x00f0) == 0x0000) {\r
709 switch (a & 0x0d)\r
710 {\r
711 case 0x00: return PicoVideoRead8DataH();\r
712 case 0x01: return PicoVideoRead8DataL();\r
713 case 0x04: return PicoVideoRead8CtlH();\r
714 case 0x05: return PicoVideoRead8CtlL();\r
715 case 0x08:\r
716 case 0x0c: return PicoVideoRead8HV_H();\r
717 case 0x09:\r
718 case 0x0d: return PicoVideoRead8HV_L();\r
719 }\r
720 }\r
721\r
722 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
723 return 0;\r
724}\r
725\r
726static u32 PicoRead16_vdp(u32 a)\r
727{\r
728 if ((a & 0x00e0) == 0x0000)\r
729 return PicoVideoRead(a);\r
730\r
731 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
732 return 0;\r
733}\r
734\r
735static void PicoWrite8_vdp(u32 a, u32 d)\r
736{\r
737 if ((a & 0x00f9) == 0x0011) { // PSG Sound\r
738 psg_write_68k(d);\r
739 return;\r
740 }\r
741 if ((a & 0x00e0) == 0x0000) {\r
742 d &= 0xff;\r
743 PicoVideoWrite(a, d | (d << 8));\r
744 return;\r
745 }\r
746\r
747 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
748}\r
749\r
750static void PicoWrite16_vdp(u32 a, u32 d)\r
751{\r
752 if ((a & 0x00f9) == 0x0010) // PSG Sound\r
753 psg_write_68k(d);\r
754 if ((a & 0x00e0) == 0x0000) {\r
755 PicoVideoWrite(a, d);\r
756 return;\r
757 }\r
758\r
759 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
760}\r
761\r
762// -----------------------------------------------------------------\r
763\r
764#ifdef EMU_M68K\r
765static void m68k_mem_setup(void);\r
766#endif\r
767\r
768PICO_INTERNAL void PicoMemSetup(void)\r
769{\r
770 int mask, rs, a;\r
771\r
772 // setup the memory map\r
773 cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);\r
774 cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);\r
775 cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);\r
776 cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);\r
777\r
778 // ROM\r
779 // align to bank size. We know ROM loader allocated enough for this\r
780 mask = (1 << M68K_MEM_SHIFT) - 1;\r
781 rs = (Pico.romsize + mask) & ~mask;\r
782 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);\r
783 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r
784\r
785 // Common case of on-cart (save) RAM, usually at 0x200000-...\r
786 if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {\r
787 rs = SRam.end - SRam.start;\r
788 rs = (rs + mask) & ~mask;\r
789 if (SRam.start + rs >= 0x1000000)\r
790 rs = 0x1000000 - SRam.start;\r
791 cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);\r
792 cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);\r
793 cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);\r
794 cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);\r
795 }\r
796\r
797 // Z80 region\r
798 cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);\r
799 cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);\r
800 cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);\r
801 cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);\r
802\r
803 // IO/control region\r
804 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);\r
805 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);\r
806 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);\r
807 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);\r
808\r
809 // VDP region\r
810 for (a = 0xc00000; a < 0xe00000; a += 0x010000) {\r
811 if ((a & 0xe700e0) != 0xc00000)\r
812 continue;\r
813 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);\r
814 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);\r
815 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);\r
816 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);\r
817 }\r
818\r
819 // RAM and it's mirrors\r
820 for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r
821 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);\r
822 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);\r
823 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);\r
824 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);\r
825 }\r
826\r
827 // Setup memory callbacks:\r
828#ifdef EMU_C68K\r
829 PicoCpuCM68k.read8 = (void *)m68k_read8_map;\r
830 PicoCpuCM68k.read16 = (void *)m68k_read16_map;\r
831 PicoCpuCM68k.read32 = (void *)m68k_read16_map;\r
832 PicoCpuCM68k.write8 = (void *)m68k_write8_map;\r
833 PicoCpuCM68k.write16 = (void *)m68k_write16_map;\r
834 PicoCpuCM68k.write32 = (void *)m68k_write16_map;\r
835 PicoCpuCM68k.checkpc = NULL; /* unused */\r
836 PicoCpuCM68k.fetch8 = NULL;\r
837 PicoCpuCM68k.fetch16 = NULL;\r
838 PicoCpuCM68k.fetch32 = NULL;\r
839#endif\r
840#ifdef EMU_F68K\r
841 PicoCpuFM68k.read_byte = m68k_read8;\r
842 PicoCpuFM68k.read_word = m68k_read16;\r
843 PicoCpuFM68k.read_long = m68k_read32;\r
844 PicoCpuFM68k.write_byte = m68k_write8;\r
845 PicoCpuFM68k.write_word = m68k_write16;\r
846 PicoCpuFM68k.write_long = m68k_write32;\r
847\r
848 // setup FAME fetchmap\r
849 {\r
850 int i;\r
851 // by default, point everything to first 64k of ROM\r
852 for (i = 0; i < M68K_FETCHBANK1 * 0xe0 / 0x100; i++)\r
853 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
854 // now real ROM\r
855 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
856 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;\r
857 // RAM already set\r
858 }\r
859#endif\r
860#ifdef EMU_M68K\r
861 m68k_mem_setup();\r
862#endif\r
863\r
864 z80_mem_setup();\r
865}\r
866\r
867#ifdef EMU_M68K\r
868unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;\r
869unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;\r
870unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;\r
871void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;\r
872void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;\r
873void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;\r
874\r
875/* it appears that Musashi doesn't always mask the unused bits */\r
876unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }\r
877unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }\r
878unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }\r
879void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }\r
880void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }\r
881void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }\r
882\r
883static void m68k_mem_setup(void)\r
884{\r
885 pm68k_read_memory_8 = m68k_read8;\r
886 pm68k_read_memory_16 = m68k_read16;\r
887 pm68k_read_memory_32 = m68k_read32;\r
888 pm68k_write_memory_8 = m68k_write8;\r
889 pm68k_write_memory_16 = m68k_write16;\r
890 pm68k_write_memory_32 = m68k_write32;\r
891}\r
892#endif // EMU_M68K\r
893\r
894\r
895// -----------------------------------------------------------------\r
896\r
897static int get_scanline(int is_from_z80)\r
898{\r
899 if (is_from_z80) {\r
900 int cycles = z80_cyclesDone();\r
901 while (cycles - z80_scanline_cycles >= 228)\r
902 z80_scanline++, z80_scanline_cycles += 228;\r
903 return z80_scanline;\r
904 }\r
905\r
906 return Pico.m.scanline;\r
907}\r
908\r
909/* probably should not be in this file, but it's near related code here */\r
910void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)\r
911{\r
912 int xcycles = z80_cycles << 8;\r
913\r
914 /* check for overflows */\r
915 if ((mode_old & 4) && xcycles > timer_a_next_oflow)\r
916 ym2612.OPN.ST.status |= 1;\r
917\r
918 if ((mode_old & 8) && xcycles > timer_b_next_oflow)\r
919 ym2612.OPN.ST.status |= 2;\r
920\r
921 /* update timer a */\r
922 if (mode_old & 1)\r
923 while (xcycles > timer_a_next_oflow)\r
924 timer_a_next_oflow += timer_a_step;\r
925\r
926 if ((mode_old ^ mode_new) & 1) // turning on/off\r
927 {\r
928 if (mode_old & 1)\r
929 timer_a_next_oflow = TIMER_NO_OFLOW;\r
930 else\r
931 timer_a_next_oflow = xcycles + timer_a_step;\r
932 }\r
933 if (mode_new & 1)\r
934 elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);\r
935\r
936 /* update timer b */\r
937 if (mode_old & 2)\r
938 while (xcycles > timer_b_next_oflow)\r
939 timer_b_next_oflow += timer_b_step;\r
940\r
941 if ((mode_old ^ mode_new) & 2)\r
942 {\r
943 if (mode_old & 2)\r
944 timer_b_next_oflow = TIMER_NO_OFLOW;\r
945 else\r
946 timer_b_next_oflow = xcycles + timer_b_step;\r
947 }\r
948 if (mode_new & 2)\r
949 elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);\r
950}\r
951\r
952// ym2612 DAC and timer I/O handlers for z80\r
953static int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
954{\r
955 int addr;\r
956\r
957 a &= 3;\r
958 if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */\r
959 {\r
960 int scanline = get_scanline(is_from_z80);\r
961 //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);\r
962 ym2612.dacout = ((int)d - 0x80) << 6;\r
963 if (ym2612.dacen)\r
964 PsndDoDAC(scanline);\r
965 return 0;\r
966 }\r
967\r
968 switch (a)\r
969 {\r
970 case 0: /* address port 0 */\r
971 ym2612.OPN.ST.address = d;\r
972 ym2612.addr_A1 = 0;\r
973#ifdef __GP2X__\r
974 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
975#endif\r
976 return 0;\r
977\r
978 case 1: /* data port 0 */\r
979 if (ym2612.addr_A1 != 0)\r
980 return 0;\r
981\r
982 addr = ym2612.OPN.ST.address;\r
983 ym2612.REGS[addr] = d;\r
984\r
985 switch (addr)\r
986 {\r
987 case 0x24: // timer A High 8\r
988 case 0x25: { // timer A Low 2\r
989 int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))\r
990 : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));\r
991 if (ym2612.OPN.ST.TA != TAnew)\r
992 {\r
993 //elprintf(EL_STATUS, "timer a set %i", TAnew);\r
994 ym2612.OPN.ST.TA = TAnew;\r
995 //ym2612.OPN.ST.TAC = (1024-TAnew)*18;\r
996 //ym2612.OPN.ST.TAT = 0;\r
997 timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r
998 if (ym2612.OPN.ST.mode & 1) {\r
999 // this is not right, should really be done on overflow only\r
1000 int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
1001 timer_a_next_oflow = (cycles << 8) + timer_a_step;\r
1002 }\r
1003 elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);\r
1004 }\r
1005 return 0;\r
1006 }\r
1007 case 0x26: // timer B\r
1008 if (ym2612.OPN.ST.TB != d) {\r
1009 //elprintf(EL_STATUS, "timer b set %i", d);\r
1010 ym2612.OPN.ST.TB = d;\r
1011 //ym2612.OPN.ST.TBC = (256-d) * 288;\r
1012 //ym2612.OPN.ST.TBT = 0;\r
1013 timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800\r
1014 if (ym2612.OPN.ST.mode & 2) {\r
1015 int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
1016 timer_b_next_oflow = (cycles << 8) + timer_b_step;\r
1017 }\r
1018 elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);\r
1019 }\r
1020 return 0;\r
1021 case 0x27: { /* mode, timer control */\r
1022 int old_mode = ym2612.OPN.ST.mode;\r
1023 int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
1024 ym2612.OPN.ST.mode = d;\r
1025\r
1026 elprintf(EL_YMTIMER, "st mode %02x", d);\r
1027 ym2612_sync_timers(cycles, old_mode, d);\r
1028\r
1029 /* reset Timer a flag */\r
1030 if (d & 0x10)\r
1031 ym2612.OPN.ST.status &= ~1;\r
1032\r
1033 /* reset Timer b flag */\r
1034 if (d & 0x20)\r
1035 ym2612.OPN.ST.status &= ~2;\r
1036\r
1037 if ((d ^ old_mode) & 0xc0) {\r
1038#ifdef __GP2X__\r
1039 if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
1040#endif\r
1041 return 1;\r
1042 }\r
1043 return 0;\r
1044 }\r
1045 case 0x2b: { /* DAC Sel (YM2612) */\r
1046 int scanline = get_scanline(is_from_z80);\r
1047 if (ym2612.dacen != (d & 0x80)) {\r
1048 ym2612.dacen = d & 0x80;\r
1049 PsndDacLine = scanline;\r
1050 }\r
1051#ifdef __GP2X__\r
1052 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);\r
1053#endif\r
1054 return 0;\r
1055 }\r
1056 }\r
1057 break;\r
1058\r
1059 case 2: /* address port 1 */\r
1060 ym2612.OPN.ST.address = d;\r
1061 ym2612.addr_A1 = 1;\r
1062#ifdef __GP2X__\r
1063 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
1064#endif\r
1065 return 0;\r
1066\r
1067 case 3: /* data port 1 */\r
1068 if (ym2612.addr_A1 != 1)\r
1069 return 0;\r
1070\r
1071 addr = ym2612.OPN.ST.address | 0x100;\r
1072 ym2612.REGS[addr] = d;\r
1073 break;\r
1074 }\r
1075\r
1076#ifdef __GP2X__\r
1077 if (PicoOpt & POPT_EXT_FM)\r
1078 return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
1079#endif\r
1080 return YM2612Write_(a, d);\r
1081}\r
1082\r
1083\r
1084#define ym2612_read_local() \\r
1085 if (xcycles >= timer_a_next_oflow) \\r
1086 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \\r
1087 if (xcycles >= timer_b_next_oflow) \\r
1088 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r
1089\r
1090static u32 ym2612_read_local_z80(void)\r
1091{\r
1092 int xcycles = z80_cyclesDone() << 8;\r
1093\r
1094 ym2612_read_local();\r
1095\r
1096 elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
1097 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
1098 return ym2612.OPN.ST.status;\r
1099}\r
1100\r
1101static u32 ym2612_read_local_68k(void)\r
1102{\r
1103 int xcycles = z80_cycles_from_68k() << 8;\r
1104\r
1105 ym2612_read_local();\r
1106\r
1107 elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
1108 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
1109 return ym2612.OPN.ST.status;\r
1110}\r
1111\r
1112void ym2612_pack_state(void)\r
1113{\r
1114 // timers are saved as tick counts, in 16.16 int format\r
1115 int tac, tat = 0, tbc, tbt = 0;\r
1116 tac = 1024 - ym2612.OPN.ST.TA;\r
1117 tbc = 256 - ym2612.OPN.ST.TB;\r
1118 if (timer_a_next_oflow != TIMER_NO_OFLOW)\r
1119 tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);\r
1120 if (timer_b_next_oflow != TIMER_NO_OFLOW)\r
1121 tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);\r
1122 elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);\r
1123 elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);\r
1124\r
1125#ifdef __GP2X__\r
1126 if (PicoOpt & POPT_EXT_FM)\r
1127 YM2612PicoStateSave2_940(tat, tbt);\r
1128 else\r
1129#endif\r
1130 YM2612PicoStateSave2(tat, tbt);\r
1131}\r
1132\r
1133void ym2612_unpack_state(void)\r
1134{\r
1135 int i, ret, tac, tat, tbc, tbt;\r
1136 YM2612PicoStateLoad();\r
1137\r
1138 // feed all the registers and update internal state\r
1139 for (i = 0x20; i < 0xA0; i++) {\r
1140 ym2612_write_local(0, i, 0);\r
1141 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1142 }\r
1143 for (i = 0x30; i < 0xA0; i++) {\r
1144 ym2612_write_local(2, i, 0);\r
1145 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1146 }\r
1147 for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards\r
1148 ym2612_write_local(2, i, 0);\r
1149 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1150 ym2612_write_local(0, i, 0);\r
1151 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1152 }\r
1153 for (i = 0xB0; i < 0xB8; i++) {\r
1154 ym2612_write_local(0, i, 0);\r
1155 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1156 ym2612_write_local(2, i, 0);\r
1157 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1158 }\r
1159\r
1160#ifdef __GP2X__\r
1161 if (PicoOpt & POPT_EXT_FM)\r
1162 ret = YM2612PicoStateLoad2_940(&tat, &tbt);\r
1163 else\r
1164#endif\r
1165 ret = YM2612PicoStateLoad2(&tat, &tbt);\r
1166 if (ret != 0) {\r
1167 elprintf(EL_STATUS, "old ym2612 state");\r
1168 return; // no saved timers\r
1169 }\r
1170\r
1171 tac = (1024 - ym2612.OPN.ST.TA) << 16;\r
1172 tbc = (256 - ym2612.OPN.ST.TB) << 16;\r
1173 if (ym2612.OPN.ST.mode & 1)\r
1174 timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);\r
1175 else\r
1176 timer_a_next_oflow = TIMER_NO_OFLOW;\r
1177 if (ym2612.OPN.ST.mode & 2)\r
1178 timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);\r
1179 else\r
1180 timer_b_next_oflow = TIMER_NO_OFLOW;\r
1181 elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);\r
1182 elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);\r
1183}\r
1184\r
1185#if defined(NO_32X) && defined(_ASM_MEMORY_C)\r
1186// referenced by asm code\r
1187u32 PicoRead8_32x(u32 a) { return 0; }\r
1188u32 PicoRead16_32x(u32 a) { return 0; }\r
1189void PicoWrite8_32x(u32 a, u32 d) {}\r
1190void PicoWrite16_32x(u32 a, u32 d) {}\r
1191#endif\r
1192\r
1193// -----------------------------------------------------------------\r
1194// z80 memhandlers\r
1195\r
1196static unsigned char z80_md_vdp_read(unsigned short a)\r
1197{\r
1198 z80_subCLeft(2);\r
1199\r
1200 if ((a & 0x00f0) == 0x0000) {\r
1201 switch (a & 0x0d)\r
1202 {\r
1203 case 0x00: return PicoVideoRead8DataH();\r
1204 case 0x01: return PicoVideoRead8DataL();\r
1205 case 0x04: return PicoVideoRead8CtlH();\r
1206 case 0x05: return PicoVideoRead8CtlL();\r
1207 case 0x08:\r
1208 case 0x0c: return get_scanline(1); // FIXME: make it proper\r
1209 case 0x09:\r
1210 case 0x0d: return Pico.m.rotate++;\r
1211 }\r
1212 }\r
1213\r
1214 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r
1215 return 0xff;\r
1216}\r
1217\r
1218static unsigned char z80_md_bank_read(unsigned short a)\r
1219{\r
1220 unsigned int addr68k;\r
1221 unsigned char ret;\r
1222\r
1223 z80_subCLeft(3);\r
1224\r
1225 addr68k = Pico.m.z80_bank68k << 15;\r
1226 addr68k |= a & 0x7fff;\r
1227\r
1228 ret = m68k_read8(addr68k);\r
1229\r
1230 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
1231 return ret;\r
1232}\r
1233\r
1234static void z80_md_ym2612_write(unsigned int a, unsigned char data)\r
1235{\r
1236 if (PicoOpt & POPT_EN_FM)\r
1237 emustatus |= ym2612_write_local(a, data, 1) & 1;\r
1238}\r
1239\r
1240static void z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
1241{\r
1242 if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r
1243 {\r
1244 psg_write_z80(data);\r
1245 return;\r
1246 }\r
1247 // at least VDP data writes hang my machine\r
1248\r
1249 if ((a>>8) == 0x60)\r
1250 {\r
1251 Pico.m.z80_bank68k >>= 1;\r
1252 Pico.m.z80_bank68k |= data << 8;\r
1253 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
1254 return;\r
1255 }\r
1256\r
1257 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
1258}\r
1259\r
1260static void z80_md_bank_write(unsigned int a, unsigned char data)\r
1261{\r
1262 unsigned int addr68k;\r
1263\r
1264 addr68k = Pico.m.z80_bank68k << 15;\r
1265 addr68k += a & 0x7fff;\r
1266\r
1267 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
1268 m68k_write8(addr68k, data);\r
1269}\r
1270\r
1271// -----------------------------------------------------------------\r
1272\r
1273static unsigned char z80_md_in(unsigned short p)\r
1274{\r
1275 elprintf(EL_ANOMALY, "Z80 port %04x read", p);\r
1276 return 0xff;\r
1277}\r
1278\r
1279static void z80_md_out(unsigned short p, unsigned char d)\r
1280{\r
1281 elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r
1282}\r
1283\r
1284static void z80_mem_setup(void)\r
1285{\r
1286 z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r
1287 z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r
1288 z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r
1289 z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r
1290 z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r
1291\r
1292 z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);\r
1293 z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);\r
1294 z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r
1295 z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r
1296 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r
1297\r
1298#ifdef _USE_DRZ80\r
1299 drZ80.z80_in = z80_md_in;\r
1300 drZ80.z80_out = z80_md_out;\r
1301#endif\r
1302#ifdef _USE_CZ80\r
1303 Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM\r
1304 Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror\r
1305 Cz80_Set_INPort(&CZ80, z80_md_in);\r
1306 Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
1307#endif\r
1308}\r
1309\r
1310// vim:shiftwidth=2:ts=2:expandtab\r
fast MegaDrive/MegaCD/32X emulator