based on hw tests busreq is affected by reset. Remove old hack too

[picodrive.git] / pico / memory.c

// This is part of Pico Library\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
// (c) Copyright 2006,2007 notaz, All rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
\r
#include "pico_int.h"\r
\r
#include "sound/ym2612.h"\r
#include "sound/sn76496.h"\r
\r
#ifndef UTYPES_DEFINED\r
typedef unsigned char  u8;\r
typedef unsigned short u16;\r
typedef unsigned int   u32;\r
#define UTYPES_DEFINED\r
#endif\r
\r
extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
\r
#ifdef _ASM_MEMORY_C\r
u32  PicoRead8(u32 a);\r
u32  PicoRead16(u32 a);\r
void PicoWrite8(u32 a,u8 d);\r
void PicoWriteRomHW_SSF2(u32 a,u32 d);\r
#endif\r
\r
\r
#ifdef EMU_CORE_DEBUG\r
u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
extern unsigned int ppop;\r
#endif\r
\r
#ifdef IO_STATS\r
void log_io(unsigned int addr, int bits, int rw);\r
#elif defined(_MSC_VER)\r
#define log_io\r
#else\r
#define log_io(...)\r
#endif\r
\r
#if defined(EMU_C68K)\r
static __inline int PicoMemBase(u32 pc)\r
{\r
  int membase=0;\r
\r
  if (pc<Pico.romsize+4)\r
  {\r
    membase=(int)Pico.rom; // Program Counter in Rom\r
  }\r
  else if ((pc&0xe00000)==0xe00000)\r
  {\r
    membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram\r
  }\r
  else\r
  {\r
    // Error - Program Counter is invalid\r
    membase=(int)Pico.rom;\r
  }\r
\r
  return membase;\r
}\r
#endif\r
\r
\r
PICO_INTERNAL u32 PicoCheckPc(u32 pc)\r
{\r
  u32 ret=0;\r
#if defined(EMU_C68K)\r
  pc-=PicoCpuCM68k.membase; // Get real pc\r
//  pc&=0xfffffe;\r
  pc&=~1;\r
  if ((pc<<8) == 0)\r
  {\r
    elprintf(EL_STATUS|EL_ANOMALY, "%i:%03i: game crash detected @ %06x\n",\r
      Pico.m.frame_count, Pico.m.scanline, SekPc);\r
    return (int)Pico.rom + Pico.romsize; // common crash condition, may happen with bad ROMs\r
  }\r
\r
  PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff);\r
  PicoCpuCM68k.membase-=pc&0xff000000;\r
\r
  ret = PicoCpuCM68k.membase+pc;\r
#endif\r
  return ret;\r
}\r
\r
\r
PICO_INTERNAL void PicoInitPc(u32 pc)\r
{\r
  PicoCheckPc(pc);\r
}\r
\r
#ifndef _ASM_MEMORY_C\r
PICO_INTERNAL_ASM void PicoMemReset(void)\r
{\r
}\r
#endif\r
\r
// -----------------------------------------------------------------\r
\r
int PadRead(int i)\r
{\r
  int pad,value,data_reg;\r
  pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
  data_reg=Pico.ioports[i+1];\r
\r
  // orr the bits, which are set as output\r
  value = data_reg&(Pico.ioports[i+4]|0x80);\r
\r
  if (PicoOpt & POPT_6BTN_PAD)\r
  {\r
    int phase = Pico.m.padTHPhase[i];\r
\r
    if(phase == 2 && !(data_reg&0x40)) { // TH\r
      value|=(pad&0xc0)>>2;              // ?0SA 0000\r
      return value;\r
    } else if(phase == 3) {\r
      if(data_reg&0x40)\r
        value|=(pad&0x30)|((pad>>8)&0xf);  // ?1CB MXYZ\r
      else\r
        value|=((pad&0xc0)>>2)|0x0f;       // ?0SA 1111\r
      return value;\r
    }\r
  }\r
\r
  if(data_reg&0x40) // TH\r
       value|=(pad&0x3f);              // ?1CB RLDU\r
  else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
\r
  return value; // will mirror later\r
}\r
\r
\r
#ifndef _ASM_MEMORY_C\r
static\r
#endif\r
u32 SRAMRead(u32 a)\r
{\r
  unsigned int sreg = Pico.m.sram_reg;\r
  if (!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
    elprintf(EL_SRAMIO, "normal sram detected.");\r
    Pico.m.sram_reg|=0x10; // should be normal SRAM\r
  }\r
  if (sreg & 4) // EEPROM read\r
    return SRAMReadEEPROM();\r
  else // if(sreg & 1) // (sreg&5) is one of prerequisites\r
    return *(u8 *)(SRam.data-SRam.start+a);\r
}\r
\r
#ifndef _ASM_MEMORY_C\r
static\r
#endif\r
u32 SRAMRead16(u32 a)\r
{\r
  u32 d;\r
  if (Pico.m.sram_reg & 4) {\r
    d = SRAMReadEEPROM();\r
    d |= d << 8;\r
  } else {\r
    u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
    d =*pm++ << 8;\r
    d|=*pm++;\r
  }\r
  return d;\r
}\r
\r
static void SRAMWrite(u32 a, u32 d)\r
{\r
  unsigned int sreg = Pico.m.sram_reg;\r
  if(!(sreg & 0x10)) {\r
    // not detected SRAM\r
    if((a&~1)==0x200000) {\r
      elprintf(EL_SRAMIO, "eeprom detected.");\r
      sreg|=4; // this should be a game with EEPROM (like NBA Jam)\r
      SRam.start=0x200000; SRam.end=SRam.start+1;\r
    } else\r
      elprintf(EL_SRAMIO, "normal sram detected.");\r
    sreg|=0x10;\r
    Pico.m.sram_reg=sreg;\r
  }\r
  if(sreg & 4) { // EEPROM write\r
    // this diff must be at most 16 for NBA Jam to work\r
    if(SekCyclesDoneT()-lastSSRamWrite < 16) {\r
      // just update pending state\r
      elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite);\r
      SRAMUpdPending(a, d);\r
    } else {\r
      int old=sreg;\r
      SRAMWriteEEPROM(sreg>>6); // execute pending\r
      SRAMUpdPending(a, d);\r
      if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed\r
        lastSSRamWrite = SekCyclesDoneT();\r
    }\r
  } else if(!(sreg & 2)) {\r
    u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
    if(*pm != (u8)d) {\r
      SRam.changed = 1;\r
      *pm=(u8)d;\r
    }\r
  }\r
}\r
\r
// for nonstandard reads\r
static u32 OtherRead16End(u32 a, int realsize)\r
{\r
  u32 d=0;\r
\r
  // 32x test\r
/*\r
  if      (a == 0xa130ec) { d = 0x4d41; goto end; } // MA\r
  else if (a == 0xa130ee) { d = 0x5253; goto end; } // RS\r
  else if (a == 0xa15100) { d = 0x0080; goto end; }\r
  else\r
*/\r
\r
  // for games with simple protection devices, discovered by Haze\r
  // some dumb detection is used, but that should be enough to make things work\r
  if ((a>>22) == 1 && Pico.romsize >= 512*1024) {\r
    if      (*(int *)(Pico.rom+0x123e4) == 0x00550c39 && *(int *)(Pico.rom+0x123e8) == 0x00000040) { // Super Bubble Bobble (Unl) [!]\r
      if      (a == 0x400000) { d=0x55<<8; goto end; }\r
      else if (a == 0x400002) { d=0x0f<<8; goto end; }\r
    }\r
    else if (*(int *)(Pico.rom+0x008c4) == 0x66240055 && *(int *)(Pico.rom+0x008c8) == 0x00404df9) { // Smart Mouse (Unl)\r
      if      (a == 0x400000) { d=0x55<<8; goto end; }\r
      else if (a == 0x400002) { d=0x0f<<8; goto end; }\r
      else if (a == 0x400004) { d=0xaa<<8; goto end; }\r
      else if (a == 0x400006) { d=0xf0<<8; goto end; }\r
    }\r
    else if (*(int *)(Pico.rom+0x00404) == 0x00a90600 && *(int *)(Pico.rom+0x00408) == 0x6708b013) { // King of Fighters '98, The (Unl) [!]\r
      if      (a == 0x480000 || a == 0x4800e0 || a == 0x4824a0 || a == 0x488880) { d=0xaa<<8; goto end; }\r
      else if (a == 0x4a8820) { d=0x0a<<8; goto end; }\r
      // there is also a read @ 0x4F8820 which needs 0, but that is returned in default case\r
    }\r
    else if (*(int *)(Pico.rom+0x01b24) == 0x004013f9 && *(int *)(Pico.rom+0x01b28) == 0x00ff0000) { // Mahjong Lover (Unl) [!]\r
      if      (a == 0x400000) { d=0x90<<8; goto end; }\r
      else if (a == 0x401000) { d=0xd3<<8; goto end; } // this one doesn't seem to be needed, the code does 2 comparisons and only then\r
                                                       // checks the result, which is of the above one. Left it just in case.\r
    }\r
    else if (*(int *)(Pico.rom+0x05254) == 0x0c3962d0 && *(int *)(Pico.rom+0x05258) == 0x00400055) { // Elf Wor (Unl)\r
      if      (a == 0x400000) { d=0x55<<8; goto end; }\r
      else if (a == 0x400004) { d=0xc9<<8; goto end; } // this check is done if the above one fails\r
      else if (a == 0x400002) { d=0x0f<<8; goto end; }\r
      else if (a == 0x400006) { d=0x18<<8; goto end; } // similar to above\r
    }\r
    // our default behaviour is to return whatever was last written a 0x400000-0x7fffff range (used by Squirrel King (R) [!])\r
    // Lion King II, The (Unl) [!]  writes @ 400000 and wants to get that val @ 400002 and wites another val\r
    // @ 400004 which is expected @ 400006, so we really remember 2 values here\r
    d = Pico.m.prot_bytes[(a>>2)&1]<<8;\r
  }\r
  else if (a == 0xa13000 && Pico.romsize >= 1024*1024) {\r
    if      (*(int *)(Pico.rom+0xc8af0) == 0x30133013 && *(int *)(Pico.rom+0xc8af4) == 0x000f0240) { // Rockman X3 (Unl) [!]\r
      d=0x0c; goto end;\r
    }\r
    else if (*(int *)(Pico.rom+0x28888) == 0x07fc0000 && *(int *)(Pico.rom+0x2888c) == 0x4eb94e75) { // Bug's Life, A (Unl) [!]\r
      d=0x28; goto end; // does the check from RAM\r
    }\r
    else if (*(int *)(Pico.rom+0xc8778) == 0x30133013 && *(int *)(Pico.rom+0xc877c) == 0x000f0240) { // Super Mario Bros. (Unl) [!]\r
      d=0x0c; goto end; // seems to be the same code as in Rockman X3 (Unl) [!]\r
    }\r
    else if (*(int *)(Pico.rom+0xf20ec) == 0x30143013 && *(int *)(Pico.rom+0xf20f0) == 0x000f0200) { // Super Mario 2 1998 (Unl) [!]\r
      d=0x0a; goto end;\r
    }\r
  }\r
  else if (a == 0xa13002) { // Pocket Monsters (Unl)\r
    d=0x01; goto end;\r
  }\r
  else if (a == 0xa1303E) { // Pocket Monsters (Unl)\r
    d=0x1f; goto end;\r
  }\r
  else if (a == 0x30fe02) {\r
    // Virtua Racing - just for fun\r
    // this seems to be some flag that SVP is ready or something similar\r
    d=1; goto end;\r
  }\r
\r
end:\r
  elprintf(EL_UIO, "strange r%i: [%06x] %04x @%06x", realsize, a&0xffffff, d, SekPc);\r
  return d;\r
}\r
\r
\r
//extern UINT32 mz80GetRegisterValue(void *, UINT32);\r
\r
static void OtherWrite8End(u32 a,u32 d,int realsize)\r
{\r
  // sram\r
  if(a >= SRam.start && a <= SRam.end) {\r
    elprintf(EL_SRAMIO, "sram w8  [%06x] %02x @ %06x", a, d, SekPc);\r
    SRAMWrite(a, d);\r
    return;\r
  }\r
\r
#ifdef _ASM_MEMORY_C\r
  // special ROM hardware (currently only banking and sram reg supported)\r
  if((a&0xfffff1) == 0xA130F1) {\r
    PicoWriteRomHW_SSF2(a, d); // SSF2 or SRAM\r
    return;\r
  }\r
#else\r
  // sram access register\r
  if(a == 0xA130F1) {\r
    elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
    Pico.m.sram_reg &= ~3;\r
    Pico.m.sram_reg |= (u8)(d&3);\r
    return;\r
  }\r
#endif\r
  elprintf(EL_UIO, "strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
\r
  // for games with simple protection devices, discovered by Haze\r
  if ((a>>22) == 1)\r
    Pico.m.prot_bytes[(a>>2)&1] = (u8)d;\r
}\r
\r
#include "memory_cmn.c"\r
\r
\r
// -----------------------------------------------------------------\r
//                     Read Rom and read Ram\r
\r
#ifndef _ASM_MEMORY_C\r
PICO_INTERNAL_ASM u32 PicoRead8(u32 a)\r
{\r
  u32 d=0;\r
\r
  if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r
\r
  a&=0xffffff;\r
\r
#ifndef EMU_CORE_DEBUG\r
  // sram\r
  if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
    d = SRAMRead(a);\r
    elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
    goto end;\r
  }\r
#endif\r
\r
  if (a<Pico.romsize) { d = *(u8 *)(Pico.rom+(a^1)); goto end; } // Rom\r
  log_io(a, 8, 0);\r
  if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
\r
  if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead8(a); goto end; } // VDP\r
\r
  d=OtherRead16(a&~1, 8);\r
  if ((a&1)==0) d>>=8;\r
\r
end:\r
  elprintf(EL_IO, "r8 : %06x,   %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
#ifdef EMU_CORE_DEBUG\r
  if (a>=Pico.romsize) {\r
    lastread_a = a;\r
    lastread_d[lrp_cyc++&15] = (u8)d;\r
  }\r
#endif\r
  return d;\r
}\r
\r
PICO_INTERNAL_ASM u32 PicoRead16(u32 a)\r
{\r
  u32 d=0;\r
\r
  if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
\r
  a&=0xfffffe;\r
\r
#ifndef EMU_CORE_DEBUG\r
  // sram\r
  if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
    d = SRAMRead16(a);\r
    elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
    goto end;\r
  }\r
#endif\r
\r
  if (a<Pico.romsize) { d = *(u16 *)(Pico.rom+a); goto end; } // Rom\r
  log_io(a, 16, 0);\r
\r
  if ((a&0xe700e0)==0xc00000)\r
       d = PicoVideoRead(a);\r
  else d = OtherRead16(a, 16);\r
\r
end:\r
  elprintf(EL_IO, "r16: %06x, %04x  @%06x", a&0xffffff, d, SekPc);\r
#ifdef EMU_CORE_DEBUG\r
  if (a>=Pico.romsize) {\r
    lastread_a = a;\r
    lastread_d[lrp_cyc++&15] = d;\r
  }\r
#endif\r
  return d;\r
}\r
\r
PICO_INTERNAL_ASM u32 PicoRead32(u32 a)\r
{\r
  u32 d=0;\r
\r
  if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r
\r
  a&=0xfffffe;\r
\r
  // sram\r
  if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
    d = (SRAMRead16(a)<<16)|SRAMRead16(a+2);\r
    elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc);\r
    goto end;\r
  }\r
\r
  if (a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+a); d = (pm[0]<<16)|pm[1]; goto end; } // Rom\r
  log_io(a, 32, 0);\r
\r
  if ((a&0xe700e0)==0xc00000)\r
       d = (PicoVideoRead(a)<<16)|PicoVideoRead(a+2);\r
  else d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
\r
end:\r
  elprintf(EL_IO, "r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#ifdef EMU_CORE_DEBUG\r
  if (a>=Pico.romsize) {\r
    lastread_a = a;\r
    lastread_d[lrp_cyc++&15] = d;\r
  }\r
#endif\r
  return d;\r
}\r
#endif\r
\r
// -----------------------------------------------------------------\r
//                            Write Ram\r
\r
#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r
PICO_INTERNAL_ASM void PicoWrite8(u32 a,u8 d)\r
{\r
  elprintf(EL_IO, "w8 : %06x,   %02x @%06x", a&0xffffff, d, SekPc);\r
#ifdef EMU_CORE_DEBUG\r
  lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
\r
  if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
  log_io(a, 8, 1);\r
\r
  a&=0xffffff;\r
  OtherWrite8(a,d);\r
}\r
#endif\r
\r
void PicoWrite16(u32 a,u16 d)\r
{\r
  elprintf(EL_IO, "w16: %06x, %04x", a&0xffffff, d);\r
#ifdef EMU_CORE_DEBUG\r
  lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
\r
  if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
  log_io(a, 16, 1);\r
\r
  a&=0xfffffe;\r
  if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; } // VDP\r
  OtherWrite16(a,d);\r
}\r
\r
static void PicoWrite32(u32 a,u32 d)\r
{\r
  elprintf(EL_IO, "w32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#ifdef EMU_CORE_DEBUG\r
  lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
\r
  if ((a&0xe00000)==0xe00000)\r
  {\r
    // Ram:\r
    u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
    pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
    return;\r
  }\r
  log_io(a, 32, 1);\r
\r
  a&=0xfffffe;\r
  if ((a&0xe700e0)==0xc00000)\r
  {\r
    // VDP:\r
    PicoVideoWrite(a,  (u16)(d>>16));\r
    PicoVideoWrite(a+2,(u16)d);\r
    return;\r
  }\r
\r
  OtherWrite16(a,  (u16)(d>>16));\r
  OtherWrite16(a+2,(u16)d);\r
}\r
\r
\r
// -----------------------------------------------------------------\r
\r
static void OtherWrite16End(u32 a,u32 d,int realsize)\r
{\r
  PicoWrite8Hook(a,  d>>8, realsize);\r
  PicoWrite8Hook(a+1,d&0xff, realsize);\r
}\r
\r
u32  (*PicoRead16Hook) (u32 a, int realsize) = OtherRead16End;\r
void (*PicoWrite8Hook) (u32 a, u32 d, int realsize) = OtherWrite8End;\r
void (*PicoWrite16Hook)(u32 a, u32 d, int realsize) = OtherWrite16End;\r
\r
PICO_INTERNAL void PicoMemResetHooks(void)\r
{\r
  // default unmapped/cart specific handlers\r
  PicoRead16Hook = OtherRead16End;\r
  PicoWrite8Hook = OtherWrite8End;\r
  PicoWrite16Hook = OtherWrite16End;\r
}\r
\r
#ifdef EMU_M68K\r
static void m68k_mem_setup(void);\r
#endif\r
\r
PICO_INTERNAL void PicoMemSetup(void)\r
{\r
  // Setup memory callbacks:\r
#ifdef EMU_C68K\r
  PicoCpuCM68k.checkpc=PicoCheckPc;\r
  PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoRead8;\r
  PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoRead16;\r
  PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoRead32;\r
  PicoCpuCM68k.write8 =PicoWrite8;\r
  PicoCpuCM68k.write16=PicoWrite16;\r
  PicoCpuCM68k.write32=PicoWrite32;\r
#endif\r
#ifdef EMU_F68K\r
  PicoCpuFM68k.read_byte =PicoRead8;\r
  PicoCpuFM68k.read_word =PicoRead16;\r
  PicoCpuFM68k.read_long =PicoRead32;\r
  PicoCpuFM68k.write_byte=PicoWrite8;\r
  PicoCpuFM68k.write_word=PicoWrite16;\r
  PicoCpuFM68k.write_long=PicoWrite32;\r
\r
  // setup FAME fetchmap\r
  {\r
    int i;\r
    // by default, point everything to first 64k of ROM\r
    for (i = 0; i < M68K_FETCHBANK1; i++)\r
      PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
    // now real ROM\r
    for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
      PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
    // .. and RAM\r
    for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
      PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
  }\r
#endif\r
#ifdef EMU_M68K\r
  m68k_mem_setup();\r
#endif\r
\r
  z80_mem_setup();\r
}\r
\r
/* some nasty things below :( */\r
#ifdef EMU_M68K\r
unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;\r
unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;\r
unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;\r
void (*pm68k_write_memory_8) (unsigned int address, unsigned char  value) = NULL;\r
void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;\r
void (*pm68k_write_memory_32)(unsigned int address, unsigned int   value) = NULL;\r
unsigned int (*pm68k_read_memory_pcr_8) (unsigned int address) = NULL;\r
unsigned int (*pm68k_read_memory_pcr_16)(unsigned int address) = NULL;\r
unsigned int (*pm68k_read_memory_pcr_32)(unsigned int address) = NULL;\r
\r
// these are here for core debugging mode\r
static unsigned int  m68k_read_8 (unsigned int a, int do_fake)\r
{\r
  a&=0xffffff;\r
  if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)    return *(u8 *)(Pico.rom+(a^1)); // Rom\r
#ifdef EMU_CORE_DEBUG\r
  if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
  return pm68k_read_memory_pcr_8(a);\r
}\r
static unsigned int  m68k_read_16(unsigned int a, int do_fake)\r
{\r
  a&=0xffffff;\r
  if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)    return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
#ifdef EMU_CORE_DEBUG\r
  if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
  return pm68k_read_memory_pcr_16(a);\r
}\r
static unsigned int  m68k_read_32(unsigned int a, int do_fake)\r
{\r
  a&=0xffffff;\r
  if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
#ifdef EMU_CORE_DEBUG\r
  if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
  return pm68k_read_memory_pcr_32(a);\r
}\r
\r
unsigned int m68k_read_pcrelative_8 (unsigned int a)   { return m68k_read_8 (a, 1); }\r
unsigned int m68k_read_pcrelative_16(unsigned int a)   { return m68k_read_16(a, 1); }\r
unsigned int m68k_read_pcrelative_32(unsigned int a)   { return m68k_read_32(a, 1); }\r
unsigned int m68k_read_immediate_16(unsigned int a)    { return m68k_read_16(a, 0); }\r
unsigned int m68k_read_immediate_32(unsigned int a)    { return m68k_read_32(a, 0); }\r
unsigned int m68k_read_disassembler_8 (unsigned int a) { return m68k_read_8 (a, 0); }\r
unsigned int m68k_read_disassembler_16(unsigned int a) { return m68k_read_16(a, 0); }\r
unsigned int m68k_read_disassembler_32(unsigned int a) { return m68k_read_32(a, 0); }\r
\r
static unsigned int m68k_read_memory_pcr_8(unsigned int a)\r
{\r
  if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
  return 0;\r
}\r
\r
static unsigned int m68k_read_memory_pcr_16(unsigned int a)\r
{\r
  if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
  return 0;\r
}\r
\r
static unsigned int m68k_read_memory_pcr_32(unsigned int a)\r
{\r
  if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
  return 0;\r
}\r
\r
#ifdef EMU_CORE_DEBUG\r
// ROM only\r
unsigned int m68k_read_memory_8(unsigned int a)\r
{\r
  u8 d;\r
  if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
       d = *(u8 *) (Pico.rom+(a^1));\r
  else d = (u8) lastread_d[lrp_mus++&15];\r
  elprintf(EL_IO, "r8_mu : %06x,   %02x @%06x", a&0xffffff, d, SekPc);\r
  return d;\r
}\r
unsigned int m68k_read_memory_16(unsigned int a)\r
{\r
  u16 d;\r
  if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
       d = *(u16 *)(Pico.rom+(a&~1));\r
  else d = (u16) lastread_d[lrp_mus++&15];\r
  elprintf(EL_IO, "r16_mu: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
  return d;\r
}\r
unsigned int m68k_read_memory_32(unsigned int a)\r
{\r
  u32 d;\r
  if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
       { u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1]; }\r
  else if (a <= 0x78) d = m68k_read_32(a, 0);\r
  else d = lastread_d[lrp_mus++&15];\r
  elprintf(EL_IO, "r32_mu: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
  return d;\r
}\r
\r
// ignore writes, Cyclone already done that\r
void m68k_write_memory_8(unsigned int address, unsigned int value)  { lastwrite_mus_d[lwp_mus++&15] = value; }\r
void m68k_write_memory_16(unsigned int address, unsigned int value) { lastwrite_mus_d[lwp_mus++&15] = value; }\r
void m68k_write_memory_32(unsigned int address, unsigned int value) { lastwrite_mus_d[lwp_mus++&15] = value; }\r
\r
#else // if !EMU_CORE_DEBUG\r
\r
/* it appears that Musashi doesn't always mask the unused bits */\r
unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }\r
unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }\r
unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }\r
void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }\r
void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }\r
void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }\r
#endif // !EMU_CORE_DEBUG\r
\r
static void m68k_mem_setup(void)\r
{\r
  pm68k_read_memory_8  = PicoRead8;\r
  pm68k_read_memory_16 = PicoRead16;\r
  pm68k_read_memory_32 = PicoRead32;\r
  pm68k_write_memory_8  = PicoWrite8;\r
  pm68k_write_memory_16 = PicoWrite16;\r
  pm68k_write_memory_32 = PicoWrite32;\r
  pm68k_read_memory_pcr_8  = m68k_read_memory_pcr_8;\r
  pm68k_read_memory_pcr_16 = m68k_read_memory_pcr_16;\r
  pm68k_read_memory_pcr_32 = m68k_read_memory_pcr_32;\r
}\r
#endif // EMU_M68K\r
\r
\r
// -----------------------------------------------------------------\r
\r
static int get_scanline(int is_from_z80)\r
{\r
  if (is_from_z80) {\r
    int cycles = z80_cyclesDone();\r
    while (cycles - z80_scanline_cycles >= 228)\r
      z80_scanline++, z80_scanline_cycles += 228;\r
    return z80_scanline;\r
  }\r
\r
  return Pico.m.scanline;\r
}\r
\r
/* probably should not be in this file, but it's near related code here */\r
void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)\r
{\r
  int xcycles = z80_cycles << 8;\r
\r
  /* check for overflows */\r
  if ((mode_old & 4) && xcycles > timer_a_next_oflow)\r
    ym2612.OPN.ST.status |= 1;\r
\r
  if ((mode_old & 8) && xcycles > timer_b_next_oflow)\r
    ym2612.OPN.ST.status |= 2;\r
\r
  /* update timer a */\r
  if (mode_old & 1)\r
    while (xcycles > timer_a_next_oflow)\r
      timer_a_next_oflow += timer_a_step;\r
\r
  if ((mode_old ^ mode_new) & 1) // turning on/off\r
  {\r
    if (mode_old & 1)\r
      timer_a_next_oflow = TIMER_NO_OFLOW;\r
    else\r
      timer_a_next_oflow = xcycles + timer_a_step;\r
  }\r
  if (mode_new & 1)\r
    elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);\r
\r
  /* update timer b */\r
  if (mode_old & 2)\r
    while (xcycles > timer_b_next_oflow)\r
      timer_b_next_oflow += timer_b_step;\r
\r
  if ((mode_old ^ mode_new) & 2)\r
  {\r
    if (mode_old & 2)\r
      timer_b_next_oflow = TIMER_NO_OFLOW;\r
    else\r
      timer_b_next_oflow = xcycles + timer_b_step;\r
  }\r
  if (mode_new & 2)\r
    elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);\r
}\r
\r
// ym2612 DAC and timer I/O handlers for z80\r
int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
{\r
  int addr;\r
\r
  a &= 3;\r
  if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */\r
  {\r
    int scanline = get_scanline(is_from_z80);\r
    //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);\r
    ym2612.dacout = ((int)d - 0x80) << 6;\r
    if (PsndOut && ym2612.dacen && scanline >= PsndDacLine)\r
      PsndDoDAC(scanline);\r
    return 0;\r
  }\r
\r
  switch (a)\r
  {\r
    case 0: /* address port 0 */\r
      ym2612.OPN.ST.address = d;\r
      ym2612.addr_A1 = 0;\r
#ifdef __GP2X__\r
      if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
#endif\r
      return 0;\r
\r
    case 1: /* data port 0    */\r
      if (ym2612.addr_A1 != 0)\r
        return 0;\r
\r
      addr = ym2612.OPN.ST.address;\r
      ym2612.REGS[addr] = d;\r
\r
      switch (addr)\r
      {\r
        case 0x24: // timer A High 8\r
        case 0x25: { // timer A Low 2\r
          int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))\r
                                     : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));\r
          if (ym2612.OPN.ST.TA != TAnew)\r
          {\r
            //elprintf(EL_STATUS, "timer a set %i", TAnew);\r
            ym2612.OPN.ST.TA = TAnew;\r
            //ym2612.OPN.ST.TAC = (1024-TAnew)*18;\r
            //ym2612.OPN.ST.TAT = 0;\r
            timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r
            if (ym2612.OPN.ST.mode & 1) {\r
              // this is not right, should really be done on overflow only\r
              int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
              timer_a_next_oflow = (cycles << 8) + timer_a_step;\r
            }\r
            elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);\r
          }\r
          return 0;\r
        }\r
        case 0x26: // timer B\r
          if (ym2612.OPN.ST.TB != d) {\r
            //elprintf(EL_STATUS, "timer b set %i", d);\r
            ym2612.OPN.ST.TB = d;\r
            //ym2612.OPN.ST.TBC = (256-d) * 288;\r
            //ym2612.OPN.ST.TBT  = 0;\r
            timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800\r
            if (ym2612.OPN.ST.mode & 2) {\r
              int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
              timer_b_next_oflow = (cycles << 8) + timer_b_step;\r
            }\r
            elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);\r
          }\r
          return 0;\r
        case 0x27: { /* mode, timer control */\r
          int old_mode = ym2612.OPN.ST.mode;\r
          int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
          ym2612.OPN.ST.mode = d;\r
\r
          elprintf(EL_YMTIMER, "st mode %02x", d);\r
          ym2612_sync_timers(cycles, old_mode, d);\r
\r
          /* reset Timer a flag */\r
          if (d & 0x10)\r
            ym2612.OPN.ST.status &= ~1;\r
\r
          /* reset Timer b flag */\r
          if (d & 0x20)\r
            ym2612.OPN.ST.status &= ~2;\r
\r
          if ((d ^ old_mode) & 0xc0) {\r
#ifdef __GP2X__\r
            if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
#endif\r
            return 1;\r
          }\r
          return 0;\r
        }\r
        case 0x2b: { /* DAC Sel  (YM2612) */\r
          int scanline = get_scanline(is_from_z80);\r
          ym2612.dacen = d & 0x80;\r
          if (d & 0x80) PsndDacLine = scanline;\r
#ifdef __GP2X__\r
          if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);\r
#endif\r
          return 0;\r
        }\r
      }\r
      break;\r
\r
    case 2: /* address port 1 */\r
      ym2612.OPN.ST.address = d;\r
      ym2612.addr_A1 = 1;\r
#ifdef __GP2X__\r
      if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
#endif\r
      return 0;\r
\r
    case 3: /* data port 1    */\r
      if (ym2612.addr_A1 != 1)\r
        return 0;\r
\r
      addr = ym2612.OPN.ST.address | 0x100;\r
      ym2612.REGS[addr] = d;\r
      break;\r
  }\r
\r
#ifdef __GP2X__\r
  if (PicoOpt & POPT_EXT_FM)\r
    return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
#endif\r
  return YM2612Write_(a, d);\r
}\r
\r
\r
#define ym2612_read_local() \\r
  if (xcycles >= timer_a_next_oflow) \\r
    ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \\r
  if (xcycles >= timer_b_next_oflow) \\r
    ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r
\r
static u32 MEMH_FUNC ym2612_read_local_z80(void)\r
{\r
  int xcycles = z80_cyclesDone() << 8;\r
\r
  ym2612_read_local();\r
\r
  elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
      timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
  return ym2612.OPN.ST.status;\r
}\r
\r
u32 ym2612_read_local_68k(void)\r
{\r
  int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;\r
\r
  ym2612_read_local();\r
\r
  elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
      timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
  return ym2612.OPN.ST.status;\r
}\r
\r
void ym2612_pack_state(void)\r
{\r
  // timers are saved as tick counts, in 16.16 int format\r
  int tac, tat = 0, tbc, tbt = 0;\r
  tac = 1024 - ym2612.OPN.ST.TA;\r
  tbc = 256  - ym2612.OPN.ST.TB;\r
  if (timer_a_next_oflow != TIMER_NO_OFLOW)\r
    tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);\r
  if (timer_b_next_oflow != TIMER_NO_OFLOW)\r
    tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);\r
  elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);\r
  elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);\r
\r
#ifdef __GP2X__\r
  if (PicoOpt & POPT_EXT_FM)\r
    YM2612PicoStateSave2_940(tat, tbt);\r
  else\r
#endif\r
    YM2612PicoStateSave2(tat, tbt);\r
}\r
\r
void ym2612_unpack_state(void)\r
{\r
  int i, ret, tac, tat, tbc, tbt;\r
  YM2612PicoStateLoad();\r
\r
  // feed all the registers and update internal state\r
  for (i = 0x20; i < 0xA0; i++) {\r
    ym2612_write_local(0, i, 0);\r
    ym2612_write_local(1, ym2612.REGS[i], 0);\r
  }\r
  for (i = 0x30; i < 0xA0; i++) {\r
    ym2612_write_local(2, i, 0);\r
    ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
  }\r
  for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards\r
    ym2612_write_local(2, i, 0);\r
    ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
    ym2612_write_local(0, i, 0);\r
    ym2612_write_local(1, ym2612.REGS[i], 0);\r
  }\r
  for (i = 0xB0; i < 0xB8; i++) {\r
    ym2612_write_local(0, i, 0);\r
    ym2612_write_local(1, ym2612.REGS[i], 0);\r
    ym2612_write_local(2, i, 0);\r
    ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
  }\r
\r
#ifdef __GP2X__\r
  if (PicoOpt & POPT_EXT_FM)\r
    ret = YM2612PicoStateLoad2_940(&tat, &tbt);\r
  else\r
#endif\r
    ret = YM2612PicoStateLoad2(&tat, &tbt);\r
  if (ret != 0) {\r
    elprintf(EL_STATUS, "old ym2612 state");\r
    return; // no saved timers\r
  }\r
\r
  tac = (1024 - ym2612.OPN.ST.TA) << 16;\r
  tbc = (256  - ym2612.OPN.ST.TB) << 16;\r
  if (ym2612.OPN.ST.mode & 1)\r
    timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);\r
  else\r
    timer_a_next_oflow = TIMER_NO_OFLOW;\r
  if (ym2612.OPN.ST.mode & 2)\r
    timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);\r
  else\r
    timer_b_next_oflow = TIMER_NO_OFLOW;\r
  elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);\r
  elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);\r
}\r
\r
// -----------------------------------------------------------------\r
//                        z80 memhandlers\r
\r
static unsigned char MEMH_FUNC z80_md_vdp_read(unsigned short a)\r
{\r
  // TODO?\r
  elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r
  return 0xff;\r
}\r
\r
static unsigned char MEMH_FUNC z80_md_bank_read(unsigned short a)\r
{\r
  extern unsigned int PicoReadM68k8(unsigned int a);\r
  unsigned int addr68k;\r
  unsigned char ret;\r
\r
  addr68k = Pico.m.z80_bank68k<<15;\r
  addr68k += a & 0x7fff;\r
\r
  if (addr68k < Pico.romsize) {\r
    ret = Pico.rom[addr68k^1];\r
    goto out;\r
  }\r
\r
  elprintf(EL_ANOMALY, "z80->68k upper read [%06x] %02x", addr68k, ret);\r
  if (PicoAHW & PAHW_MCD)\r
       ret = PicoReadM68k8(addr68k);\r
  else ret = PicoRead8(addr68k);\r
\r
out:\r
  elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
  return ret;\r
}\r
\r
static void MEMH_FUNC z80_md_ym2612_write(unsigned int a, unsigned char data)\r
{\r
  if (PicoOpt & POPT_EN_FM)\r
    emustatus |= ym2612_write_local(a, data, 1) & 1;\r
}\r
\r
static void MEMH_FUNC z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
{\r
  // TODO: allow full VDP access\r
  if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r
  {\r
    if (PicoOpt & POPT_EN_PSG)\r
      SN76496Write(data);\r
    return;\r
  }\r
\r
  if ((a>>8) == 0x60)\r
  {\r
    Pico.m.z80_bank68k >>= 1;\r
    Pico.m.z80_bank68k |= data << 8;\r
    Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
    return;\r
  }\r
\r
  elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
}\r
\r
static void MEMH_FUNC z80_md_bank_write(unsigned int a, unsigned char data)\r
{\r
  extern void PicoWriteM68k8(unsigned int a, unsigned char d);\r
  unsigned int addr68k;\r
\r
  addr68k = Pico.m.z80_bank68k << 15;\r
  addr68k += a & 0x7fff;\r
\r
  elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
  if (PicoAHW & PAHW_MCD)\r
       PicoWriteM68k8(addr68k, data);\r
  else PicoWrite8(addr68k, data);\r
}\r
\r
// -----------------------------------------------------------------\r
\r
static unsigned char z80_md_in(unsigned short p)\r
{\r
  elprintf(EL_ANOMALY, "Z80 port %04x read", p);\r
  return 0xff;\r
}\r
\r
static void z80_md_out(unsigned short p, unsigned char d)\r
{\r
  elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r
}\r
\r
void z80_mem_setup(void)\r
{\r
  z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r
  z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r
  z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r
  z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r
  z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r
\r
  z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);\r
  z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);\r
  z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r
  z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r
  z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r
\r
#ifdef _USE_DRZ80\r
  drZ80.z80_in = z80_md_in;\r
  drZ80.z80_out = z80_md_out;\r
#endif\r
#ifdef _USE_CZ80\r
  Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (UINT32)Pico.zram); // main RAM\r
  Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (UINT32)Pico.zram); // mirror\r
  Cz80_Set_INPort(&CZ80, z80_md_in);\r
  Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
#endif\r
}\r
\r