| 1 | /*\r |
| 2 | * PicoDrive\r |
| 3 | * (C) notaz, 2006-2009\r |
| 4 | *\r |
| 5 | * This work is licensed under the terms of MAME license.\r |
| 6 | * See COPYING file in the top-level directory.\r |
| 7 | */\r |
| 8 | \r |
| 9 | @@ .include "port_config.s"\r |
| 10 | \r |
| 11 | .equ SRR_MAPPED, (1 << 0)\r |
| 12 | .equ SRR_READONLY, (1 << 1)\r |
| 13 | .equ SRF_EEPROM, (1 << 1)\r |
| 14 | .equ POPT_6BTN_PAD, (1 << 5)\r |
| 15 | .equ POPT_EN_32X, (1 << 20)\r |
| 16 | \r |
| 17 | .text\r |
| 18 | .align 4\r |
| 19 | \r |
| 20 | .global PicoRead8_sram\r |
| 21 | .global PicoRead8_io\r |
| 22 | .global PicoRead16_sram\r |
| 23 | .global PicoRead16_io\r |
| 24 | .global PicoWrite8_io\r |
| 25 | .global PicoWrite16_io\r |
| 26 | \r |
| 27 | PicoRead8_sram: @ u32 a, u32 d\r |
| 28 | ldr r2, =(SRam)\r |
| 29 | ldr r3, =(Pico+0x22200)\r |
| 30 | ldr r1, [r2, #8] @ SRam.end\r |
| 31 | cmp r0, r1\r |
| 32 | bgt m_read8_nosram\r |
| 33 | ldr r1, [r2, #4] @ SRam.start\r |
| 34 | cmp r0, r1\r |
| 35 | blt m_read8_nosram\r |
| 36 | ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r |
| 37 | tst r1, #SRR_MAPPED\r |
| 38 | beq m_read8_nosram\r |
| 39 | ldr r1, [r2, #0x0c]\r |
| 40 | tst r1, #SRF_EEPROM\r |
| 41 | bne m_read8_eeprom\r |
| 42 | ldr r1, [r2, #4] @ SRam.start\r |
| 43 | ldr r2, [r2] @ SRam.data\r |
| 44 | sub r0, r0, r1\r |
| 45 | add r0, r0, r2\r |
| 46 | ldrb r0, [r0]\r |
| 47 | bx lr\r |
| 48 | \r |
| 49 | m_read8_nosram:\r |
| 50 | ldr r1, [r3, #4] @ romsize\r |
| 51 | cmp r0, r1\r |
| 52 | movgt r0, #0\r |
| 53 | bxgt lr @ bad location\r |
| 54 | @ XXX: banking unfriendly\r |
| 55 | ldr r1, [r3]\r |
| 56 | eor r0, r0, #1\r |
| 57 | ldrb r0, [r1, r0]\r |
| 58 | bx lr\r |
| 59 | \r |
| 60 | m_read8_eeprom:\r |
| 61 | stmfd sp!,{r0,lr}\r |
| 62 | bl EEPROM_read\r |
| 63 | ldmfd sp!,{r1,lr}\r |
| 64 | tst r1, #1\r |
| 65 | moveq r0, r0, lsr #8\r |
| 66 | bx lr\r |
| 67 | \r |
| 68 | \r |
| 69 | PicoRead8_io: @ u32 a, u32 d\r |
| 70 | bic r2, r0, #0x001f @ most commonly we get i/o port read,\r |
| 71 | cmp r2, #0xa10000 @ so check for it first\r |
| 72 | bne m_read8_not_io\r |
| 73 | \r |
| 74 | m_read8_misc_io:\r |
| 75 | ands r0, r0, #0x1e\r |
| 76 | beq m_read8_misc_hwreg\r |
| 77 | cmp r0, #4\r |
| 78 | movlt r0, #0\r |
| 79 | moveq r0, #1\r |
| 80 | ble PadRead\r |
| 81 | ldr r3, =(Pico+0x22000)\r |
| 82 | mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])\r |
| 83 | ldrb r0, [r3, r0]\r |
| 84 | bx lr\r |
| 85 | \r |
| 86 | m_read8_misc_hwreg:\r |
| 87 | ldr r3, =(Pico+0x22200)\r |
| 88 | ldrb r0, [r3, #0x0f] @ Pico.m.hardware\r |
| 89 | bx lr\r |
| 90 | \r |
| 91 | m_read8_not_io:\r |
| 92 | and r2, r0, #0xfc00\r |
| 93 | cmp r2, #0x1000\r |
| 94 | bne m_read8_not_brq\r |
| 95 | \r |
| 96 | ldr r3, =(Pico+0x22200)\r |
| 97 | mov r1, r0\r |
| 98 | ldr r0, [r3, #8] @ Pico.m.rotate\r |
| 99 | add r0, r0, #1\r |
| 100 | strb r0, [r3, #8]\r |
| 101 | eor r0, r0, r0, lsl #6\r |
| 102 | \r |
| 103 | tst r1, #1\r |
| 104 | bxne lr @ odd addr -> open bus\r |
| 105 | bic r0, r0, #1 @ bit0 defined in this area\r |
| 106 | and r2, r1, #0xff00\r |
| 107 | cmp r2, #0x1100\r |
| 108 | bxne lr @ not busreq\r |
| 109 | \r |
| 110 | ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r |
| 111 | ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r |
| 112 | orr r0, r0, r1\r |
| 113 | orr r0, r0, r2\r |
| 114 | bx lr\r |
| 115 | \r |
| 116 | m_read8_not_brq:\r |
| 117 | ldr r2, =PicoOpt\r |
| 118 | ldr r2, [r2]\r |
| 119 | tst r2, #POPT_EN_32X\r |
| 120 | bne PicoRead8_32x\r |
| 121 | mov r0, #0\r |
| 122 | bx lr\r |
| 123 | \r |
| 124 | @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r |
| 125 | \r |
| 126 | PicoRead16_sram: @ u32 a, u32 d\r |
| 127 | ldr r2, =(SRam)\r |
| 128 | ldr r3, =(Pico+0x22200)\r |
| 129 | ldr r1, [r2, #8] @ SRam.end\r |
| 130 | cmp r0, r1\r |
| 131 | bgt m_read16_nosram\r |
| 132 | ldr r1, [r2, #4] @ SRam.start\r |
| 133 | cmp r0, r1\r |
| 134 | blt m_read16_nosram\r |
| 135 | ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r |
| 136 | tst r1, #SRR_MAPPED\r |
| 137 | beq m_read16_nosram\r |
| 138 | ldr r1, [r2, #0x0c]\r |
| 139 | tst r1, #SRF_EEPROM\r |
| 140 | bne EEPROM_read\r |
| 141 | ldr r1, [r2, #4] @ SRam.start\r |
| 142 | ldr r2, [r2] @ SRam.data\r |
| 143 | sub r0, r0, r1\r |
| 144 | add r0, r0, r2\r |
| 145 | ldrb r1, [r0], #1\r |
| 146 | ldrb r0, [r0]\r |
| 147 | orr r0, r0, r1, lsl #8\r |
| 148 | bx lr\r |
| 149 | \r |
| 150 | m_read16_nosram:\r |
| 151 | ldr r1, [r3, #4] @ romsize\r |
| 152 | cmp r0, r1\r |
| 153 | movgt r0, #0\r |
| 154 | bxgt lr @ bad location\r |
| 155 | @ XXX: banking unfriendly\r |
| 156 | ldr r1, [r3]\r |
| 157 | ldrh r0, [r1, r0]\r |
| 158 | bx lr\r |
| 159 | \r |
| 160 | \r |
| 161 | PicoRead16_io: @ u32 a, u32 d\r |
| 162 | bic r2, r0, #0x001f @ most commonly we get i/o port read,\r |
| 163 | cmp r2, #0xa10000 @ so check for it first\r |
| 164 | bne m_read16_not_io\r |
| 165 | stmfd sp!,{lr}\r |
| 166 | bl m_read8_misc_io @ same as read8\r |
| 167 | orr r0, r0, r0, lsl #8 @ only has bytes mirrored\r |
| 168 | ldmfd sp!,{pc}\r |
| 169 | \r |
| 170 | m_read16_not_io:\r |
| 171 | and r2, r0, #0xfc00\r |
| 172 | cmp r2, #0x1000\r |
| 173 | bne m_read16_not_brq\r |
| 174 | \r |
| 175 | ldr r3, =(Pico+0x22200)\r |
| 176 | and r2, r0, #0xff00\r |
| 177 | ldr r0, [r3, #8] @ Pico.m.rotate\r |
| 178 | add r0, r0, #1\r |
| 179 | strb r0, [r3, #8]\r |
| 180 | eor r0, r0, r0, lsl #5\r |
| 181 | eor r0, r0, r0, lsl #8\r |
| 182 | bic r0, r0, #0x100 @ bit8 defined in this area\r |
| 183 | cmp r2, #0x1100\r |
| 184 | bxne lr @ not busreq\r |
| 185 | \r |
| 186 | ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r |
| 187 | ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r |
| 188 | orr r0, r0, r1, lsl #8\r |
| 189 | orr r0, r0, r2, lsl #8\r |
| 190 | bx lr\r |
| 191 | \r |
| 192 | m_read16_not_brq:\r |
| 193 | ldr r2, =PicoOpt\r |
| 194 | ldr r2, [r2]\r |
| 195 | tst r2, #POPT_EN_32X\r |
| 196 | bne PicoRead16_32x\r |
| 197 | mov r0, #0\r |
| 198 | bx lr\r |
| 199 | \r |
| 200 | @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r |
| 201 | \r |
| 202 | PicoWrite8_io: @ u32 a, u32 d\r |
| 203 | bic r2, r0, #0x1e @ most commonly we get i/o port write,\r |
| 204 | eor r2, r2, #0xa10000 @ so check for it first\r |
| 205 | eors r2, r2, #1\r |
| 206 | bne m_write8_not_io\r |
| 207 | \r |
| 208 | m_write8_io:\r |
| 209 | ldr r2, =PicoOpt\r |
| 210 | and r0, r0, #0x1e\r |
| 211 | ldr r2, [r2]\r |
| 212 | ldr r3, =(Pico+0x22000) @ Pico.ioports\r |
| 213 | tst r2, #POPT_6BTN_PAD\r |
| 214 | beq m_write8_io_done\r |
| 215 | cmp r0, #2\r |
| 216 | cmpne r0, #4\r |
| 217 | bne m_write8_io_done @ not likely to happen\r |
| 218 | add r2, r3, #0x200 @ Pico+0x22200\r |
| 219 | mov r12,#0\r |
| 220 | cmp r0, #2\r |
| 221 | streqb r12,[r2,#0x18]\r |
| 222 | strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0\r |
| 223 | tst r1, #0x40 @ TH\r |
| 224 | beq m_write8_io_done\r |
| 225 | ldrb r12,[r3, r0, lsr #1]\r |
| 226 | tst r12,#0x40\r |
| 227 | bne m_write8_io_done\r |
| 228 | cmp r0, #2\r |
| 229 | ldreqb r12,[r2,#0x0a]\r |
| 230 | ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase\r |
| 231 | add r12,r12,#1\r |
| 232 | streqb r12,[r2,#0x0a]\r |
| 233 | strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase\r |
| 234 | m_write8_io_done:\r |
| 235 | strb r1, [r3, r0, lsr #1]\r |
| 236 | bx lr\r |
| 237 | \r |
| 238 | m_write8_not_io:\r |
| 239 | tst r0, #1\r |
| 240 | bne m_write8_not_z80ctl @ even addrs only\r |
| 241 | and r2, r0, #0xff00\r |
| 242 | cmp r2, #0x1100\r |
| 243 | moveq r0, r1\r |
| 244 | beq ctl_write_z80busreq\r |
| 245 | cmp r2, #0x1200\r |
| 246 | moveq r0, r1\r |
| 247 | beq ctl_write_z80reset\r |
| 248 | \r |
| 249 | m_write8_not_z80ctl:\r |
| 250 | @ unlikely\r |
| 251 | eor r2, r0, #0xa10000\r |
| 252 | eor r2, r2, #0x003000\r |
| 253 | eors r2, r2, #0x0000f1\r |
| 254 | bne m_write8_not_sreg\r |
| 255 | ldr r3, =(Pico+0x22200)\r |
| 256 | ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r |
| 257 | and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r |
| 258 | bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r |
| 259 | orr r2, r2, r1\r |
| 260 | strb r2, [r3, #(8+9)]\r |
| 261 | bx lr\r |
| 262 | \r |
| 263 | m_write8_not_sreg:\r |
| 264 | ldr r2, =PicoOpt\r |
| 265 | ldr r2, [r2]\r |
| 266 | tst r2, #POPT_EN_32X\r |
| 267 | bne PicoWrite8_32x\r |
| 268 | bx lr\r |
| 269 | \r |
| 270 | @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r |
| 271 | \r |
| 272 | PicoWrite16_io: @ u32 a, u32 d\r |
| 273 | bic r2, r0, #0x1f @ most commonly we get i/o port write,\r |
| 274 | cmp r2, #0xa10000 @ so check for it first\r |
| 275 | beq m_write8_io\r |
| 276 | \r |
| 277 | m_write16_not_io:\r |
| 278 | and r2, r0, #0xff00\r |
| 279 | cmp r2, #0x1100\r |
| 280 | moveq r0, r1, lsr #8\r |
| 281 | beq ctl_write_z80busreq\r |
| 282 | cmp r2, #0x1200\r |
| 283 | moveq r0, r1, lsr #8\r |
| 284 | beq ctl_write_z80reset\r |
| 285 | \r |
| 286 | m_write16_not_z80ctl:\r |
| 287 | @ unlikely\r |
| 288 | eor r2, r0, #0xa10000\r |
| 289 | eor r2, r2, #0x003000\r |
| 290 | eors r2, r2, #0x0000f0\r |
| 291 | bne m_write16_not_sreg\r |
| 292 | ldr r3, =(Pico+0x22200)\r |
| 293 | ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r |
| 294 | and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r |
| 295 | bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r |
| 296 | orr r2, r2, r1\r |
| 297 | strb r2, [r3, #(8+9)]\r |
| 298 | bx lr\r |
| 299 | \r |
| 300 | m_write16_not_sreg:\r |
| 301 | ldr r2, =PicoOpt\r |
| 302 | ldr r2, [r2]\r |
| 303 | tst r2, #POPT_EN_32X\r |
| 304 | bne PicoWrite16_32x\r |
| 305 | bx lr\r |
| 306 | \r |
| 307 | .pool\r |
| 308 | \r |
| 309 | @ vim:filetype=armasm\r |