| | 1 | /* |
| | 2 | * (C) GraÅžvydas "notaz" Ignotas, 2011 |
| | 3 | * |
| | 4 | * This work is licensed under the terms of any of these licenses |
| | 5 | * (at your option): |
| | 6 | * - GNU GPL, version 2 or later. |
| | 7 | * - GNU LGPL, version 2.1 or later. |
| | 8 | * See the COPYING file in the top-level directory. |
| | 9 | */ |
| | 10 | |
| | 11 | #ifndef __GPULIB_GPU_H__ |
| | 12 | #define __GPULIB_GPU_H__ |
| | 13 | |
| | 14 | #include <stdint.h> |
| | 15 | #include <string.h> |
| | 16 | #include "../../include/compiler_features.h" |
| | 17 | |
| | 18 | //#define RAW_FB_DISPLAY |
| | 19 | |
| | 20 | #define gpu_log(gpu, fmt, ...) \ |
| | 21 | SysPrintf("%d:%03d: " fmt, *(gpu)->state.frame_count, *(gpu)->state.hcnt, ##__VA_ARGS__) |
| | 22 | |
| | 23 | #ifdef LOG_UNHANDLED |
| | 24 | #define log_anomaly gpu_log |
| | 25 | #else |
| | 26 | #define log_anomaly(...) |
| | 27 | #endif |
| | 28 | |
| | 29 | #ifdef __cplusplus |
| | 30 | extern "C" { |
| | 31 | #endif |
| | 32 | |
| | 33 | #define CMD_BUFFER_LEN 1024 |
| | 34 | |
| | 35 | #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ |
| | 36 | #define HTOLE32(x) __builtin_bswap32(x) |
| | 37 | #define HTOLE16(x) __builtin_bswap16(x) |
| | 38 | #define LE32TOH(x) __builtin_bswap32(x) |
| | 39 | #define LE16TOH(x) __builtin_bswap16(x) |
| | 40 | #else |
| | 41 | #define HTOLE32(x) (x) |
| | 42 | #define HTOLE16(x) (x) |
| | 43 | #define LE32TOH(x) (x) |
| | 44 | #define LE16TOH(x) (x) |
| | 45 | #endif |
| | 46 | |
| | 47 | #undef BIT |
| | 48 | #define BIT(x) (1u << (x)) |
| | 49 | |
| | 50 | #define PSX_GPU_STATUS_DHEIGHT BIT(19) |
| | 51 | #define PSX_GPU_STATUS_PAL BIT(20) |
| | 52 | #define PSX_GPU_STATUS_RGB24 BIT(21) |
| | 53 | #define PSX_GPU_STATUS_INTERLACE BIT(22) |
| | 54 | #define PSX_GPU_STATUS_BLANKING BIT(23) |
| | 55 | #define PSX_GPU_STATUS_IMG BIT(27) |
| | 56 | #define PSX_GPU_STATUS_DMA(x) ((x) << 29) |
| | 57 | #define PSX_GPU_STATUS_DMA_MASK (BIT(29) | BIT(30)) |
| | 58 | |
| | 59 | struct psx_gpu_async; |
| | 60 | |
| | 61 | struct psx_gpu_screen { |
| | 62 | short hres, vres; |
| | 63 | short x, y, w, h; |
| | 64 | short x1, x2; |
| | 65 | short y1, y2; |
| | 66 | short src_x, src_y; |
| | 67 | }; |
| | 68 | |
| | 69 | struct psx_gpu { |
| | 70 | uint32_t regs[16]; |
| | 71 | uint16_t *vram; |
| | 72 | uint32_t status; |
| | 73 | uint32_t gp0; |
| | 74 | uint32_t ex_regs[8]; // in native endian |
| | 75 | struct psx_gpu_screen screen; |
| | 76 | struct { |
| | 77 | int x, y, w, h; |
| | 78 | short int offset, is_read; |
| | 79 | } dma, dma_start; |
| | 80 | int cmd_len; |
| | 81 | uint32_t zero; |
| | 82 | struct { |
| | 83 | uint32_t fb_dirty:1; |
| | 84 | uint32_t fb_dirty_display_area:1; |
| | 85 | uint32_t draw_display_intersect:1; |
| | 86 | uint32_t old_interlace:1; |
| | 87 | uint32_t allow_interlace:2; |
| | 88 | uint32_t blanked:1; |
| | 89 | uint32_t vblank:1; |
| | 90 | uint32_t use_alternative_flip:1; |
| | 91 | uint32_t enhancement_enable:1; |
| | 92 | uint32_t enhancement_active:1; |
| | 93 | uint32_t enhancement_was_active:1; |
| | 94 | uint32_t downscale_enable:1; |
| | 95 | uint32_t dims_changed:1; |
| | 96 | uint32_t show_overscan:2; |
| | 97 | uint32_t *frame_count; |
| | 98 | uint32_t *hcnt; /* hsync count */ |
| | 99 | struct { |
| | 100 | uint32_t addr; |
| | 101 | uint32_t cycles; |
| | 102 | uint32_t frame; |
| | 103 | uint32_t hcnt; |
| | 104 | } last_list; |
| | 105 | uint32_t last_vram_read_frame; |
| | 106 | uint32_t last_adflip_frame; |
| | 107 | uint16_t w_out_old, h_out_old, src_y_old; |
| | 108 | uint32_t status_vo_old; |
| | 109 | short screen_centering_type; |
| | 110 | short screen_centering_type_default; |
| | 111 | short screen_centering_x; |
| | 112 | short screen_centering_y; |
| | 113 | int screen_centering_h_adj; |
| | 114 | } state; |
| | 115 | struct { |
| | 116 | int32_t set:3; /* -1 auto, 0 off, 1-3 fixed */ |
| | 117 | int32_t cnt:3; /* amount skipped in a row */ |
| | 118 | uint32_t active:1; |
| | 119 | uint32_t allow:1; |
| | 120 | uint32_t frame_ready:1; |
| | 121 | uint32_t ecmds_dirty_renderer:1; |
| | 122 | const int *advice; |
| | 123 | const int *force; |
| | 124 | int *dirty; |
| | 125 | uint32_t last_flip_frame; |
| | 126 | uint32_t pending_fill[3]; |
| | 127 | } frameskip; |
| | 128 | uint32_t cmd_buffer[CMD_BUFFER_LEN]; |
| | 129 | struct psx_gpu_async *async; |
| | 130 | void *(*get_enhancement_bufer) |
| | 131 | (int *x, int *y, int *w, int *h, int *vram_h); |
| | 132 | uint16_t *(*get_downscale_buffer) |
| | 133 | (int *x, int *y, int *w, int *h, int *vram_h); |
| | 134 | void *(*mmap)(unsigned int size); |
| | 135 | void (*munmap)(void *ptr, unsigned int size); |
| | 136 | void (*gpu_state_change)(int what, int cycles); // psx_gpu_state |
| | 137 | }; |
| | 138 | |
| | 139 | extern struct psx_gpu gpu; |
| | 140 | |
| | 141 | extern const unsigned char cmd_lengths[256]; |
| | 142 | |
| | 143 | struct rearmed_cbs; |
| | 144 | |
| | 145 | // ex_regs: renderer should write Ex values for gpulib, never use them itself |
| | 146 | int renderer_do_cmd_list(uint32_t *list, int count, uint32_t *ex_regs, |
| | 147 | int *cycles_sum, int *cycles_last, int *last_cmd); |
| | 148 | |
| | 149 | int renderer_init(void); |
| | 150 | void renderer_finish(void); |
| | 151 | void renderer_sync_ecmds(uint32_t * ecmds); |
| | 152 | void renderer_update_caches(int x, int y, int w, int h, int state_changed); |
| | 153 | void renderer_flush_queues(void); |
| | 154 | void renderer_set_interlace(int enable, int is_odd); |
| | 155 | void renderer_set_config(const struct rearmed_cbs *config); |
| | 156 | void renderer_notify_screen_change(const struct psx_gpu_screen *screen); |
| | 157 | |
| | 158 | int vout_init(void); |
| | 159 | int vout_finish(void); |
| | 160 | int vout_update(struct psx_gpu *gpu, int src_x, int src_y); |
| | 161 | void vout_blank(struct psx_gpu *gpu); |
| | 162 | void vout_set_config(const struct rearmed_cbs *config); |
| | 163 | |
| | 164 | // helpers |
| | 165 | #define VRAM_MEM_XY(vram_, x, y) &vram_[(y) * 1024 + (x)] |
| | 166 | |
| | 167 | int do_vram_copy(uint16_t *vram, const uint32_t *ex_regs, |
| | 168 | const uint32_t *params, int *cpu_cycles); |
| | 169 | |
| | 170 | int prim_try_simplify_quad_t (void *simplified, const void *prim); |
| | 171 | int prim_try_simplify_quad_gt(void *simplified, const void *prim); |
| | 172 | |
| | 173 | void cpy_mask(uint16_t *dst, const uint16_t *src, int l, uint32_t r6); |
| | 174 | |
| | 175 | static inline void do_vram_line(uint16_t *vram_, int x, int y, |
| | 176 | uint16_t *mem, int l, int is_read, uint32_t r6) |
| | 177 | { |
| | 178 | uint16_t *vram = VRAM_MEM_XY(vram_, x, y); |
| | 179 | if (unlikely(is_read)) |
| | 180 | memcpy(mem, vram, l * 2); |
| | 181 | else if (unlikely(r6)) |
| | 182 | cpy_mask(vram, mem, l, r6); |
| | 183 | else |
| | 184 | memcpy(vram, mem, l * 2); |
| | 185 | } |
| | 186 | |
| | 187 | /* listing these here for correct linkage if rasterizer uses c++ */ |
| | 188 | struct GPUFreeze; |
| | 189 | |
| | 190 | long GPUinit(void); |
| | 191 | long GPUshutdown(void); |
| | 192 | void GPUwriteDataMem(uint32_t *mem, int count); |
| | 193 | long GPUdmaChain(uint32_t *rambase, uint32_t addr, |
| | 194 | uint32_t *progress_addr, int32_t *cycles_last_cmd); |
| | 195 | void GPUwriteData(uint32_t data); |
| | 196 | void GPUreadDataMem(uint32_t *mem, int count); |
| | 197 | uint32_t GPUreadData(void); |
| | 198 | uint32_t GPUreadStatus(void); |
| | 199 | void GPUwriteStatus(uint32_t data); |
| | 200 | long GPUfreeze(uint32_t type, struct GPUFreeze *freeze, uint16_t **vram_ptr); |
| | 201 | long GPUopen(unsigned long *disp, char *cap, char *cfg); |
| | 202 | long GPUclose(void); |
| | 203 | void GPUvBlank(int is_vblank, int lcf); |
| | 204 | void GPUgetScreenInfo(int *y, int *base_hres); |
| | 205 | void GPUrearmedCallbacks(const struct rearmed_cbs *cbs_); |
| | 206 | |
| | 207 | void SysPrintf(const char *fmt, ...); |
| | 208 | |
| | 209 | #ifdef __cplusplus |
| | 210 | } |
| | 211 | #endif |
| | 212 | |
| | 213 | #endif /* __GPULIB_GPU_H__ */ |