| | 1 | #ifndef __SPUNULL_REGISTER_H__\r |
| | 2 | #define __SPUNULL_REGISTER_H__\r |
| | 3 | \r |
| | 4 | #define H_SPUirqAddr 0x0da4\r |
| | 5 | #define H_SPUaddr 0x0da6\r |
| | 6 | #define H_SPUdata 0x0da8\r |
| | 7 | #define H_SPUctrl 0x0daa\r |
| | 8 | #define H_SPUstat 0x0dae\r |
| | 9 | #define H_SPUon1 0x0d88\r |
| | 10 | #define H_SPUon2 0x0d8a\r |
| | 11 | #define H_SPUoff1 0x0d8c\r |
| | 12 | #define H_SPUoff2 0x0d8e\r |
| | 13 | #define H_FMod1 0x0d90\r |
| | 14 | #define H_FMod2 0x0d92\r |
| | 15 | #define H_Noise1 0x0d94\r |
| | 16 | #define H_Noise2 0x0d96\r |
| | 17 | #define H_RVBon1 0x0d98\r |
| | 18 | #define H_RVBon2 0x0d9a\r |
| | 19 | #define H_SPUIsOn1 0x0d9c\r |
| | 20 | #define H_SPUIsOn2 0x0d9e\r |
| | 21 | #define H_CDLeft 0x0db0\r |
| | 22 | #define H_CDRight 0x0db2\r |
| | 23 | #define H_Reverb 0x0dc0\r |
| | 24 | \r |
| | 25 | #define H_SPUPitch0 0x0c04\r |
| | 26 | #define H_SPUPitch1 0x0c14\r |
| | 27 | #define H_SPUPitch2 0x0c24\r |
| | 28 | #define H_SPUPitch3 0x0c34\r |
| | 29 | #define H_SPUPitch4 0x0c44\r |
| | 30 | #define H_SPUPitch5 0x0c54\r |
| | 31 | #define H_SPUPitch6 0x0c64\r |
| | 32 | #define H_SPUPitch7 0x0c74\r |
| | 33 | #define H_SPUPitch8 0x0c84\r |
| | 34 | #define H_SPUPitch9 0x0c94\r |
| | 35 | #define H_SPUPitch10 0x0ca4\r |
| | 36 | #define H_SPUPitch11 0x0cb4\r |
| | 37 | #define H_SPUPitch12 0x0cc4\r |
| | 38 | #define H_SPUPitch13 0x0cd4\r |
| | 39 | #define H_SPUPitch14 0x0ce4\r |
| | 40 | #define H_SPUPitch15 0x0cf4\r |
| | 41 | #define H_SPUPitch16 0x0d04\r |
| | 42 | #define H_SPUPitch17 0x0d14\r |
| | 43 | #define H_SPUPitch18 0x0d24\r |
| | 44 | #define H_SPUPitch19 0x0d34\r |
| | 45 | #define H_SPUPitch20 0x0d44\r |
| | 46 | #define H_SPUPitch21 0x0d54\r |
| | 47 | #define H_SPUPitch22 0x0d64\r |
| | 48 | #define H_SPUPitch23 0x0d74\r |
| | 49 | \r |
| | 50 | #define H_SPUStartAdr0 0x0c06\r |
| | 51 | #define H_SPUStartAdr1 0x0c16\r |
| | 52 | #define H_SPUStartAdr2 0x0c26\r |
| | 53 | #define H_SPUStartAdr3 0x0c36\r |
| | 54 | #define H_SPUStartAdr4 0x0c46\r |
| | 55 | #define H_SPUStartAdr5 0x0c56\r |
| | 56 | #define H_SPUStartAdr6 0x0c66\r |
| | 57 | #define H_SPUStartAdr7 0x0c76\r |
| | 58 | #define H_SPUStartAdr8 0x0c86\r |
| | 59 | #define H_SPUStartAdr9 0x0c96\r |
| | 60 | #define H_SPUStartAdr10 0x0ca6\r |
| | 61 | #define H_SPUStartAdr11 0x0cb6\r |
| | 62 | #define H_SPUStartAdr12 0x0cc6\r |
| | 63 | #define H_SPUStartAdr13 0x0cd6\r |
| | 64 | #define H_SPUStartAdr14 0x0ce6\r |
| | 65 | #define H_SPUStartAdr15 0x0cf6\r |
| | 66 | #define H_SPUStartAdr16 0x0d06\r |
| | 67 | #define H_SPUStartAdr17 0x0d16\r |
| | 68 | #define H_SPUStartAdr18 0x0d26\r |
| | 69 | #define H_SPUStartAdr19 0x0d36\r |
| | 70 | #define H_SPUStartAdr20 0x0d46\r |
| | 71 | #define H_SPUStartAdr21 0x0d56\r |
| | 72 | #define H_SPUStartAdr22 0x0d66\r |
| | 73 | #define H_SPUStartAdr23 0x0d76\r |
| | 74 | \r |
| | 75 | #define H_SPULoopAdr0 0x0c0e\r |
| | 76 | #define H_SPULoopAdr1 0x0c1e\r |
| | 77 | #define H_SPULoopAdr2 0x0c2e\r |
| | 78 | #define H_SPULoopAdr3 0x0c3e\r |
| | 79 | #define H_SPULoopAdr4 0x0c4e\r |
| | 80 | #define H_SPULoopAdr5 0x0c5e\r |
| | 81 | #define H_SPULoopAdr6 0x0c6e\r |
| | 82 | #define H_SPULoopAdr7 0x0c7e\r |
| | 83 | #define H_SPULoopAdr8 0x0c8e\r |
| | 84 | #define H_SPULoopAdr9 0x0c9e\r |
| | 85 | #define H_SPULoopAdr10 0x0cae\r |
| | 86 | #define H_SPULoopAdr11 0x0cbe\r |
| | 87 | #define H_SPULoopAdr12 0x0cce\r |
| | 88 | #define H_SPULoopAdr13 0x0cde\r |
| | 89 | #define H_SPULoopAdr14 0x0cee\r |
| | 90 | #define H_SPULoopAdr15 0x0cfe\r |
| | 91 | #define H_SPULoopAdr16 0x0d0e\r |
| | 92 | #define H_SPULoopAdr17 0x0d1e\r |
| | 93 | #define H_SPULoopAdr18 0x0d2e\r |
| | 94 | #define H_SPULoopAdr19 0x0d3e\r |
| | 95 | #define H_SPULoopAdr20 0x0d4e\r |
| | 96 | #define H_SPULoopAdr21 0x0d5e\r |
| | 97 | #define H_SPULoopAdr22 0x0d6e\r |
| | 98 | #define H_SPULoopAdr23 0x0d7e\r |
| | 99 | \r |
| | 100 | #define H_SPU_ADSRLevel0 0x0c08\r |
| | 101 | #define H_SPU_ADSRLevel1 0x0c18\r |
| | 102 | #define H_SPU_ADSRLevel2 0x0c28\r |
| | 103 | #define H_SPU_ADSRLevel3 0x0c38\r |
| | 104 | #define H_SPU_ADSRLevel4 0x0c48\r |
| | 105 | #define H_SPU_ADSRLevel5 0x0c58\r |
| | 106 | #define H_SPU_ADSRLevel6 0x0c68\r |
| | 107 | #define H_SPU_ADSRLevel7 0x0c78\r |
| | 108 | #define H_SPU_ADSRLevel8 0x0c88\r |
| | 109 | #define H_SPU_ADSRLevel9 0x0c98\r |
| | 110 | #define H_SPU_ADSRLevel10 0x0ca8\r |
| | 111 | #define H_SPU_ADSRLevel11 0x0cb8\r |
| | 112 | #define H_SPU_ADSRLevel12 0x0cc8\r |
| | 113 | #define H_SPU_ADSRLevel13 0x0cd8\r |
| | 114 | #define H_SPU_ADSRLevel14 0x0ce8\r |
| | 115 | #define H_SPU_ADSRLevel15 0x0cf8\r |
| | 116 | #define H_SPU_ADSRLevel16 0x0d08\r |
| | 117 | #define H_SPU_ADSRLevel17 0x0d18\r |
| | 118 | #define H_SPU_ADSRLevel18 0x0d28\r |
| | 119 | #define H_SPU_ADSRLevel19 0x0d38\r |
| | 120 | #define H_SPU_ADSRLevel20 0x0d48\r |
| | 121 | #define H_SPU_ADSRLevel21 0x0d58\r |
| | 122 | #define H_SPU_ADSRLevel22 0x0d68\r |
| | 123 | #define H_SPU_ADSRLevel23 0x0d78\r |
| | 124 | \r |
| | 125 | #endif /* __SPUNULL_REGISTER_H__ */\r |
notaz.gp2x.de / pcsx_rearmed.git / blame_incremental