| 1 | /*************************************************************************** |
| 2 | * Copyright (C) 2010 by Blade_Arma * |
| 3 | * * |
| 4 | * This program is free software; you can redistribute it and/or modify * |
| 5 | * it under the terms of the GNU General Public License as published by * |
| 6 | * the Free Software Foundation; either version 2 of the License, or * |
| 7 | * (at your option) any later version. * |
| 8 | * * |
| 9 | * This program is distributed in the hope that it will be useful, * |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
| 12 | * GNU General Public License for more details. * |
| 13 | * * |
| 14 | * You should have received a copy of the GNU General Public License * |
| 15 | * along with this program; if not, write to the * |
| 16 | * Free Software Foundation, Inc., * |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * |
| 18 | ***************************************************************************/ |
| 19 | |
| 20 | /* |
| 21 | * Internal PSX counters. |
| 22 | */ |
| 23 | |
| 24 | #include "psxcounters.h" |
| 25 | #include "gpu.h" |
| 26 | #include "debug.h" |
| 27 | |
| 28 | /******************************************************************************/ |
| 29 | |
| 30 | enum |
| 31 | { |
| 32 | Rc0Gate = 0x0001, // 0 not implemented |
| 33 | Rc1Gate = 0x0001, // 0 not implemented |
| 34 | Rc2Disable = 0x0001, // 0 partially implemented |
| 35 | RcUnknown1 = 0x0002, // 1 ? |
| 36 | RcUnknown2 = 0x0004, // 2 ? |
| 37 | RcCountToTarget = 0x0008, // 3 |
| 38 | RcIrqOnTarget = 0x0010, // 4 |
| 39 | RcIrqOnOverflow = 0x0020, // 5 |
| 40 | RcIrqRegenerate = 0x0040, // 6 |
| 41 | RcUnknown7 = 0x0080, // 7 ? |
| 42 | Rc0PixelClock = 0x0100, // 8 fake implementation |
| 43 | Rc1HSyncClock = 0x0100, // 8 |
| 44 | Rc2Unknown8 = 0x0100, // 8 ? |
| 45 | Rc0Unknown9 = 0x0200, // 9 ? |
| 46 | Rc1Unknown9 = 0x0200, // 9 ? |
| 47 | Rc2OneEighthClock = 0x0200, // 9 |
| 48 | RcUnknown10 = 0x0400, // 10 ? |
| 49 | RcCountEqTarget = 0x0800, // 11 |
| 50 | RcOverflow = 0x1000, // 12 |
| 51 | RcUnknown13 = 0x2000, // 13 ? (always zero) |
| 52 | RcUnknown14 = 0x4000, // 14 ? (always zero) |
| 53 | RcUnknown15 = 0x8000, // 15 ? (always zero) |
| 54 | }; |
| 55 | |
| 56 | #define CounterQuantity ( 4 ) |
| 57 | //static const u32 CounterQuantity = 4; |
| 58 | |
| 59 | static const u32 CountToOverflow = 0; |
| 60 | static const u32 CountToTarget = 1; |
| 61 | |
| 62 | static const u32 FrameRate[] = { 60, 50 }; |
| 63 | static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL |
| 64 | #define VBlankStart 240 |
| 65 | |
| 66 | #define VERBOSE_LEVEL 0 |
| 67 | |
| 68 | /******************************************************************************/ |
| 69 | #ifdef DRC_DISABLE |
| 70 | Rcnt rcnts[ CounterQuantity ]; |
| 71 | #endif |
| 72 | u32 hSyncCount = 0; |
| 73 | u32 frame_counter = 0; |
| 74 | static u32 hsync_steps = 0; |
| 75 | static u32 base_cycle = 0; |
| 76 | |
| 77 | u32 psxNextCounter = 0, psxNextsCounter = 0; |
| 78 | |
| 79 | /******************************************************************************/ |
| 80 | |
| 81 | static inline |
| 82 | void setIrq( u32 irq ) |
| 83 | { |
| 84 | psxHu32ref(0x1070) |= SWAPu32(irq); |
| 85 | } |
| 86 | |
| 87 | static |
| 88 | void verboseLog( u32 level, const char *str, ... ) |
| 89 | { |
| 90 | #if VERBOSE_LEVEL > 0 |
| 91 | if( level <= VERBOSE_LEVEL ) |
| 92 | { |
| 93 | va_list va; |
| 94 | char buf[ 4096 ]; |
| 95 | |
| 96 | va_start( va, str ); |
| 97 | vsprintf( buf, str, va ); |
| 98 | va_end( va ); |
| 99 | |
| 100 | printf( "%s", buf ); |
| 101 | fflush( stdout ); |
| 102 | } |
| 103 | #endif |
| 104 | } |
| 105 | |
| 106 | /******************************************************************************/ |
| 107 | |
| 108 | static inline |
| 109 | void _psxRcntWcount( u32 index, u32 value ) |
| 110 | { |
| 111 | if( value > 0xffff ) |
| 112 | { |
| 113 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); |
| 114 | value &= 0xffff; |
| 115 | } |
| 116 | |
| 117 | rcnts[index].cycleStart = psxRegs.cycle; |
| 118 | rcnts[index].cycleStart -= value * rcnts[index].rate; |
| 119 | |
| 120 | // TODO: <=. |
| 121 | if( value < rcnts[index].target ) |
| 122 | { |
| 123 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; |
| 124 | rcnts[index].counterState = CountToTarget; |
| 125 | } |
| 126 | else |
| 127 | { |
| 128 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
| 129 | rcnts[index].counterState = CountToOverflow; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static inline |
| 134 | u32 _psxRcntRcount( u32 index ) |
| 135 | { |
| 136 | u32 count; |
| 137 | |
| 138 | count = psxRegs.cycle; |
| 139 | count -= rcnts[index].cycleStart; |
| 140 | if (rcnts[index].rate > 1) |
| 141 | count /= rcnts[index].rate; |
| 142 | |
| 143 | if( count > 0x10000 ) |
| 144 | { |
| 145 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
| 146 | } |
| 147 | count &= 0xffff; |
| 148 | |
| 149 | return count; |
| 150 | } |
| 151 | |
| 152 | static |
| 153 | void _psxRcntWmode( u32 index, u32 value ) |
| 154 | { |
| 155 | rcnts[index].mode = value; |
| 156 | |
| 157 | switch( index ) |
| 158 | { |
| 159 | case 0: |
| 160 | if( value & Rc0PixelClock ) |
| 161 | { |
| 162 | rcnts[index].rate = 5; |
| 163 | } |
| 164 | else |
| 165 | { |
| 166 | rcnts[index].rate = 1; |
| 167 | } |
| 168 | break; |
| 169 | case 1: |
| 170 | if( value & Rc1HSyncClock ) |
| 171 | { |
| 172 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); |
| 173 | } |
| 174 | else |
| 175 | { |
| 176 | rcnts[index].rate = 1; |
| 177 | } |
| 178 | break; |
| 179 | case 2: |
| 180 | if( value & Rc2OneEighthClock ) |
| 181 | { |
| 182 | rcnts[index].rate = 8; |
| 183 | } |
| 184 | else |
| 185 | { |
| 186 | rcnts[index].rate = 1; |
| 187 | } |
| 188 | |
| 189 | // TODO: wcount must work. |
| 190 | if( value & Rc2Disable ) |
| 191 | { |
| 192 | rcnts[index].rate = 0xffffffff; |
| 193 | } |
| 194 | break; |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | /******************************************************************************/ |
| 199 | |
| 200 | static |
| 201 | void psxRcntSet() |
| 202 | { |
| 203 | s32 countToUpdate; |
| 204 | u32 i; |
| 205 | |
| 206 | psxNextsCounter = psxRegs.cycle; |
| 207 | psxNextCounter = 0x7fffffff; |
| 208 | |
| 209 | for( i = 0; i < CounterQuantity; ++i ) |
| 210 | { |
| 211 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); |
| 212 | |
| 213 | if( countToUpdate < 0 ) |
| 214 | { |
| 215 | psxNextCounter = 0; |
| 216 | break; |
| 217 | } |
| 218 | |
| 219 | if( countToUpdate < (s32)psxNextCounter ) |
| 220 | { |
| 221 | psxNextCounter = countToUpdate; |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | psxRegs.interrupt |= (1 << PSXINT_RCNT); |
| 226 | new_dyna_set_event(PSXINT_RCNT, psxNextCounter); |
| 227 | } |
| 228 | |
| 229 | /******************************************************************************/ |
| 230 | |
| 231 | static |
| 232 | void psxRcntReset( u32 index ) |
| 233 | { |
| 234 | u32 rcycles; |
| 235 | |
| 236 | rcnts[index].mode |= RcUnknown10; |
| 237 | |
| 238 | if( rcnts[index].counterState == CountToTarget ) |
| 239 | { |
| 240 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
| 241 | if( rcnts[index].mode & RcCountToTarget ) |
| 242 | { |
| 243 | rcycles -= rcnts[index].target * rcnts[index].rate; |
| 244 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; |
| 245 | } |
| 246 | else |
| 247 | { |
| 248 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
| 249 | rcnts[index].counterState = CountToOverflow; |
| 250 | } |
| 251 | |
| 252 | if( rcnts[index].mode & RcIrqOnTarget ) |
| 253 | { |
| 254 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) |
| 255 | { |
| 256 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
| 257 | setIrq( rcnts[index].irq ); |
| 258 | rcnts[index].irqState = 1; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | rcnts[index].mode |= RcCountEqTarget; |
| 263 | |
| 264 | if( rcycles < 0x10000 * rcnts[index].rate ) |
| 265 | return; |
| 266 | } |
| 267 | |
| 268 | if( rcnts[index].counterState == CountToOverflow ) |
| 269 | { |
| 270 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
| 271 | rcycles -= 0x10000 * rcnts[index].rate; |
| 272 | |
| 273 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; |
| 274 | |
| 275 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
| 276 | { |
| 277 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; |
| 278 | rcnts[index].counterState = CountToTarget; |
| 279 | } |
| 280 | |
| 281 | if( rcnts[index].mode & RcIrqOnOverflow ) |
| 282 | { |
| 283 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) |
| 284 | { |
| 285 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
| 286 | setIrq( rcnts[index].irq ); |
| 287 | rcnts[index].irqState = 1; |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | rcnts[index].mode |= RcOverflow; |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | void psxRcntUpdate() |
| 296 | { |
| 297 | u32 cycle; |
| 298 | |
| 299 | cycle = psxRegs.cycle; |
| 300 | |
| 301 | // rcnt 0. |
| 302 | while( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) |
| 303 | { |
| 304 | psxRcntReset( 0 ); |
| 305 | } |
| 306 | |
| 307 | // rcnt 1. |
| 308 | while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) |
| 309 | { |
| 310 | psxRcntReset( 1 ); |
| 311 | } |
| 312 | |
| 313 | // rcnt 2. |
| 314 | while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) |
| 315 | { |
| 316 | psxRcntReset( 2 ); |
| 317 | } |
| 318 | |
| 319 | // rcnt base. |
| 320 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) |
| 321 | { |
| 322 | u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle; |
| 323 | u32 next_vsync; |
| 324 | |
| 325 | hSyncCount += hsync_steps; |
| 326 | |
| 327 | // VSync irq. |
| 328 | if( hSyncCount == VBlankStart ) |
| 329 | { |
| 330 | HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF); |
| 331 | GPU_vBlank( 1, 0 ); |
| 332 | setIrq( 0x01 ); |
| 333 | |
| 334 | EmuUpdate(); |
| 335 | GPU_updateLace(); |
| 336 | |
| 337 | if( SPU_async ) |
| 338 | { |
| 339 | SPU_async( cycle, 1 ); |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | // Update lace. (with InuYasha fix) |
| 344 | if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) |
| 345 | { |
| 346 | hSyncCount = 0; |
| 347 | frame_counter++; |
| 348 | |
| 349 | gpuSyncPluginSR(); |
| 350 | if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS)) |
| 351 | HW_GPU_STATUS |= SWAP32(frame_counter << 31); |
| 352 | GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31); |
| 353 | } |
| 354 | |
| 355 | // Schedule next call, in hsyncs |
| 356 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; |
| 357 | next_vsync = VBlankStart - hSyncCount; // ok to overflow |
| 358 | if( next_vsync && next_vsync < hsync_steps ) |
| 359 | hsync_steps = next_vsync; |
| 360 | |
| 361 | rcnts[3].cycleStart = cycle - leftover_cycles; |
| 362 | if (Config.PsxType) |
| 363 | // 20.12 precision, clk / 50 / 313 ~= 2164.14 |
| 364 | base_cycle += hsync_steps * 8864320; |
| 365 | else |
| 366 | // clk / 60 / 263 ~= 2146.31 |
| 367 | base_cycle += hsync_steps * 8791293; |
| 368 | rcnts[3].cycle = base_cycle >> 12; |
| 369 | base_cycle &= 0xfff; |
| 370 | } |
| 371 | |
| 372 | psxRcntSet(); |
| 373 | |
| 374 | #ifndef NDEBUG |
| 375 | DebugVSync(); |
| 376 | #endif |
| 377 | } |
| 378 | |
| 379 | /******************************************************************************/ |
| 380 | |
| 381 | void psxRcntWcount( u32 index, u32 value ) |
| 382 | { |
| 383 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); |
| 384 | |
| 385 | _psxRcntWcount( index, value ); |
| 386 | psxRcntSet(); |
| 387 | } |
| 388 | |
| 389 | void psxRcntWmode( u32 index, u32 value ) |
| 390 | { |
| 391 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); |
| 392 | |
| 393 | _psxRcntWmode( index, value ); |
| 394 | _psxRcntWcount( index, 0 ); |
| 395 | |
| 396 | rcnts[index].irqState = 0; |
| 397 | psxRcntSet(); |
| 398 | } |
| 399 | |
| 400 | void psxRcntWtarget( u32 index, u32 value ) |
| 401 | { |
| 402 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); |
| 403 | |
| 404 | rcnts[index].target = value; |
| 405 | |
| 406 | _psxRcntWcount( index, _psxRcntRcount( index ) ); |
| 407 | psxRcntSet(); |
| 408 | } |
| 409 | |
| 410 | /******************************************************************************/ |
| 411 | |
| 412 | u32 psxRcntRcount( u32 index ) |
| 413 | { |
| 414 | u32 count; |
| 415 | |
| 416 | count = _psxRcntRcount( index ); |
| 417 | |
| 418 | // Parasite Eve 2 fix. |
| 419 | if( Config.RCntFix ) |
| 420 | { |
| 421 | if( index == 2 ) |
| 422 | { |
| 423 | if( rcnts[index].counterState == CountToTarget ) |
| 424 | { |
| 425 | count /= BIAS; |
| 426 | } |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); |
| 431 | |
| 432 | return count; |
| 433 | } |
| 434 | |
| 435 | u32 psxRcntRmode( u32 index ) |
| 436 | { |
| 437 | u16 mode; |
| 438 | |
| 439 | mode = rcnts[index].mode; |
| 440 | rcnts[index].mode &= 0xe7ff; |
| 441 | |
| 442 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); |
| 443 | |
| 444 | return mode; |
| 445 | } |
| 446 | |
| 447 | u32 psxRcntRtarget( u32 index ) |
| 448 | { |
| 449 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); |
| 450 | |
| 451 | return rcnts[index].target; |
| 452 | } |
| 453 | |
| 454 | /******************************************************************************/ |
| 455 | |
| 456 | void psxRcntInit() |
| 457 | { |
| 458 | s32 i; |
| 459 | |
| 460 | // rcnt 0. |
| 461 | rcnts[0].rate = 1; |
| 462 | rcnts[0].irq = 0x10; |
| 463 | |
| 464 | // rcnt 1. |
| 465 | rcnts[1].rate = 1; |
| 466 | rcnts[1].irq = 0x20; |
| 467 | |
| 468 | // rcnt 2. |
| 469 | rcnts[2].rate = 1; |
| 470 | rcnts[2].irq = 0x40; |
| 471 | |
| 472 | // rcnt base. |
| 473 | rcnts[3].rate = 1; |
| 474 | rcnts[3].mode = RcCountToTarget; |
| 475 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); |
| 476 | |
| 477 | for( i = 0; i < CounterQuantity; ++i ) |
| 478 | { |
| 479 | _psxRcntWcount( i, 0 ); |
| 480 | } |
| 481 | |
| 482 | hSyncCount = 0; |
| 483 | hsync_steps = 1; |
| 484 | |
| 485 | psxRcntSet(); |
| 486 | } |
| 487 | |
| 488 | /******************************************************************************/ |
| 489 | |
| 490 | s32 psxRcntFreeze( void *f, s32 Mode ) |
| 491 | { |
| 492 | u32 spuSyncCount = 0; |
| 493 | u32 count; |
| 494 | s32 i; |
| 495 | |
| 496 | gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity ); |
| 497 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
| 498 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); |
| 499 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); |
| 500 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); |
| 501 | |
| 502 | if (Mode == 0) |
| 503 | { |
| 504 | // don't trust things from a savestate |
| 505 | rcnts[3].rate = 1; |
| 506 | for( i = 0; i < CounterQuantity; ++i ) |
| 507 | { |
| 508 | _psxRcntWmode( i, rcnts[i].mode ); |
| 509 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; |
| 510 | _psxRcntWcount( i, count ); |
| 511 | } |
| 512 | hsync_steps = 0; |
| 513 | if (rcnts[3].target) |
| 514 | hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target; |
| 515 | psxRcntSet(); |
| 516 | |
| 517 | base_cycle = 0; |
| 518 | } |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | /******************************************************************************/ |